Printed circuit board

Abstract

To provide a printed circuit board with excellent warpage control by the application of a glass layer.SOLUTION: A printed circuit board 100A includes a glass layer 111, a plurality of blind cavities C1 to C4 each penetrating a portion of the glass layer from an upper surface or a lower surface of the glass layer, a plurality of passive elements 151 to 154 disposed in the plurality of blind cavities, and an insulating layer 112 covering at least a portion of the glass layer and the plurality of passive elements and filling at least a portion of the plurality of blind cavities. At least two of the plurality of blind cavities have different depths.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] As semiconductors become more powerful, the size of package substrates is constantly increasing, and the thickness of cores is continually increasing to reduce warpage of large-area substrates. Recently, there has been a demand to reduce the thickness of cores in order to reduce the pitch of through vias formed in the cores, and the application of glass cores is being considered. In the case of high-performance semiconductors to which glass cores are applied, passive elements must be embedded to improve power efficiency and power integrity characteristics, and various types of passive elements such as ceramic capacitors and silicon capacitors may be required to improve performance. Summary of the Invention [Problem to be solved by the invention]

[0003] Among the various objects of the present invention is to provide a printed circuit board with excellent warpage control through the application of a glass layer.

[0004] Another of the various objects of the present invention is to provide a printed circuit board that allows for a wide variety of passive components to be embedded in the glass layer.

[0005] Yet another of the various objects of the present invention is to provide a printed circuit board that allows for increased capacitance, reduced parasitic inductance (ESL), reduced power paths, etc. [Means for solving the problem]

[0006] One of several solutions proposed through the present invention is to form blind cavities of various depths in a glass layer applied as a core layer of a substrate, and further form through cavities as necessary, and respectively arrange and embed passive elements and electronic components including various types of capacitors in the blind cavities and through cavities.

[0007] For example, one example of a printed circuit board includes a glass layer, a plurality of blind cavities each penetrating a portion of the glass layer from an upper or lower surface of the glass layer, a plurality of passive elements respectively disposed in the plurality of blind cavities, and an insulating layer covering the glass layer and at least a portion of each of the plurality of passive elements and filling at least a portion of each of the plurality of blind cavities, wherein at least two of the plurality of blind cavities may have different depths from each other.

[0008] For example, a printed circuit board according to one example may include a glass layer, a blind cavity penetrating a portion of the glass layer from an upper or lower surface of the glass layer, a through cavity penetrating between the upper and lower surfaces of the glass layer, a passive element disposed in the blind cavity, an electronic component disposed in the through cavity, and an insulating layer covering the glass layer, at least a portion of the passive element, and the electronic component, and filling at least a portion of each of the blind cavity and the through cavity. Effect of the Invention

[0009] Among other advantages of the present invention is that the application of a glass layer provides a printed circuit board with excellent warpage control.

[0010] Another advantage of the present invention is that it provides a printed circuit board that allows a wide variety of passive components to be embedded in the glass layer.

[0011] Another advantage of the present invention is that it provides a printed circuit board that can increase capacitance, reduce parasitic inductance (ESL), and reduce power paths. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating an example of a printed circuit board. [Figure 4] FIG. 4 is a cross-sectional view that illustrates a modification of the printed circuit board of FIG. [Figure 5a] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5b] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5c] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5d] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5e] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5f] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5g] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 6] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 7] FIG. 7 is a cross-sectional view that illustrates a modification of the printed circuit board of FIG. [Figure 8a] 7A to 7C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6. [Figure 8b] 7A to 7C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6. [Figure 8c] 7A to 7C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6. [Figure 8d] 7A to 7C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6. [Figure 8e] 7A to 7C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6. [Figure 8f] 7A to 7C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6. [Figure 8g] 7A to 7C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6. [Figure 8h] 7A to 7C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6. [Figure 9] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 10] 10 is a cross-sectional view that illustrates a modification of the printed circuit board of FIG. 9. [Figure 11a] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 11b] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 11c] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 11d] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 11e] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 11f] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 11g] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 11h] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0014] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0015] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0016] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0017] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0018] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0019] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0020] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0021] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0022] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0023] Printed Circuit Board FIG. 3 is a cross-sectional view that illustrates an example of a printed circuit board.

[0024] Referring to the drawings, an example printed circuit board 100A includes a glass layer 111, first to fourth blind cavities C1, C2, C3, C4 that penetrate a portion of the glass layer 111 from the upper or lower surface of the glass layer 111, respectively, first to fourth passive elements 151, 152, 153, 154 arranged in the first to fourth blind cavities C1, C2, C3, C4, respectively, a through cavity H that penetrates between the upper and lower surfaces of the glass layer 111, an electronic component 155 arranged in the through cavity H, and an insulating layer 112 that covers at least a portion of each of the glass layer 111, the first to fourth passive elements 151, 152, 153, 154, and the electronic component 155, and fills at least a portion of each of the first to fourth blind cavities C1, C2, C3, C4. At least two of the first to fourth blind cavities C1, C2, C3, and C4 may have different depths. In the thickness direction, the first and third blind cavities C1 and C3 may at least partially overlap with each other, and the second and fourth blind cavities C2 and C4 may at least partially overlap with each other. The electronic component 155 may be thicker than each of the first to fourth passive elements 151, 152, 153, and 154. For example, the electronic component 155 may include a high-capacitance ceramic capacitor, and each of the first to fourth passive elements 151, 152, 153, and 154 may include a silicon capacitor with low parasitic inductance (ESL).

[0025] In this way, the printed circuit board 100A according to an example may include the glass layer 111 as a core layer, so that warpage control may be easy in various situations. In addition, the first to fourth blind cavities C1, C2, C3, and C4 of various depths may be formed in the glass layer 111, and the first to fourth passive elements 151, 152, 153, and 154 may be appropriately arranged in the first to fourth blind cavities C1, C2, C3, and C4 of various depths, and a through cavity H may be further formed as necessary, and an electronic component 155 may be arranged in the through cavity H. At this time, the first to fourth passive elements 151, 152, 153, and 154 and the electronic component 155 may include various types of capacitors. Therefore, since various types of capacitors can be arranged at various positions in the board, power efficiency may be improved, and the characteristics of signal integrity (SI) and power integrity (PI) may be improved. In addition, the first and third passive elements 151 and 153 may be connected in parallel to each other, and the second and fourth passive elements 152 and 154 may be connected in parallel to each other. This can have the effects of increasing capacitance, reducing parasitic inductance (ESL), and reducing power paths.

[0026] Meanwhile, the printed circuit board 100A according to an example may further include a first wiring layer 121 arranged on the bottom surfaces of the first and second blind cavities C1, C2, a second wiring layer 122 arranged on the bottom surfaces of the third and fourth blind cavities C3, C4, third and fourth wiring layers 123, 124 arranged on the upper and lower surfaces of the glass layer 111, respectively, fifth and sixth wiring layers 125, 126 arranged on the upper and lower surfaces of the insulating layer 112, respectively, a first via layer 131 penetrating the glass layer 111 between the first and third blind cavities C1, C3 and the second and fourth blind cavities C2, C4, a second via layer 132 penetrating between the upper and lower surfaces of the glass layer 111, a third via layer 133 penetrating a portion of the upper side of the insulating layer 112, and a fourth via layer 134 penetrating a portion of the lower side of the insulating layer 112. The first to fourth passive elements 151, 152, 153, and 154 may each include a through silicon via v, and the through silicon via v of each of the first to fourth passive elements 151, 152, 153, and 154 may be coupled to at least a portion of each of the first and second wiring layers 121 and 122 via a first electrically connecting metal 160. The first to fourth passive elements 151, 152, 153, and 154 may each have a connection pad p, and the connection pad p of each of the first to fourth passive elements 151, 152, 153, and 154 may be coupled to at least a portion of each of the fifth and sixth wiring layers 125 and 126 via at least a portion of each of the third and fourth via layers 133 and 134. The electronic component 155 may have an external electrode P, and the external electrode P of the electronic component 155 may be connected to at least a portion of each of the fifth and sixth wiring layers 125, 126 through at least a portion of each of the third and fourth via layers 133, 134.

[0027] As described above, in the printed circuit board 100A according to an example, the first and second wiring layers 121 and 122 may be disposed on the bottom surfaces of the first to fourth blind cavities C1, C2, C3, and C4, respectively, and the first to fourth passive elements 151, 152, 153, and 154 may be connected to the first and second wiring layers 121 and 122, respectively. Also, the first to fourth passive elements 151, 152, 153, and 154 may each include a through silicon via v. Therefore, the parallel connection between the silicon capacitors may be more easily realized. Also, the first to fourth passive elements 151, 152, 153, and 154 and the electronic component 155 may be more easily electrically connected to the first to sixth wiring layers 121, 122, 123, 124, 125, and 126 in the substrate. Therefore, the power efficiency may be more effectively improved, and the characteristics of signal integrity (SI) and power integrity (PI) may be more effectively improved. In addition, it is possible to more effectively increase capacitance, reduce parasitic inductance (ESL), and reduce power paths.

[0028] The components of the example printed circuit board 100A are described in more detail below with reference to the drawings.

[0029] The glass layer 111 may include glass, which is a non-crystalline solid. Glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc. However, alternative glass materials, such as fluoride glass, phosphate glass, chalcogenide glass, etc., may also be used as materials, without being limited thereto. Other additives may also be included to form glass with specific physical properties. Such additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of such elements and other elements. The glass layer 111 may be a layer distinct from organic insulating materials, such as glass fiber (glass cloth, glass fabric), for example, CCL (copper clad laminate), PPG (prepreg), etc. For example, the glass layer 111 may include plate glass.

[0030] The insulating layer 112 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or a glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymeric materials may be used. The insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric). The insulating layer 112 may include multiple layers, but the boundaries between these layers may be unclear after curing.

[0031] Each of the first to sixth wiring layers 121, 122, 123, 124, 125, and 126 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first to sixth wiring layers 121, 122, 123, 124, 125, and 126 may perform various functions according to the design. For example, the first to sixth wiring layers 121, 122, 123, 124, 125, and 126 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. Each of the first to sixth wiring layers 121, 122, 123, 124, 125, and 126 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). It may include a sputtering layer instead of the electroless plating layer (or chemical copper), or it may include both the electroless plating layer (or chemical copper) and the sputtering layer as necessary.

[0032] The first and second via layers 131 and 132 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. The first and second via layers 131 and 132 may include a through glass via. For example, the through glass via of the first via layer 131 may include a PTH (Plated Through Hole) formed by filling the first through hole 131v penetrating the glass layer 111 with the above-mentioned metal material by plating. The through glass via of the second via layer 132 may include a PTH (Plated Through Hole) in which the above-mentioned metal material is conformally formed on the wall surface of the second through hole 132v penetrating the glass layer 111 by plating, and an insulating material is filled therein. The first and second via layers 131 and 132 may have various functions depending on the design of the through glass vias of the layers. For example, they may include ground vias, power vias, signal vias, etc. The first and second via layers 131 and 132 may include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, and both the electroless plating layer (or chemical copper) and the sputtering layer may be included as necessary.

[0033] The third and fourth via layers 133 and 134 may each include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. The third and fourth via layers 133 and 134 may each include a microvia. The microvia may be a filled via that fills a via hole, or may be a conformal via that is arranged along the wall surface of a via hole. The microvia may be arranged in a stacked type and / or staggered type. The microvias of the third and fourth via layers 133 and 134 may perform various functions depending on the design of the layer. For example, they may include a ground via, a power via, a signal via, and the like. The third and fourth via layers 133, 134 may include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), respectively. A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The third and fourth via layers 133, 134 may have tapered shapes in opposite directions to each other.

[0034] The first via layer 131 may penetrate the glass layer 111 between the first and third blind cavities C1, C3 and between the second and fourth blind cavities C2, C4 to connect at least a portion of the first and second wiring layers 121, 122 to each other. The second via layer 132 may penetrate between the upper and lower surfaces of the glass layer 111 to connect at least a portion of the third and fourth wiring layers 123, 124 to each other. The third via layer 133 may penetrate a portion of the upper side of the insulating layer 112 to connect at least a portion of the third and fifth wiring layers 123, 125 to each other. The fourth via layer 134 may penetrate a portion of the lower side of the insulating layer 112 to connect at least a portion of the fourth and sixth wiring layers 124, 126 to each other.

[0035] Each of the first to fourth passive elements 151, 152, 153, and 154 may include a chip-type capacitor. The chip-type capacitor may include a silicon capacitor. Each of the silicon capacitors may include a connection pad p and a through silicon via v. Each of the connection pad p and the through silicon via v may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. The first to fourth passive elements 151, 152, 153, and 154 may have the same or different thicknesses. For example, the first and third passive elements 151 and 153 may have substantially the same thickness. Also, the first and third passive elements 151 and 153 may have different thicknesses from the second and fourth passive elements 152 and 154. From this perspective, the first and third blind cavities C1 and C3 may have substantially the same depth. In addition, the first and third blind cavities C1, C3 and the second and fourth blind cavities C2, C4 may have different depths. However, this is merely an example, and the thicknesses and depths of the first to fourth passive elements 151, 152, 153, 154 and the first to fourth blind cavities C1, C2, C4, C4 may have more various relationships. Arranging the first to fourth passive elements 151, 152, 153, 154 in the first to fourth blind cavities C1, C2, C3, C4, respectively, includes arranging at least a portion of each of the first to fourth passive elements 151, 152, 153, 154 in the first to fourth blind cavities C1, C2, C3, C4.

[0036] The electronic component 155 may be a chip-type component, and may be an active component or a passive component. For example, the electronic component 155 may be an active component such as a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory; an application processor chip such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller; or a logic chip such as an analog-to-digital converter or an application-specific IC (ASIC). Alternatively, the electronic component 155 may be a passive component such as a high-frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low temperature co-firing ceramics (LTCC), an EMI (Electro Magnetic Interference) filter, or a multi-layer ceramic capacitor (MLCC). Preferably, the electronic component 155 may be a ceramic capacitor such as a multi-layer ceramic capacitor (MLCC). The external electrode P of the electronic component 155 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Placing the electronic component 155 in the through cavity H may include placing at least a portion of the electronic component 155 in the through cavity H.

[0037] The first electrical connection metal 160 may be formed of a low melting point metal, for example, solder such as tin (Sn)-aluminum (Al)-copper (Cu), but this is merely an example and the material is not particularly limited thereto. The first electrical connection metal 160 may be formed in a multi-layer or single layer. If formed in a multi-layer, it may include copper pillars and solder, and if formed in a single layer, it may include tin-silver solder or copper, but is also not limited thereto.

[0038] FIG. 4 is a cross-sectional view that illustrates a schematic modification of the printed circuit board of FIG.

[0039] 1. Referring to the drawings, the printed circuit board 500A according to the modified example has a structure similar to that of the printed circuit board 100A according to the above-described example, except that the printed circuit board 500A includes first and second built-up insulating layers 113 and 114 respectively disposed on the upper and lower surfaces of the insulating layer 112, a first built-up wiring layer 127 disposed on the upper surface of the first built-up insulating layer 113, a second built-up wiring layer 128 disposed on the lower surface of the second built-up insulating layer 114, a first built-up via layer 135 penetrating the first built-up insulating layer 113, and a second built-up via layer 136 disposed on the lower surface of the second built-up insulating layer 114. The semiconductor chip 200 may further include a second build-up via layer 136 penetrating the first build-up insulating layer 114, a first resist layer 141 disposed on the upper surface of the first build-up insulating layer 113 and covering at least a portion of the first build-up wiring layer 127, a second resist layer 142 disposed on the lower surface of the second build-up insulating layer 114 and covering at least a portion of the second build-up wiring layer 128, and a semiconductor chip 200 disposed on the first resist layer 141 and connected to the first build-up wiring layer 127 via a second electrically connecting metal 210.

[0040] In this manner, the printed circuit board 500A according to the modified example may include the printed circuit board 100A according to the above-mentioned example as a package substrate having the first to fourth passive elements 151, 152, 153, 154 and the electronic component 155 built therein, and may have the form of a semiconductor package with the semiconductor chip 200 mounted thereon.

[0041] The components of the modified printed circuit board 500A will be described in more detail below with reference to the drawings.

[0042] Each of the first and second build-up insulating layers 113 and 114 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or a glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto. Other polymer materials may be used, or a photosensitive insulating material such as PID (Photo Imageable Dielectric) may be used.

[0043] Each of the first and second build-up wiring layers 127 and 128 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first and second build-up wiring layers 127 and 128 may perform various functions according to the design. For example, the first and second build-up wiring layers 127 and 128 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. Each of the first and second build-up wiring layers 127 and 128 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, the first and second build-up wiring layers 127 and 128 may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, the first and second build-up wiring layers 127 and 128 may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). A sputtered layer may be included instead of the electroless plated layer (or chemical copper), or both may be included if desired.

[0044] Each of the first and second build-up via layers 135 and 136 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first and second build-up via layers 135 and 136 may include a microvia. The microvia may be a filled via that fills a via hole, or a conformal via that is arranged along the wall surface of a via hole. The microvia may be arranged in a stacked type and / or staggered type. The microvias of the first and second build-up via layers 135 and 136 may perform various functions depending on the design of the layer. For example, they may include a ground via, a power via, a signal via, and the like. The first and second build-up via layers 135, 136 may include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), respectively. A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The first and second build-up via layers 135, 136 may have tapered shapes in opposite directions. The first build-up via layer 135 may connect parts of the fifth wiring layer 125 and the first build-up wiring layer 127 to each other. The second build-up via layer 136 may connect parts of the sixth wiring layer 126 and the second build-up wiring layer 128 to each other.

[0045] The first and second resist layers 141, 142 may each include, but are not limited to, a liquid or film type solder resist, and may also include other types of insulating materials such as ABF. The first and second resist layers 141, 142 may have openings that expose at least a portion of the first and second build-up wiring layers 127, 128, respectively, and a surface treatment layer may be formed on the exposed patterns as necessary.

[0046] The semiconductor chip 200 may include an integrated circuit (IC) die in which hundreds to millions of elements are integrated into one chip. In this case, the integrated circuit may be, for example, a logic chip such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an application processor (e.g., AP), an analog-to-digital converter, or an application-specific IC (ASIC), but is not limited thereto, and may be a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, or a High Bandwidth Memory (HBM), or may be another type of memory such as a Power Management IC (PMIC).

[0047] The semiconductor chip 200 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a base material forming each body. Various circuits may be formed on the body. Connection pads may be formed on the body, and the connection pads may include a conductive material such as aluminum (Al) or copper (Cu). The semiconductor chip 200 may be a bare die, and in this case, metal bumps may be disposed on the connection pads. The semiconductor chip 200 may be a packaged die, and in this case, a redistribution layer may be further formed on the connection pads, and metal bumps may be disposed on the redistribution layer.

[0048] The second electrical connection metal 210 may be formed of a low melting point metal, for example, solder such as tin (Sn)-aluminum (Al)-copper (Cu), but this is merely an example and the material is not particularly limited thereto. The second electrical connection metal 210 may be formed in a multi-layer or single layer. If formed in a multi-layer, it may include copper pillars and solder, and if formed in a single layer, it may include tin-silver solder or copper, but is also not limited thereto.

[0049] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example, and therefore will not be described again.

[0050] 5a to 5g are cross-sectional views illustrating steps of a manufacturing method for the printed circuit board of FIG.

[0051] Referring to FIG. 5a, a glass layer 111 is prepared. The glass layer 111 may be in the form of a plate glass. Next, the first to fourth blind cavities C1, C2, C3, and C4, the through cavity H, and the second through hole 132v are formed in the glass layer 111. The first to fourth blind cavities C1, C2, C3, and C4, the through cavity H, and the second through hole 132v may be formed by etching using a mask, but are not limited thereto. Meanwhile, when the glass layer 111 is used, it is easy to adjust the depths of the first to fourth blind cavities C1, C2, C3, and C4, and it may be possible to form them to various depths. In addition, since the glass layer 111 has a high rigidity property, even if the intervals between the first to fourth blind cavities C1, C2, C3, and C4 are narrow, the risk of deformation can be reduced.

[0052] 5b, a first through hole 131v is formed in the glass layer 111. The first through hole 131v can also be formed by etching using a mask, but is not limited to this. In this case, the glass layer 111 can also have the above-mentioned effects.

[0053] 5c, first and second wiring layers 121, 122 and a first via layer 131 are formed on a glass layer 111. The first and second wiring layers 121, 122 and the first via layer 131 may be formed by a plating process, for example, by using an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), or a tenting process (TT).

[0054] 5d, third and fourth wiring layers 123, 124 and a second via layer 132 are formed on the glass layer 111. The third and fourth wiring layers 123, 124 and the second via layer 132 may also be formed by a plating process, for example, by using AP (Additive Process), SAP (Semi AP), MSAP (Modified SAP), TT (Tenting), etc. When forming the second via layer 132, a plugging process may be further performed after the plating process.

[0055] 5e, first to fourth passive elements 151, 152, 153, and 154 are disposed in the first to fourth blind cavities C1, C2, C3, and C4, respectively. At this time, the first to fourth passive elements 151, 152, 153, and 154 may be connected to the first and second wiring layers 121 and 122 via the first electrically connecting metal 160. Meanwhile, when the glass layer 111 is used, the risk of deformation due to heat can be reduced even if soldering is performed at a narrow interval.

[0056] 5f, the electronic component 155 is disposed in the through cavity H. For example, the electronic component 155 may be disposed in the through cavity H by attaching the tape 310 to the underside of the glass layer 111, and then attaching the tape 310 to the through cavity H.

[0057] Referring to FIG. 5g, the insulating layer 112 is formed. The insulating layer 112 may be formed in such a manner that a part of the insulating layer 112 is formed on the tape 310 and another part is formed in the area where the tape 310 is removed. The insulating layer 112 may be formed by a lamination process in a state where the insulating layer 112 is attached to a film such as PET (PolyEthylene Terephthalate). Next, the fifth and sixth wiring layers 125, 126 and the third and fourth via layers 133, 134 are formed on the insulating layer 112. The via holes for forming the third and fourth via layers 133, 134 may be formed by a laser drill or the like. The fifth and sixth wiring layers 125, 126 and the third and fourth via layers 133, 134 may also be formed by a plating process, for example, by using AP (Additive Process), SAP (Semi AP), MSAP (Modified SAP), TT (Tenting), or the like.

[0058] The printed circuit board 100A according to the above-mentioned embodiment can be manufactured through a series of processes, and the other repeated explanations will be omitted.

[0059] FIG. 6 is a cross-sectional view that shows a schematic diagram of another example of the printed circuit board, and FIG. 7 is a cross-sectional view that shows a schematic diagram of a modified example of the printed circuit board of FIG.

[0060] Referring to the drawings, the printed circuit board 100B according to another example and the printed circuit board 500B according to the modified example may further include an insulating material 170 disposed between each of the first to fourth wiring layers 121, 122, 123, 124 and the glass layer 111 in the printed circuit board 100A according to the above example and the printed circuit board 500A according to the modified example, and a fifth via layer 137 penetrating the insulating material 170 and connecting at least a portion of each of the first to fourth wiring layers 121, 122, 123, 124 and the first and second via layers 131, 132 to each other. The insulating material 170 may include the insulating material described for the insulating layer 112. The insulating material 170 may protect the glass layer 111 and improve adhesion to the insulating layer 112. Also, the adhesion between the first to fourth wiring layers 121, 122, 123, and 124 can be improved, and plating for forming the first to fourth wiring layers 121, 122, 123, and 124 can be more easily performed. Meanwhile, for electrical conduction and easier connection with the fifth via layer 137, the through-glass vias of the second via layer 132 may be filled only by plating without plugging, similar to the through-glass vias of the first via layer 131.

[0061] The other contents are substantially the same as those described in the printed circuit board 100A according to the above example and the printed circuit board 500A according to the modified example, and therefore, a duplicated description will be omitted.

[0062] 8a to 8h are cross-sectional views illustrating steps of a manufacturing method for the printed circuit board of FIG.

[0063] 8a and 8b, as described above with reference to Fig. 5a and 5b, a glass layer 111 is prepared. Next, first to fourth blind cavities C1, C2, C3, and C4, a through cavity H, and first and second through holes 131v and 132v are formed in the glass layer 111.

[0064] 8c, first and second via layers 131 and 132 are formed in the glass layer 111. The first and second via layers 131 and 132 may be formed by filling the first and second through holes 131v and 132v with a metal material using a plating process.

[0065] 8d, an insulating material 170 is formed. For example, the insulating material 170 is coated on the upper and lower surfaces of the glass layer 111 and the bottom surfaces of the first to fourth blind cavities C1, C2, C3, and C4.

[0066] 8e, the first to fourth wiring layers 121, 122, 123, 124 and the fifth via layer 137 are formed on the insulating material 170. The first to fourth wiring layers 121, 122, 123, 124 and the fifth via layer 137 may be formed by a plating process, for example, using AP (Additive Process), SAP (Semi AP), MSAP (Modified SAP), TT (Tenting), etc.

[0067] 8f to 8h, as described above with reference to FIGS. 5e to 5g, the first to fourth passive elements 151, 152, 153, and 154 are arranged in the first to fourth blind cavities C1, C2, C3, and C4, respectively. Next, the electronic component 155 is arranged in the through cavity H. Next, the insulating layer 112 is formed. Next, the fifth and sixth wiring layers 125 and 126 and the third and fourth via layers 133 and 134 are formed in the insulating layer 112.

[0068] Through a series of processes, the printed circuit board 100B according to the above-mentioned embodiment can be manufactured, and the other repeated explanations will be omitted.

[0069] FIG. 9 is a cross-sectional view that shows a schematic diagram of another example of the printed circuit board, and FIG. 10 is a cross-sectional view that shows a schematic diagram of a modified example of the printed circuit board of FIG.

[0070] With reference to the drawings, in the printed circuit board 100C according to another example and the printed circuit board 500C according to the modified example, in the printed circuit board 100B according to another example and the printed circuit board 500B according to the modified example described above, the insulating material 170 can extend onto each of the wall surfaces of the first to fourth blind cavities C1, C2, C3, C4 and the through cavity H. This can protect each of the wall surfaces of the first to fourth blind cavities C1, C2, C3, C4 and the through cavity H, and can further improve the adhesion with the insulating layer 112.

[0071] The other contents are substantially the same as those described in the above-mentioned printed circuit board 100A according to one example and the printed circuit board 500A according to a modified example, as well as the above-mentioned printed circuit board 100B according to another example and the printed circuit board 500B according to a modified example, so duplicated explanations will be omitted.

[0072] 11a to 11h are cross-sectional views illustrating steps of a manufacturing method for the printed circuit board of FIG.

[0073] 11a to 11c, a glass layer 111 is prepared as described above with reference to FIGS. 5a, 5b, and 8a to 8c. Next, first to fourth blind cavities C1, C2, C3, and C4, a through cavity H, and first and second through holes 131v and 132v are formed in the glass layer 111. Next, first and second via layers 131 and 132 are formed in the glass layer 111.

[0074] 11d, an insulating material 170 is formed. For example, the insulating material 170 is coated on the upper and lower surfaces of the glass layer 111, the bottom and wall surfaces of the first to fourth blind cavities C1, C2, C3, and C4, and the wall surface of the through cavity H.

[0075] 11e to 11h, as described above with reference to FIGS. 5e to 5g and 8e to 8h, the first to fourth wiring layers 121, 122, 123, 124 and the fifth via layer 137 are formed in the insulating material 170. Next, the first to fourth passive elements 151, 152, 153, 154 are arranged in the first to fourth blind cavities C1, C2, C3, C4, respectively. Next, the electronic component 155 is arranged in the through cavity H. Next, the insulating layer 112 is formed. Next, the fifth and sixth wiring layers 125, 126 and the third and fourth via layers 133, 134 are formed in the insulating layer 112.

[0076] Through a series of processes, the printed circuit board 100C according to the above-mentioned embodiment can be manufactured, and the other repeated explanations will be omitted.

[0077] In the present invention, the term "cover" can include not only the case of covering entirely, but also the case of covering at least a part, and further, can include not only the case of covering directly, but also the case of covering indirectly. Furthermore, the term "fill" can include not only the case of filling completely, but also the case of filling almost entirely, for example, the case where some gaps or voids are present.

[0078] In the present invention, the meaning of "on a cross section" can mean the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is viewed in a side view, and the meaning of "on a plane" can mean the planar shape when an object is cut horizontally, or the planar shape when an object is viewed in a top view or a bottom view.

[0079] In the present invention, the "thickness, width, length, depth" and the like can be measured with a scanning microscope or optical microscope based on a cross section obtained by polishing or cutting the printed circuit board. The cut section can be a vertical section or a horizontal section, and each value can be measured based on the required cut section. If the value is not constant, the value can be determined by averaging the values ​​measured at any five points. The width of the upper end and / or lower end of the via or cavity can be measured on a cross section cut along the central axis of the via in the thickness direction of the board. The depth of the via or cavity can be measured as the distance from the upper end to the lower end of each object on a cross section cut along the central axis of each object in the thickness direction of the board.

[0080] In the present invention, for convenience, terms such as "lower side, lower part, bottom surface" are used to mean a downward direction based on a cross section of the drawing, and terms such as "upper side, upper part, top surface" are used to mean the opposite direction. Also, terms such as "side, side surface" are used to mean a direction perpendicular to the top and bottom surfaces. The thickness direction is used to mean a downward and / or upward direction based on a cross section of the drawing, just like terms such as "lower side, lower part, bottom surface, upper side, upper part, top surface", etc. However, these are definitions of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of such directions, and the concepts of up / down can be changed at any time.

[0081] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0082] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0083] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0084] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060:Antenna 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140: Speaker 100A, 100B, 100C, 500A, 500B, 500C: Printed circuit boards 111: Glass layer 112: Insulating layer 113, 114: Build-up insulating layer 121, 122, 123, 124, 125, 126: Wiring layer 127, 128: Build-up wiring layers 131, 132, 133, 134, 137: Via layers 131v, 132v: Through hole 135, 136: Build-up via layer 141, 142: resist layer 151, 152, 153, 154: Passive elements 155: Electronic parts C1, C2, C3, C4: Blind cavity H: Through cavity p: Connection pad v: through silicon via P: External electrode 200: Semiconductor chips 160, 210: Electrically connected metal 310: Tape

Claims

1. A glass layer; a plurality of blind cavities each penetrating a portion of the glass layer from an upper surface or a lower surface of the glass layer; a plurality of passive elements disposed in the blind cavities, respectively; an insulating layer covering the glass layer and at least a portion of each of the plurality of passive elements and filling at least a portion of each of the plurality of blind cavities; At least two of the blind cavities have different depths from one another.

2. a through cavity extending between an upper surface and a lower surface of the glass layer; an electronic component disposed in the through cavity, The printed circuit board of claim 1 , wherein the insulating layer further covers the electronic component and further fills at least a portion of the through cavity.

3. The printed circuit board of claim 2 , wherein the electronic component is thicker than each of the plurality of passive elements.

4. each of the plurality of passive elements includes a silicon capacitor; The printed circuit board of claim 3 , wherein the electronic component comprises a ceramic capacitor.

5. the plurality of blind cavities include a first blind cavity and a second blind cavity each penetrating a portion of the glass layer from an upper surface of the glass layer, and a third blind cavity and a fourth blind cavity each penetrating a portion of the glass layer from a lower surface of the glass layer; 3. The printed circuit board of claim 2, wherein the plurality of passive elements include a first passive element to a fourth passive element disposed in the first blind cavity to the fourth blind cavity, respectively.

6. Based on the thickness direction, the first blind cavity and the third blind cavity at least partially overlap each other; The printed circuit board of claim 5 , wherein the second blind cavity and the fourth blind cavity at least partially overlap each other.

7. a first wiring layer disposed on bottom surfaces of the first blind cavity and the second blind cavity; a second wiring layer disposed on bottom surfaces of the third blind cavity and the fourth blind cavity; a third wiring layer and a fourth wiring layer disposed on an upper surface and a lower surface of the glass layer, respectively; a fifth wiring layer and a sixth wiring layer disposed on an upper surface and a lower surface of the insulating layer, respectively; a first via layer penetrating the glass layer between the first blind cavity and the third blind cavity and between the second blind cavity and the fourth blind cavity, and connecting at least a portion of the first wiring layer and the second wiring layer to each other; a second via layer that penetrates between the upper surface and the lower surface of the glass layer and connects at least a portion of the third wiring layer and the fourth wiring layer to each other; a third via layer penetrating a portion of an upper side of the insulating layer and connecting at least a portion of the third wiring layer and the fifth wiring layer to each other; The printed circuit board according to claim 6 , further comprising: a fourth via layer penetrating a portion of a lower side of the insulating layer and connecting at least a portion of the fourth wiring layer and the sixth wiring layer to each other.

8. each of the first passive element to the fourth passive element includes a through silicon via; 8. The printed circuit board of claim 7, wherein each of the through silicon vias of the first passive element to the fourth passive element is connected to at least a portion of each of the first wiring layer and the second wiring layer via a first electrically connecting metal.

9. an insulating material disposed between each of the first wiring layer to the fourth wiring layer and the glass layer; The printed circuit board of claim 7, further comprising a fifth via layer that penetrates the insulating material and connects the first wiring layer to the fourth wiring layer and at least a portion of each of the first via layer and the second via layer to each other.

10. 10. The printed circuit board of claim 9, wherein the insulating material is disposed to extend on each of the wall surfaces of the first blind cavity to the fourth blind cavity and the through cavity.

11. a first build-up insulating layer and a second build-up insulating layer disposed on an upper surface and a lower surface of the insulating layer, respectively; a first build-up wiring layer disposed on an upper surface of the first build-up insulating layer; a second build-up wiring layer disposed on a lower surface of the second build-up insulating layer; a first build-up via layer penetrating the first build-up insulating layer and connecting at least a portion of the fifth wiring layer and the first build-up wiring layer to each other; a second build-up via layer penetrating the second build-up insulating layer and connecting at least a portion of the sixth wiring layer and the second build-up wiring layer to each other; a first resist layer disposed on an upper surface of the first build-up insulating layer and covering at least a portion of the first build-up wiring layer; a second resist layer disposed on a lower surface of the second build-up insulating layer and covering at least a portion of the second build-up wiring layer; The printed circuit board of claim 7 , further comprising: a semiconductor chip disposed on the first resist layer and connected to the first build-up wiring layer via a second electrically connecting metal.

12. The printed circuit board of claim 1 , wherein the glass layer comprises plate glass.

13. A glass layer; A blind cavity penetrating a portion of the glass layer from an upper surface or a lower surface of the glass layer; a through cavity extending between an upper surface and a lower surface of the glass layer; a passive element disposed in the blind cavity; an electronic component disposed in the through cavity; an insulating layer covering the glass layer, at least a portion of each of the passive elements and the electronic components, and filling at least a portion of each of the blind cavities and the through cavities.

14. the passive element includes a silicon capacitor; The printed circuit board of claim 13 , wherein the electronic component comprises a ceramic capacitor.

15. a first wiring layer disposed on a bottom surface of the blind cavity; a third wiring layer and a fourth wiring layer disposed on an upper surface and a lower surface of the glass layer, respectively; a first build-up insulating layer and a second build-up insulating layer disposed on an upper surface and a lower surface of the insulating layer, respectively; a first build-up wiring layer disposed on an upper surface of the first build-up insulating layer; a second build-up wiring layer disposed on a lower surface of the second build-up insulating layer; a first resist layer disposed on an upper surface of the first build-up insulating layer and covering at least a portion of the first build-up wiring layer; a second resist layer disposed on a lower surface of the second build-up insulating layer and covering at least a portion of the second build-up wiring layer; The printed circuit board of claim 14 , further comprising: a semiconductor chip disposed on the first resist layer and connected to the first build-up wiring layer via an electrical connection metal.

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