New 3D NAND memory device and method for forming the same

Abstract

To provide a 3D-NAND memory devices.SOLUTION: A memory device includes: a substrate; a bottom selection gate (BSG) disposed on the substrate; a plurality of word lines installed on the BSG having a stair step configuration; and a plurality of insulation layers disposed among the substrate, the BSG, and the plurality of word lines. In the memory device to be disclosed, one or a plurality of first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to partition the BSG into a plurality of sub-BSGs. In addition, one or a plurality of common source regions are formed on the substrate and extend in a length direction of the substrate. The one or the plurality of common source regions further extend through the BSG, the plurality of word lines, and the plurality of insulation layers.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have turned to techniques for stacking multiple planes of memory cells to achieve greater storage capacity while achieving lower cost per bit. [Background technology]

[0002] 3D-NAND memory devices are exemplary devices that stack multiple planes of memory cells to achieve higher storage capacity and lower cost per bit. As 3D NAND technology transitions toward higher density and capacity, especially from 64L architecture to 128L architecture, the number of word line layers (or gate control layers) in the vertical direction perpendicular to the substrate has increased significantly. As the number of word line layers increases, the block size of 3D-NAND memory devices increases dramatically, which causes increased read and erase times, increased data transfer times, and reduced storage efficiency. Summary of the Invention [Means for solving the problem]

[0003] The inventive concepts relate to forming a 3D NAND memory device having a split block structure and a method for performing partial block erase based on the split block structure.

[0004] The associated 3D-NAND memory device may include a plurality of memory cell blocks or memory cell arrays. Each of the blocks may include a plurality of vertical NAND memory cell strings. Each of the vertical NAND memory cell strings may have one or more bottom select transistors (BSTs), one or more dummy BSTs, a plurality of memory cells (MCs), one or more dummy top select transistors (TSTs), and one or more TSTs, which are sequentially arranged in series on the substrate along the height direction (or Z direction) of the substrate. The source region of the bottom BST in each of the vertical NAND memory cell strings is connected to a common source line (CSL), and the drain region of the top TST in each of the vertical NAND memory cell strings is connected to a bit line. In the associated 3D-NAND memory device, the vertical NAND memory cell strings of the same block may share a bottom select gate (BSG). Thus, the shared BSG simultaneously controls all the BSTs of the vertical NAND memory cell strings in the block during operation of the associated 3D-NAND memory device, such as erasing the associated 3D-NAND memory device. As related 3D-NAND memory devices transition to higher capacities with increased block sizes, the shared BSG may induce longer erase times, longer data transfer times, and lower storage efficiency.

[0005] In the disclosed 3D-NAND memory device, each of the blocks can be partitioned into multiple sub-blocks by dividing a shared BSG into multiple sub-BSGs via one or more first dielectric grooves. Thus, each of the sub-blocks has a respective sub-BSG, and each of the sub-blocks can be individually operated via controlling the respective sub-BSGs. By introducing such a divided BSG structure, the disclosed 3D-NAND memory device can effectively reduce the parasitic capacitance and coupling effect between the BSG and the adjacent dielectric layer, and significantly improve the Vt performance of the bottom select transistor (BST). In addition, the erase time and data transfer time can be significantly reduced, and the data storage efficiency can also be improved.

[0006] In the disclosed 3D-NAND memory device, each of the sub-blocks can also have a respective sub-TSG by dividing the shared / common TSG into multiple sub-top select gates (sub-TSGs) through one or more second dielectric grooves. Each of the sub-TSGs can control the respective sub-block during read / programming operations. In some embodiments, the first and second dielectric grooves can be formed through the same reticle set so that manufacturing costs can be reduced.

[0007] According to one aspect of the disclosure, a memory device is provided. The memory device may include a substrate, a bottom select gate (BSG) disposed on the substrate, a plurality of word lines disposed on the BSG having a staircase configuration, and a top select gate (TSG) disposed on the plurality of word lines. The memory device also includes a plurality of insulating layers disposed between the substrate, the BSG, the plurality of word lines, and the TSG. In the disclosed memory device, one or more first dielectric grooves are formed in the BSG and extend along the length of the substrate to partition the BSG into a plurality of sub-BSGs.

[0008] In addition, one or more second dielectric trenches are formed in the TSG and extend along the length of the substrate (X-direction) to partition the TSG into a number of sub-TSGs. The memory device further includes one or more common source regions formed on the substrate and extending along the length of the substrate. Each of the one or more common source regions extends through the BSG, the word lines, the TSG, and the insulating layers and is electrically coupled to the substrate via a respective doped region. The one or more common source regions, the first dielectric trench, and the second dielectric trench further extend parallel to one another along the length of the substrate.

[0009] In some embodiments, the first and second dielectric trenches are aligned with each other across the width of the substrate (Y direction) and are separated by a number of word lines.

[0010] The memory device also includes a plurality of channel structures formed on the substrate along a height direction (Z direction) of the substrate perpendicular to the substrate. Each of the plurality of channel structures is electrically coupled to the substrate via a respective bottom channel contact that passes through the BSG, the plurality of word lines, the TSG, and the plurality of insulating layers and extends into the substrate. Each of the plurality of channel structures further includes a channel layer, a tunnel layer, a charge trapping layer, and a barrier layer.

[0011] The memory device also includes a plurality of dummy channel structures formed along a height of the substrate, the plurality of dummy channel structures extending into the substrate through the BSG, the plurality of wordlines, and the plurality of insulating layers.

[0012] The memory device also includes a plurality of memory cell strings, each of which includes a respective channel structure, a respective sub-BSG, a plurality of word lines, a respective sub-TSG, and a plurality of insulating layers separating the respective sub-BSG, the plurality of word lines, and the respective sub-TSG from one another.

[0013] The memory device also includes a plurality of memory cell sub-blocks, each of which includes a respective plurality of memory cell strings connected to the same sub-BSG and the same sub-TSG, and each of which is individually operated.

[0014] The memory device may further include a plurality of dummy channel structures formed along a height of the substrate, the plurality of dummy channel structures extending into the substrate through the BSG, the plurality of wordlines, the TSG, and the plurality of insulating layers.

[0015] In some embodiments, the one or more first dielectric trenches and the one or more common source regions are alternatively arranged across the width of the substrate such that multiple channel structures are disposed therebetween.

[0016] In some embodiments, the memory device further includes one or more dummy BSGs formed between the plurality of wordlines and the BSG, partitioned into a plurality of dummy sub-BSGs by one or more first dielectric trenches, and separated from the plurality of wordlines and the BSG by a plurality of insulating layers.

[0017] In some embodiments, the memory device further includes one or more dummy TSGs formed between the multiple wordlines and the TSG, partitioned into multiple dummy sub-TSGs by one or more second dielectric trenches, and separated from the multiple wordlines and the TSGs by multiple insulating layers.

[0018] According to one aspect of the present disclosure, a method for manufacturing a memory device is provided. In the disclosed method, a bottom select gate (BSG) layer is formed on a substrate, one or more dummy BSG layers are formed on the BSG layer, and a plurality of first insulating layers are disposed between the substrate, the BSG layer, and the one or more dummy BSG layers. Then, one or more first dielectric grooves are formed. The one or more first dielectric grooves extend through the BSG layer, the one or more dummy BSG layers, and the plurality of first insulating layers into the substrate along a length direction of the substrate. The BSG layer is partitioned into a plurality of sub-BSG layers by the one or more first dielectric grooves, and the one or more dummy BSG layers are partitioned into a plurality of dummy sub-BSG layers by the one or more first dielectric grooves.

[0019] In the disclosed method, a plurality of wordline layers are subsequently formed on the dummy BSG layer, one or more dummy top select gate (TSG) layers are formed on the plurality of wordline layers, a TSG layer is formed on the dummy BSG layer, and a plurality of second insulating layers are disposed between the dummy BSG layer, the plurality of wordline layers, the one or more dummy TSG layers, and the TSG layer. Then, one or more second dielectric grooves are formed. The second dielectric groove extends in the length direction of the substrate and passes through the one or more dummy TSG layers, the TSG layer, and a portion of the plurality of second insulating layers that separate the top wordline layer, the one or more dummy TSG layers, and the TSG layers from each other. The first dielectric groove and the second dielectric groove are aligned with each other in the width direction of the substrate and are separated by the plurality of wordline layers. The TSG layer is divided into a plurality of sub-TSG layers by the one or more second dielectric grooves, and the one or more dummy TSG layers are divided into a plurality of dummy sub-TSG layers by the one or more second dielectric grooves.

[0020] According to yet another aspect of the present disclosure, a method for erasing a 3D-NAND memory device is provided. The 3D-NAND memory device is formed on a substrate and includes a plurality of vertical NAND strings, in which a first block of the plurality of vertical NAND strings is connected to a first bottom select gate (BSG), a second block of the plurality of vertical NAND strings is connected to a second BSG, the first BSG and the second BSG are separated by a dielectric groove, and both the first block and the second block of the vertical NAND strings are connected to a plurality of shared word lines. In the disclosed method, the substrate is set to a first voltage, the first BSG is set to a second voltage lower than the first voltage, the second BSG is set to a third voltage higher than the second voltage, and one or more word lines are set to a fourth voltage equal to zero.

[0021] In some embodiments, a first block of the plurality of vertical NAND strings is erased via applying a second voltage to the first BSG, and a second block of the plurality of vertical NAND strings is not erased via applying a third voltage to the second BSG.

[0022] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard industry practice, various features have not been drawn to scale, and in fact the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. [Brief description of the drawings]

[0023] [Figure 1A] 1 is a cross-sectional view of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Figure 1B] FIG. 2 is a top view of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Figure 1C-1] FIG. 2 is a first cross-sectional view of a channel structure in a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Figure 1C-2]FIG. 2 is a second cross-sectional view of a channel structure in a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Figure 1D-1] FIG. 2 is a first top view of a channel structure in a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Figure 1D-2] FIG. 2 is a second top view of a channel structure in a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Figure 1E] FIG. 2 is an equivalent circuit diagram of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Diagram 2] FIG. 1 is a schematic perspective view of a 3D-NAND memory device in three dimensions, according to an exemplary embodiment of the present disclosure. [Figure 3A] 1 is a cross-sectional view of a related 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Figure 3B] FIG. 2 is an equivalent circuit diagram of a related 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Figure 4A] FIG. 1 is a schematic diagram of operational parameters for erasing an associated 3D-NAND memory device, according to an exemplary embodiment of the present disclosure. [Figure 4B] FIG. 13 is a schematic diagram of another operational parameter for erasing a 3D-NAND memory device, according to an exemplary embodiment of the present disclosure. [Figure 5A] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 5B] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 5C] 1A-1D are top view diagrams of intermediate steps in manufacturing a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 6] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 7A]1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 7B] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 7C] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 7D] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 7E] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 7F] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 8A] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 8B] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 8C] 1A-1D are top view diagrams of intermediate steps in manufacturing a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 9A] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 9B] 1A-1D are top view diagrams of intermediate steps in manufacturing a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 10A] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 10B] 1A-1D are top view diagrams of intermediate steps in manufacturing a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 11A]1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 11B] 1A-1D are top view diagrams of intermediate steps in manufacturing a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 11C] 1A-1D are top view diagrams of intermediate steps in manufacturing a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 11D] 1A-1D are cross-sectional views of intermediate steps in fabricating a 3D-NAND memory device according to exemplary embodiments of the present disclosure. [Figure 12] 1 is a flowchart of a process for manufacturing a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first feature on or in contact with a second feature may include embodiments in which the first and second features are formed and are in direct contact with each other, as well as embodiments in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact with each other. In addition, the disclosure may repeat reference numbers and / or letters in the various examples. This repetition is for simplicity and clarity and does not inherently describe a relationship between the various embodiments and / or configurations described.

[0025] Additionally, spatial terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to facilitate description to describe the relationship of one element or feature to another element or feature as illustrated. The spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatial descriptors used herein may be similarly interpreted accordingly.

[0026] Figure 1A is a cross-sectional view of a 3D-NAND memory device 100, and Figure 1B is a top view of the 3D-NAND memory device 100, where the cross-sectional view of the 3D-NAND memory device 100 in Figure 1A is taken from line A-A' along the Z direction (i.e., height direction) of the substrate in Figure 1B. The dashed line in Figure 1B indicates a perspective view.

[0027] As shown in FIG. 1A, memory device 100 may have a substrate 10 made of silicon, a high voltage P-type well (HVPW) 14 formed on top of substrate 10, and a deep N-type well 12 disposed below the HVPW. HVPW 14 extends from a top surface of substrate 10 into the substrate and has a depth of 0.5 μm to 5 μm according to design requirements. HVPW 14 may have a top and a bottom. The top (not shown) of HVPW 14 is flush with the top surface of substrate 10 and has a depth of 10e11 cm. -3 From 10e14cm -3 The top of the HVPW 14 forms the array (i.e., memory cell area) P-well. The array P-well is also known as the "active tub" because a voltage is applied to the tub during erasing or programming the memory devices. The top may also be configured to create bipolar junction transistor (BJT) devices in the periphery occupied by the control circuitry. The bottom of the HVPW 14 (not shown) is formed below the top and is 10e11 cm -3From 10e14cm -3 The bottom is doped with phosphorus at a dopant concentration of up to 1000 .mu.m. The bottom creates a deep "N-tub" that helps isolate the array P-wells (i.e., the top) from the peripheral P-wells. The bottom can also be configured to create BJT devices in the periphery.

[0028] The deep N-type well 12 shown in FIG. -3 From 10e14cm -3 The HVPW 14 may be doped via high energy implantation with phosphorus at a dopant concentration of up to 1000 .mu.m. The deep N-type well 12 is formed below the HVPW 14 and extends into the substrate, having a depth of 0.1 to 1 .mu.m according to design requirements. In some embodiments, the deep N-type well 12 may surround the HVPW 14, isolating it from adjacent components.

[0029] 1A, the memory device 100 may also have one or more P+ regions 24a and 24b formed in the HVPW 14. The P+ regions extend from the top surface of the substrate 10 into the substrate and have a depth of 0.01 μm to 0.2 μm. -3 From 10e18cm -3 The P+ regions may be doped with boron at a dopant concentration of up to 1000 .mu.m. In a subsequent fabrication step, a respective array contact may be formed on each of the P+ regions, the P+ regions configured to reduce resistance between the array contacts and the HVPW.

[0030] Similarly, one or more N+ regions 18 and 22 may be formed in the substrate 10. The N+ regions 18 and 22 extend from the top surface of the substrate into the substrate and have a depth of 0.01 μm to 0.2 μm. The N+ regions may have a depth of 10e14 cm -3 From 10e18cm -3The N+ region may be doped with phosphorus at a dopant concentration of up to 1000 .mu.m. One or more substrate contacts (not shown) may be formed over the N+ region in a subsequent fabrication step, the N+ region being configured to reduce resistance between the substrate contacts and the substrate.

[0031] The disclosed memory device 100 may also include one or more high voltage N-type wells (HVNWs). Each of the N+ regions may be surrounded by a respective high voltage N-type well (HVNW). For example, N+ region 22 is surrounded by HVNW 20, and N+ region 18 is surrounded by HVNW 16. The HVNW may have a width of 10e11 cm. -3 From 10e14cm -3 The HVNW may be formed by doping the substrate with phosphorus at a dopant concentration of up to 1000 .mu.m. The HVNW extends from the top surface of the substrate and into the substrate 10 to a depth of 0.1 to 1 μm. The HVNW is configured to isolate the N+ region from adjacent components.

[0032] 1A, a bottom select gate (BSG) 62p, one or more dummy BSGs (or bottom dummy word lines such as 62n-62o), a plurality of word lines (e.g., 62d-62m), one or more dummy top select gates (TSGs) (or top dummy word lines such as 62b-62c), and a TSG 62a are sequentially disposed on the substrate. In addition, a plurality of insulating layers, such as seventeen insulating layers 60a-60q, are disposed between the substrate 10, the BSGs, the dummy BSGs, the word lines, the dummy TSGs, and the TSGs to separate the substrate 10, the BSGs, the dummy BSGs, the word lines, the dummy TSGs, and the TSGs from each other.

[0033] In some embodiments, the insulating layers 60, BSG, dummy BSG, word lines, dummy TSG, and TSG are stacked alternately on the substrate 10 in a staircase configuration, in which the TSG 62a and the top insulating layer 60a have the smallest length and the BSG 62p and the bottom insulating layer 60q have the largest length.

[0034] 1A is merely an example 3D-NAND memory device 100, and it should be understood that the 3D-NAND memory device 100 can include any number of BSGs, dummy BSGs, word lines, dummy TSGs, and TSGs. For example, the 3D-NAND memory device 100 can have 3 BSGs, 3 TSGs, and 64 word lines.

[0035] In some embodiments (i.e., gate-last formation techniques), the BSG 62p, dummy BSGs 62n-62o, word lines 62d-62m, dummy TSGs 62b-62c, and TSGs 62a shown in FIG. 1A are first formed using a sacrificial layer (i.e., SiN). The sacrificial layer may be removed and replaced with a high-K layer, an adhesive layer, and one or more metal layers. The high-K layer may be made of aluminum oxide (Al2O3) and / or hafnium oxide (HfO2) and / or tantalum oxide (Ta2O5), and / or high-K (dielectric constant). The metal layer may be made of tungsten (W), cobalt (Co), for example. The word lines may have a thickness in the range of 10 nm to 100 nm according to requirements such as product specifications, device operation, and manufacturing capabilities. In one embodiment of FIG. 1, the insulating layer 60 may be made of SiO2 and may have a thickness of 5 nm to 50 nm.

[0036] Still referring to FIG. 1A, one or more first dielectric grooves (or first grooves), such as two first grooves 26 and 28, are formed in one or more BSGs (e.g., 62p) and one or more dummy BSGs (e.g., 62n-62o). The first grooves 26 and 28 extend in the X-direction (i.e., lengthwise direction) of the substrate 10 to partition the layer of BSGs 62p and dummy BSGs 62n-62o into a plurality of sub-BSGs and sub-dummy BSGs, or, for example, into a plurality of cell strings. For example, three sub-BSGs 62p-1, 62p-2, and 62p-3 are included in the embodiment shown in FIG. 1A. In addition, one or more second dielectric grooves (or second grooves), such as two second grooves 56 and 58 shown in FIG. 1A, are formed in one or more TSGs (e.g., 62a) and one or more dummy TSGs (e.g., 62b-62c). The second trench also extends in the X-direction (length direction) of the substrate 10 to partition the TSG 62a and the dummy TSGs 62b-62c into a plurality of sub-TSGs and sub-dummy TSGs. For example, a sub-TSG 62a-1 and two sub-dummy TSGs 62b-1 and 62c-1 are shown in FIG. 1A. In some embodiments, the first trench and the second trench are optically aligned with each other in the Y-direction (i.e., width direction, top view) of the substrate 10 and are separated by a plurality of word lines 62d-62m. In some embodiments, the first and second trenches can have a CD of 50 nm to 150 nm and are filled with SiO2, SiON, SiOCN, or other suitable dielectric material. In some embodiments, the first trenches 26 and 28 can extend into the HVPW 14 and have a depth between 10 nm and 100 nm.

[0037] By introducing the first and second grooves into the memory device 100, the BSG and TSG are partitioned into a plurality of sub-BSGs and sub-TSGs. The sub-BSGs and sub-TSGs can divide the memory device 100 into a plurality of sub-blocks, or, for example, a plurality of cell strings. Each of the sub-blocks has a respective sub-BSG and a respective sub-TSG. Each of the sub-blocks can be individually operated through controlling the respective sub-BSG and the respective sub-TSG. Accordingly, the disclosed 3D-NAND memory device 100 can precisely control the desired sub-block / array area to effectively reduce the programming time, the reading time, the erasing time and the data transfer time, and to significantly improve the data storage efficiency.

[0038] Still referring to FIG. 1A, one or more common source regions (CSR), such as one common source region 52, are formed on the substrate and extend in the X-direction (length direction) of the substrate. The common source region 52 is electrically coupled to the substrate 10 through the BSG 62p, the dummy BSG 62n-62o, the plurality of word lines 62d-62m, the dummy TSG 62b-62c, the TSG 62a, and the plurality of insulating layers 60 via the doped region 54. The common source region 52, the first trenches 26 and 28, and the second trenches 56 and 58 extend parallel to each other in the X-direction (length direction) of the substrate 10. The common source region 52 can have sides and a bottom that are electrically coupled to the doped region 54. Dielectric spacers 68 are formed along the sides and in direct contact with the word lines 62d-62m and the insulating layer 60. A conductive layer 70 is formed on the doped region 54 along the dielectric spacers 68. The common source region 52 further includes a top contact 64 formed on a conductive layer 70 along a dielectric spacer 68. The doped region 54 may be N-type doped via one or more ion implantation processes. In one embodiment of FIG. 1A, the dielectric spacer 68 is made of SiO2, the conductive layer 70 is made of polysilicon, and the top contact 64 is made of tungsten.

[0039] In some embodiments, the common source region 52 may have a continuous configuration to extend along the X-direction (length direction) of the substrate. In some embodiments, the common source region 52 may be partitioned into two or more sub-CSRs. The sub-CSRs are aligned with each other in the X-direction of the substrate.

[0040] In the 3D-NAND memory device 100, a plurality of channel structures are formed on the substrate 10 along the Z-direction (or height direction) of the substrate. As shown in FIG. 1A, five contact structures 30, 32, 34, 36, and 38 are included. Each of the channel structures is electrically coupled to the substrate via a respective bottom channel contact that passes through the BSG, dummy BSG, word line, dummy TSG, TSG, and insulating layer and extends into the substrate. For example, the contact structure 30 is electrically coupled to the substrate via the bottom contact 202 shown in FIG. 1C. In addition, each of the channel structures further includes a channel layer 206, a tunnel layer 208, a charge trapping layer 210, and a barrier layer 212, which are shown in detail in FIG. 1C and FIG. 1D.

[0041] The memory device 100 may further include a number of dummy channel structures formed along the Z-direction (height direction) of the substrate. For example, six dummy channel structures 40, 42, 44, 46, 48, and 50 are included in the memory device 100. In some embodiments, the memory device 100 may be divided into three regions, namely, two staircase regions 100A and 100C and one core region 100B. As shown, the staircase regions 100A and 100C may be arranged on one or both sides of the central core region 100B of the memory device 100. The staircase regions 100A and 100C do not include a channel structure, and the core region 100B includes a number of channel structures. In some embodiments, the dummy channel structures are formed only in the staircase regions 100A and 100C and extend through the BSG, dummy BSG, word lines, and insulating layers into the substrate. In other embodiments, the dummy channel structure may be formed in both the staircase regions 100A and 100C and in the core region 100B. When the dummy channel structure is formed in the core region 100B, the dummy channel structure extends through the TSG, dummy TSG, word lines, dummy BSG, and BSG into the substrate. The dummy channel structure serves as a support component to support the staircase region and / or the core region when the sacrificial word lines are removed. In one embodiment of FIG. 1A, the dummy channel structure is made of SiO2.

[0042] FIG. 1B is a top view of a 3D NAND memory device 100 according to some embodiments of the present disclosure. As shown in FIG. 1B, the memory device 100 may have three common source regions 52a-52c extending along the X-direction (length direction) of the substrate 10. The common source regions 52b and 52c are disposed at two boundaries of the memory device 100 having a continuous configuration. The common source regions 52b and 52c may serve as common source regions for the memory device 100, further isolating the memory device 100 from adjacent components. In some embodiments, the memory device 100 is one of the memory cell blocks of a 3D-NAND chip (not shown). Thus, the common source regions 52b and 52c isolate the memory device 100 (or the memory cell block 100) from adjacent memory cell blocks of the 3D-NAND chip. The common source region 52a is disposed at a central position of the memory device 100. The common source region 5a is partitioned into two or more sub-CSRs by one or more "H-cuts". As shown in FIG. 1B, CRS 52a is divided by an H-cut 72 into two sub-CSRs 52a-1 and 52a-2.

[0043] Still referring to FIG. 1B, the first grooves 26 and 28 and the second grooves 56 and 58 are optionally aligned with each other in the Y direction (width direction) of the substrate 10. The first groove and the second groove are disposed between two adjacent common source regions. For example, the first groove 26 and the second groove 56 are aligned and disposed between the common source region 52a and the common source region 52b. In addition, the dummy channel structures 40, 42 and 44 are disposed in the staircase region 100A, and the dummy structures 46, 48 and 50 are disposed in the staircase region 100C. A plurality of channel structures, such as the channel structures 30 and 32, are disposed in the core region 100B.

[0044] By introducing the first / second trenches, the 3D-NAND memory device 100 (or the memory cell block 100) can be divided into multiple sub-blocks. For example, three sub-blocks SUB-BLK1-3 are formed in FIG. 1B. Each sub-block can have a respective sub-BSG and a respective sub-TSG. The sub-BSG is formed by dividing the BSG 62p into three sub-BSGs (i.e., 62p-1, 62p-2, and 62p-3) by the first trench, and the sub-TSG is formed by dividing the TSG 62a into three sub-TSGs by the second trench. It should be mentioned that the SUB-BLK2 can have two parts SUB-BLK2_1 and SUB-BLK2_2 that are electrically connected to each other via the H-cut 72. Therefore, the SUB-BLK2 can have a larger size than the SUB-BLK1 and SUB-BLK3. Without introducing the first / second grooves, memory device 100 (or memory cell block 100) has a shared BSG such as 62p and a shared TSG such as 62a.

[0045] It should be understood that FIG. 1B is merely an exemplary 3D NAND memory device 100, and the 3D NAND memory device 100 can include any number of first trenches and second trenches between two adjacent common source regions. For example, two or more first trenches or two or more second trenches can be disposed between two adjacent common source regions. The 3D NAND memory device 100 can also include any number of common source regions.

[0046] FIG. 1C-1 is a first cross-sectional view of the channel structure 30 in the 3D-NAND memory device 100, and FIG. 1D-1 is a first top view of the channel structure 30, where the cross-sectional view of FIG. 1C-1 is taken from line B-B' along the Z direction (height direction) of the substrate of FIG. 1D-1. FIG. 1C-2 is a second cross-sectional view of the channel structure 30, and FIG. 1D-2 is a second top view, where the cross-sectional view of FIG. 1C-2 is taken from line C-C' along the Z direction (height direction) of the substrate of FIG. 1D-2.

[0047] As shown in FIG. 1C-1 / FIG. 1D-1, the channel structure 30 may have a cylindrical shape with sidewalls and a bottom region. Of course, other shapes are possible. The channel structure 30 is formed along a Z direction perpendicular to the substrate 10 and is electrically coupled to the substrate 10 via a bottom channel contact 202 located at the bottom region of the channel structure. The channel structure 30 further includes a channel layer 206, a tunnel layer 208, a charge trapping layer 210, and a barrier layer 212. The barrier layer 212 is formed on the bottom channel contact 202 along the sidewalls of the channel structure 30. The barrier layer 212 is in direct contact with the word lines 62d-62m and the insulating layer 60. The charge trapping layer 210 is formed on the bottom channel contact 202 along the barrier layer 212, and the tunnel layer 208 is formed on the bottom channel contact 202 along the charge trapping layer 210. The channel layer 206 has sides formed along the tunnel layer 208 and has a T-shaped bottom extending through the bottom of the tunnel layer 208, charge trapping layer 210, and barrier layer 212 located on the bottom channel contact 202. The T-shaped bottom of the channel layer 206 is further located on the bottom contact 206 and in direct contact with the bottom channel contact 202. In addition, the tunnel layer 208, charge trapping layer 210, and barrier layer 212 can form an “L-foot” configuration in the channel structure 30. The L-foot configuration can include sides formed along the sidewalls of the channel structure and a bottom on the bottom channel contact 202.

[0048] The channel structure 30 may also have a channel insulating layer 204 formed along the channel layer 206 to fill the channel structure 30. The channel insulating layer 204 may have a T-shaped bottom that extends through the bottom of the channel layer 206, the tunnel layer 208, the charge trapping layer 210, and the barrier layer 212 to land on the channel layer 206. In some embodiments, the channel insulating layer 204 may include a void located in a central position of the channel insulating layer 204. The channel structure 30 may further include a top channel contact 214 formed along the channel insulating layer 204 and in direct contact with the channel layer 206. The top channel contact 214 is located on the TSG 62a to prevent electrical interference between the top channel contact 214 and the TSG 62a. In the channel structure 30, a gate dielectric layer 216 is further formed between the BSG 62p and the bottom channel contact 202. A gate dielectric layer 216 may be disposed between insulating layers 60p and 60q and has an annular shape to surround bottom channel contact 202.

[0049] In the embodiment of FIG. 1C-1 / FIG. 1D-1, the barrier layer 212 is made of SiO2. In another embodiment, the barrier layer 212 can include multiple layers, such as SiO2 and Al2O3. In the embodiment of FIG. 1C-1 / FIG. 1D-1, the charge trapping layer 210 is made of SiN. In another embodiment, the charge trapping layer 210 can include a multi-layer configuration, such as a SiN / SiON / SiN multi-layer configuration. In some embodiments, the tunnel layer 208 can include a multi-layer configuration, such as a SiO / SiON / SiO multi-layer configuration. In the embodiment of FIG. 1C-1 / FIG. 1D-1, the channel layer 206 is made of polysilicon via a furnace low pressure chemical vapor deposition (CVD) process. The channel insulating layer 204 can be made of SiO2, and the top and bottom channel contacts can be made of polysilicon.

[0050] As shown in Figure 1C-1 / 1D-1, the channel structure 30 can have a cylindrical shape. However, the present disclosure is not limited thereto, and the channel structure 30 can be formed in other shapes, such as a square pillar shape, an oval pillar shape, or any other suitable shape.

[0051] 1C-2 / 1D-2 provide another configuration for disposing the top channel contact 214 in the channel structure 30. As shown in FIG. 1C-2 / 1D-2, the top channel contact 214 is formed on the channel layer 206, the tunnel layer 208, the charge trapping layer 210, the barrier layer 212, and the channel insulating layer 204 along the insulating layer 60a. The bottom surface of the top channel contact 214 is in direct contact with the top surface of the channel layer 206. Compared with the top channel contact 214 in FIG. 1C-1 / 1D-1, the top channel contact 214 in FIG. 1C-2 / 1D-2 has a larger size, which provides a larger processing window for disposing a via to be formed later on the top channel contact.

[0052] FIG. 1E is an equivalent circuit diagram of a 3D NAND memory device according to an exemplary embodiment of the present disclosure. As shown in FIG. 1E, the circuit diagram includes a memory cell block 200 or memory cell array 200. The memory cell block 200 can include a plurality of vertical NAND memory cell strings ST0-ST17. Each of the memory cell strings can have one or more bottom select transistors (BST), one or more dummy BSTs (DUMBST), a plurality of memory cells (MC), one or more dummy top select transistors (DUMTST), and one or more TSTs. For example, the memory cell string ST0 can have a BST, two dummy BSTs (DUMBST0 and DUMBSTn), 64 memory cells MC0-MC63, two dummy TSTs (DUMTST0 and DUMTSTn), and two TSTs (TST0 and TSTn). The top end of each of the memory cell strings can be a drain region connected to a bit line (BL), and the bottom end of each of the memory cell strings can be a source region connected to a common source line (CSL). For example, memory cell string ST0 is connected to bit line BL1 through the drain region of TSTn and to CSL through the source region of BST.

[0053] The memory cell block 200 may be divided into six sub-blocks, SUB-BLK0 through SUB-BLK5, by the first and second trenches shown in FIG. 1A. Each of the sub-blocks may have a respective set of memory cell strings. For example, SUB-BLK0 may include a set of memory cell strings ST0, ST6, and ST12, and SUB-BLK1 may include another set of memory cell strings ST1, ST7, and ST13.

[0054] In a related memory cell block, such as the memory cell block 400 shown in FIG. 3B, the bottom select gates (BSGs) of each of the memory cell strings are connected to each other and shared. Similarly, the dummy BSGs of each of the memory cell strings are also connected to each other and shared. In the memory cell block 200, the bottom select gates BSGs and dummy BSGs (e.g., DUMBSG0 and DUMBSGn) can be divided into a plurality of sub-BSGs and sub-dummy BSGs by a first trench, such as 26 and 28 shown in FIG. 1A. For example, the BSGs can be divided into a plurality of sub-BSGs, from BSG0 to BSG5, by a first trench. In addition, the top select gates TSGs (e.g., TSG0 and TSGn) and dummy TSGs (e.g., DUMTSG0 and DUMTSGn) can be divided into a plurality of sub-TSGs and sub-dummy TSGs by a second trench, such as 56 and 58 shown in FIG. 1A. For example, TSG0 may be divided into multiple sub-TSGs, TSG0-0 to TSG0-5, by second grooves.

[0055] Thus, the BST, dummy BST, dummy TST, and TST in each of the sub-blocks can have respective control gates that are sub-BSG, sub-dummy BSG, sub-dummy TSG, and sub-TSG, respectively. For example, in SUB-BLK0, the BSTs of strings ST0, ST6, and ST12 have individual control gates of BSG0 formed by a first trench to separate the control gates BSG, and the TST0 of strings ST0, ST6, and ST12 have individual control gates of TSG0-0 formed by a second trench to separate the control gates TSG. Similarly, in SUB-BLK1, the BSTs of ST1, ST7, and ST13 have control gates of BSG1, and the TST0 of ST1, ST7, and ST13 have control gates of TSG0-1. Without introducing the first / second trenches, the memory cell block 200 has a shared BSG, dummy BSG, dummy TSG, and TSG. An exemplary shared BSG is shown in Figures 3A and 3B, where the BSGs of each of the memory cell strings are connected to and shared with each other.

[0056] By introducing such a split BSG structure, the disclosed 3D-NAND memory device can effectively reduce the parasitic capacitance and coupling effect between the BSG and the adjacent dielectric layer, and significantly improve the Vt performance of the bottom select transistor (BST). In addition, the split BSG structure allows erasing a specific sub-block instead of the entire block 200. Thus, the erase time and data transfer time can be significantly reduced, and the data storage efficiency can also be improved. Furthermore, the split TSG structure allows reading / programming a specific sub-block instead of the entire block 200, thereby reducing the read / programming time and improving the data transfer / storage efficiency.

[0057] In the memory cell block 200, the sub-blocks can share one or more word lines. For example, as shown in FIG. 1E, 18 MCs in six sub-blocks are connected to each other to have a common / shared word line WLn. Similarly, other MCs in all six sub-blocks can also have a common / shared word line.

[0058] Each of the sub-blocks can have one or more bit line connections. For example, in the sub-block SUB-BLK0, the memory cell string ST0 is connected to BL1, the memory cell string ST6 is connected to BL2, and the memory cell string ST12 is connected to BLn. In the disclosed memory cell block 200, all 18 memory cell strings are connected to the same CSL (or common source region).

[0059] Still referring to FIG. 1E, each of the memory cell strings may be composed of one or more sub-BSGs, one or more sub-dummy BSGs, a plurality of word lines, one or more sub-dummy TSGs, one or more sub-TSGs, and a channel structure passing through the sub-TSGs, sub-dummy TSGs, word lines, sub-dummy BSGs, and sub-BSGs, and is electrically coupled to the substrate / same common source region (i.e., CSL). For example, the memory cell string ST0 may be composed of the channel structure 30, the sub-BSG 62p-1 (i.e., BSG0 in FIG. 1E), two sub-dummy BSGs 62n-1 and 62o-1, the word lines 62d-62m, two sub-dummy TSGs 62b-1 and 62c-1, and the sub-TSG 62a-1 (i.e., TSG0-1 in FIG. 1E), which are shown in FIG. 1A. Note that TSGn is not shown in FIG. 1A. Thus, the bottom select transistor (BST) of the string ST0 may be formed by the channel structure 30 and the sub-BSG 62p-1. A memory cell such as MC63 may be formed by the channel structure 30 and the world line 62d. The top select transistor TST0 may be formed by the channel structure 30 and the sub-TSG 62a-1. The DUMTST0 may be formed by the channel structure 30 and the sub-dummy TSG 62c-1. The common source line (CSL) shown in FIG. 1E may be the common source region 52 shown in FIG. 1A.

[0060] FIG. 2 is a schematic perspective view of a 3D NAND memory device according to an exemplary embodiment of the present disclosure. As shown in FIG. 2, a plurality of dummy channel structures, such as 40, 42, 44, 46, 48, and 50, are disposed in the staircase region. A plurality of channel structures, such as 30, 38, are disposed in the core region. Two first grooves (26 and 28) and two second grooves (56 and 58) are formed along the X direction, aligned in the Y direction, and spaced apart from each other by a plurality of word lines 62d-62m. The first grooves divide the BSG 62p into a plurality of sub-BSGs and the dummy BSG (62n and 62o) into a plurality of sub-dummy BSGs. For example, three sub-BSGs 62p-1, 62p-2, and 62p-3 are included in the embodiment shown in FIG. 2. Similarly, the second trench divides the TSG 62a into a plurality of sub-TSGs and the dummy TSG (62b and 62c) into a plurality of sub-dummy TSGs. A plurality of insulating layers 60a-60q are formed between the substrate, the BSG, the dummy BSG, the word lines, the dummy TSG, and the TSG. The common source region 52 is formed along the X direction and is disposed parallel to the first and second trenches. The common source region 52 extends into the substrate 10 through the TSG, the dummy TSG, the word lines, the dummy BSG, and the BSG. The common source region 52 is divided into two sub-common source regions by the H-cut 72.

[0061] 3A is a cross-sectional view taken along the Z direction (height direction) of the substrate of a related 3D NAND memory device 300. In comparison with memory device 100, related memory device 300 does not include first trenches such as 26 and 28 shown in FIG. 1A.

[0062] FIG. 3B illustrates an equivalent circuit diagram of a related 3D NAND memory device 300. As shown in FIG. 3B, the circuit diagram includes a memory cell block or memory cell array 400. The memory cell block 400 may include six sub-blocks, SUB-BLK0 to SUB-BLK5, by second grooves, such as 56 and 58 in FIG. 3A. Similar to the memory device 100, the top select gates TSG (e.g., TSG0 and TSGn) and the dummy TSGs (e.g., DUMTSG0 and DUMTSGn) may be partitioned into multiple sub-TSGs and sub-dummy TSGs by second grooves. For example, TSG0 may be partitioned into multiple sub-TSGs, TSG0-0 to TSG0-5, by second grooves. Thus, each of the sub-blocks may have a respective sub-TSG and a respective sub-dummy TSG. For example, the sub-block SUB-BLK0 may have a sub-TSG TSG0-0, and the sub-block SUB-BLK1 may have a sub-TSG TSG0-1. The difference between the related memory device 300 and the disclosed memory device 100 is that in the related memory device 300, the BSGs or dummy BSGs (e.g., DUMBSG0 and DUMBSGn) in each of the sub-blocks are connected to and shared with each other.

[0063] 4A is a schematic diagram of operational parameters for erasing an associated 3D NAND memory device 300 according to an exemplary embodiment of the present disclosure. FIG. 4B is a schematic diagram of another operational parameter for erasing a 3D-NAND memory device 100 according to an exemplary embodiment of the present disclosure.

[0064] As shown in FIG. 4A, during erasing of the associated 3D-NAND memory device 300, the word lines controlling the memory cells (MC) are set to an operating voltage equal to zero volts (V). An input voltage applied to an HVPW, such as HVPW 14 in FIG. 3A, may be set to a first operating voltage V1. The first operating voltage V1 is positive and may have a value between 18V and 22V. An input voltage to a selected BSG of a particular sub-block, such as SUB-BLK0 in FIG. 3B, may be set to a second operating voltage V2 that may be lower than the first operating voltage but still positive. For example, the second operating voltage V2 may be in the range from zero volts to 13V. In addition, a dummy BSG in a particular sub-block may be set to a switch voltage (not shown in FIG. 4A) that is 0.5V to 2V lower than the second operating voltage V2. In some embodiments, the selected BSG and the selected dummy BSG in a particular sub-block may be set to float.

[0065] A detailed erase process can be described based on the channel structure 30 shown in Figures 1C and 1D and the memory cell string ST0 / sub-block SUB-BLK0 shown in Figures 1E and 3B. It should be mentioned again that the memory cell string ST0 can be composed of the channel structure 30 and the surrounding BSG, dummy BSG, word line, dummy TSG, and TSG shown in Figures 1C and 1D.

[0066] As shown in FIG. 1C and FIG. 1D, when a first operating voltage is applied to the HVPW 14, the first operating voltage V1 is electrically coupled to the channel layer 206 through the bottom channel contact 202. Since the word lines 62d-62m are all set to an operating voltage equal to zero volts, the channel layer 206 forms a relatively high potential with respect to the word lines. The formed high potential attracts the electrons trapped in the trapping layer 210 back to the channel layer 206. In addition, holes can be injected from the HVPW 14 / common source region 52 into the channel layer by the first operating voltage V1. The injected holes maintain a positive potential in the channel layer and can further recombine with the electrons attracted into the channel layer 206. When the electron-hole recombination is completed, the memory cell string ST0 is erased. Thus, the input voltages V1, V2 are set to zero volts.

[0067] During an erase operation, the selected BSG is set to float or to a second operating voltage V2 that allows the selected BSG to remain at a relatively lower positive voltage than the first voltage V1 applied to the HVPW 14. Such a relatively lower voltage can reduce the electric field across the gate dielectric (e.g., the gate dielectric layer 216 shown in FIG. 1C), which in turn can prevent the gate dielectric layer from collapsing. In some embodiments, the second voltage V2 applied to the selected BSG can further help generate holes via the gate-induced drain leakage (GIDL) effect and improve the flow of holes from the substrate to the top of the channel layer 206 (e.g., a location closer to the TSG).

[0068] In some embodiments, the dummy BSG is set to float or set to a switch voltage (not shown). The applied switch voltage may be gradually reduced in a direction from the BSG 62p to the word line 62m. The gradually reducing voltage on the dummy BSG in a direction from the BSG to the word line reduces the electric field between the BSG (set to a high voltage) and the word line (set to a low voltage such as zero), thereby reducing carrier generation between the BSG and the word line and eliminating erase disturb.

[0069] Since the associated memory devices 300 have a common or shared BSG, when the second voltage V2 is applied to the BSG of string ST0 / SUB-BLK0 during an erase operation, the bottom select transistors (BSTs) in the remaining 17 memory cell strings ST1-ST17 may also be influenced to turn on by the second operating voltage V2. Accordingly, an erase operation may occur in all six sub-blocks. As 3D-NAND memory devices transition to higher capacities with increased block sizes, the common / shared BSG may induce longer erase times, longer data transfer times, and lower storage efficiency.

[0070] FIG. 4B is a schematic diagram of another operating parameter for erasing the 3D NAND memory device 100. As shown in FIG. 1E, each of the sub-blocks shown in FIG. 1E may have a respective sub-BSG formed by introducing a first groove to partition the BSG. When the erase operation starts, a second voltage V2 may be applied to each sub-BSG of the selected sub-block. For example, if SUB-BLK0 is selected, the second voltage V2 may be applied to the corresponding sub-BSG BSG0. In addition, a third voltage V3 may be applied to each sub-BSG of the unselected sub-block. For example, if SUB-BLK1 is unselected, the third voltage V3 may be applied to the corresponding sub-BSG BSG1. The third voltage V3 may be close to the first voltage V1 and higher than the second voltage V2. For example, V3 may range from 18V to 25V. The third voltage V3, which is relatively high relative to the second voltage V2, can discard the holes generated from the HVPW / substrate and prevent the holes from flowing into the channel layer of the unselected sub-blocks. Thus, the erase process can occur only in the selected sub-blocks, and the erase time and data transfer time can be significantly reduced, and the data storage efficiency can also be improved.

[0071] 5A-11D are cross-sectional and top view illustrations of various intermediate steps in fabricating a 3D-NAND memory device 100 according to exemplary embodiments of the present disclosure.

[0072] FIG. 5A is a cross-sectional view taken along the Z direction (i.e., height direction) of the substrate. As shown in FIG. 5A, a plurality of doped regions 12, 14, 16, 18, 20, 22, and 24 are formed in the substrate 10 based on a photolithography process and a doping and / or ion implantation process. The doped regions in FIG. 5A may be substantially similar to the doped regions described above with reference to FIG. 1A. To form the doped regions, a pattern mask may be formed on the substrate by a photolithography process. The pattern mask exposes desired regions of the substrate that require dopants. A doping process such as an ion implantation process, in-situ doped epitaxial growth, a plasma doping process (PLAD), or other methods known in the art may be applied to transfer suitable dopants into the exposed regions of the substrate 10. The dopant concentration, doping profile, and doping depth may be controlled by adjusting the energy, angle, and dopant type of the doping process.

[0073] A bottom select gate (BSG) 62p, two dummy BSGs 62n-62o, and a plurality of first insulating layers 60n-60q may be subsequently formed on the substrate 10. The substrate 10, the BSG 62p, and the dummy BSGs 62n-62o are separated from each other by the first insulating layers 60n-60q.

[0074] The BSG 62p and the two dummy BSGs 62n-62o may be sacrificial layers made of SiN. The sacrificial layers may be removed and replaced with a high-K layer and a metal layer in a future fabrication step. The BSG 62p and the two dummy BSGs 62n-62o may have a thickness in the range of 10 nm to 100 nm. The first insulating layer may include SiO, SiCN, SiOCN, or other suitable material. The first insulating layer 60n-60q may have a thickness of 5 nm to 50 nm. Any suitable deposition process may be applied to form the BSG, the dummy BSG, and the first insulating layer, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof.

[0075] Still referring to FIG. 5A, two first grooves 26 and 28 may be formed in the BSG 62p and the dummy BSGs 62n-62o when the BSGs, the dummy BSGs and the first insulating layer are stacked on the substrate 10. The first grooves 26 and 28 extend in the X-direction (i.e., length direction) of the substrate 10 to divide the BSG 62p and the dummy BSGs 62n-62o into a plurality of sub-BSGs and sub-dummy BSGs. For example, three sub-BSGs 62p-1-62p-3 and three sub-dummy BSGs 62n-1-62n-3 are included in FIG. 5A.

[0076] The first trenches 26 and 28 can have a CD of 50 nm to 150 nm. The first trenches can be filled with SiO2, SiON, SiOCN, or other suitable dielectric material. In some embodiments, the first trenches 26 and 28 can extend into the HVPW 14 and have a depth between 10 nm and 100 nm. The first trenches can be formed by a photolithography process, a subsequent etching process, filling with a dielectric material, and then CMP (chemical mechanical polishing) when necessary. For example, a pattern mask stack can be formed on the insulating layer 60n by a photolithography process. A subsequent etching process can be introduced to etch through the insulating layer, the BSG, the dummy BSG, and further extend into the HVPW 14 to form two trench openings. The trench openings can then be filled with a dielectric material, such as SiO2, SiON, SiOCN, or other suitable material, by applying chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof. A surface planarization may be performed to remove excess dielectric material above the insulating layer 60n.

[0077] Figure 5B is a cross-sectional view taken along the X-direction (lengthwise) of the substrate, and Figure 5C is a top view showing the final structure when the first grooves 26 and 28 are formed. As shown in Figure 5B, the first grooves 26 and 28 are not visible when the cross-sectional view is made along the X-direction (lengthwise) of the substrate 10. In Figure 5C, the insulating layer 60n is shown as the top surface, and the two first grooves 26 and 28 extend along the lengthwise direction of the substrate, further dividing the substrate 10 into three equal regions.

[0078] In FIG. 6, a plurality of word lines 62d-62m, two dummy top select gates (TSGs) 62b-62c, and a TSG 62a are sequentially formed on a first insulating layer 60n. A plurality of second insulating layers 60a-60m are also deposited on the first insulating layer 60n. The world lines 62d-62m, the dummy TSGs 62b-62c, and the TSG 62a are separated from each other by the second insulating layers 60a-60m. The world lines 62d-62m, the dummy TSGs 62b-62c, and the TSG 62a are sacrificial layers made of SiN and may have a thickness in the range of 10 nm to 100 nm. The sacrificial layers may be removed and replaced with high-K layers and metal layers in a future fabrication step. The second insulating layers 60a-60m may have a thickness between 5 nm and 50 nm and may include SiO2, SiCN, SiOCN, or other suitable materials. Any suitable deposition process may be applied to form the TSG, dummy TSG, and second insulating layer, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof.

[0079] In FIG. 7A, two staircase regions 100A and 100C are formed. The formation of the two staircase regions 100A and 100C may be shown in the exemplary fabrication steps shown in FIG. 7B-FIG. 7F. As shown in FIG. 7B, a plurality of word sacrificial lines 62a-62c and a plurality of insulating layers 60a-60c may be formed and interleaved. A patterned mask stack 702 may be formed on the insulating layer 60a. The patterned mask stack 702 exposes two terminal ends of the insulating layer 60a. The mask stack 702 may include an amorphous carbon hard mask layer, a dielectric antireflective coating (DARC), a bottom antireflective coating (BARC) layer, and a photoresist layer. In some other embodiments, the mask stack 702 may be only photoresist for staircase formation. The mask stack 702 may be patterned according to any suitable technique, such as a lithographic process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), and the like.

[0080] In FIG. 7C, a first plasma etch process may be performed to remove the exposed terminations of the insulating layer 60a. The first plasma etch process may further remove portions of the underlying word lines 62a that are not protected by the mask stack 702, stopping on the insulating layer 60b with precise process control. In FIG. 7D, a trim process may be applied to remove portions of the mask stack 702 from the two ends to further expose the insulating layer 60a. The exposed portions of the insulating layer 60a may be two terminations 60a-A and 60a-B. In addition, the insulating layer 60b may have exposed terminations 60b-A and 60b-B.

[0081] In FIG. 7E, a second etching process may be performed. The second etching process may remove the exposed terminations 60a-A and 60a-B from the insulating layer 60a. By precisely controlling the second etching process via either the etching time or the end point trace, the second etching process may further remove the portions of the word line 62a under 60b-A and 60b-B and stop on the insulating layer 60b. Meanwhile, the exposed terminations 60b-A and 60b-B from the insulating layer 60b and the portions of the word line 62b under 60b-A and 60b-B may be removed simultaneously. When the second etching process is completed, two staircase regions may be formed on both sides. In FIG. 7F, a subsequent plasma ash may be applied to remove the remaining mask stack 702. Briefly, a multi-cycle trim-etch process on multiple masks (as shown in FIG. 7B-7F) may be applied to form the staircases 100A and 100C of FIG. 7A.

[0082] In FIG. 8A, two second grooves 56 and 58 may be formed in the TSG 62a and the dummy TSGs 62b-62c. The second grooves 56 and 58 extend in the X-direction (i.e., length direction) of the substrate 10 to divide the TSG 62a and the dummy TSGs 62b-62c into a plurality of sub-BSGs and a plurality of sub-dummy BSGs, respectively. For example, three sub-BSGs 62a-1, 62a-2, and 62a-3 may be included in FIG. 8A. In some embodiments, the second grooves 56 and 58 may be aligned with the first grooves 26 and 28 in the Y-direction (width direction) of the substrate.

[0083] The second trenches 56 and 58 have a CD of 50 nm to 150 nm and may comprise SiO2, SiON, SiOCN, or other suitable dielectric material. The second trenches may be formed by a photolithography process and a subsequent etching process. For example, a pattern mask stack may be formed on the insulating layer 60a based on a photolithography process. A subsequent etching process is introduced to etch through the insulating layers 60a to 60d, the TSG 62a, the dummy BSGs 62b to 62c, and stop on the word line 62d to form two trench openings. The trench openings may then be filled with a dielectric material, such as SiO2, SiON, SiOCN, or other suitable material, by applying chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof. A surface planarization, such as a CMP process, may be performed to remove excess dielectric material on the insulating layer 60a. After the surface planarization, the dielectric material remaining in the trench openings forms the second trenches.

[0084] FIG. 8B is a cross-sectional view taken along the X-direction (length direction) of the substrate, and FIG. 8C is a top view showing the final structure when the second grooves 56 and 58 are formed. As shown in FIG. 8B, both the first and second grooves are not visible when the cross-sectional view is made along the X-direction (length direction) of the substrate 10. In FIG. 8C, the insulating layer 60a is the top layer. The second grooves 56 and 58 are formed along the length direction of the substrate and are further aligned with the first grooves 26 and 28 in the Y-direction (width direction) of the substrate 10. The first and second grooves together divide the substrate 10 into three regions (or sub-blocks). In addition, two staircase regions 100A and 100C are located on both sides, and a core region 100C is located in the center of the substrate.

[0085] FIG. 9A is a cross-sectional view taken in the Z direction (height direction) of the substrate to show the formation of a plurality of channel structures. To form the channel structures, a plurality of channel openings may be first formed. The channel openings may be formed through a photolithography process to form a pattern mask and a subsequent etching process to transfer the pattern of the mask. The formed channel openings may extend through the TSG, dummy TSG, word lines, dummy BSG, and BSG, and further into the HVPW 14. Each of the channel openings may have a side and a bottom to expose the HVPW 14. Once the channel openings are formed, a plurality of bottom channel contacts may be formed at the bottom of the channel openings, such as the bottom channel contact 202 shown in FIG. 1C. Each of the channel openings may have a respective bottom contact at the bottom. The bottom channel contacts may protrude from the BSG 62p, and the top surface of each of the bottom channel contacts may be located between the BSG 62p and the dummy BSG 62o.

[0086] Still referring to FIG. 9A, once the bottom channel contacts are formed, a barrier layer, a charge trapping layer, and a tunnel layer may be sequentially formed over the bottom channel contacts along the sides of the channel opening. A subsequent anisotropic plasma etch may be applied to remove portions of the barrier layer, charge trapping layer, and tunnel layer disposed over the bottom channel contacts to form a plurality of interconnect openings. Each interconnect opening exposes a respective bottom channel contact. A channel layer may be later formed along the sides of the channel opening and further extend through the interconnect openings to connect the bottom channel contacts.

[0087] When the channel layer is formed, it can have sides formed along the tunnel layer and a T-shaped bottom extending through the bottom of the tunnel layer, charge trapping layer, and barrier layer that sits on the bottom channel contact. The T-shaped bottom of the channel layer is in direct contact with the bottom channel contact, which can be seen in Figures 1C and 1D. In addition, the tunnel layer, charge trapping layer, and barrier layer can form an L-leg configuration within the channel opening. The L-leg configuration can include sides formed along the sidewalls of the channel opening and a bottom above the bottom channel contact.

[0088] In some embodiments, once the channel layer is formed, a subsequent annealing process may be applied, one to relieve stress in the wafer, another to reduce defects (dangling bonds), and in some cases, to convert the channel layer to polycrystalline. In some embodiments, forming the channel structure further includes forming a channel insulating layer on the channel layer to fill the channel opening, and forming a top channel contact on the channel insulating layer, where the top channel contact is in direct contact with the channel layer. A detailed channel structure may be shown in FIG. 1C and FIG. 1D.

[0089] 9B is a top view showing the formation of multiple channel structures. As shown in FIG. 9B, multiple channel structures can be formed in the core region 100B and divided into three sub-blocks by the second grooves 56 and 58.

[0090] FIG. 10A is a cross-sectional view taken in the Z direction (height direction) of the substrate to show the formation of multiple dummy channel structures 40, 42, 44, 46, 48, and 50. The dummy channel structures serve as support components to support the staircase regions 100A and 100C and / or the core region 100B when the sacrificial word lines are removed and replaced with metal. To form the dummy channel structures, multiple dummy channel openings may be first formed. The dummy channel openings may be formed via a photolithography process to form a pattern mask and a subsequent etching process to transfer the pattern of the mask. The dummy channel openings may be formed in the staircase regions. The formed dummy channel openings may extend through the word lines, the dummy BSG, and the BSG, and further into the HVPW 14. Each of the dummy channel openings may have sides and a bottom to expose the HVPW 14. Once the dummy channel openings are formed, a dielectric layer may be formed to fill the dummy channel openings. The dielectric layer may include SiO2, SiCN, SiOCN, or other suitable materials. Subsequent surface planarization, such as a CMP process, may be required to remove any excess dielectric layer above the insulating layer 60a. Once surface planarization is complete, the dielectric layer remaining in the dummy channel opening forms a dummy channel structure.

[0091] In some embodiments, the dummy channel structures can have a critical dimension (CD) between 50 nm and 200 nm. In some embodiments, the dummy channel structures can extend into the HVPW 14 to a depth between 10 nm and 200 nm. The dummy channel structures can have a circular shape. In some embodiments, the dummy channel structures can have a non-circular shape, such as a capsule shape, a rectangular shape, an arc shape, a bone shape, etc. The non-circular shape can be tailored by two or more parameters, such as width, length, arc radius, arc angle, etc. Furthermore, in some embodiments, the non-circular shapes can be arranged in a symmetrical or asymmetrical pattern with respect to other junctions in the staircase region. In some embodiments, the dummy channel structure may be formed before the staircase region is formed. In some embodiments, the dummy channel structure may be formed in the core region. Thus, the dummy channel structure may extend through the BSG, the dummy BSG, the word lines, the dummy TSG, the TSG, and the insulating layers into the substrate. In some embodiments, the dummy channel structure may be formed together with the channel structure and have a similar structure to the channel structure. For example, the dummy channel structure may also include a barrier layer, a trap layer, a tunnel layer, and a channel layer.

[0092] 10B is a top view showing the formation of multiple dummy channel structures. As shown in FIG. 10B, multiple dummy channel structures can be formed in the two staircase regions 100A and 100C, as well as in the core array region 100B (especially in the transition zone from the core region to the staircase region).

[0093] FIG. 11A is a cross-sectional view taken in the Z direction (height direction) of the substrate to show the formation of one or more common source regions. To form a channel structure, one or more common source openings may be formed first. The common source openings may be formed through a photolithography process to form a pattern mask and a subsequent etching process to transfer the pattern of the mask. The formed common source openings extend through the TSG, dummy TSG, word lines, dummy BSG, and BSG, and further into the HVPW 14. Each of the common source openings may have sides and a bottom that extend into the HVPW. The common source openings may further extend along the X direction (length direction) of the substrate and be disposed parallel to the first and second trenches.

[0094] FIG. 11B shows an exemplary embodiment of forming a common source opening. As shown in FIG. 11B, two common source openings 52b' and 52c' are formed at two boundaries of a substrate having a continuous configuration. The common source regions 52a and 52c can be subsequently formed in the common source openings 52b' and 52c', respectively. The common source opening 52a' is formed at a central position of the substrate. The common source opening 52a' can include two or more sub-openings based on a pattern of a formed mask. For example, two sub-openings 52a-1' and 52a-2' are included in FIG. 11B. The space between the two sub-openings 52a-1' and 52a-2' forms an H-cut, such as the H-cut 72 in FIG. 11B. The common source regions 52a-1 and 52a-2 can be formed in the two sub-openings 52a-1' and 52a-2', respectively.

[0095] After the common source openings are formed, the subsequent fabrication steps to complete the formation of the common source region may differ between gate-first and gate-last fabrication flows. In a gate-first fabrication flow, ion implantation may continue to be applied to form doped regions, such as doped region 54, at the bottom of each of the common source openings. Dielectric spacers, such as dielectric spacer 68, may be formed on the doped regions along the sides of the common source openings. An anisotropic plasma etch may be performed to remove the bottoms of the dielectric spacers formed on the doped regions to expose the doped regions. A conductive layer, such as conductive layer 70, may be deposited along the dielectric spacers to fill the common source openings. The conductive layer may be recessed back by an etching process, and a top contact, such as top contact 64, may be formed on the conductive layer along the dielectric spacers. Once the top contacts are formed, the formation of the common source region is complete, and the completed common source region 52 may be shown in FIG. 11A.

[0096] However, in a gate-last manufacturing flow, once the common source opening is formed, the BSG, dummy BSG, word lines, dummy TSG, and TSG are subsequently removed to form a plurality of voids by a wet etching chemical introduced through the common source opening. An ion implantation can then be applied to form a doped region (e.g., 54) at the bottom of each of the common source openings. Following the implantation step, the BSG, dummy BSG, word lines, dummy TSG, and TSG are reformed by filling the voids with a high-K layer plus a metal layer through the common source opening. A dielectric spacer, such as dielectric spacer 68, can then be formed over the doped regions along the sides of the common source opening. A followed anisotropic plasma etch can be performed to remove the bottom of the dielectric spacer formed over the doped regions to expose the doped regions. A conductive layer, such as conductive layer 70, can be deposited along the dielectric spacers to fill the common source opening. The conductive layer may be recessed back by an etching process, and a top contact, such as top contact 64, may be formed on the conductive layer along the dielectric spacer. Once the top contact is formed, the formation of the common source region is complete, and the completed common source region may be shown in FIG.

[0097] After formation of the common source region, the final memory device 100 is formed, which is identical to the memory device 100 shown in FIG. 1A.

[0098] FIG. 11C is a top view illustrating the formation of one or more common source regions. As shown in FIG. 11C, the memory device 100 can have three common source regions 52a-52c. The common source regions 52a-52c are formed along the X-direction (length direction) of the substrate 10 and are disposed at two boundaries and a central position of the memory device 100. The common source regions 52b and 52c are disposed at two boundaries of the memory device 100 having a continuous configuration. The common source region 52a is disposed at a central position of the memory device 100. The common source region (CSR) 52a is divided into two sub-CSRs 52a-1 and 52a-2 by an H-cut 72. The first trenches 26 and 28 and the second trenches 56 and 58 are aligned with each other in the Y-direction (width direction) of the substrate 10. The first trench and the second trench are disposed between two adjacent common source regions.

[0099] 11D is a cross-sectional view taken in the X-direction (length direction) of the substrate to show the final structure of memory device 100. As shown in FIG 11D, the first trench, the second trench, and the common source region are not visible from the cross-sectional view taken in the X-direction (length direction) of the substrate.

[0100] 12 is a flow chart of a process 1200 for manufacturing a 3D NAND memory device 100 according to some embodiments. The process 1200 starts at step 1204 where one or more BSGs and one or more dummy BSGs are sequentially formed on a substrate. In addition, a plurality of first insulating layers are formed between the substrate, the BSGs, and the dummy BSGs. The substrate may include a plurality of doped regions to reduce resistance between the substrate and a channel structure to be formed later. The substrate, the BSGs, and the dummy BSGs are separated from each other by the first insulating layer.

[0101] In step 1206 of process 1200, one or more first trenches are formed in the BSG and the dummy BSG. The first trenches extend through the BSG, the dummy BSG, and the first insulating layer into the substrate. The first trenches further extend along the X-direction (length direction) of the substrate. The first trenches partition the BSG, the dummy BSG into a number of sub-BSGs and sub-dummy BSGs. In some embodiments, steps 1204 and 1206 may be performed as shown with reference to FIGS. 5A-5C.

[0102] Process 1200 then proceeds to step 1208, where a plurality of word lines, one or more dummy TSGs, and one or more TSGs are sequentially stacked on the dummy BSG. In addition, a plurality of second insulating layers are formed on the dummy BSGs and disposed between the dummy BSGs, the word lines, the dummy TSGs, and the TSGs. In some embodiments, step 1208 may be performed as shown with reference to FIG.

[0103] In step 1210, one or more staircase regions may be formed. The staircase regions are configured to provide space for forming dummy channel structures as well as word line contacts (not shown). Formation of the staircase regions may be performed by alternating mask patterning and plasma etching processes. The formed staircase regions are located on both sides of the substrate and the core region is located in the center. In some embodiments, step 1208 may be performed as shown with reference to FIGS. 7A-7F.

[0104] The process 1200 proceeds to step 1212 where one or more second trenches are formed in the dummy TSGs and the TSGs. The second trenches extend along the length of the substrate. The second trenches also pass through the dummy TSGs, the TSGs, and a portion of the second insulating layer therebetween. The first and second trenches are aligned with each other across the width of the substrate and are separated by a plurality of word line layers. The TSGs are partitioned into groups of sub-TSGs by the second trenches, and the TSGs are partitioned into groups of sub-dummy TSGs by the second trenches. In some embodiments, step 1212 may be performed as shown with reference to FIGS. 8A-8C.

[0105] In step 1214 of process 1200, a plurality of channel structures may be formed in the core region. The formation of the channel structures may be performed as shown with reference to Figures 9A-9B. Next, a plurality of dummy channel structures may be formed in the staircase region. The formation of the dummy channel structures may be performed as shown with reference to Figures 10A-10B.

[0106] It should be understood that the channel structure may also be formed before the step region is formed. In some embodiments, the dummy channel structure may be formed in the core region. In some embodiments, the dummy channel structure may be formed together with the channel structure and have a similar structure to the channel structure. For example, the dummy channel structure may also include a barrier layer, a trap layer, a tunnel layer, and a channel layer.

[0107] Still in step 1214, one or more common source regions may be formed after the formation of the dummy channel structures. The common source regions extend through the BSG, the dummy BSG, the word lines, the dummy TSG, the TSG, and the first and second insulating layers. Each of the common source regions is electrically coupled to the substrate via a respective doped region. The common source regions, the first trench, and the second trench further extend parallel to each other along the length of the substrate. In some embodiments, the formation of the common source region further includes removing the BSG, the dummy BSG, the word lines, the dummy TSG, and the TSG, and reforming the BSG, the dummy BSG, the word lines, the dummy TSG, and the TSG with high-K and metal layers. In some embodiments, the formation of the common source region may be performed as shown with reference to FIGS. 11A-11D.

[0108] It should be noted that additional steps may be provided before, during, and after process 1200, and some of the described steps may be substituted, omitted, or performed in a different order for additional embodiments of process 1200. In subsequent process steps, various additional interconnect structures (e.g., metallization layers having conductive lines and / or vias) may be formed on semiconductor device 1200. Such interconnect structures electrically connect semiconductor device 1200 with other channel structures and / or active devices to form functional circuits. Additional device features, such as passivation layers, input / output structures, etc. may also be formed.

[0109] Various embodiments described herein provide several advantages over related memory devices. For example, in the related memory devices, multiple memory cell blocks or memory cell arrays may be included. Each of the blocks may include multiple vertical NAND memory cell strings. In the related memory devices, the vertical NAND memory cell strings in the same block may have a common / shared bottom select gate (BSG). Thus, the shared BSG simultaneously controls all bottom select transistors (BSTs) of the vertical NAND memory cell strings in that block while operating the related 3D-NAND memory device, such as erasing the related 3D-NAND memory device. As the related 3D-NAND memory devices transition to higher capacities with increasing block sizes, the shared BSG may induce longer erase times, longer data transfer times, and lower storage efficiency.

[0110] In the disclosed memory device, each of the blocks is partitioned into multiple sub-blocks by dividing a shared BSG into multiple sub-BSGs via one or more first trenches. Each of the sub-blocks has a respective sub-BSG, and each of the sub-blocks can be individually operated via controlling the respective sub-BSG. By introducing such a divided BSG structure, the disclosed 3D-NAND memory device effectively reduces the parasitic capacitance and coupling effect between the BSG and the adjacent dielectric layer, and reduces the V of the bottom select transistor (BST). t The performance can be significantly improved. In addition, the erase time and data transfer time can be significantly reduced, and the data storage efficiency can be improved.

[0111] In the disclosed memory device, each of the sub-blocks can further have a respective sub-top select gate (sub-TSG) by dividing the shared TSG into multiple sub-TSGs through one or more second trenches. Each of the sub-TSGs can control the respective sub-block during read / programming operations. In some embodiments, the first and second trenches can be formed through the same reticle set so that manufacturing costs can be reduced.

[0112] The above outlines the features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same purpose and / or achieve the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various modifications, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0113] 10 Substrate 12 Deep N-well, doped region 14 High Voltage P-well (HVPW), doped region 16 High Voltage N-type Well (HVNW), doped region 18 N+ region, doped region 20 HVNW, doped region 22 N+ region, doped region 24 Doped Region 24a P+ area 24b P+ region 26 First dielectric groove 28 First dielectric groove 30 Channel Structure 32 Channel Structure 34 Channel Structure 36 Channel Structure 38 Channel Structure 40 Dummy Channel Structure 42 Dummy Channel Structure 44 Dummy Channel Structure 46 Dummy Channel Structure 48 Dummy Channel Structure 50 Dummy Channel Structure 52 Common Source Area (CSR) 52a CSR 52a' CSR 52b CSR 52b' CSR 52c CSR 52c' CSR 52a-1 Sub-CSR 52a-1' Sub CSR 52a-2 Sub-CSR 52a-2' Sub CSR 54 Doped Region 56 Second dielectric groove 58 Second dielectric groove 60 Insulating layer 60a~60q Insulation layer 60a-A Terminal part 60a-B Termination 60b-A Termination 60b-B Termination 62a Top Select Gate (TSG) 62b Top Dummy Word Line 62c Top Dummy Word Line 62d~62m Word Line 62n Bottom Dummy Word Line 62o Bottom Dummy Word Line 62p Bottom Select Gate (BSG) 62a-1 Sub-TSG 62a-2 Sub-TSG 62a-3 Sub-TSG 62b-1 Sub-dummy TSG 62c-1 Sub-dummy TSG 62n-1 Sub-dummy BSG 62o-1 Sub-dummy BSG 62o-2 Sub-dummy BSG 62o-3 Sub-dummy BSG 62p-1 Sub BSG 62p-2 Sub BSG 62p-3 Sub BSG 64 Top contact 68 Dielectric Spacer 70 Conductive Layer 72 H-Cut 100 3D-NAND memory devices 100A stair area 100B Core Area 100C stair area 202 Bottom Channel Contact 204 Channel Insulation Layer 206 Channel Layer 208 Tunnel Layer 210 Charge trapping layer 212 Barrier Layer 214 Top Channel Contact 216 Gate dielectric layer 702 Pattern Mask Stack

Claims

1. A substrate, a bottom select gate (BSG) disposed over the substrate; a plurality of word lines disposed over the BSG; a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines; one or more first dielectric grooves formed in the BSG and extending along the length of the substrate to partition the BSG into a plurality of sub-BSGs; one or more common source regions formed over and extending along the length of the substrate; the one or more common source regions extend through the BSG, the word lines, and the insulating layers, at least one of the word lines being disposed over the one or more first dielectric trenches.

2. A top select gate (TSG) disposed over the plurality of word lines, the TSG and the plurality of word lines being separated by the plurality of insulating layers; 2. The memory device of claim 1 , further comprising: one or more second dielectric trenches formed in said TSG and extending along said length of said substrate to partition said TSG into a plurality of sub-TSGs.

3. The memory device of claim 2, wherein the first dielectric groove and the second dielectric groove are aligned with each other in the width direction of the substrate.

4. The memory device of claim 2, wherein the one or more common source regions further pass through the TSG, and the one or more common source regions, the first dielectric trench, and the second dielectric trench extend parallel to each other in the longitudinal direction of the substrate.

5. The memory device of claim 2, further comprising a plurality of channel structures formed on the substrate along a height direction of the substrate perpendicular to the substrate, each of the plurality of channel structures passing through the BSG, the plurality of word lines, the TSG, and the plurality of insulating layers.

6. A memory device as described in claim 5, wherein the one or more first dielectric grooves and the one or more common source regions are arranged alternately in the width direction of the substrate.

7. A memory device as described in claim 5, wherein the one or more second dielectric grooves and the one or more common source regions are arranged alternately in the width direction of the substrate so that multiple channel structures are arranged between them.

8. The memory device of claim 1, wherein a plurality of word lines disposed above the BSG have a staircase configuration.

9. The memory device of claim 2, wherein the plurality of word lines and the TSG are stacked alternately on the substrate having a staircase configuration.

10. The memory device of claim 2, further comprising a dummy channel structure, the dummy channel structure extending through the BSG, the word lines, and the insulating layer.

11. A bottom select gate (BSG); a word line disposed above the BSG having a staircase configuration; a top select gate (TSG) disposed above the word line; an insulating layer disposed between the BSG, the word lines, and the TSG; a first dielectric trench formed in the BSG and partitioning the BSG into a plurality of sub-BSGs; a second dielectric trench formed in the TSG and partitioning the TSG into a plurality of sub-TSGs, The first dielectric trench and the second dielectric trench are aligned with each other along the height of the insulating layer and are separated by the word lines.

12. The memory device of claim 11, further comprising a common source region, the common source region extending through the BSG, the word lines, and the insulating layer.

13. The memory device of claim 12, wherein the common source region extends further through the TSG.

14. The memory device of claim 11, further comprising a channel structure, the channel structure extending through the BSG, the word line, the insulating layer, and the TSG.

15. The memory device of claim 11, further comprising a dummy channel structure, the dummy channel structure extending through the BSG, the word lines, and the insulating layer.

16. A stack of alternating gate line layers and insulating layers, the stack including an array region, the gate line layers including a bottom select gate (BSG), and one or more dummy bottom select gate (DUMBSG) layers formed between the bottom select gate (BSG) and other gate line layers; one or more first dielectric grooves formed in the bottom select gate (BSG) of the gate line layer and extending along the length of the stack to partition the bottom select gate (BSG) into sub-bottom select gates (BSG); A memory device comprising: the one or more first dielectric trenches partition the one or more dummy bottom select gate (DUMBSG) layers into a plurality of sub-dummy bottom select gate layers; the one or more first dielectric trenches extend into at least one of the plurality of insulating layers between the bottom select gate (BSG) layer and the one or more dummy bottom select gate (DUMBSG) layers.

17. The memory device of claim 16, wherein the plurality of gate line layers further includes a top select gate (TSG) disposed on the bottom select gate (BSG).

18. The memory device of claim 17, further comprising one or more second dielectric grooves formed in a top select gate (TSG) of one of the plurality of gate line layers and extending in the length direction of the stack to divide the top select gate (TSG) into sub-top select gates (TSGs).

19. A memory device, wherein the plurality of gate line layers further comprises a plurality of word lines.

20. The memory device of claim 18, further comprising a plurality of channel structures, at least one of said plurality of channel structures passing through said BSG, said word line, said TSG, and said insulating layer.

20. The memory device of claim 19, wherein the plurality of word lines are disposed above the BSG having a staircase configuration.

Images