Semiconductor device

Abstract

To provide a semiconductor device with stable electric characteristics, or a semiconductor device with normally off electric characteristics.SOLUTION: A semiconductor device includes a gate electrode, a gate insulator, and an oxide semiconductor. The oxide semiconductor contains fluorine in a channel formation region, and the fluorine concentration in the channel formation region is 1×1020 atoms / cm3 or more and 1×1022 atoms / cm3 or less. Fluorine addition is performed by an ion injection method.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device. The present invention also relates to a method for manufacturing a semiconductor device, a transistor, and a display device, for example. Devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, processors, electronic devices Or, the manufacture of display devices, liquid crystal display devices, light-emitting devices, storage devices, imaging devices, and electronic devices. The present invention relates to a display device, a liquid crystal display device, a light emitting device, a storage device, an imaging device, a battery, and a method for manufacturing the same. This relates to a method for driving a child device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It is about the nature of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, storage devices, imaging devices, electro-optical devices, semiconductor The electronic circuits and devices may include semiconductor devices. [Background technology]

[0004] Technology that uses semiconductors on substrates with insulating surfaces to construct transistors has been attracting attention. Such transistors are widely used in semiconductor devices such as integrated circuits and display devices. Silicon is known as a semiconductor that can be used for transistors.

[0005] Silicon used as a semiconductor in transistors is classified into amorphous silicon and polycrystalline silicon depending on the application. For example, it is used in transistors that make up large display devices. In this case, it is preferable to use amorphous silicon, for which a film formation technique for a large-area substrate has been established. On the other hand, it is applied to transistors that constitute high-performance display devices that are integrated with driving circuits. In this case, if polycrystalline silicon is used, transistors with high field effect mobility can be fabricated. Polycrystalline silicon is preferably obtained by subjecting amorphous silicon to high-temperature heat treatment or laser light. A method for forming the same by processing is known.

[0006] In recent years, the development of transistors using oxide semiconductors (typically In-Ga-Zn oxide) has become Development is intensifying.

[0007] The history of oxide semiconductors is long. In 1988, crystalline In-Ga-Zn oxide was used in semiconductor devices. In 1995, the use of oxide A transistor using a semiconductor has been invented, and its electrical characteristics have been disclosed (Patent Document See reference 2. ).

[0008] The transistor using an oxide semiconductor includes a transistor using amorphous silicon and a It has different characteristics from transistors using crystalline silicon. For example, It is known that a display device using such a transistor has low power consumption. Conductors can be formed into films using methods such as sputtering, so they can be used to make transistors that form large display devices. In addition, a transistor using an oxide semiconductor can be used as a high-field transistor. Since the organic electroluminescent device has a high effective mobility, it is possible to realize a highly functional display device in which a driving circuit is integrally formed. It is possible to use some of the production facilities for amorphous silicon transistors by improving them. This also has the advantage of reducing capital investment.

[0009] For example, in order to mass-produce semiconductor devices such as display devices, transistors using oxide semiconductors are required. The electrical characteristics of the capacitor must be stable.

[0010] In a transistor using an oxide semiconductor, it is very important to control oxygen vacancies in the oxide semiconductor. It is important to minimize oxygen vacancies in order to obtain stable transistor characteristics. It is preferable to do so, and one technique for this purpose is to inject oxygen into an oxide semiconductor (particularly See patent document 3. ). [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 63-239117 [Patent Document 2] Special Publication No. 11-505377 [Patent Document 3] JP 2012-238880 A Summary of the Invention [Problem to be solved by the invention]

[0012] It is an object of the present invention to provide a transistor having stable electrical characteristics. An object of the present invention is to provide a transistor having marrow-off electrical characteristics. An object of the present invention is to provide a transistor with a small subthreshold swing value. Another object of the present invention is to provide a transistor with a small short-channel effect. Another object of the present invention is to provide a transistor having a small leakage current when off. Another object of the present invention is to provide a transistor having excellent electrical characteristics. Another object of the present invention is to provide a transistor having high frequency characteristics. One of the objectives is to provide a

[0013] Another object of the present invention is to provide a semiconductor device including the transistor. Another object of the present invention is to provide a module having the semiconductor device. Another object of the present invention is to provide a device having such a module, or an electronic device having such a module. It is an object of the present invention to provide a novel semiconductor device. Another object of the present invention is to provide a novel electronic device.

[0014] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0015] As mentioned above, it is very important to control oxygen vacancies in oxide semiconductors. In order to obtain transistor characteristics, it is preferable to reduce oxygen vacancies as much as possible. In addition, the compensated oxygen vacancies may be repopulated by oxygen due to damage during the transistor manufacturing process. It is also important to form stable bonds to avoid defects.

[0016] Therefore, one embodiment of the present invention is to add fluorine to a channel formation region of a semiconductor. It compensates for oxygen vacancies in semiconductors and also fills the oxygen vacancies with fluorine, which forms stable bonds. By performing compensation, a transistor having stable and good electrical characteristics is provided.

[0017] One embodiment of the present invention is a gate electrode, a gate insulator, and an oxide semiconductor. The conductor is a semiconductor device having fluorine in a channel forming region.

[0018] In one embodiment of the present invention, the fluorine concentration in the channel formation region is 1×10 20 atom s / cm 3 More than 1×10 22 atoms / cm 3 The semiconductor device is as follows.

[0019] In one embodiment of the present invention, the oxide semiconductor is This is a semiconductor device in which the fluorine concentration in the region is low.

[0020] In one embodiment of the present invention, the oxide semiconductor is a semiconductor containing indium, zinc, and an element M (the element M is aluminum). Semiconductor devices having one or more elements selected from the group consisting of tin, gallium, yttrium, and tin. It is located.

[0021] One embodiment of the present invention is a module including the semiconductor device described above and a printed board. do.

[0022] One embodiment of the present invention is a semiconductor device including the above-described semiconductor device or the above-described module and a speaker. , an operation key, or a battery.

[0023] One embodiment of the present invention is a method for forming an oxide semiconductor over a substrate, and and forming a source electrode and a drain electrode, doping fluorine into the oxide semiconductor, and and a semiconductor device in which an insulator is formed on a drain electrode and a gate electrode is formed on the insulator. This is the method of production.

[0024] Another embodiment of the present invention is a semiconductor device formed over a substrate, in which fluorine is added to the oxide semiconductor. A source electrode and a drain electrode are formed in contact with the oxide semiconductor. A semiconductor device in which an insulator is formed on a drain electrode and a gate electrode, and a gate electrode is formed on the insulator. This is a method for making the device.

[0025] Another embodiment of the present invention is a method for forming an oxide semiconductor over a substrate, and forming an insulating layer on the oxide semiconductor, the source electrode, and the drain electrode. A gate electrode is formed on the insulator by adding fluorine to the oxide semiconductor through the insulator. The present invention relates to a method for manufacturing a semiconductor device.

[0026] Another embodiment of the present invention is a method for forming a gate electrode over a substrate, forming an insulator over the gate electrode, An oxide semiconductor is formed on a gate electrode via an insulator, and fluorine is added to the oxide semiconductor; A method for manufacturing a semiconductor device in which a source electrode and a drain electrode are formed in contact with an oxide semiconductor be.

[0027] Another embodiment of the present invention is a method for forming a gate electrode over a substrate, forming an insulator over the gate electrode, An oxide semiconductor is formed on a gate electrode via an insulator, and a source electrode is formed in contact with the oxide semiconductor. and a method for manufacturing a semiconductor device in which a drain electrode is formed and fluorine is added to an oxide semiconductor. be.

[0028] One embodiment of the present invention is a method for manufacturing a semiconductor device, in which the addition of fluorine is performed by an ion implantation method. It is law.

[0029] In one embodiment of the present invention, the oxide semiconductor is a semiconductor containing indium, zinc, and an element M (the element M is aluminum). Semiconductor devices having one or more elements selected from the group consisting of tin, gallium, yttrium, and tin. This is a method for making the device. Effect of the Invention

[0030] It is possible to provide a transistor having stable electrical characteristics. Alternatively, a transistor having subthreshold electrical characteristics can be provided. It is possible to provide a transistor with a small swing value. It is possible to provide a small transistor. Alternatively, it is possible to provide a transistor with a small leakage current when non-conducting. To provide a transistor having excellent electrical characteristics. Alternatively, a highly reliable transistor can be provided. It is possible to provide a transistor having excellent frequency characteristics.

[0031] Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module having the semiconductor device or the module may be provided. It is possible to provide an electronic device having a novel semiconductor device. Alternatively, a new module may be provided. Alternatively, a new electronic Equipment can be provided.

[0032] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0033] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 2] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 3] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 4] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 5] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 7] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 9] FIG. 2 is a band diagram according to one embodiment of the present invention. [Figure 10] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 11] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 12] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 13] Electron diffraction pattern of CAAC-OS. [Figure 14] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 15] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 17] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 18] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 19] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 21] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 22] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 23] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 24] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 25] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 29] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 30] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 31] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 32]FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 33] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 34] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 35] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 36] 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 37] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 39] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 40] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 41] FIG. 1 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Diagram 42] FIG. 4 is a diagram for explaining the amount of fluorine added in the depth direction. [Diagram 43] FIG. 13 is a graph showing sheet resistance values ​​of samples. [Diagram 44] FIG. 1 shows the ESR results of the sample. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and detail can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used in different The hatch pattern is used in common among drawings. In some cases, no particular symbol is attached.

[0035] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where

[0036] In this specification and the like, the terms "film" and "layer" are interchangeable. It is possible to replace it.

[0037] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, it is possible to say "voltage" as "potential". In general, potential (voltage) is relative, and the magnitude is measured relative to a reference potential. Therefore, even if it is described as "ground potential", The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." With respect to the potential, a positive potential and a negative potential are defined for .

[0038] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. and the ordinal numbers used to identify an aspect of the invention may not match.

[0039] Even if a material is described as a "semiconductor," if its electrical conductivity is sufficiently low, it may be considered an "insulator." In addition, the boundary between "semiconductor" and "insulator" is unclear, and Therefore, the term "semiconductor" as used herein may not be distinguishable from "insulator." Similarly, the term "insulator" used in this specification may be interpreted as "semiconductor." " This can sometimes be rephrased as ".

[0040] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it should be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear, and Therefore, the term "semiconductor" as used herein may not be distinguished from "conductor." Similarly, the term "conductor" used in this specification may be used interchangeably with "semiconductor." " This can sometimes be rephrased as ".

[0041] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the body and carrier mobility In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, for example, Hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies can be eliminated by the inclusion of impurities such as hydrogen. In addition, when the semiconductor is silicon, there are cases where a defect that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0042] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode (the part of the semiconductor through which current flows) overlaps with the The source region or source potential in the region where the This refers to the distance between the drain (drain region or drain electrode) and the In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is defined as any one value, maximum value, or The minimum or average value.

[0043] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. This refers to the length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0044] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the ratio of the channel formation region to the total area may be increased. The effective channel width is smaller than the apparent channel width shown by the The width will be larger.

[0045] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0046] In this specification, therefore, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the overlapping area between the source and drain The channel width of the In this specification, it is sometimes referred to as the "channel width". In some cases, this may refer to the enclosed channel width or apparent channel width; or In this specification, when simply referring to a channel width, it may refer to an effective channel width. In addition, the channel length, channel width, effective channel width, apparent channel width, and enclosure The width of the inclusion channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0047] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width may be used. The value may differ from that calculated using the channel width.

[0048] In this specification, when it is stated that A has a shape protruding from B, it is to be understood that the shape is not limited to a top view. or in a cross-sectional view, at least one end of A is outside at least one end of B. Therefore, it may be described as having a shape in which A protrudes more than B. For example, in the top view, one end of A is on the outside of one end of B. It can be read as having.

[0049] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0050] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0051] In the present specification, the term "semiconductor" may be interpreted as an oxide semiconductor. Other semiconductors include group 14 semiconductors such as silicon and germanium, silicon carbide, , germanium disilicide, gallium arsenide, indium phosphide, zinc selenide, cadmium sulfide Compound semiconductors such as ZnO and organic semiconductors can be used.

[0052] (Embodiment 1) In this embodiment, an example of a transistor according to one embodiment of the present invention will be described.

[0053] <Transistor 1> FIG. 1 illustrates a transistor according to one embodiment of the present invention. FIG. 1A illustrates a transistor 100. 1(B) is a top view of the structure shown in FIG. 1(A) along the dashed line A1-A2 and dashed line A3- The transistor 100 includes a substrate 400, a conductor 413, and An insulator 402, a semiconductor 406a, a semiconductor 406b, a semiconductor 406c, and a conductor 416a. , a conductor 416b, an insulator 412, and a conductor 404.

[0054] The semiconductor 406a, 406b, or 406c in the transistor 100 has fluorine. Fluorine may be contained in all three layers. Either one layer may have it, or either two layers may have it.

[0055] As shown in this embodiment, the semiconductor in the transistor is formed of a plurality of layers. In this case, it is preferable that the semiconductor having the channel formation region contains fluorine. For example, when the semiconductor 406b has a channel formation region, the semiconductor 406b may contain fluorine. is preferred.

[0056] Note that the conductor 404 is a first gate electrode (front gate electrode) of the transistor 100. The conductor 413 functions as a second transistor of the transistor 100. The conductor 416 also functions as a gate electrode (also called a back gate electrode). a and conductor 416b serve as the source and drain electrodes of transistor 100. The insulator 412 also functions as a gate insulator.

[0057] In addition, the transistor 100 in this embodiment is a top gate transistor having a back gate. However, this is not limited to this type of transistor. For example, a transistor without a back gate may be used. Alternatively, a bottom gate structure may be used. In that case, the conductor 413 is a front gate. The conductor 404 functions as a gate and the conductor 404 functions as a back gate. It may be configured without it.

[0058] A method for manufacturing the transistor 100 shown in FIG. 1 will be described with reference to FIGS.

[0059] 2(A), 3(A), 4(A), 5(A) and 6(A) show an embodiment of the present invention. 1 is a top view illustrating a method for manufacturing a transistor 100 according to the present invention. A1-A2 and a dashed line A3-A4 are shown, and the corresponding cross-sectional view is shown in FIG. 3(B), 4(B), 5(B) and 6(B).

[0060] First, a substrate 400 is prepared.

[0061] The substrate 400 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, and a stabilized zirconia substrate. There are also semiconductor substrates, such as zirconia substrates stabilized with yttria, and resin substrates. The substrate may be, for example, a single semiconductor substrate such as silicon or germanium, or a silicon carbide substrate. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates made of insulators inside the aforementioned semiconductor substrates. A semiconductor substrate having a region, such as SOI (Silicon On Insulator) Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or a semiconductor is provided on a semiconductor substrate, or a substrate with a semiconductor or insulator provided on a conductive substrate, etc. Alternatively, a substrate having elements provided thereon may be used. The elements include a capacitance element, a resistance element, a switch element, a light-emitting element, and a memory element.

[0062] A flexible substrate may be used as the substrate 400. The method of providing the transistor is to fabricate the transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 400. A peeling layer may be provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil having woven fibers may be used. The substrate 400 may be stretchable. Also, the substrate 400 may be designed to retain its original shape when the bending or pulling is stopped. The substrate 4 may have a property of returning to its original shape. Alternatively, the substrate 4 may have a property of not returning to its original shape. The thickness of the 00 is, for example, 5 μm or more and 1000 μm or less, preferably 10 μm or more and 700 μm or less. The thickness of the substrate 400 is preferably 15 μm or more and 500 μm or less. In addition, by making the substrate 400 thin, the weight of the semiconductor device can be reduced. In any case, it may have elasticity or may return to its original shape when bending or pulling is stopped. Therefore, the semiconductor device on the substrate 400 may be damaged if it is dropped or the like. In other words, a robust semiconductor device can be provided. Cut.

[0063] The substrate 400, which is a flexible substrate, may be made of, for example, a metal, an alloy, a resin, or a glass. The substrate 400, which is a flexible substrate, has a linear expansion coefficient of 1.0. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester or polystyrene. Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, so it is suitable for flexible substrates. 400 is preferable.

[0064] Next, a conductive film is formed. The conductive film is formed by a method such as sputtering or chemical vapor deposition (CVD). Chemical Vapor Deposition, Molecular Beam Epitaxy (MB E: Molecular Beam Epitaxy (MBE) or Pulsed Laser Deposition (PL D: Pulsed Laser Deposition) method, atomic layer deposition (ALD: At This can be done using a omic layer deposition method or the like.

[0065] The CVD method is a method that uses plasma CVD (PECVD: Plasma ECVD). enhanced CVD method, and thermal CVD (TCVD: Thermal CVD) method D) method, photo CVD method, etc. Depending on the source gas, metal CVD (MCVD) method, metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0066] The PECVD method can obtain high-quality films at relatively low temperatures. Since no plasma is used, the film formation method does not cause damage to the workpiece due to plasma. For example, The wiring, electrodes, elements (transistors, capacitors, etc.) included in the semiconductor device are It may become charged up by receiving an electric charge from Zuma. At this time, the accumulated electric charge The wiring, electrodes, elements, etc., included in the semiconductor device may be destroyed by the above. In the case of the TCVD method, which does not use plasma, such plasma damage does not occur, so The yield of semiconductor devices can be increased. In addition, the TCVD method uses plasma during film formation. Since no damage occurs, a film with few defects is easily obtained.

[0067] In addition, the ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. Easy to obtain.

[0068] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less susceptible to the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. However, the ALD method has a relatively low deposition rate. Because the deposition rate is slow, it can be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this is preferable.

[0069] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0070] Next, a resist or the like is formed on the conductor, and the conductor 413 is formed by processing using the resist. In addition, when simply forming a resist, it is assumed that an anti-reflection layer is formed under the resist. This also includes cases where

[0071] The resist is removed after the object is processed by etching or other methods. In this case, plasma treatment and / or wet etching are used. Plasma ashing is suitable for this purpose. If removal of resist, etc. is insufficient, Hydrofluoric acid and / or ozone at a concentration of 1% to 1% by volume Any remaining resist may be removed using water or the like.

[0072] The conductor 413 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, Phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium tungsten, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, Conductors containing one or more of tantalum and tungsten may be used in a single layer or a multilayer structure. For example, the conductor may be an alloy or compound, and may include aluminum, copper and titanium. Conductors containing copper and manganese, Conductors containing indium, tin and oxygen Conductors containing titanium and nitrogen, etc. may also be used.

[0073] Next, the insulator 402 is formed (see FIG. 2(A) and FIG. 2(B)). The film is formed by sputtering, CVD, MBE, PLD, ALD, etc. It can be done.

[0074] The insulator 402 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 402 may be made of aluminum oxide, oxide magnesium oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0075] In addition, the insulator 402 is an insulator having excess oxygen and / or hydrogen traps. preferable.

[0076] Insulators that have excess oxygen are analyzed by thermal desorption spectroscopy (TDS) at temperatures above 100°C. 1×10 at surface temperatures of 700℃ or less, or between 100℃ and 500℃ 18 atoms / cm 3 That's it, 1×10 19 atoms / cm 3 or more than 1×10 20 at oms / cm 3 It may even release more than this amount of oxygen (calculated as the number of oxygen atoms).

[0077] The method for measuring the amount of released oxygen using TDS analysis is described below.

[0078] The total amount of gas released when the measurement sample was subjected to TDS analysis was calculated based on the integral value of the ion intensity of the released gas. By comparison with a standard sample, the total amount of gas released can then be calculated.

[0079] For example, the results of a TDS analysis of a silicon substrate containing a given density of hydrogen as a standard sample, From the TDS analysis results of the measured sample, the amount of oxygen molecules released from the measured sample (N O2 ) is expressed as follows: Here, the gas detected with a mass-to-charge ratio of 32 obtained by TDS analysis is We assume that all of the CH3OH is derived from oxygen molecules. The possibility of this is low, so it is not considered here. The abundance of oxygen atoms and oxygen molecules containing the oxygen atom with mass number 18 in nature is also The rate is so small that it is not taken into consideration.

[0080] N O2 =N H2 / S H2 ×S O2 ×α

[0081] N H2 is the density of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let us assume that S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. Measurements are performed using a silicon substrate containing a fixed amount of hydrogen atoms.

[0082] In addition, some of the oxygen is detected as oxygen atoms in the TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen molecules is included in the calculation, the amount of oxygen atoms released can be calculated by evaluating the amount of oxygen molecules released. It is possible to estimate even if

[0083] In addition, N O2 is the amount of oxygen molecules released. The amount of oxygen released in terms of oxygen atoms is This is twice the amount released.

[0084] Alternatively, an insulator that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to the peroxide radical is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (ES R: Electron Spin Resonance, g value is near 2.01. It may also have symmetrical signals.

[0085] The insulator 402 may have a function of preventing diffusion of impurities from the substrate 400 or the like. stomach.

[0086] Next, a semiconductor film that will become the semiconductor 406a is formed. The semiconductor film that will become the semiconductor 406a is formed as follows: This is done using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can be done.

[0087] Next, by adding oxygen, the semiconductor 406a can be made to contain excess oxygen. The addition of oxygen is preferably performed by, for example, ion implantation at an acceleration voltage of 2 kV to 10 kV. The dose is 5×10 14 ions / cm 2 More than 1×10 17 ions / cm 2 below This can be done as follows.

[0088] Next, fluorine may be added to the semiconductor that will become the semiconductor 406a. The addition of oxygen to the semiconductor that will become semiconductor 406a and the addition of fluorine to the semiconductor that will become semiconductor 406b are sequentially performed. You may switch the order.

[0089] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than or equal to 1×10 20 ions / cm 3 1 more ×10 22 ions / cm 3 This can be done as follows.

[0090] Next, a semiconductor film that will become the semiconductor 406b is formed. The semiconductor film that will become the semiconductor 406b is formed as follows: This is done using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. In addition, the semiconductor film that becomes the semiconductor 406a and the semiconductor film that becomes the semiconductor 406b can be formed. By performing the deposition and deposition in succession without exposing the film to the atmosphere, impurities are prevented from being mixed into the film or at the interface. can be reduced.

[0091] Next, heat treatment is preferably performed. The hydrogen concentration in the semiconductor that becomes the conductor and semiconductor 406b may be reduced. In addition, the oxygen vacancies in the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b are reduced. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably The heating may be performed at a temperature of 450°C or higher and 600°C or lower, and more preferably at a temperature of 520°C or higher and 570°C or lower. Heat treatment is performed in an inert gas atmosphere or with oxidizing gas at 10 ppm or more, 1% or more The heat treatment is carried out in an atmosphere containing 10% or more of fluorine. The heat treatment may be carried out under reduced pressure. After heat treatment in an inert gas atmosphere, oxidizing gas was introduced at 10p to replenish the desorbed oxygen. The heat treatment may be performed in an atmosphere containing at least pm, at least 1%, or at least 10%. Therefore, the crystallinity of the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b is improved. It is possible to reduce the amount of oxygen in the air and to remove impurities such as hydrogen and water.

[0092] Next, fluorine is added to the semiconductor that will become the semiconductor 406a and the semiconductor that will become the semiconductor 406b. In addition, the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b may be Heat treatment and fluorine doping to the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b The addition of and may be performed in reverse order.

[0093] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below Top 5×10 22 ions / cm 3 Less than or equal to 1×10 20 ions / cm 3 1 more ×10 22 ions / cm 3 This can be done as follows.

[0094] Next, a resist or the like is formed on the semiconductor that will become the semiconductor 406b, and processing is performed using the resist. The semiconductor 406b and the semiconductor 406a are formed (see FIGS. 3A and 3B). .).

[0095] Next, a conductive film is formed. The conductive film may be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be carried out by using a PLD method, an ALD method, or the like.

[0096] Examples of conductors include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, and aluminum. , titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium , zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and tantalum A conductor containing one or more types of tin may be used in a single layer or a multilayer structure. For example, an alloy or The conductor may be a compound, and may be an aluminum-containing conductor, a copper and titanium-containing conductor, a copper and Conductors containing indium, tin and oxygen; conductors containing titanium and nitrogen A conductor containing elements may also be used.

[0097] Next, a resist or the like is formed on the conductor, and the conductor 416a and And a conductor 416b is formed (see FIG. 4(A) and FIG. 4(B)).

[0098] Next, fluorine may be added to the semiconductor 406a and the semiconductor 406b. This can be done by using the conductor 416a and the conductor 416b as a mask. In the semiconductor 406a and the semiconductor 406b, the conductor 416a and the conductor 416b The non-overlapping regions can be selectively doped with fluorine.

[0099] In addition, for example, by reducing the thickness of the conductors 416a and 416b, In the conductor 406a and the semiconductor 406b, the conductor 416a and the conductor 416b overlap. Fluorine may be added to the overlapping region. The semiconductor 406a has a different fluorine concentration in the area overlapping with the semiconductor 6b and the area not overlapping with the semiconductor 406a. For example, semiconductor 406a and semiconductor 406b can be formed. In FIG. 6b, the region overlapping with the conductor 416a and the conductor 416b is the conductor 416 The fluorine concentration is lower than that of a and the region that does not overlap with the conductor 416b.

[0100] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than or equal to 1×10 20 ions / cm 3 1 more ×10 22 ions / cm 3 This can be done as follows.

[0101] Here, for example, the conductor 413 is a gate electrode, the insulator 402 is a gate insulator, and the conductor 416 is a If a is a source electrode and conductor 416b is a drain electrode, the process is completed up to FIG. The transistor may have a Tom gate structure.

[0102] Next, the semiconductor 436c is formed. The semiconductor 436c is formed by a method such as sputtering or CVD. The method can be performed by using a method such as a deposition method, an MBE method, a PLD method, or an ALD method. Before the deposition of the semiconductor 406a, the semiconductor 406b, the conductor 416a, and the conductor 416b, The surface of the substrate may be etched. For example, the surface may be etched using a plasma containing a rare gas. After that, the semiconductor 436c can be formed without being exposed to the air. As a result, the semiconductor 406a, the semiconductor 406b, the conductor 416a, and the conductor 416b are formed. It is possible to reduce the inclusion of impurities in the interface with the semiconductor 436c. Impurities present in the film may be more diffusible than impurities in the film. By reducing the amount of foreign matter in the transistor, it is possible to provide stable electrical characteristics. do.

[0103] Next, fluorine may be added to the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c. It should be noted that all of the semiconductors 406a, 406b, and 436c are fluorine-doped. It is not necessary to add fluorine to any one or two layers.

[0104] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than or equal to 1×10 20 ions / cm 3 1 more ×10 22 ions / cm 3 This can be done as follows.

[0105] Next, the insulator 442 is formed. The insulator 442 is formed by a sputtering method, a CVD method, or the like. This can be done by using MBE, PLD, ALD, or the like. The deposition of the insulating film 442 and the deposition of the insulating film 443 are performed in succession without exposure to the air. Furthermore, the incorporation of impurities into the interface can be reduced.

[0106] The insulator 442 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 442 may be made of aluminum oxide, oxide film, or a laminate. magnesium oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0107] Next, the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c are In addition, the semiconductor 406a, the semiconductor 406b, and the semiconductor 436 It is not necessary to add fluorine to all of c. Fluorine may be added to one or two layers. Fluorine may also be added to the insulator 442.

[0108] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below Top 5×10 22 ions / cm 3 Less than or equal to 1×10 20 ions / cm 3 1 more ×10 22 ions / cm 3 This can be done as follows.

[0109] Next, the conductor 434 is formed. The conductor 434 is formed by a sputtering method, a CVD method, or the like. This can be done by using the MBE method, the PLD method, the ALD method, or the like. The deposition of the conductive material 434 and the deposition of the conductive material 435 are performed successively without exposure to the atmosphere. Furthermore, the incorporation of impurities into the interface can be reduced (see FIG. 5(A) and FIG. 5(B)). ).

[0110] The conductor 434 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. nium, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Lithium, Zirconium, Molybdenum, Ruthenium, Silver, Indium, Tin, Tantalum and A conductor containing one or more of tungsten and silicon may be used in a single layer or a multilayer structure. For example, Conductors that may be alloys or compounds include aluminum-containing conductors, copper- and titanium-containing conductors, etc. , conductors containing copper and manganese, conductors containing indium, tin and oxygen, conductors containing titanium and Conductors containing nitrogen may also be used.

[0111] Next, a resist or the like is formed on the conductor 434, and the conductor 40 is processed using the resist. In addition, the resist or conductor 404 is used to process the insulator 442, In addition, the resist, the conductor 404, or the insulator 412 is used to form a semiconductor. The conductor 436c is processed to form the semiconductor 406c. The conductive body 404 and the conductive body 405 have the same shape when viewed from above, but the conductive body 404 and the conductive body 405 are the same shape when viewed from above, but the conductive body 404 and the conductive body 405 have ... The resistor is not limited to this shape. For example, the semiconductor 406c and the insulator 412 The conductor 404 may be processed using a different resist. For example, the insulator 412 may be formed. Then, a conductor that will become the conductor 404 may be formed, or the conductor 404 may be formed and then the insulating layer may be formed. A resist or the like may be separately formed on the insulator that will become the insulating body 412. 406c may be connected to an adjacent transistor or the like (FIGS. 6(A) and 6(B)). See B). ).

[0112] Next, an insulator film may be formed. The insulator film may be formed by a sputtering method, a CVD method, or an MBE method. The method can be carried out by using a PLD method, an ALD method, or the like.

[0113] Examples of the insulator include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in a single layer or in The insulator is preferably aluminum oxide, silicon nitride oxide, Silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, acid Insulators containing neodymium oxide, hafnium oxide or tantalum oxide are used in single or multilayered configurations. Just use it.

[0114] The insulator preferably functions as a barrier layer. The insulator has a function of blocking hydrogen. It is preferable that the insulating material 412 has a higher ability to block oxygen and / or hydrogen than the insulating material 412. It is nice.

[0115] Through the above steps, the transistor 100 of one embodiment of the present invention can be manufactured.

[0116] As described above, by adding fluorine to the channel formation region of the semiconductor, It is possible to compensate for oxygen vacancies. In addition, oxygen vacancies can be compensated for by fluorine, which forms stable bonds. To provide a transistor having stable and good electrical characteristics by compensating for the above. can be done.

[0117] As shown in FIG. 6B, the semiconductor 40 6b can be electrically surrounded (the electric field generated by the conductor electrically surrounds the semiconductor The structure of the transistor that surrounds the Therefore, the entire semiconductor 406b (upper surface, lower surface, and side surface) In the s-channel structure, the source-drain of the transistor A large current can be passed between the gates, and the current when conductive (on-state current) can be increased.

[0118] In addition, when the transistor has an s-channel structure, the semiconductor 406b is also Therefore, the thicker the semiconductor 406b, the larger the channel formation region. That is, the thicker the semiconductor 406b, the higher the on-state current of the transistor. In addition, the thicker the semiconductor 406b, the greater the proportion of the region with high carrier controllability. Therefore, the subthreshold swing value can be reduced. For example, 10 nm or more. Preferably, the thickness is 20 nm or more, more preferably, 40 nm or more, and even more preferably, 100 nm or more. However, the productivity of the semiconductor device is low. Therefore, for example, the thickness is set to 300 nm or less, preferably 200 nm or less, and more preferably Preferably, the semiconductor 406b has a region with a thickness of 150 nm or less.

[0119] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, a semiconductor having the transistor can be The device can be a highly integrated, high-density semiconductor device. The transistor has a channel length of preferably 40 nm or less, more preferably 30 nm or less. More preferably, the region is 20 nm or less, and the transistor preferably has a channel width of Preferably, the thickness is 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. has.

[0120] Note that the conductor 413 is not necessarily required (see FIG. 7A). In addition, the semiconductor 406c may protrude from the conductor 404 (see FIG. 7B). The insulator 442 and the semiconductor 436c do not necessarily need to be processed (see FIG. 7C). In addition, the width of the conductor 413 in the A1-A2 cross section is larger than that of the semiconductor 406b. In addition, the conductor 413 and the conductor 404 may be connected through an opening. The conductor 404 may be provided (see FIG. 8(B)). Also, the conductor 404 may not be provided (see FIG. 8(C)). )reference.).

[0121] <Semiconductors> As shown in this embodiment, the semiconductor 406a and the semiconductor 406b are disposed above and below the semiconductor 406b. By providing 6c, the electrical characteristics of the transistor can be improved in some cases.

[0122] The semiconductor 406b is, for example, an oxide semiconductor containing indium. For example, the inclusion of indium increases carrier mobility (electron mobility). 406b preferably contains the element M. The element M is preferably aluminum, gallium, or the like. , yttrium, or tin. Other elements that can be used for M include ho, Uranium, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, la Examples include tantalum, cerium, neodymium, hafnium, and tungsten. In some cases, the element M may be a combination of the above elements. For example, it is an element with a high bond energy with oxygen. Alternatively, the element M may be, for example, an element having an energy density higher than that of an oxide semiconductor. It is an element that has a function of increasing the gap. In addition, the semiconductor 406b preferably contains zinc. When an oxide semiconductor contains zinc, it may be easily crystallized.

[0123] However, the semiconductor 406b is not limited to an oxide semiconductor containing indium. 6b is a zinc-free oxide such as zinc tin oxide or gallium tin oxide. Oxide semiconductors containing lead, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. That's okay.

[0124] The semiconductor 406b is made of, for example, an oxide having a large energy gap. The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 The excitation voltage is preferably from 3 eV to 3.5 eV, and more preferably from 3 eV to 3.8 eV.

[0125] For example, the semiconductor 406a and the semiconductor 406c contain oxygen other than that constituting the semiconductor 406b. The semiconductor 406b is an oxide semiconductor composed of one or more elements. The semiconductor 406a and the semiconductor 406 are made of one or more elements other than oxygen. c is formed, the interface between the semiconductor 406a and the semiconductor 406b and the semiconductor 406b Defect levels are unlikely to be formed at the interface between the semiconductor 406c and the semiconductor 406b.

[0126] The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c each contain at least indium. When the semiconductor 406a is an In-M-Zn oxide, the sum of In and M is preferably When 100 atomic %, In is preferably less than 50 atomic % and M is preferably less than 50 atomic %. More preferably, In is less than 25 atomic % and M is 75 atomic % or more. When the semiconductor 406b is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, In is preferably 25 atomic %. %, M is less than 75 atomic %, and more preferably In is 34 atomic % The semiconductor 406c is In-M-Zn In the case of oxides, when the sum of In and M is 100 atomic %, In is preferably 50 atomic %, M is higher than 50 atomic %, and more preferably In is 2 5 atomic % or less, and M is higher than 75 atomic %. However, the same oxide as the semiconductor 406a may be used. In addition, the semiconductor 406c may not necessarily contain indium. For example, The semiconductor 406a and / or the semiconductor 406c may be gallium oxide. The number of atoms of each element contained in the body 406a, the semiconductor 406b, and the semiconductor 406c is simply It does not have to be an integer ratio.

[0127] The semiconductor 406b is an oxide having a higher electron affinity than the semiconductors 406a and 406c. For example, the semiconductor 406b is made of a material selected from the semiconductors 406a and 406c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. Preferably, the oxide has a larger electric field strength by 0.15 eV or more and 0.4 eV or less. Electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0128] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor 406c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and Preferably, the ratio is 90% or more.

[0129] In this way, a transistor in which the semiconductor 406a and the semiconductor 406c are arranged above and below the semiconductor 406b is When a gate voltage is applied to the transistor, the semiconductor 406a, the semiconductor 406b, and the semiconductor A channel is formed in the semiconductor 406b having a large electron affinity among the layers 406c.

[0130] Here, between the semiconductor 406a and the semiconductor 406b, In addition, between the semiconductor 406b and the semiconductor 406c, The semiconductor 406b may have a mixed region of the semiconductor 406c. Therefore, the level density of the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c is low. In the laminate, the energy changes continuously near each interface (also called continuous junction). (See FIG. 9.) The semiconductor 406a, the semiconductor 406b, and In the semiconductor 406c, the interfaces between the two may not be clearly distinguishable.

[0131] At this time, the electrons flow into the semiconductor 406b, not into the semiconductor 406a and the semiconductor 406c. As described above, the electrons move mainly through the interface between the semiconductor 406a and the semiconductor 406b. The defect density at the interface between the semiconductor 406b and the semiconductor 406c is By lowering the concentration, the movement of electrons in the semiconductor 406b is less hindered, The on-state current of the transistor can be increased.

[0132] The on-current of a transistor can be increased by reducing the factors that inhibit the movement of electrons. For example, if there are no factors that impede the movement of electrons, it is assumed that electrons will move efficiently. The movement of electrons is also hindered, for example, when the channel formation region has large physical irregularities. will be done.

[0133] In order to increase the on-current of the transistor, for example, the upper or lower surface of the semiconductor 406b (The surface to be formed, the semiconductor 406a in this case) is the root mean square of the area of ​​1 μm × 1 μm Root (RMS: Root Mean Square) roughness is less than 1 nm, preferably 0.6 nm or less, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in an area of ​​1 μm x 1 μm is less than 1 nm. Preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm m. Also, the maximum height difference (PV) in the range of 1 μm x 1 μm ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably The RMS roughness, Ra and PV are measured by SII Nanotech. The measurement was performed using a scanning probe microscope system SPA-500 manufactured by Knology Co., Ltd. It is possible.

[0134] In addition, in order to increase the on-state current of the transistor, the thickness of the semiconductor 406c is as small as possible. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the semiconductor 406c may be a semiconductor having a channel region. The semiconductor 406b is then subjected to a thermal treatment using an element other than oxygen (such as hydrogen or silicon) that constitutes the adjacent insulator. The semiconductor 406c has a function of blocking the intrusion of certain substances. For example, the thickness is 0.3 nm or more, preferably 1 nm or more. More preferably, the semiconductor 406c has a region having a thickness of 2 nm or more. The semiconductor 406c is formed by: It is preferable that the material has oxygen blocking properties.

[0135] In order to increase reliability, the semiconductor 406a is thick and the semiconductor 406c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. The semiconductor 406a may have a region with a thickness of 60 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor 406a, the interface between the adjacent insulator and the semiconductor 406a Therefore, the distance to the semiconductor 406b where the channel is formed can be increased. Since the productivity of the device may decrease, for example, the thickness is set to 200 nm or less, preferably 120 nm or less. The semiconductor 406a may have a thickness of 80 nm or less, and more preferably a thickness of 80 nm or less. stomach.

[0136] For example, a secondary ion mass spectrometry (SIMS) method is used to measure the distance between the semiconductor 406b and the semiconductor 406a. Secondary Ion Mass Spectrometry (1×1 0 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below, preferably 1×1 0 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 More preferably, 1×10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 Silicon concentration below In addition, a region between the semiconductor 406b and the semiconductor 406c is 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 The following are the preferred Or 1×10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 The following is further Preferably 1 x 10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 below The silicon concentration in the region is .gtoreq..gtoreq.1.

[0137] In order to reduce the hydrogen concentration in the semiconductor 406b, the semiconductor 406a and the semiconductor 406 It is preferable to reduce the hydrogen concentration in the semiconductor 406a and the semiconductor 406c. In, 1×10 16 atoms / cm 3 More than 2×10 20 atoms / cm 3 below, Preferably 1 x 10 16 atoms / cm 3 5×10 or more 19 atoms / cm 3below, More preferably, 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below or less, and more preferably 1×10 16 atoms / cm 3 5×10 or more 18 atoms / c m 3 In addition, in order to reduce the nitrogen concentration in the semiconductor 406b, For this reason, it is preferable to reduce the nitrogen concentration in the semiconductor 406a and the semiconductor 406c. 06a and semiconductor 406c are 1×10 15 atoms / cm 3 Below Top 5×10 19 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 Below Top 5×10 18 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 Less than 1×10, more preferably 15 atoms / cm 3 5×10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0138] The three-layer structure described above is an example. For example, a two-layer structure without semiconductor 406a or semiconductor 406c Alternatively, the semiconductor 406a may be disposed above or below the semiconductor 406c. Above or below the semiconductor 406, a semiconductor 406a, a semiconductor 406b, and a semiconductor 406c are illustrated. Alternatively, the semiconductor 406a may have a four-layer structure having any one of the above semiconductors. , at least two of the following locations: under the semiconductor 406a, over the semiconductor 406c, and under the semiconductor 406c In addition, any of the semiconductors exemplified as semiconductor 406a, semiconductor 406b, and semiconductor 406c Alternatively, it may have an n-layer structure (n is an integer of 5 or more) having one or more of these layers.

[0139] <Structure of oxide semiconductors> The structure of an oxide semiconductor will be described below.

[0140] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Examples of the oxide semiconductor include a conductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor.

[0141] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0142] <caac-os> First, we will explain CAAC-OS. It is also called an oxide semiconductor with aligned nanocrystals. can.

[0143] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0144] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0145] The following describes the CAAC-OS observed by TEM. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0146] An enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 10(A) is shown in FIG. 10(B). From FIG. 10(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0147] As shown in Figure 10(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 10(B) and Figure 10(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the inclination of the The zeolites can also be referred to as nanocrystals (nc).

[0148] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 10(D)). The inclination between the pellets observed in FIG. 10(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0149] FIG. 11(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in Figure 11(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 11(B), Fig. 11(C), and Fig. 11(D), respectively. 11(D). From FIG. 11(B), FIG. 11(C) and FIG. 11(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0150] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the structure is analyzed using the out-of-plane method, the results are as shown in Figure 12(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0151] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0152] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. 12(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is In the case of scanning, as shown in FIG. 12(C), the peaks attributable to the crystal plane equivalent to the (110) plane Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0153] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in FIG. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. The first ring in FIG. 13(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and other factors. The second ring in Figure 13(B) This is thought to be due to the (110) plane, etc.

[0154] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects include impurity-induced defects and oxygen vacancies. C-OS can be said to be an oxide semiconductor with a low impurity concentration. It can also be said that the oxide semiconductor has few oxygen vacancies.

[0155] Impurities contained in an oxide semiconductor can act as carrier traps or carrier generation sources. In addition, oxygen vacancies in an oxide semiconductor may become carrier traps or may cause hydrogen By capturing atoms, they can become a carrier generation source.

[0156] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0157] In addition, an oxide semiconductor with a low density of defect states (few oxygen vacancies) can reduce the carrier density. Such an oxide semiconductor can be obtained by using a high-purity intrinsic or substantially high-purity intrinsic oxide. CAAC-OS has a low impurity concentration and a low density of defect states. It is easy to obtain a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. A transistor using C-OS has electrical characteristics in which the threshold voltage is negative (normal Also, it is rare for the acid to become "on". The oxide semiconductor has fewer carrier traps. The charge takes a long time to be discharged and behaves like a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect state densities are On the other hand, transistors using CAAC-OS may have unstable electrical characteristics. The resulting transistor has small fluctuations in electrical characteristics and is highly reliable.

[0158] In addition, because the density of defect states in CAAC-OS is low, the capacitive coupling generated by light irradiation can be suppressed. Therefore, the transistor using CAAC-OS is less likely to be captured by the defect level. The electrical characteristics of a transistor vary little when exposed to visible or ultraviolet light.

[0159] <Microcrystalline oxide semiconductor> Next, a microcrystalline oxide semiconductor will be described.

[0160] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often found. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline- The nc-OS is called the "High Resolution Oxide Semiconductor." In some cases, the grain boundaries cannot be clearly seen in the TEM images. Therefore, in the following, we will refer to the pellets in nc-OS as the pellets of the same origin. The crystalline part of S is sometimes called a pellet.

[0161] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peaks were detected. Also, for nc-OS, the probe diameter (e.g. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size. When the electron diffraction pattern is applied to the nc-OS, a spot is observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a patchy region.

[0162] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0163] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. Therefore, nc-OS is The defect level density is higher than that of AC-OS.

[0164] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0165] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystal parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0166] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0167] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction is performed, no spots are observed, and only a halo pattern is observed. It is measured.

[0168] There are various views on amorphous structures. For example, A structure that does not have a completely amorphous structure is called a completely amorphous structure. In addition, although it does not have long-range order, the order of the nearest neighbors from a given atom is called a "cture." A structure that has order within the range of atoms or the second nearest neighbors is called an amorphous structure. Therefore, according to the strictest definition, an oxide that has even a slight degree of order in its atomic arrangement is Amorphous oxide semiconductors cannot be called amorphous oxide semiconductors. Therefore, an oxide semiconductor having a crystal part cannot be called an amorphous oxide semiconductor. Therefore, for example, the CAAC-OS and the nc-OS can be used as an amorphous oxide semiconductor or It cannot be called a completely amorphous oxide semiconductor.

[0169] <Amorphous-like oxide semiconductor> Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called

[0170] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portion can be identified.

[0171] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0172] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0173] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0174] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0175] Figure 14 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 14, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 14, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0176] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0177] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0178] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0179] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be determined by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0180] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a semiconductor and a CAAC-OS.

[0181] (Embodiment 2) In this embodiment mode, a transistor having a shape partially different from that of the transistor shown in the first embodiment mode is used. The method for producing the capacitor will be described below.

[0182] <Transistor 2> Figure 15(A), Figure 16(A), Figure 17(A), Figure 18(A), Figure 19(A), Figure 20(A 21A and 21B are top views illustrating a method for manufacturing a transistor. In FIG. 1, dashed lines F1-F2 and F3-F4 are drawn, and cross-sectional views corresponding thereto are shown. 15(B), Fig. 16(B), Fig. 17(B), Fig. 18(B), Fig. 19(B), Fig. 20(B) and shown in FIG.

[0183] First, prepare the substrate 500. For the substrate 500, refer to the description of the substrate 400.

[0184] Next, a conductive film is formed. The conductive film may be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be carried out by using a PLD method, an ALD method, or the like.

[0185] Next, a resist or the like is formed on the conductor, and the conductor 513 is formed by processing using the resist. Complete.

[0186] Next, an insulator is formed. The insulator is formed by a method such as sputtering, CVD, MBE or the like. This can be carried out by using a PLD method, an ALD method, or the like.

[0187] Next, an edge is formed from the upper surface of the insulator toward the lower surface thereof so as to be parallel to the lower surface of the substrate 500. By performing the etching, the conductor 513 is exposed and the insulator 503 is formed (FIG. 15(A)). 15B.) By forming the insulator 503 in this manner, the conductor The height of the upper surface of 513 and the height of the upper surface of the insulator 503 can be made approximately the same. Therefore, shape defects in the subsequent steps can be suppressed.

[0188] Next, the insulator 502 is formed (see FIG. 16(A) and FIG. 16(B)). The deposition of 2 is performed by sputtering, CVD, MBE, PLD, ALD, etc. For the insulator 502, refer to the description of the insulator 402.

[0189] Next, the semiconductor 536a is formed. The semiconductor 536a is formed by a method such as sputtering or CVD. The method may be, for example, a deposition method, an MBE method, a PLD method, or an ALD method. For details, refer to the description of the semiconductor that becomes the semiconductor 406a.

[0190] Next, oxygen may be added to the semiconductor 536a so that the semiconductor 536a contains excess oxygen. The doping is carried out, for example, by ion implantation at an acceleration voltage of 2 kV to 10 kV, and a dose of Amount 5 x 10 14 ions / cm 2 More than 1×10 17 ions / cm 2 If you do this as follows: good.

[0191] Next, fluorine may be added to the semiconductor 536a. The order of the addition of fluorine to the semiconductor 536a and the addition of fluorine to the semiconductor 536b may be reversed.

[0192] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than or equal to 1×10 20 ions / cm 3 1 more ×10 22 ions / cm 3 This can be done as follows.

[0193] Next, the semiconductor 536b is formed. The semiconductor 536b is formed by a method such as sputtering or CVD. The method may be, for example, the MBE method, the PLD method, or the ALD method. For details, refer to the description of the semiconductor that becomes the semiconductor 406b. The deposition of the semiconductor 536b and the film 536c are performed successively without exposure to the atmosphere. This can reduce the inclusion of impurities at the interface.

[0194] Next, it is preferable to carry out a heat treatment. The heat treatment is preferably carried out at a temperature of 250° C. or higher and 650° C. or lower. The temperature is preferably 450° C. to 600° C., more preferably 520° C. to 570° C. Heat treatment should be performed in an inert gas atmosphere or with an oxidizing gas concentration of 10 ppm or more, or 1% or more. The heat treatment is carried out in an atmosphere containing at least 10% of fluorine. The heat treatment may be carried out under reduced pressure. The treatment is carried out by heating in an inert gas atmosphere, followed by one minute of oxidizing gas to replenish the desorbed oxygen. The heat treatment may be performed in an atmosphere containing 0 ppm or more, 1% or more, or 10% or more. The crystallinity of the semiconductor 536a and the semiconductor 536b can be increased by the above-mentioned process, and hydrogen, water, etc. can be eliminated. What impurities can be removed?

[0195] Next, fluorine may be added to the semiconductor 536a and the semiconductor 536b. Heat treatment of the semiconductor 536a and the semiconductor 536b, and The order of the addition of fluorine and the addition of fluorine may be reversed.

[0196] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below Top 5×10 22 ions / cm 3 Less than or equal to 1×10 20 ions / cm 3 1 more ×10 22 ions / cm 3 This can be done as follows.

[0197] Next, a conductive film is formed. The conductive film may be formed by a sputtering method, a CVD method, an MBE method, or the like. The deposition can be performed by using a PLD method, an ALD method, or the like. Please refer to the description of the conductor that becomes conductor 416b.

[0198] Next, a resist or the like is formed on the conductor, and the conductor 516a and And a conductor 516b is formed (see FIG. 17(A) and FIG. 17(B)).

[0199] Next, fluorine may be added to the semiconductor 536a and the semiconductor 536b. This can be done by using the conductors 516a and 516b as a mask. In the semiconductor 536a and the semiconductor 536b, the conductor 516a and the conductor 516b The non-overlapping regions can be selectively doped with fluorine.

[0200] In addition, for example, by reducing the thickness of the conductors 516a and 516b, The conductor 536a and the semiconductor 536b overlap with the conductor 516a and the conductor 516b. Fluorine may be added to the overlapping region. The semiconductor 536a has a different fluorine concentration in the area overlapping with the semiconductor 6b and the area not overlapping with the semiconductor 536a. For example, semiconductor 536a and semiconductor 536b can be formed. In the case of conductor 516b, the region overlapping with conductor 516a and conductor 516b is the conductor 516 The fluorine concentration is lower than that of a and the region that does not overlap with the conductor 516b.

[0201] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than or equal to 1×10 20 ions / cm 3 1 more ×10 22 ions / cm 3 This can be done as follows.

[0202] Next, a resist or the like is formed on the semiconductor 536b, and the resist, the conductor 516a, and the conductor The semiconductor 506b and the semiconductor 506a are formed by processing using the dielectric 516b (FIG. 18). See Figure 18(A) and Figure 18(B).

[0203] The conductor 516a, the conductor 516b, the semiconductor 506a, and the semiconductor 506b are formed by Alternatively, after the conductor is formed, the following method may be used.

[0204] First, a resist or the like is formed on the conductor, and the resist is used to process the conductor 516 and the semiconductor A conductor 506b and a semiconductor 506a are formed (see FIGS. 21(A) and 21(B). At this time, the semiconductor 506b and the semiconductor 506a are formed by removing the resist and then applying a conductive 516 may be used for processing.

[0205] Next, a resist or the like is formed on the conductor 516, and the conductor 51 is processed using the resist. 6a and conductor 516b are formed (see FIG. 18(A) and FIG. 18(B)).

[0206] Next, the semiconductor 536c is formed. The semiconductor 536c is formed by a method such as sputtering or CVD. The method can be performed by using a method such as a deposition method, an MBE method, a PLD method, or an ALD method. Please refer to the description of the semiconductor 436c.

[0207] Next, the insulator 542 is formed. The insulator 542 is formed by a sputtering method, a CVD method, or the like. This can be done by using the MBE method, the PLD method, the ALD method, or the like. Please refer to the description of edge 442.

[0208] Next, the semiconductor 506a, the semiconductor 506b, and the semiconductor 536c are In addition, fluorine may be added to the semiconductor 506a, the semiconductor 506b, and the semiconductor 536. It is not necessary to add fluorine to all of c. Fluorine may be added to one or two layers. Also, fluorine may be added to the insulator 542.

[0209] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below Top 5×10 22 ions / cm 3 Less than or equal to 1×10 20 ions / cm 3 1 more ×10 22 ions / cm 3 This can be done as follows.

[0210] Next, a conductor 534 is formed (see FIG. 19(A) and FIG. 19(B)). The film formation of 4 is performed by sputtering, CVD, MBE, PLD, ALD, etc. The conductor 534 can be described in the same manner as the conductor 434.

[0211] Next, a resist or the like is formed on the conductor 534, and the conductor 50 is processed using the resist. In addition, the resist or conductor 504 is used to process the insulator 542, In addition, the resist, the conductor 504, or the insulator 542 is used to form a semiconductor. The conductor 536c is processed to form a semiconductor 506c (see FIG. 20(A) and FIG. 20(B)). Here, the semiconductor 506c, the insulator 512, and the conductor 504 are shown as viewed from above. Sometimes they are processed to have a similar shape, but they are not limited to this shape. For example, the insulator 512 and the conductor 504 may be processed using different resists. After forming the edge 512, a conductor that will become the conductor 504 may be formed, or the conductor 504 may be formed. After forming the insulating layer 4, a resist or the like may be formed separately on the insulating layer that will become the insulating layer 512. Also, for example, the semiconductor 506c may be connected to an adjacent transistor.

[0212] Next, an insulator film may be formed. The insulator film may be formed by a sputtering method, a CVD method, or an MBE method. The method can be carried out by using a PLD method, an ALD method, or the like.

[0213] Examples of the insulator include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in a single layer or in The insulator is preferably aluminum oxide, silicon nitride oxide, Silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, acid Insulators containing neodymium oxide, hafnium oxide or tantalum oxide are used in single or multilayered configurations. Just use it.

[0214] The insulator preferably functions as a barrier layer. and / or has a function of blocking hydrogen. Alternatively, the insulator may be, for example, insulator 502 Alternatively, it is preferable that the insulating material 512 has a higher ability to block oxygen and / or hydrogen than the insulating material 512. I wish.

[0215] Through the above steps, a transistor according to one embodiment of the present invention can be manufactured.

[0216] As described above, by adding fluorine to the channel formation region of the semiconductor, It is possible to compensate for oxygen vacancies. In addition, oxygen vacancies can be compensated for by fluorine, which forms stable bonds. To provide a transistor having stable and good electrical characteristics by compensating for the above. can be done.

[0217] As shown in FIG. 20B, the transistor has an s-channel structure. The electric field from the conductor 504 and the conductor 513 acts on the conductor 51 at the side of the semiconductor 506b. This structure is unlikely to be obstructed by conductor 6a and conductor 516b.

[0218] Note that the conductor 513 is not necessarily required (see FIG. 22A). Alternatively, the semiconductor 506c may protrude from the conductor 504 (see FIG. 22B). ). In addition, the insulator 542 and the semiconductor 536c do not need to be processed (see FIG. 22C). In addition, even if the width of the conductor 513 in the F1-F2 cross section is larger than that of the semiconductor 506b, (See FIG. 23(A)). In addition, the conductor 513 and the conductor 504 are connected through the opening. The conductor 504 may be omitted (see FIG. 23B). See (C). ).

[0219] (Embodiment 3) In this embodiment, a circuit of a semiconductor device using a transistor according to one embodiment of the present invention An example of the above will be described.

[0220] <CMOSインバータ> The circuit diagram shown in FIG. 24A includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected. The figure shows the configuration of an S inverter. An n-channel transistor 2100 has an oxide semiconductor It is preferable to use transistors having conductors, thereby forming a CMOS inverter. The power consumption in the circuit can be reduced.

[0221] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 24B is that of a transistor 2100 and a transistor 2200. The source and drain of each transistor are connected. It can function as a so-called CMOS analog switch. The transistor 2100 is preferably a transistor including an oxide semiconductor.

[0222] <Semiconductor device structure 1> 25 is a cross-sectional view of the semiconductor device corresponding to FIG. 24(A). The transistor 2200 includes a transistor 2100. The transistor 2100 is disposed above the transistor 2200. 20 is used as an example, a semiconductor device according to one embodiment of the present invention may be used as the semiconductor device. The body device is not limited to this. For example, the body device shown in FIG. 6, FIG. 7, FIG. 8, FIG. 22 or FIG. The transistor 2100 may be a transistor such as that shown in FIG. Therefore, for the transistor 2100, the above-mentioned transistor description will be used as appropriate. I will take part.

[0223] A transistor 2200 shown in FIG. 25 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472 a in the semiconductor substrate 450 and a It has a region 472b, an insulator 462, and a conductor 454.

[0224] In transistor 2200, regions 472a and 472b are source and The insulator 462 functions as a gate insulator. The conductor 454 also functions as a gate electrode. The resistance of the channel forming region can be controlled by applying a potential to the body 454. That is, the electric potential applied to the conductor 454 causes a conduction line between the region 472a and the region 472b. The non-conduction can be controlled.

[0225] The semiconductor substrate 450 may be, for example, a single semiconductor substrate such as silicon or germanium. or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A compound semiconductor substrate made of, for example, gallium oxide may be used. A single crystal silicon substrate is used as the substrate 450 .

[0226] The semiconductor substrate 450 is a semiconductor substrate having impurities that impart n-type conductivity. The semiconductor substrate 450 is a semiconductor substrate having an impurity that imparts p-type conductivity. In that case, the region that will become the transistor 2200 is given n-type conductivity. Alternatively, even if the semiconductor substrate 450 is an i-type, That's fine.

[0227] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The on-characteristics of the transistor 2200 can be improved.

[0228] Regions 472a and 472b are regions having impurities that impart p-type conductivity. In this manner, transistor 2200 constitutes a p-channel transistor.

[0229] Note that transistor 2200 is isolated from adjacent transistors by regions 460, etc. The region 460 is an insulating region.

[0230] The semiconductor device shown in FIG. 25 includes an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b. , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and insulator It has an edge 490 , an insulator 492 , and an insulator 494 .

[0231] The insulator 464 is disposed on the transistor 2200. The insulator 466 is disposed on the insulator 4 64. Insulator 468 is disposed on insulator 466. Insulator 4 90 is disposed on the insulator 468. Also, the transistor 2100 is disposed on the insulator 490. Also, an insulator 492 is disposed on the transistor 2100. Also, an insulator 4 94 is disposed on the insulator 492 .

[0232] The insulator 464 has an opening reaching the region 472a, an opening reaching the region 472b, and a conductive The openings each include a conductor 480a, a conductor 480b, and an opening that reaches the conductor 454. The conductive body 480b or the conductive body 480c is embedded therein.

[0233] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0234] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0235] The insulator 490 has an opening overlapping the channel formation region of the transistor 2100 and a conductive The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. is.

[0236] The conductor 474a may function as a gate electrode of the transistor 2100. Alternatively, for example, a constant potential may be applied to the conductor 474a to turn on the transistor 210. Alternatively, the electrical properties of the conductor 474 may be controlled, such as the threshold voltage of 0. a and the conductor 404 serving as the gate electrode of the transistor 2100 are electrically This can increase the on-state current of the transistor 2100. In addition, since the punch-through phenomenon can be suppressed, the transistor 210 The electrical characteristics in the saturation region of 0 can be stabilized.

[0237] Also, the insulator 492 is connected to one of the source and drain electrodes of the transistor 2100. An opening through one conductor 516b to conductor 474b and a transistor 2100 An opening reaching the conductor 516a, which is the other of the source electrode or drain electrode of the transistor, An opening reaching the conductor 504, which is the gate electrode of the transistor 2100, and an opening reaching the conductor 474c The openings are provided with a conductor 496a and a conductor 496b. , a conductor 496c or a conductor 496d is embedded in each opening. may further pass through any of the components such as transistor 2100.

[0238] The insulator 494 has an opening that reaches the conductor 496a, and a conductor 496b and a The opening reaches the conductor 496d, and the opening reaches the conductor 496c. The conductive body 498a, the conductive body 498b, and the conductive body 498c are embedded in the conductive body 498a, the conductive body 498b, and the conductive body 498c, respectively. do.

[0239] Insulator 464, insulator 466, insulator 468, insulator 490, insulator 492 and insulator Examples of 494 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in a single layer or in For example, the insulator 401 may be aluminum oxide, magnesium oxide, or the like. Nesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gas oxide Sodium oxide, Germanium oxide, Yttrium oxide, Zirconium oxide, Lanthanum oxide, Neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0240] Insulator 464, insulator 466, insulator 468, insulator 490, insulator 492 or insulator At least one of 494 has an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to add impurities such as hydrogen and oxygen to the vicinity of the transistor 2100. By disposing an insulator having a locking function, the electrical characteristics of the transistor 2100 are It can stabilize the sex.

[0241] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in a single layer or in a multilayer.

[0242] Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, Conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, Conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, The conductor 498a, the conductor 498b, and the conductor 498c may be, for example, boron, nitrogen, or the like. , oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt , nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium A conductor containing one or more of aluminum, silver, indium, tin, tantalum and tungsten is formed in a single layer. For example, the material may be an alloy or a compound, and aluminum may be used. Conductor containing copper and titanium Conductor containing copper and manganese Conductor containing indium Alternatively, a conductor containing tin and oxygen, or a conductor containing titanium and nitrogen may be used.

[0243] The semiconductor device shown in FIG. 26 is the same as the transistor 2200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The transistor 2200 is a Fin type. This increases the effective channel width, thereby improving the on-characteristics of the transistor 2200. In addition, the contribution of the electric field of the gate electrode can be increased, The off characteristics of the transistor 2200 can be improved.

[0244] 27 is a semiconductor device in which the transistor 2200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 200 is provided on a semiconductor substrate 450 which is an SOI substrate. 1 shows a structure in which region 456 is separated from semiconductor substrate 450 by insulator 452. By using an SOI substrate as the conductive substrate 450, punch-through phenomenon and the like can be suppressed. Therefore, the off-state characteristics of the transistor 2200 can be improved. The insulator 452 may be formed by insulating a portion of the semiconductor substrate 450. For example, the insulator 452 can be made of silicon oxide.

[0245] The semiconductor device shown in FIG. 25 to FIG. 27 is a p-channel transistor formed on a semiconductor substrate. By fabricating a MOSFET and fabricating an n-channel transistor above it, the area occupied by the device is reduced. In other words, the integration density of the semiconductor device can be increased. A p-channel transistor and a p-channel transistor were fabricated using the same semiconductor substrate. Since the process can be simplified compared to the conventional method, the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. The transistor is in the LDD (Lightly Doped Drain) region, shallow trench In some cases, complex processes such as ch-structure and distortion design can be omitted. Compared to manufacturing transistors using a semiconductor substrate, the productivity and yield are improved. It may be possible to reduce the

[0246] <Storage device 1> A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied FIG. 28 shows an example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written. As shown in.

[0247] The semiconductor device shown in FIG. 28A includes a transistor 3200 using a first semiconductor and a The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 can be any of the transistors described above.

[0248] The transistor 3300 is preferably a transistor having a low off-state current. For example, a transistor including an oxide semiconductor can be used as the transistor 00. The small off-state current of the capacitor 3300 allows for long-term recording at a specific node of the semiconductor device. The contents of the memory can be retained, i.e., no refresh operation is required, or This allows the frequency of refresh operations to be reduced significantly, resulting in a semiconductor with low power consumption. It becomes a body device.

[0249] In FIG. 28A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400 .

[0250] The semiconductor device shown in FIG. 28A can hold a gate potential of the transistor 3200. This property makes it possible to write, hold, and read information, as shown below. do.

[0251] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which the transistor 3300 is turned on. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the The signal is applied to a node FG that is electrically connected to one of the electrodes of the capacitance element 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). Charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) Then, the potential of the fourth wiring 3004 is applied to the transistor. By setting the potential at which the transistor 3300 is in a non-conducting state, the transistor 3300 is in a non-conducting state. As a result, charge is held at the node FG (retention).

[0252] Since the off-state current of the transistor 3300 is small, the charge of the node FG is retained for a long period of time. It will be held.

[0253] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, 3002 takes a potential according to the amount of charge held in the node FG. This is the transistor If 3200 is an n-channel type, a high-level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it in a "conductive state." Then, the potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential between For example, in a write, the charge applied to node FG can be determined. When a high-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 is in a "conducting state." On the other hand, the node FG When a low-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. It can be put out.

[0254] When memory cells are arranged in an array, the information of a desired memory cell is read. In order not to read information from other memory cells, A potential at which transistor 3200 is in a "non-conducting state" regardless of the charge applied to FG. , that is, V th_H A lower potential may be applied to the fifth wiring 3005. A potential at which transistor 3200 is "on" regardless of the charge applied to the FG. , that is, V th_L A higher potential may be applied to the fifth wiring 3005 .

[0255] <Storage device 2> The semiconductor device shown in FIG. 28B differs from the semiconductor device shown in FIG. 28A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information more easily.

[0256] The reading of data in the semiconductor device shown in FIG. When the capacitor 3300 is turned on, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and electric charges are redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is expressed by the capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0257] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 takes two states, V1 and V0 (V1>V0), , the potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V 1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (= It can be seen that it is higher than (CB×VB0+C×V0) / (CB+C)).

[0258] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0259] In this case, the transistor in which the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the driving circuit.

[0260] The above-described semiconductor device uses a transistor including an oxide semiconductor and has low off-state current. By doing so, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store the potential for a long period of time. It is possible to maintain the capacity.

[0261] In addition, the semiconductor device does not require a high voltage to write information, so that deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, injection of electrons into the floating gate Since electrons are not introduced or removed from the floating gate, there is no risk of degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the problem of a conventional nonvolatile memory. A semiconductor device with dramatically improved reliability, without the problematic limit on the number of times it can be rewritten Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This enables high-speed operation.

[0262] <Structure of semiconductor device 2> 29 is a cross-sectional view of the semiconductor device corresponding to FIG. 28(A). The semiconductor memory device includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are disposed above the transistor 3200. The transistor 3300 is arranged in the same manner as the transistor 2100 described above. In addition, the transistor 3200 may be the transistor shown in FIG. Please refer to the description of transistor 2200 in FIG. The case where the transistor 3200 is an n-channel transistor has been described. A transistor of a channel type may also be used.

[0263] A transistor 3200 shown in FIG. 29 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 472 a in the semiconductor substrate 450 and a It has a region 472b, an insulator 462, and a conductor 454.

[0264] The semiconductor device shown in FIG. 29 includes an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b. , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and conductor It has an insulator 498d, an insulator 490, an insulator 492, and an insulator 494.

[0265] An insulator 464 is disposed on the transistor 3200. Also, an insulator 466 is disposed on the insulator 4 64. Insulator 468 is disposed on insulator 466. Insulator 4 90 is disposed on the insulator 468. Also, the transistor 3300 is disposed on the insulator 490. Also, an insulator 492 is disposed on the transistor 3300. Also, an insulator 4 94 is disposed on the insulator 492 .

[0266] The insulator 464 has an opening reaching the region 472a, an opening reaching the region 472b, and a conductive The openings each include a conductor 480a, a conductor 480b, and an opening that reaches the conductor 454. The conductive body 480b or the conductive body 480c is embedded therein.

[0267] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0268] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0269] The insulator 490 has an opening overlapping the channel formation region of the transistor 3300 and a conductive The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. is.

[0270] The conductor 474a may function as a bottom gate electrode of the transistor 3300. Alternatively, for example, applying a constant potential to the conductor 474a may cause the transistor It is also possible to control electrical properties such as the threshold voltage of 3300. 474a is electrically connected to the conductor 404 which is the top gate electrode of the transistor 3300. This can increase the on-current of the transistor 3300. In addition, the punch-through phenomenon can be suppressed, so the transistor 3300 The electrical characteristics in the saturation region can be stabilized.

[0271] Also, the insulator 492 is connected to one of the source and drain electrodes of the transistor 3300. An opening through one conductor 516b to conductor 474b and a transistor 3300 The other of the source electrode or drain electrode is overlapped with a conductor 516a via an insulator 511. 514, which is the gate electrode of the transistor 3300, and 04 and the other of the source electrode or drain electrode of the transistor 3300. An opening extending through a certain conductor 516a to a conductor 474c. The portions are provided with conductors 496a, 496b, 496c, or conductors 496 However, each opening is filled with transistors 3300, etc. This may be via any of the components.

[0272] Further, the insulator 494 has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b. 496c, and an opening reaching conductor 496d. In addition, the openings are provided with a conductor 498a, a conductor 498b, a conductor 498c, or Electrical body 498d is embedded.

[0273] Insulator 464, insulator 466, insulator 468, insulator 490, insulator 492 or insulator At least one of 494 has an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to add impurities such as hydrogen and oxygen to the vicinity of the transistor 3300. By disposing an insulator having a locking function, the electrical characteristics of the transistor 3300 are It can stabilize the sex.

[0274] As the conductor 498d, for example, a conductor containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, magnesium, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, indium, yttrium, zirconium, molybdenum, ruthenium, silver, tin, tantalum, and tungsten may be used in a single layer or in a laminated form. For example, it may be an alloy or a compound, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium, and nitrogen, etc. may be used.

[0275] The source or drain of the transistor 3200 is electrically connected to the conductor 516b, which is one of the source electrode or drain electrode of the transistor 3300, via the conductor 480b, the conductor 478b, the conductor 476a, the conductor 474b, and the conductor 496c. Further, the conductor 454, which is the gate electrode of the transistor 3200, is electrically connected to the conductor 516a, which is the other of the source electrode or drain electrode of the transistor 3300, via the conductor 480c, the conductor 478c, the conductor 476b, the conductor 474c, and the conductor 496d.

[0276] The capacitor element 3400 has an electrode that is electrically connected to the other of the source electrode or drain electrode of the transistor 3300, the conductor 514, and the insulator 511. Note that since the insulator 511 can be formed through the same process as the insulator 512 that functions as the gate insulator of the transistor 3300, it may be preferable in that productivity can be improved. Also, the conductor 51 4, the same process as that for the conductor 504 functioning as the gate electrode of the transistor 3300 is performed. In some cases, it is preferable to use a layer formed through a thermal expansion process since the productivity can be increased.

[0277] For other structures, please refer to the descriptions in Figure 25 etc. as appropriate.

[0278] The semiconductor device shown in FIG. 30 is the same as the transistor 3200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The figure shows a case where the transistor 200 is a fin type. For details, refer to the description of the transistor 2200 shown in FIG. The transistor 2200 is a p-channel transistor. The transistor 3200 may be an n-channel transistor.

[0279] 31 is a semiconductor device having a transistor 3200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 200 is provided on a semiconductor substrate 450 which is an SOI substrate. The transistor 3200 provided on the semiconductor substrate 450 is shown in FIG. Please refer to the description of the transistor 2200. Note that in FIG. The case where the transistor 3200 is an n-channel transistor has been described. A transistor of a channel type may also be used.

[0280] <Imaging device> An imaging device according to an aspect of the present invention will be described below.

[0281] FIG. 32A is a plan view showing an example of an imaging device 200 according to one embodiment of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) have a plurality of pixels 211 arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 each include a plurality of The pixel 211 is connected to the pixel 211 and has a function of supplying a signal for driving the pixel 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 may be considered a part of the peripheral circuit.

[0282] The imaging device 200 preferably also includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0283] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the same substrate as the pixel portion 210. Also, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuits. The peripheral circuits are a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. Any one or more of these may be omitted.

[0284] As shown in FIG. 32B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel size in the row direction and the pixel size in the pixel area can be increased. The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the captured images.

[0285] <Pixel configuration example 1> The imaging device 200 has one pixel 211 that is composed of a plurality of sub-pixels 212. The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By this, it is possible to obtain information for realizing a color image display.

[0286] FIG. 33A is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 33(A) is provided with a color filter that transmits light in the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") receives light in the green (G) wavelength band. A subpixel 212 (hereinafter, also referred to as “subpixel 212G”) is provided with a color filter that transmits A subpixel 212 is provided with a color filter that transmits light in the blue (B) and blue (C) wavelength bands. (hereinafter, also referred to as "subpixel 212B"). The subpixel 212 has a photo sensor. It can be made to function.

[0287] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, in the nth line (n is an integer between 1 and p) The wiring 248 and the wiring 249 connected to the pixel 211 of and wiring 249[n]. For example, in the m-th column (m is an integer between 1 and q), The wiring 253 connected to the pixel 211 is referred to as wiring 253[m]. ), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is 53[m]R, the wiring 253 connected to the subpixel 212G is the wiring 253[m]G, and The wiring 253 connected to the subpixel 212B is indicated as wiring 253[m]B. , and are electrically connected to the peripheral circuits via the wiring.

[0288] In addition, the imaging device 200 detects color filters of adjacent pixels 211 that transmit light of the same wavelength band. The sub-pixels 212 provided with filters are electrically connected to each other via switches. FIG. 33B shows a sub-pixel 212 of a pixel 211 arranged in n rows and m columns, and 1 shows an example of a connection of a sub-pixel 212 of a pixel 211 arranged in the (n+1)th row and the (m)th column adjacent to the pixel 11. In FIG. 33B, the subpixel 212R arranged in the nth row and the mth column and the subpixel 212R arranged in the n+1th row and the mth column are The sub-pixels 212R arranged in the nth row and the mth column are connected via the switches 201. The subpixel 212G arranged in the n+1th row and the mth column is connected to the switch 202. In addition, the sub-pixel 212B arranged in the nth row and the mth column is connected via The sub-pixel 212B arranged in the second direction is connected via the switch 203.

[0289] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 211 may have three sub-pixels for detecting light of different wavelength bands. By providing 212, a full color image can be obtained.

[0290] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are provided. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Alternatively, pixel 211 may be used with pixel 212, or with cyan (C), yellow (Y In addition to the subpixel 212 provided with a color filter that transmits light of red (A) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. A single pixel 211 may include sub-pixels 211 for detecting light of four different wavelength bands. By providing the second filter 12, the color reproducibility of the captured image can be further improved.

[0291] Also, for example, in FIG. 33A, a sub-pixel 212 detects the red wavelength band, The ratio of the number of sub-pixels 212 that detect the blue wavelength band and the number of sub-pixels 212 that detect the blue wavelength band ( or light receiving area ratio) does not have to be 1:1:1. For example, The Bayer array may be used with red:green:blue=1:2:1. The light area ratio may be red:green:blue=1:6:1.

[0292] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the device 200.

[0293] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0294] In addition, ND (Neutral Density) filters are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows the dynamic range of the device to be increased.

[0295] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described with reference to a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 34A, a lens 255 and a filter 25 formed in a pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0296] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is Therefore, as shown in Figure 34(B), A lens 255 and a filter 254 are disposed on the conversion element 220 side. It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, the imaging device 200 with high detection sensitivity is provided. can be done.

[0297] As the photoelectric conversion element 220 shown in FIG. 34, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0298] In addition, the photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be a sintered material. Iron, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0299] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0300] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2, may include a subpixel 212 having a first filter.

[0301] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of forming a pixel using the above will be described.

[0302] 35(A) and 35(B) are cross-sectional views of elements constituting an imaging device. The imaging device shown in FIG. 1 includes a silicon transistor 35 provided on a silicon substrate 300. 1. Transistor 35 using an oxide semiconductor stacked over transistor 351 2 and a transistor 353, and a photodiode provided on the silicon substrate 300. Each transistor and photodiode 360 ​​is connected to a different plug 370. and is electrically connected to the wiring 371. 61 has an electrical connection to plug 370 through low resistance region 363 .

[0303] The imaging device includes a transistor 351 and a photodiode 352 disposed on a silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20 and in contact with layer 320, and includes transistors 352 and 353. A layer 330 is provided in contact with the layer 330 and has wiring 372 and wiring 373. It has 40.

[0304] In the example of the cross-sectional view of FIG. 35(A), the transistor 35 is disposed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the surface opposite to the surface on which the photodiode 1 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. This makes it possible to form pixels with a high aperture ratio. The light receiving surface of 360 may be the same as the surface on which the transistor 351 is formed.

[0305] In addition, when a pixel is configured using only transistors using an oxide semiconductor, the layer 31 Alternatively, the layer 310 may be omitted. Alternatively, a pixel may be formed using only a transistor including an oxide semiconductor.

[0306] If the pixel is constructed using only silicon transistors, layer 330 can be omitted. An example of a cross-sectional view in which the layer 330 is omitted is shown in FIG.

[0307] The silicon substrate 300 may be an SOI substrate. Instead, germanium, silicon germanium, silicon carbide, gallium arsenide, and aluminum arsenide The substrate has a gallium nitride, indium phosphide, gallium nitride or organic semiconductor. You can also be there.

[0308] Here, a layer 310 having a transistor 351 and a photodiode 360, An insulator 380 is provided between the layer 330 having the resistor 352 and the transistor 353. However, the position of the insulator 380 is not limited.

[0309] The hydrogen in the insulator provided near the channel forming region of the transistor 351 is converted into silicon diaphragm. This has the effect of terminating the ring bond and improving the reliability of the transistor 351. , hydrogen in an insulator provided near the transistor 352 and the transistor 353, etc. This is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 52 and the transistor 353. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When the capacitors are stacked, an insulator 380 having a function of blocking hydrogen is provided between them. It is preferable to provide the insulator 380. By confining hydrogen below the insulator 380, the transistor The reliability of the insulator 351 can be improved. Since hydrogen diffusion to layers above 380 can be suppressed, the transistors 352 and This can improve the reliability of the transistor 353 and the like.

[0310] As the insulator 380, for example, an insulator having a function of blocking oxygen or hydrogen is used. There are.

[0311] In the cross-sectional view of FIG. 35(A), a photodiode 360 ​​provided in the layer 310 and a The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0312] As shown in FIG. 36(A1) and FIG. 36(B1), a part or the whole of the imaging device may be 36(A1) shows the imaging device in the direction of the dashed line X1-X2 in the figure. FIG. 36(A2) shows the curved state. FIG. 36(A3) is a cross-sectional view of the portion indicated by the dashed line Y1-2 in FIG. This is a cross-sectional view of the portion indicated by Y2.

[0313] FIG. 36(B1) shows a case where the imaging device is bent in the direction of the dashed line X3-X4 in the same figure, and FIG. 36(B2) shows a state where the wire is bent in the direction of the dashed line Y3-Y4 in the figure. FIG. 36(B3) is a cross-sectional view of a portion indicated by a dashed line X3-X4 in FIG. 36(B1) is a cross-sectional view of a portion indicated by dashed dotted line Y3-Y4 in FIG.

[0314] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the lenses and other components used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, which contributes to the miniaturization of electronic devices that use imaging devices. It is possible to realize a lighter weight and a smaller camera. It is also possible to improve the quality of the captured image. .

[0315] <cpu> The following describes a CPU including the above-mentioned transistor and the above-mentioned semiconductor device such as the memory device. I will explain this in more detail.

[0316] FIG. 37 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. be.

[0317] The CPU shown in FIG. 37 includes an ALU 1191 (ALU: Arithmetic logic unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on a separate chip. The CPU shown in FIG. 37 is merely an example showing a simplified configuration. There are many different configurations depending on the application. For example, the CPU or arithmetic circuit shown in FIG. A configuration including the above is considered as one core, and multiple such cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is as follows: For example, it can be 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0318] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0319] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0320] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0321] In the CPU shown in FIG. 37, a register 1196 is provided with a memory cell. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0322] In the CPU shown in FIG. 37, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of the Select whether to hold data by flip-flops. If the power supply voltage is set to 0, the power supply voltage is supplied to the memory cells in the register 1196. If data retention is selected for the capacitive element, data is rewritten to the capacitive element. This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped.

[0323] FIG. 38 is a circuit diagram of an example of a storage element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a A circuit 1202 that prevents stored data from volatilizing when the circuit is turned off, a switch 1203, and a switch 1204. 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 10. The memory element 1200 may include a diode, a resistor, It may further include other elements such as an inductor.

[0324] Here, the above-mentioned memory device can be used for the circuit 1202. When the supply of power supply voltage to the ND (0V) or a potential at which the transistor 1209 is turned off is continuously input. For example, the gate of the transistor 1209 is grounded via a load such as a resistor. .

[0325] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the conductive or non-conductive state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The conductive or non-conductive state of transistor 1214 is selected.

[0326] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection part is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0327] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0328] A control signal WE is input to the gate of the transistor 1209. and the switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first and second terminals of one switch is selected. When the terminals of the switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. It becomes.

[0329] The other of the source and drain of the transistor 1209 is connected to a data register 1204. In FIG. 38, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. The signal is then input to the circuit 1201.

[0330] In FIG. 38, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0331] In addition, in FIG. 38, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed at 0 can be used. The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include other elements besides the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be a transistor having a capacitance of 100 .mu.m.

[0332] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0333] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0334] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor The off-current is significantly lower than that of transistors with a channel formed in silicon. By using this transistor as the transistor 1209, the memory element 120 The signal held in the capacitance element 1208 is maintained for a long period of time even while the power supply voltage is not supplied to the In this way, the memory element 1200 can retain its stored contents (data) even when the supply of power supply voltage is stopped. ) can be held.

[0335] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0336] In the circuit 1202, the signal held by the capacitor 1208 is The power supply voltage to the memory element 1200 is then restarted. After that, the signal held by the capacitance element 1208 is converted into the state of the transistor 1210 ( The state can be converted to a conductive state or a non-conductive state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0337] Such a memory element 1200 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0338] Although the memory element 1200 has been described as being used as a CPU, the memory element 1200 can also be used as a DSP ( Digital Signal Processor), Custom LSI, PLD (Pr LSIs such as grammable logic devices, RF (Radio Frequency It can also be applied to low-requency devices.

[0339] <Display device> A display device according to one embodiment of the present invention will be described below with reference to FIGS. 39 and 40. do.

[0340] Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, etc. The light-emitting element can be a light-emitting display element. Therefore, the category includes elements whose luminance can be controlled, specifically inorganic EL (Electroluminescent) The following is an example of a display device. Display devices using EL elements (EL display devices) and display devices using liquid crystal elements (liquid crystal display devices) This section explains the display device.

[0341] The display device described below is a panel in which a display element is sealed, and a control circuit is attached to the panel. This includes modules in which ICs including controllers are mounted.

[0342] The display device described below refers to an image display device or a light source (including a lighting device). Also, connectors, such as FPC, modules with TCP attached, and TCP with printers The IC (integrated circuit) is directly mounted on the module or display element with a printed circuit board by the COG method. All mounted modules are also included in the display device.

[0343] 39A and 39B are diagrams illustrating an example of an EL display device according to one embodiment of the present invention. FIG. 39(B) is a top view showing the entire EL display device. FIG. 39(C) is a cross section of the MN corresponding to a part of the dashed line MN in FIG. 39(B). .

[0344] FIG. 39A is an example of a circuit diagram of a pixel used in an EL display device.

[0345] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of devices (capacitive elements, resistive elements, etc.), the connection destination is not specified. However, a person skilled in the art may be able to configure one aspect of the invention. Even if the destination is not specified, one aspect of the invention is clear. When the contents are described in this specification, etc., one aspect of the invention that does not specify a connection destination is the same as the embodiment of the present specification. In particular, if the terminal is connected to multiple When multiple locations are anticipated, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistive elements) By specifying the connection destinations of only some of the terminals on It may be possible to configure a clear embodiment.

[0346] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art can identify an invention by at least specifying the function. In other words, if the function is specified, one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0347] The EL display device shown in FIG. 39(A) includes a switch element 743, a transistor 741, and a capacitor. The light emitting element 719 includes a capacitance element 742 and a light emitting element 719 .

[0348] Note that FIG. 39(A) is an example of a circuit configuration, and therefore, if a transistor is added, Conversely, at each node in FIG. 39(A), It is also possible to avoid adding passive elements.

[0349] The gate of the transistor 741 is connected to one end of the switch element 743 and one end of the capacitance element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. and is electrically connected to one electrode of the light-emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other end of the switch element 743 is connected to the signal line 7 The other electrode of the light-emitting element 719 is electrically connected to the light-emitting element 44. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0350] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. The switch element 743 is a transistor manufactured through the same process as the transistor 741. By using the transistor 74, the productivity of the EL display device can be improved. As the switch element 743, for example, the above-mentioned transistor is applied. It is possible.

[0351] FIG. 39(B) is a top view of the EL display device. The EL display device is made up of a substrate 700 and a substrate 7 50, a sealant 734, a driving circuit 735, a driving circuit 736, a pixel 737, and an FP The sealing material 734 includes the pixel 737, the driving circuit 735, and the driving circuit The driving circuit 735 is disposed between the substrate 700 and the substrate 750 so as to surround the driving circuit 736. Alternatively / and the driving circuit 736 may be disposed outside the sealing material 734 .

[0352] FIG. 39(C) is a cross-sectional view of an EL display device corresponding to a part of the dashed line MN in FIG. 39(B). It is.

[0353] In FIG. 39C, a conductor 704 a on a substrate 700 and a conductor An insulator 712a on the body 704a, an insulator 712b on the insulator 712a, and an insulator 712 Semiconductor 706a and semiconductor 706b are located on conductor 704a and overlap with semiconductor 706b. Conductors 716a and 716b in contact with semiconductor 706a and semiconductor 706b, respectively. 6b, an insulator 718a on the conductor 716a and on the conductor 716b, and an insulator 718a an insulator 718b on the insulator 718b, an insulator 718c on the insulator 718c, The semiconductor 706b and the conductor 714a overlap each other. The structure of 41 is just an example, and the structure may be different from that shown in FIG.

[0354] Therefore, in the transistor 741 shown in FIG. The insulators 712a and 712b function as gate insulators. The conductor 716a functions as a source electrode, and the conductor 716b functions as a drain electrode. The insulators 718a, 718b, and 718c function as gate electrodes. The conductor 714a functions as a gate insulator, and the conductor 714b functions as a gate electrode. The electrical characteristics of the semiconductors 706a and 706b may vary when exposed to light. Therefore, the conductor 704a, the conductor 716a, the conductor 716b, and the conductor 714a It is preferable that at least one of them has a light-shielding property.

[0355] The interface between the insulator 718a and the insulator 718b is shown by a dashed line. For example, insulators 718a and 718b may not be clearly defined. Therefore, when the same type of insulator is used, it may be difficult to distinguish between the two depending on the observation method.

[0356] In FIG. 39C, a conductor 704b on a substrate and a conductor 704b are used as the capacitor 742. an insulator 712a on the insulator 712a, an insulator 712b on the insulator 712a, and an insulator 712b on the insulator 712b. A conductor 716a overlapping the conductor 704b, an insulator 718a on the conductor 716a, and an insulating An insulator 718b on the insulator 718a, an insulator 718c on the insulator 718b, and an insulator 718 and a conductor 714b that is on the conductor 714c and overlaps the conductor 716a. In the overlapping region of the insulator 714b, a part of the insulator 718a and the insulator 718b are removed. The structure shown is as follows:

[0357] In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode. The conductor 716a serves as the other electrode.

[0358] Therefore, the capacitor 742 can be formed using a film common to the transistor 741. In addition, it is preferable that the conductor 704a and the conductor 704b are made of the same type of conductor. In this case, the conductor 704a and the conductor 704b can be formed through the same process. In addition, the conductor 714a and the conductor 714b are preferably made of the same type of conductor. In this case, the conductor 714a and the conductor 714b can be formed through the same process. .

[0359] A capacitor 742 shown in FIG. 39C has a large capacitance per occupied area. Therefore, the EL display device shown in FIG. 39(C) has high display quality. The illustrated capacitive element 742 is formed by thinning the overlapping area of ​​the conductor 716a and the conductor 714b. Therefore, the insulator 718a and the insulator 718b are partially removed. The capacitive element according to one embodiment is not limited to this. For example, the conductors 716a and A structure in which a part of the insulator 718c is removed to thin the overlapping area of ​​the conductor 714b. It is okay to have one.

[0360] An insulator 720 is provided over the transistor 741 and the capacitor 742. The insulator 720 extends to a conductor 716a which serves as a source electrode of the transistor 741. The insulator 720 may have an opening. A conductor 781 is disposed on the insulator 720. The conductor 78 1 may be electrically connected to transistor 741 through an opening in insulator 720.

[0361] A partition 784 having an opening reaching the conductor 781 is disposed over the conductor 781. A light-emitting layer 782 is disposed on the wall 784 so as to be in contact with the conductor 781 at the opening of the partition wall 784. A conductor 783 is disposed over the light-emitting layer 782. The overlapping region of the conductor 783 becomes the light-emitting element 719 .

[0362] So far, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described. do.

[0363] FIG. 40(A) is a circuit diagram showing an example of the configuration of a pixel of a liquid crystal display device. The pixel shown in FIG. A transistor 751, a capacitor element 752, and an element in which liquid crystal is filled between a pair of electrodes (liquid crystal The liquid crystal element 753 is also included.

[0364] In the transistor 751, one of the source and the drain is electrically connected to a signal line 755. The gate is electrically connected to a scan line 754 .

[0365] In the capacitor 752, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential.

[0366] In the liquid crystal element 753, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential. A common potential applied to a wiring to which the other electrode of the capacitor 752 is electrically connected, The common potential applied to the other electrode of the liquid crystal element 753 may be different from the common potential applied to the other electrode of the liquid crystal element 753 .

[0367] The liquid crystal display device will be described assuming that the top view is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dotted-chain line MN is shown in FIG. In this case, the FPC 732 is connected to the wiring 733a via the terminal 731. 3a is a conductor or a semiconductor of the same type as the conductor or semiconductor that constitutes the transistor 751. Alternatively, a semiconductor may be used.

[0368] For the transistor 751, refer to the description of the transistor 741. For 752, refer to the description of the capacitor 742. Although the structure of the capacitor 752 corresponding to the capacitor 742 in (C) is shown, the present invention is not limited to this. stomach.

[0369] Note that when an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current is extremely small. Therefore, the charge held in the capacitor 752 can be Therefore, the voltage applied to the liquid crystal element 753 can be maintained for a long period of time. Therefore, when displaying a moving image or a still image with little movement, the transistor 751 is turned off. This eliminates the need for power to operate the transistor 751, and the liquid crystal display has low power consumption. In addition, the area occupied by the capacitor 752 can be reduced; It is possible to provide a liquid crystal display device with a high aperture ratio or a high-definition liquid crystal display device.

[0370] An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening that reaches the transistor 751. The conductor 791 is disposed on the insulator 721. The conductor 791 is connected to the transistor Electrically connect to 751.

[0371] An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is disposed on the liquid crystal layer 793. An insulator 794 that functions as an alignment film is disposed on the liquid crystal layer 793. 94 is disposed on the insulator 794. A spacer 795 is disposed on the insulator 794. A conductor 796 is disposed on the insulator 794. The substrate 79 7 is placed.

[0372] By using the above-mentioned structure, it is possible to provide a display device having a capacitance element with a small occupancy area. Alternatively, a display device with high display quality can be provided. It is possible to provide a display device.

[0373] For example, in this specification and the like, the term "display element," "display device having a display element," "light-emitting element," A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element, or the light-emitting device may include, for example, For example, light-emitting diodes (LEDs) that are white, red, green, or blue ting Diode), transistor (transistor that emits light according to electric current), electron Output element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV) , plasma displays (PDP), MEMS (microelectromechanical systems) Display elements using a digital micromirror device (DMD), a digital micromirror device (DMS), Micro Shutter), IMOD (Interference Modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electro Wetting elements, piezoelectric ceramic displays, and displays using carbon nanotubes In addition to these, the device has at least one of the following functions: Alternatively, the display medium may have a variable contrast, brightness, reflectance, transmittance, etc.

[0374] An example of a display device using an EL element is an EL display. An example of a display device using this method is a field emission display (FED). is a flat panel display using the SED method (SED: Surface-conduction E LCD displays are used in the following applications: An example of the device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). play, reflective LCD, direct-view LCD, projection LCD) An example of a display device using electronic ink or electrophoretic elements is the electronic pen. In addition, there are also other LCDs that can realize semi-transmissive LCDs and reflective LCDs. In this case, a part or the whole of the pixel electrode is made to function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM can be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0375] When using an LED, graphene or graphene is placed under the LED electrode or nitride semiconductor. Graphene and graphite can be arranged in layers to form a multilayer film. In this way, by providing graphene or graphite, it is possible to form a nitride on the graphene or graphite. Semiconductors, such as n-type GaN semiconductors having crystals, can be easily formed into films. Furthermore, a p-type GaN semiconductor having crystals can be placed on top of it to form an LED. It is possible to fabricate a crystalline n-type GaN semiconductor using graphene or graphite. An AlN layer may be provided. The GaN semiconductor in the LED is formed by MOCVD. However, by providing graphene, the GaN semiconductor of the LED can be It is also possible to form the film by a tar deposition method.

[0376] <Electronic equipment> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, audio playback devices (car audio, digital audio players, copiers, fax machines, printers, printer-combiners, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0377] FIG. 41A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation key 907, stylus 908 The portable game machine shown in FIG. However, the number of display units that the portable game machine has is not limited to this. .

[0378] FIG. 41B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit 9 13, a second display unit 914, a connection unit 915, an operation key 916, etc. The first display unit 911 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. 12. Also, the first display unit 913 may be configured to switch according to the angle between the first display unit 913 and the second display unit 913. and a display having a function as a position input device added to at least one of the first and second display units 914. The function of the position input device may be achieved by touching the display device. The function as a position input device can be added by providing a touch panel. It can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It is possible.

[0379] FIG. 41C shows a notebook personal computer, which includes a housing 921, a display unit 922, and a keyboard. The display device 922 includes a keyboard 923, a pointing device 924, and the like.

[0380] FIG. 41(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 93. Holds 3rd place.

[0381] FIG. 41E shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0382] FIG. 41(F) shows an automobile, which includes a body 951, wheels 952, a dashboard 953, and lights. 954 etc.

[0383] As described above, one embodiment of the present invention has been described in this embodiment. One embodiment is not limited to the above. For example, a semiconductor such as semiconductor 406b may have fluorine. However, the present invention is not limited to this example. The semiconductor may contain elements other than fluorine. Semiconductors such as b may not contain fluorine. EXAMPLES

[0384] In this example, fluorine was added to an oxide semiconductor film, and the fluorine concentration in the oxide semiconductor film was investigated. The results will be explained below.

[0385] The sample was prepared by forming a 100 nm thick silicon oxide layer on a silicon substrate by thermal oxidation. Then, an oxide semiconductor film was formed using In-Ga-Zn-O (atomic ratio In:Ga:Zn=1:1). 1) An IGZO film was deposited to a thickness of 100 nm by sputtering using a target. It was formed and produced.

[0386] The prepared sample was implanted with 1.0×10 15 ions / cm 2 and 1 .0×10 16 ions / cm 2 The dose of fluorine ions ( 19 F + ) was added. The accelerating voltage was 20 kV. The amount of fluorine added in the depth direction was measured by SIMS. The results of this investigation are shown in FIG.

[0387] From the results shown in Figure 42, fluorine was added at 1.0 × 10 15 ions / cm 2 When added, IG 3.0 × 10 on ZO membrane 20 atoms / cm 3 It was also found that the amount of The element is 1.0×10 16 ions / cm 2 When added, the IGZO film had a 3.0×10 21 a toms / cm 3 It was found to contain a certain amount. EXAMPLES

[0388] In this example, fluorine was added to an oxide semiconductor film, and the sheet resistance of the oxide semiconductor film was investigated. The results will be explained below.

[0389] The sample was an oxide semiconductor film of In-Ga-Zn-O (atomic ratio In:Ga) on a quartz substrate. The IGZO film was deposited by sputtering using a Zn (a:Zn=1:1:1) target. The thin film was fabricated with a thickness of 100 nm.

[0390] The prepared sample was implanted with 1.0×10 14 ions / cm 2 , 1.0 ×10 15 ions / cm 2 and 1.0×10 16 ions / cm 2 The dose of fluorine Elementary ions ( 19 F + The accelerating voltage was set to 20 kV. The results of measuring the sheet resistance of the prepared samples are shown in Figure 43. The upper limit of measurement is 1×10 6 It is Ω / □.

[0391] The results shown in Figure 43 show that the more fluorine is added to the IGZO film, the higher the sheet resistance. It was also confirmed that fluorine was 1.0×10 16 ions / cm 2 When added, IG The sheet resistance of the ZO film is 1×10 6 The value was over Ω / □. By adding fluorine to the film, the carrier concentration of the IGZO film decreases, making it closer to an i-type semiconductor. I realized that. EXAMPLES

[0392] In this embodiment, fluorine is added to the oxide semiconductor film, and defects in the oxide semiconductor film are detected by ESR. The results of the survey will be explained below.

[0393] The sample was an oxide semiconductor film of In-Ga-Zn-O (atomic ratio In:Ga) on a quartz substrate. The IGZO film was deposited by sputtering using a Zn (a:Zn=1:1:1) target. The thin film was fabricated with a thickness of 100 nm.

[0394] The prepared sample was implanted with 1.0×10 14 ions / cm 2 , 1.0 ×10 15 ions / cm 2 or 1.0×10 16 ions / cm 2 The dose of fluorine Elementary ions ( 19 F + The accelerating voltage was set to 20 kV. The results of ESR measurements of the prepared samples are shown in FIG.

[0395] The ESR spectrum is shown in FIG. 44(A). From the results shown in FIG. 44(A), the IGZO film It was found that the more fluorine was added, the smaller the signal at the g value of around 1.93 became. In addition, in Figure 44(B), the spin densities of the signals observed at g values ​​around 1.93 are compared. As shown in FIG. 44(B), the g value increases with increasing amount of fluorine added to the IGZO film, decreasing from 1.93 to 1.93. It was found that the spin density of the signal seen in the vicinity was reduced.

[0396] In the IGZO film, the signal seen at a g value of around 1.93 is due to oxygen vacancies. Therefore, by adding fluorine to the IGZO film, the oxygen vacancies in the IGZO film can be reduced. It was found that it is possible to reduce [Explanation of symbols]

[0397] 100 Transistors 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 Pixel Circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 Silicon substrate 310 layers 320 layers 330 layers 340 layers 351 Transistor 352 Transistor 353 Transistor 360 Photodiode 361 Anode 363 Low resistance region 370 Plug 371 Wiring 372 Wiring 373 Wiring 380 Insulator 400 Substrates 401 Insulators 402 Insulator 404 Conductors 406a Semiconductors 406b Semiconductors 406c Semiconductors 412 Insulators 413 Conductors 416a Conductor 416b Conductor 434 Conductors 436c Semiconductors 442 Insulator 450 Semiconductor Substrate 452 Insulator 454 Conductors 456 areas 460 areas 462 Insulator 464 Insulator 466 Insulators 468 Insulator 472a area 472b area 474a Conductors 474b Conductors 474c Electrical conductors 476a Conductors 476b Conductors 478a Conductors 478b Conductor 478c Conductor 480a Conductor 480b Conductor 480c conductor 490 Insulator 492 Insulators 494 Insulators 496a Conductors 496b Conductors 496c Conductors 496d Conductors 498a Conductors 498b Conductor 498c Electrical conductor 498d Conductor 500 boards 502 Insulator 503 Insulators 504 Conductors 506a Semiconductors 506b Semiconductors 506c Semiconductor 511 Insulators 512 Insulators 513 Conductors 514 Conductors 516 Conductors 516a Conductor 516b Conductor 534 Conductors 536a Semiconductors 536b Semiconductors 536c Semiconductors 542 Insulator 700 Substrates 704a Conductor 704b Conductor 706a Semiconductors 706b Semiconductors 712a Insulator 712b Insulator 714a Conductor 714b Conductor 716a Conductor 716b Conductor 718a Insulator 718b Insulator 718c Insulator 719 Light emitting element 720 Insulator 721 Insulators 731 Terminal 732 FPC 733a Wiring 734 Sealing material 735 Drive Circuit 736 Drive Circuit 737 pixels 741 Transistor 742 Capacitive element 743 Switching element 744 Signal Line 750 Substrate 751 Transistor 752 Capacitive element 753 Liquid crystal element 754 scan lines 755 Signal Line 781 Conductors 782 Light-emitting layer 783 Conductors 784 Bulkhead 791 Conductors 792 Insulators 793 Liquid crystal layer 794 Insulators 795 Spacer 796 Conductors 797 Circuit Board 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 5100 pellets 5120 Circuit Board 5161 area< / cpu>

Claims

[Claim 1] a gate electrode, a gate insulator, and an oxide semiconductor; The semiconductor device according to claim 1, wherein the oxide semiconductor has fluorine in a channel formation region.

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