Display device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- JAPAN DISPLAY INC
- Filing Date
- 2023-08-28
- Publication Date
- 2026-06-16
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
[Technical field]
[0001] The present embodiment relates to a display device. [Background technology]
[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. The display elements include a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.
[0003] In manufacturing such display devices, a technique for improving the yield in the manufacturing process is required. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]
[0005] An object of the present invention is to provide a display device capable of improving the yield in the manufacturing process. [Means for solving the problem]
[0006] A display device according to one embodiment has a display area in which a plurality of display elements are arranged, and a peripheral area around the display area. The display device has a partition wall arranged in the display area and between adjacent display elements, an electrode layer arranged in the peripheral area, a conductive layer arranged above the electrode layer, and an inorganic insulating layer arranged between the electrode layer and the conductive layer.
[0007] The partition wall and the conductive layer have a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The electrode layer has an electrode opening penetrating in the stacking direction. The conductive layer overlaps the electrode opening.
[0008] A display device according to one embodiment has a display area in which a plurality of display elements are arranged, and a peripheral area around the display area. The display device has a partition wall arranged in the display area and between adjacent display elements, an electrode layer arranged in the peripheral area, a conductive layer arranged above the electrode layer, and an inorganic insulating layer arranged between the electrode layer and the conductive layer.
[0009] The partition wall and the conductive layer have a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The conductive layer has a conductive opening penetrating therethrough in a stacking direction. The electrode layer overlaps the conductive opening.
[0010] A display device according to one embodiment has a display area in which a plurality of display elements are arranged, and a peripheral area around the display area. The display device has a partition wall arranged in the display area and between adjacent display elements, a first organic insulating layer arranged in the peripheral area, an electrode layer arranged above the first organic insulating layer, and an inorganic insulating layer arranged above the electrode layer.
[0011] The partition wall has a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The first organic insulating layer has an inclined surface located at an end portion of the first organic insulating layer. The electrode layer has an electrode opening that penetrates in the stacking direction and overlaps with the inclined surface. [Brief description of the drawings]
[0012] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of a layer structure that can be applied to the organic layer. [Diagram 5] FIG. 5 is a schematic plan view showing an enlarged portion of the display device. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the display device taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the display device taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of a display device according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0013] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.
[0014] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of a plane including the X-direction and the Y-direction. In this embodiment, the Z-direction corresponds to the stacking direction. Also, viewing various elements parallel to the Z-direction is called planar view.
[0015] The display device according to one embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.
[0016] 1 is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. A plurality of display elements, which will be described later, are arranged in the display area DA. The substrate 10 may be glass or a flexible resin film.
[0017] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.
[0018] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.
[0019] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.
[0020] In the display area DA, there are arranged a plurality of scanning lines GL which supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL which supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example shown in Fig. 1, the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.
[0021] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.
[0022] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.
[0023] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example shown in Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.
[0024] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and a column in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example shown in FIG.
[0025] A rib 5 is disposed in the display area DA. The rib 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example shown in Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio, and the subpixel SP3 has the smallest aperture ratio.
[0026] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.
[0027] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later.
[0028] In the display area DA, conductive partition walls 6 are arranged. The partition walls 6 are arranged on the ribs 5. The partition walls 6 entirely overlap the ribs 5 and have the same planar shape as the ribs 5. The partition walls 6 are arranged between the adjacent display elements DE1, DE2, and DE3.
[0029] That is, the partition 6 has an opening in each of the subpixels SP1, SP2, and SP3. From another perspective, the rib 5 and the partition 6 have a lattice shape in a plan view and surround each of the subpixels SP1, SP2, and SP3. The partition 6 serves as a wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.
[0030] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 serves as a planarizing film that planarizes unevenness caused by the circuit layer 11.
[0031] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5.
[0032] Although not shown in the cross section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.
[0033] The partition 6 includes a conductive lower portion 61 disposed on the rib 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition 6 is called an overhang shape.
[0034] 3, the lower portion 61 has a bottom layer 63 disposed on the rib 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In the example shown in FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.
[0035] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR1 is disposed between the lower electrode LE1 and the upper electrode UE1.
[0036] The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.
[0037] The display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. The display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. The display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.
[0038] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.
[0039] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located below the partition wall 6 (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located below the partition wall 6 (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located below the partition wall 6 (a part that constitutes the display element DE3).
[0040] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE2 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE3 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.
[0041] 3, the stacked film FL1 and the sealing layer SE1 on the partition 6 between the subpixels SP1 and SP2 are separated from the stacked film FL2 and the sealing layer SE2 on the partition 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition 6 between the subpixels SP1 and SP3 are separated from the stacked film FL3 and the sealing layer SE3 on the partition 6.
[0042] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15. The resin layers 13, 15, and the sealing layer 14 are provided continuously at least throughout the display area DA, and a portion of them extends into the peripheral area SA.
[0043] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer 15. Such a cover member may be adhered to the resin layer 15 via an adhesive layer such as OCA (Optical Clear Adhesive).
[0044] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib 5 and the sealing layers 14, SE1, SE2, and SE3 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the rib 5 is formed of silicon oxynitride, and the sealing layers 14, SE1, SE2, and SE3 are formed of silicon nitride. The resin layers 13 and 15 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.
[0045] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).
[0046] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.
[0047] 4 is a diagram showing an example of a layer structure applicable to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including an emitting layer EML. In this embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of emitting layers EML.
[0048] The cap layers CP1, CP2, and CP3 each have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers made of inorganic materials and layers made of organic materials. In addition, these transparent layers have different refractive indices.
[0049] For example, the refractive index of these transparent layers is different from the refractive index of the upper electrodes UE1, UE2, UE3 and the refractive index of the sealing layers SE1, SE2, SE3. At least one of the cap layers CP1, CP2, CP3 may be omitted.
[0050] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb).
[0051] Examples of the metal material that can be used for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be made of an insulating material.
[0052] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. The metal material forming the lower layer may be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the upper layer may be, for example, ITO or IZO. The upper portion 62 may have a single layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.
[0053] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal of the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.
[0054] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in the red wavelength region.
[0055] As another example, the emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the emitting layers EML into light of a color corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the emitting layers EML to generate light of a color corresponding to the subpixels SP1, SP2, and SP3.
[0056] Next, a structure that can be applied to the surrounding area SA will be described. Fig. 5 is a schematic plan view showing an enlarged portion of the display device DSP. Fig. 6 is a schematic cross-sectional view of the display device DSP taken along line VI-VI in Fig. 5. Fig. 7 is a schematic cross-sectional view of the display device DSP taken along line VII-VII in Fig. 5. Fig. 8 is a schematic cross-sectional view of the display device DSP taken along line VIII-VIII in Fig. 5.
[0057] 5 shows a part of the display area DA and the peripheral area SA near the edge of the substrate 10. In Fig. 6 and subsequent figures, the substrate 10, the resin layers 13 and 15, the sealing layer 14, etc. are omitted.
[0058] 5, the substrate 10 has a display area DA and a peripheral area SA. The display area DA includes a plurality of pixels PX, each including subpixels SP1, SP2, and SP3. The partition wall 6 is disposed between adjacent display elements DE1, DE2, and DE3.
[0059] 6, the display device DSP has organic insulating layers 12 and 16, an electrode layer 21, an inorganic insulating layer 50, a conductive layer 60, a laminated film FL, and a sealing layer SE. In this embodiment, the organic insulating layer 16 corresponds to the second organic insulating layer, and the organic insulating layer 12 corresponds to the first organic insulating layer.
[0060] In Fig. 5, in the display region DA, dots are applied to portions where the ribs 5 are not formed. In Fig. 5, in the peripheral region SA, dots are applied to portions where the inorganic insulating layer 50 is not formed, and hatched portions where the conductive layer 60 is not formed are applied. Also, in Fig. 5, in the peripheral region SA excluding the region where a plurality of dummy pixels DX described below are formed, portions where the electrode layer 21 is not formed are designated as electrode openings 23 and are colored black.
[0061] The organic insulating layer 16 corresponds to one of the elements constituting the circuit layer 11 (shown in FIG. 3). The organic insulating layer 16 is formed of, for example, an organic insulating material. The organic insulating layers 12 and 16 are disposed across the display area DA and the peripheral area SA. The organic insulating layer 16 is disposed below the organic insulating layer 12.
[0062] The electrode layer 21 is disposed in the peripheral area SA. The electrode layer 21 is disposed on the organic insulating layer 12. The electrode layer 21 is formed, for example, from the same material and through the same manufacturing process as the lower electrodes LE1, LE2, and LE3 in the display area DA.
[0063] The inorganic insulating layer 50 is disposed between the electrode layer 21 and the conductive layer 60. The inorganic insulating layer 50 is formed of the same material and through the same manufacturing process as the ribs 5 in the display area DA. The inorganic insulating layer 50 is connected to the ribs 5 disposed in the display area DA.
[0064] The conductive layer 60 is disposed above the electrode layer 21. Focusing on the electrode layer 21, the organic insulating layers 12 and 16 are disposed below the electrode layer 21, and the inorganic insulating layer 50 is disposed above the electrode layer 21.
[0065] The conductive layer 60 is formed of the same material and in the same manufacturing process as the partition walls 6 in the display area DA. The conductive layer 60 is connected to the partition walls 6 arranged in the display area DA.
[0066] Similar to the partition wall 6 (shown in FIG. 3), the conductive layer 60 has a conductive lower portion 61 and an upper portion 62 protruding from the side surface of the lower portion 61. The lower portion 61 has a bottom layer 63 disposed on the inorganic insulating layer 50 and an axis layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the axis layer 64. In addition, both ends of the bottom layer 63 protrude from the side surfaces of the axis layer 64, for example.
[0067] The laminated film FL includes an organic layer ORs, an upper electrode UEs, and a cap layer CPs. The organic layer ORs is formed of the same material and by the same manufacturing process as any one of the organic layers OR1, OR2, and OR3. The upper electrode UEs is formed of the same material and by the same manufacturing process as any one of the upper electrodes UE1, UE2, and UE3.
[0068] The cap layer CPs is formed of the same material and by the same manufacturing process as any one of the cap layers CP1, CP2, and CP3. In one example, the organic layer ORs, the upper electrode UEs, and the cap layer CPs are formed of the same material and by the same manufacturing process as the organic layer OR3, the upper electrode UE3, and the cap layer CP3, respectively.
[0069] The sealing layer SE is formed of the same material and by the same manufacturing process as any one of the sealing layers SE1, SE2, and SE3. In one example, the sealing layer SE is formed of the same material and by the same manufacturing process as the sealing layer SE3. The stacked film FL and the sealing layer SE overlap the conductive layer 60 in a planar view.
[0070] 6, the organic insulating layer 12 has an end E12. The end E12 is formed, for example, in a frame shape surrounding the display area DA in a plan view. The end E12 is covered with the electrode layer 21. An inclined surface S12 is located at the end E12.
[0071] The inclined surface S12 corresponds to a part of the surface facing the electrode layer 21. The inclined surface S12 is inclined so as to approach the organic insulating layer 16 with increasing distance from the display region DA. In other words, the thickness of the organic insulating layer 12 at the end E12 decreases with increasing distance from the display region DA.
[0072] The inclined surface S12 is curved in the example shown in Fig. 6. However, the inclined surface S12 does not have to be curved. The width W (shown in Fig. 5) of the inclined surface S12 is about 50 µm in one example.
[0073] 6, the organic insulating layer 16 protrudes beyond an end E12 of the organic insulating layer 12 in the peripheral region SA. Specifically, the organic insulating layer 16 has a portion P16 that protrudes beyond the end E12. An upper surface S16 of the portion P16 is covered with the electrode layer 21.
[0074] The upper surface S16 corresponds to a part of the surface facing the organic insulating layer 12. On the electrode layer 21 covering the portion P16, an inorganic insulating layer 50, a conductive layer 60, a laminated film FL, and a sealing layer SE are further laminated.
[0075] 5, the electrode layer 21 has a plurality of electrode openings 23. The electrode openings 23 serve as openings for releasing moisture from the organic insulating layer 12, for example, after the electrode layer 21 is formed.
[0076] 6, the multiple electrode openings 23 penetrate the electrode layer 21 in the Z direction. The conductive layer 60 overlaps the electrode openings 23 in a plan view. In other words, the conductive layer 60 is disposed above the electrode openings 23.
[0077] Specifically, a lower portion 61 of the conductive layer 60 is disposed above the electrode opening 23. More specifically, an axial layer 64 of the conductive layer 60 is disposed above the electrode opening 23. A part of the inorganic insulating layer 50 is located in the electrode opening 23.
[0078] Focusing on the inclined surface S12, the electrode opening 23 overlaps with the inclined surface S12 in a plan view. In other words, the electrode opening 23 is also formed in a region that overlaps with the inclined surface S12 in a plan view.
[0079] Moreover, the conductive layer 60 also overlaps the electrode opening 23 that overlaps the inclined surface S12 in a plan view. The electrode opening 23 is not formed in a region that overlaps with the portion P16 of the organic insulating layer 16 in a plan view.
[0080] 5, the electrode opening 23 has a quadrangular shape in plan view. Here, the quadrangular shape includes a rectangular shape and a square shape. As another example, the electrode opening 23 may have a circular shape, an elliptical shape, or another polygonal shape.
[0081] 5, the width (e.g., length in the Y direction) of the electrode opening 23 is smaller than the distance between two conductive openings 65. Specifically, the width of the electrode opening 23 is smaller than the width of the lower portion 61 of the conductive layer 60 in the example shown in Fig. 6. More specifically, the width of the electrode opening 23 is smaller than the width of the axial layer 64 of the conductive layer 60 in the example shown in Fig. 6.
[0082] As shown in Fig. 5, the conductive layer 60 has a plurality of conductive openings 65. As shown in Fig. 6, the plurality of conductive openings 65 penetrate the conductive layer 60 in the Z direction. The electrode layer 21 overlaps the conductive openings 65 in a plan view. Moreover, the electrode openings 23 do not overlap the conductive openings 65 in a plan view.
[0083] Focusing on the inclined surface S12, the conductive opening 65 does not overlap the inclined surface S12 in a plan view. In other words, the conductive opening 65 is not formed in a region that overlaps with the inclined surface S12 in a plan view.
[0084] 5, the conductive opening 65 has a rectangular shape in plan view. As another example, the electrode opening 23 may have a circular shape, an elliptical shape, or another polygonal shape.
[0085] In a plan view, the conductive opening 65 is, for example, larger than the electrode opening 23. Note that the conductive opening 65 may be smaller than the electrode opening 23 in a plan view, or may be equal in size to the electrode opening 23.
[0086] A part of the laminated film FL is located in the conductive opening 65. The part of the laminated film FL located above the conductive layer 60 is separated from the part of the laminated film FL located below the conductive layer 60.
[0087] 6, the sealing layer SE is disposed above the conductive layer 60 and the conductive opening 65. In other words, a part of the sealing layer SE is located in the conductive opening 65. By having a part of the sealing layer SE enter the conductive opening 65, the sealing layer SE bites into the conductive layer 60, making it difficult for the sealing layer SE to peel off.
[0088] Next, the dummy pixel DX will be described. 5, the display device DSP has a plurality of dummy pixels DX that do not display an image in the peripheral area SA. The plurality of dummy pixels DX are arranged so as to surround the display area DA. A plurality of electrode openings 23 and a plurality of conductive openings 65 are formed between the plurality of dummy pixels DX and the end E12 of the organic insulating layer 12.
[0089] The dummy pixels DX have, for example, the same shape as the pixels PX in a plan view and are arranged in the same layout as the pixels PX. In this embodiment, it is assumed that the dummy pixels DX include sub-pixels DP1, DP2, and DP3.
[0090] 5, the subpixels DP2 and DP3 are aligned with the subpixel DP1 in the X direction. Furthermore, the subpixels DP1 are aligned in the Y direction, and the subpixels DP2 and DP3 are aligned in the Y direction.
[0091] When the sub-pixels DP1, DP2, and DP3 are laid out in this manner, the peripheral area SA is formed with a column in which the sub-pixels DP2 and DP3 are alternately arranged in the Y direction, and a column in which a plurality of sub-pixels DP1 are repeatedly arranged in the Y direction. These columns are alternately arranged in the X direction. These columns surround the display area DA. Note that the layout of the sub-pixels DP1, DP2, and DP3 is not limited to the example shown in FIG.
[0092] In the region of the peripheral region SA where the dummy pixels DX are formed, the partition 6 has a lattice-like planar shape. The partition 6 has openings in each of the sub-pixels DP1, DP2, and DP3.
[0093] In the region of the peripheral region SA where the dummy pixels DX are formed, the inorganic insulating layer 50 does not have openings corresponding to the pixel openings AP1, AP2, AP3 as shown in FIG.
[0094] As shown in Fig. 7, the subpixel DP1 includes a lower electrode LE1 and a laminated film FL1. An inorganic insulating layer 50 is disposed between the lower electrode LE1 and the laminated film FL1. In other words, the organic layer OR1 (shown in Fig. 3) included in the laminated film FL1 is not in contact with the lower electrode LE1.
[0095] As shown in Fig. 7, the subpixel DP3 includes a lower electrode LE3 and a laminated film FL3. An inorganic insulating layer 50 is disposed between the lower electrode LE3 and the laminated film FL3. In other words, the organic layer OR3 (shown in Fig. 3) included in the laminated film FL3 is not in contact with the lower electrode LE3.
[0096] Sealing layers SE1 and SE3 are disposed in the sub-pixels DP1 and DP3, respectively. The sealing layer SE1 continuously covers the laminated film FL1 and the partition wall 6 around the sub-pixel DP1. The sealing layer SE3 continuously covers the laminated film FL3 and the partition wall 6 around the sub-pixel DP3. In the example shown in Fig. 7, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels DP1 and DP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.
[0097] 7, the subpixel DP2 includes a lower electrode LE2 and a laminated film FL2, and an inorganic insulating layer 50 is disposed between the lower electrode LE2 and the laminated film FL2. A sealing layer SE2 is disposed in each of the subpixels DP2. The sealing layer SE2 continuously covers the laminated film FL2 and the partition wall 6 around the subpixel DP2. The laminated film FL1 and the sealing layer SE1 on the conductive layer 60 between the subpixels DP1 and DP2 are spaced apart from the laminated film FL2 and the sealing layer SE2 on the partition wall 6.
[0098] In one example, the sub-pixels DP1, DP2, and DP3 of the dummy pixel DX are formed of the same material and in the same manufacturing process as the sub-pixels SP1, SP2, and SP3 of the display area DA.
[0099] In the subpixel DP1, no opening is formed in the inorganic insulating layer 50. Therefore, even if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, no voltage is applied to the organic layer OR1, and the emitting layer EML of the organic layer OR1 does not emit light. Similarly, in the subpixels DP2 and DP3, no opening is formed in the inorganic insulating layer 50. As a result, the dummy pixel DX does not display an image.
[0100] Next, the contact portion H1 of the inorganic insulating layer 50 will be described. The inorganic insulating layer 50 has a plurality of contact portions H1 in the peripheral region SA, as shown in Fig. 5. The plurality of contact portions H1 penetrate the inorganic insulating layer 50 in the Z direction, as shown in Fig. 8.
[0101] The contact parts H1 are located between the dummy pixels DX and the end E12 of the organic insulating layer 12 in a plan view. The contact parts H1 are formed, for example, to surround the display area DA. Some of the contact parts H1 are aligned in the Y direction in the example shown in FIG. However, the layout of the contact parts H1 is not limited to this example.
[0102] The contact portion H1 has a rectangular shape in a plan view in the example shown in Fig. 5. As another example, the contact portion H1 may have a circular shape, an elliptical shape, or another polygonal shape.
[0103] In a plan view, the contact portion H1 is, for example, larger than the conductive opening 65 and the electrode opening 23. Note that the contact portion H1 may be smaller than the conductive opening 65 and the electrode opening 23 in a plan view, or may be equal in size to the conductive opening 65 and the electrode opening 23.
[0104] The conductive layer 60 covers the electrode layer 21 through the contact portion H1. In other words, the conductive layer 60 is electrically connected to the electrode layer 21 through the contact portion H1. Specifically, a lower portion 61 of the conductive layer 60 is electrically connected to the electrode layer 21. More specifically, a bottom layer 63 of the lower portion 61 is in contact with the electrode layer 21.
[0105] The electrode layer 21 is electrically connected to a power supply line (not shown) at an end of the substrate 10. A common voltage is supplied to the power supply line. The conductive layer 60 is electrically connected to the upper electrodes UE1, UE2, and UE3 constituting the display elements DE1, DE2, and DE3 via the partition wall 6. Therefore, the common voltage is supplied to the upper electrodes UE1, UE2, and UE3 from the electrode layer 21 via the contact portion H1.
[0106] The display device DSP configured as above can improve the yield in the manufacturing process, as will be described below.
[0107] 9 is a schematic cross-sectional view of a display device DSP10 according to a comparative example. The display device DSP10 differs from the display device DSP according to this embodiment in that the electrode opening 23 overlaps the conductive opening 65.
[0108] In the inorganic insulating layer 50 formed of an inorganic insulating material, cracks may occur due to steps in the electrode layer 21 at the edges of the electrode openings 23. If such cracks occur, they may cause moisture to penetrate into the organic insulating layer 12 through the cracks and the electrode openings 23 in the process of sequentially forming elements above the inorganic insulating layer 50 (rib 5).
[0109] Similar cracks may also occur in the sealing layer SE made of an inorganic insulating material. If cracks occur in both the inorganic insulating layer 50 and the sealing layer SE, a path for moisture penetration into the organic insulating layer 12 may be formed in the process of patterning the sealing layer SE (e.g., the sealing layer SE3) or in a process subsequent to the patterning.
[0110] Moisture that has penetrated into the organic insulating layer 12 may cause corrosion of elements in the peripheral area SA and the display area DA, non-illumination of the display elements DE, etc. Therefore, the occurrence of cracks in the inorganic insulating layer 50 and the sealing layer SE may cause a decrease in the yield in the manufacturing process.
[0111] In the display device DSP according to this embodiment, the electrode opening 23 does not overlap the conductive opening 65. In other words, the conductive layer 60 is formed so as to cover the electrode opening 23.
[0112] Therefore, even if a crack occurs in the inorganic insulating layer 50 near the electrode opening 23, the crack is covered by the conductive layer 60. This makes it possible to block the path of moisture penetration into the organic insulating layer 12 through the crack.
[0113] As a result, the display device DSP according to the present embodiment can improve the yield in the manufacturing process. In addition, the present embodiment can improve the process margin by blocking the path through which moisture penetrates, and can also improve the reliability of the display device DSP.
[0114] In this embodiment, the organic insulating layer 12 has an inclined surface S12 located at the end E12. The electrode opening 23 also overlaps the inclined surface S12 in a planar view. The conductive layer 60 overlaps the electrode opening 23 which overlaps the inclined surface S12 in a planar view. In contrast, the conductive opening 65 is not formed in a region which overlaps with the inclined surface S12 in a planar view.
[0115] This makes it difficult for shape abnormalities to occur in the conductive layer 60 during the manufacturing process when the conductive layer 60 is formed. As a result, the display device DSP according to this embodiment can further improve the yield in the manufacturing process.
[0116] In this embodiment, the display device DSP has a plurality of dummy pixels DX surrounding the display area in the peripheral area SA. This makes it difficult for shape abnormalities caused by etching unevenness to occur in elements such as the partition 6 and the display elements DE1, DE2, and DE3 arranged in the display area DA during the manufacturing process. As a result, the display device DSP according to this embodiment can further improve the yield in the manufacturing process.
[0117] All display devices that can be implemented by those skilled in the art through appropriate design modifications based on the display devices described above as the embodiments of the present invention belong to the scope of the present invention as long as they include the gist of the present invention.
[0118] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.
[0119] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]
[0120] 5...rib, 6...partition wall, 10...substrate, 12...organic insulating layer, 16...organic insulating layer, 21...electrode layer, 23...electrode opening, 50...inorganic insulating layer, 60...conductive layer, 61...lower part, 62...upper part, 65...conductive opening, AP1, AP2, AP3...pixel opening, DA...display area, DE1, DE2, DE3...display element, DP1, DP2, DP3...sub-pixel, DSP...display device, DX...dummy pixel, E12...end, FL...laminated film, H1...contact part, PX...pixel, S12...inclined surface, SA...peripheral area, SE...sealing layer, SP1, SP2, SP3...sub-pixel.
Claims
1. A display device having a display area on which multiple display elements are arranged, and a peripheral area surrounding the display area, A partition wall is placed in the display area and between adjacent display elements, The electrode layer arranged in the peripheral region, A conductive layer disposed above the electrode layer, It has an inorganic insulating layer disposed between the electrode layer and the conductive layer, The partition wall and the conductive layer have a conductive lower portion and an upper portion that protrudes from the side surface of the lower portion. The electrode layer has electrode openings that penetrate in the stacking direction, The conductive layer overlaps the electrode opening, Display device.
2. The conductive layer has conductive openings that penetrate in the stacking direction, The electrode layer overlaps the conductive opening, The display device according to claim 1.
3. The electrode opening does not overlap the conductive opening. The display device according to claim 2.
4. In the aforementioned peripheral region, the electrode layer further comprises an organic insulating layer disposed below the electrode layer. The organic insulating layer has an inclined surface located at the edge of the organic insulating layer. The display device according to claim 2.
5. The electrode opening overlaps the inclined surface, The display device according to claim 4.
6. The conductive layer overlaps the electrode opening which overlaps the inclined surface. The display device according to claim 5.
7. The conductive layer and the sealing layer disposed above the conductive opening are further comprising The display device according to claim 2.
8. Each of the plurality of display elements includes a lower electrode, an upper electrode facing the lower electrode, and an organic layer disposed between the lower electrode and the upper electrode, which emits light in accordance with the potential difference between the lower electrode and the upper electrode. The electrode layer is formed of the same material as the lower electrode. The display device according to claim 1.
9. The display area is arranged and further has a rib having a pixel aperture that overlaps with the lower electrode, The organic layer covers the lower electrode through the pixel aperture, The ribs are formed of the same inorganic insulating material as the inorganic insulating layer. The display device according to claim 8.
10. The partition wall is positioned on the rib, The display device according to claim 9.
11. A display device having a display area on which multiple display elements are arranged, and a peripheral area surrounding the display area, A partition wall is placed in the display area and between adjacent display elements, The first organic insulating layer arranged in the peripheral region, An electrode layer disposed above the first organic insulating layer, It comprises an inorganic insulating layer disposed above the electrode layer, The partition wall has a conductive lower portion and an upper portion that protrudes from the side surface of the lower portion. The first organic insulating layer has an inclined surface located at the end of the first organic insulating layer, The electrode layer has electrode openings that penetrate in the stacking direction and overlap the inclined surface. Display device.
12. The electrode layer is further disposed above the conductive layer and has the lower and upper parts, The display device according to claim 11.
13. The conductive layer overlaps the electrode opening, The display device according to claim 12.
14. The aforementioned peripheral region further includes a plurality of dummy pixels that do not display an image, The inorganic insulating layer has a contact portion that penetrates in the lamination direction, The conductive layer is electrically connected to the electrode layer via the contact portion. The contact portion is located between the plurality of dummy pixels and the end of the first organic insulating layer. The display device according to claim 12.
15. The invention further comprises a second organic insulating layer disposed below the first organic insulating layer, The second organic insulating layer protrudes beyond the end, The display device according to claim 11.
16. The aforementioned protruding portion is covered by the electrode layer. The display device according to claim 15.