Semiconductor device and method of manufacturing the same

Abstract

To stably provide a highly pressure-proof semiconductor device having a positive bevel terminal structure, particularly, a highly pressure-proof rectifying device suitable for power application, with little damage.SOLUTION: In a semiconductor device, a bottom electrode, a substrate, a semiconductor layer made of a single crystal GaN having a wurtzite structure, and an upper structure are stacked in sequence. The semiconductor layer assumes a hexagonal shape, the plane of which is composed of sides perpendicular to an m-axis. Its cross-section assumes an inverse tapered and undercut shape with an inclination angle of 43.2±5° or 62.0±5°.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In recent years, the demand for power devices has been increasing rapidly, and they have already become key devices in hybrid cars, high-efficiency trains, and power circuit breakers. Furthermore, power devices are positioned as essential electronic devices to support the smart society of the future. For this reason, the demand for power devices is expected to continue to increase in the future.

[0003] One of the important characteristics required for power devices is their breakdown voltage, and it is known that the breakdown voltage of electronic devices can be significantly improved by performing termination treatment that alleviates electric field concentration at the junction edges of semiconductor layers.

[0004] This termination process includes field plate termination, guard ring termination, and bevel termination, all of which have the effect of extending the depletion layer at the edge and reducing electric field concentration. Of these, the most effective is said to be the positive bevel termination.

[0005] A positive bevel termination is realized by performing a bevel processing on the junction edge so that the semiconductor layer gradually narrows in the direction in which the depletion layer expands, as disclosed in Non-Patent Document 1. In this case, the smaller the bevel angle, that is, the shallower the bevel, the greater the effect of reducing the electric field at the edge (here, a bevel angle of 90° means vertical). On the other hand, in rectifying elements that expand the depletion layer toward the substrate, reverse taper processing is required to achieve this. Although there have been research reports on reverse taper processing using wafer cutting, there are concerns about the introduction of processing damage to device junctions, and it is not easy to apply this to products. For this reason, although positive bevel termination is known to be effective, it has not yet been put to practical use. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] BLDAVIS et al., IEEE Transactions on Electron Devices 14, 157 (1967) [Non-Patent Document 2] DAStocker et al.,Appl.Phys.Lett.,73,2654(1998)https: / / doi.org / 10.1063 / 1.122543 [Non-Patent Document 3] RSQhalid Hareedtocker et al.,Appl.Phys.Lett.,77,2345(2000)https: / / doi.org / 10.1063 / 1.1316063 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention aims to provide a semiconductor device having a positive bevel termination structure and high breakdown voltage, particularly a rectifying element having high breakdown voltage suitable for power applications, with little damage and in a stable manner. Another object of the present invention is to provide a method for manufacturing the semiconductor device. [Means for solving the problem]

[0008] The configuration of the present invention is shown below. (Configuration 1) A semiconductor device in which a lower electrode, a substrate, a semiconductor layer made of single crystal GaN with a wurtzite structure, and an upper electrode are sequentially stacked, The semiconductor layer has a hexagonal plane with sides perpendicular to the m-axis, and a cross section of an inverted taper undercut shape with an inclination angle of 43.2±5° or 62.0±5°. (Configuration 2) 2. The semiconductor device according to claim 1, wherein at least a surface of a reverse tapered undercut portion of the semiconductor layer not in contact with the substrate and the upper electrode is covered with an insulating passivation layer. (Configuration 3) 3. The semiconductor device according to configuration 2, wherein the passivation layer is made of at least one material selected from the group consisting of a silicon oxide film, a silicon nitride film, and an oxynitride film. (Configuration 4) 4. The semiconductor device according to claim 2 or 3, wherein the passivation layer has a thickness of 1 nm or more and 1000 nm or less. (Configuration 5) The substrate is a single crystal GaN or single crystal 4H-SiC with a wurtzite structure, and has a donor impurity concentration of 10 17 cm -3 Over 10 20 cm -3 5. The semiconductor device according to any one of configurations 1 to 4, doped with: (Configuration 6) 6. The semiconductor device according to any one of configurations 1 to 5, wherein the lower electrode is made of a material including one or more selected from the group consisting of nickel (Ni), platinum (Pt), zinc (Zn), aluminum (Al), cadmium (Cd), gold (Au), silver (Ag), tungsten (W), chromium (Cr), copper (Cu), lead (Pb), magnesium (Mg), manganese (Mn), titanium (Ti), iron (Fe), and tin (Sn). (Configuration 7) 7. The semiconductor device according to any one of configurations 1 to 6, wherein the upper electrode is made of a material including one or more selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), cobalt (Co) and palladium (Pd). (Configuration 8) The semiconductor layer is doped with n-type impurities at 15 cm -3 Over 10 18 cm -3 8. The semiconductor device according to any one of configurations 1 to 7, wherein the following concentration is introduced: (Configuration 9) The semiconductor layer is doped with at least two kinds of impurities, and the impurities cause n - layer, p - Layer and p + 8. The semiconductor device of any one of configurations 1 to 7, wherein the layers are stacked in order from bottom to top. (Configuration 10) 10. The semiconductor device according to any one of configurations 1 to 9, wherein the semiconductor layer has a planar shape of a regular hexagon. (Configuration 11) forming a mask layer having a hexagonal opening with sides perpendicular to an m-axis on a first main surface of a substrate made of a single crystal; forming a semiconductor layer made of GaN by selective epitaxial growth of GaN in the opening on the substrate; removing the mask layer by wet etching; Etching the semiconductor layer with an anisotropic wet etching solution to form an undercut-shaped GaN semiconductor layer having a sloped sidewall with an angle of 43.2±5° or 62.0±5° between a top surface and a side surface; forming a first conductor layer on at least a portion of an upper surface of the sloped sidewall semiconductor layer; forming an insulating passivation layer so that at least an exposed portion of the sloped sidewall semiconductor layer is covered with the passivation layer; forming a second conductive layer on a second main surface of the substrate. (Configuration 12) 12. The method for manufacturing a semiconductor device according to claim 11, wherein the opening is a regular hexagon. (Configuration 13) The anisotropic wet etchant is H 3 PO 4 , H 2 SO 4 , HCl, HNO 3 13. The method for producing a semiconductor device according to claim 11 or 12, wherein the solvent is one selected from the group consisting of HF, KOH, NaOH and TMAH. (Configuration 14) 14. The method for manufacturing a semiconductor device according to any one of claims 11 to 13, wherein the substrate is a single crystal GaN having a wurtzite structure. (Configuration 15) 15. The method of claim 11, wherein the mask layer is made of at least one material selected from the group consisting of a silicon oxide film, a silicon nitride film, and an oxynitride film. (Configuration 16) 15. The method for manufacturing a semiconductor device according to any one of claims 11 to 14, wherein the mask layer is made of one selected from the group consisting of tungsten (W), ruthenium (Ru), molybdenum (Mo), and tantalum (Ta). (Configuration 17) The passivation layer is made of SiO 2 , Si 3 N 4 , Al 2 O 3 , and HfO 2 17. The method for manufacturing a semiconductor device according to any one of configurations 11 to 16, comprising one selected from the group consisting of: (Configuration 18) 18. The method for manufacturing a semiconductor device according to any one of structures 11 to 17, wherein the second conductive layer is made of a material including one or more selected from the group consisting of nickel (Ni), platinum (Pt), zinc (Zn), aluminum (Al), cadmium (Cd), gold (Au), silver (Ag), tungsten (W), chromium (Cr), copper (Cu), lead (Pb), magnesium (Mg), manganese (Mn), titanium (Ti), iron (Fe), and tin (Sn). (Configuration 19) 19. The method for manufacturing a semiconductor device according to any one of configurations 11 to 18, wherein the first conductive layer is made of a material including one or more selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), cobalt (Co) and palladium (Pd). (Configuration 20) The semiconductor layer is doped with n-type impurities at 15 cm -3 Over 10 18 cm -3 20. The method for producing a semiconductor device according to any one of configurations 11 to 19, wherein the following concentration is introduced: (Configuration 21) The semiconductor layer is doped with at least two kinds of impurities, and the impurities cause n - layer, p - Layer and p + 20. The method for manufacturing a semiconductor device according to any one of configurations 11 to 19, wherein the layers are stacked in order from bottom to top. Effect of the Invention

[0009] According to the present invention, it is possible to stably provide a semiconductor device having a positive bevel termination structure with high breakdown voltage, in particular a rectifying element with high breakdown voltage suitable for power applications, with little damage, and also to provide a method for manufacturing the semiconductor device. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device of the present invention. [Diagram 2] 1 is a plan view showing a planar shape of a semiconductor layer of a semiconductor device according to the present invention; [Diagram 3] 4 is a cross-sectional view showing an electric field distribution in the vicinity of a termination portion of the semiconductor device of the present invention. [Figure 4] 1A to 1C are process diagrams illustrating, in cross-section, a manufacturing process for a semiconductor device according to the present invention; [Diagram 5] 1A to 1C are process diagrams illustrating, in cross-section, a manufacturing process for a semiconductor device according to the present invention; [Figure 6] FIG. 2 is a plan view showing the planar shape of a mask layer. [Figure 7] FIG. 2 is a flow chart showing a manufacturing process of the semiconductor device of the present invention. [Figure 8] FIG. 4 is a cross-sectional view showing the structure of a second semiconductor device of the present invention. [Figure 9] 5A to 5C are cross-sectional views showing a process for manufacturing a second semiconductor device according to the present invention. [Figure 10] 5A to 5C are cross-sectional views showing a process for manufacturing a second semiconductor device according to the present invention. [Figure 11] FIG. 11 is a flow chart showing a manufacturing process of the second semiconductor device of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (Embodiment 1) In the first embodiment, a Schottky rectifier device (semiconductor device) 101 will be described.

[0012] <Structure> 1, this Schottky rectifier device 101 is a semiconductor device in which a lower electrode (cathode electrode, second conductive layer) 16, a substrate 11, a semiconductor layer 13, and an upper electrode (anode electrode, first conductive layer) 14 are laminated from the bottom, and at least the exposed side surface of the semiconductor layer 13 is protected (covered) with a passivation layer 15. The semiconductor layer 13 is characterized by having a cross-sectional shape (see FIG. 1) that is an inverse tapered undercut shape with a cross-sectional inclination angle θ of 43.2±5° or 62.0±5°, and a planar shape (see FIG. 2) that is a hexagon with sides perpendicular to the m-axis.

[0013] Here, the lower electrode 16 is not particularly limited to a material as long as it can make ohmic contact with the substrate 11 and has high conductivity, but a material containing one or more selected from the group consisting of nickel (Ni), platinum (Pt), zinc (Zn), aluminum (Al), cadmium (Cd), gold (Au), silver (Ag), tungsten (W), chromium (Cr), copper (Cu), lead (Pb), magnesium (Mg), manganese (Mn), titanium (Ti), iron (Fe), and tin (Sn) is preferably used. These materials can be easily formed into a film by sputtering, MOCVD (Metal Organic Chemical Vapour Deposition) thermal evaporation, electron beam evaporation, and coating methods, and have the characteristic of having a relatively high conductivity. The thickness of the lower electrode 16 is not particularly limited, but may be, for example, 0.1 μm or more and 1 μm or less.

[0014] The substrate 11 may be made of single crystal GaN or single crystal 4H-SiC having a wurtzite structure. Here, when single crystal GaN with a wurtzite structure is used as the substrate 11, it becomes possible to easily form a high-quality semiconductor layer 13 with few crystal defects. For this reason, single crystal GaN with a wurtzite structure is particularly preferably used as the substrate 11. Note that a thick epitaxially formed GaN film may also be used as the substrate 11. In order for the Schottky rectifier 101 to have sufficient current characteristics, the substrate 11 must have a donor impurity concentration of 10.17 cm -3 Over 10 20 cm -3 It is preferable that the semiconductor layer is doped with the following: The donor impurity may be one or more selected from the group consisting of Si, Ge, and Sn. The thickness of the substrate is not particularly limited, but if the substrate has sufficient rigidity to stand on its own, it is easy to handle as a semiconductor device. On the other hand, if the substrate is too thick, resources are wasted and electrical resistance increases, so the substrate thickness can be, for example, 200 μm to 1000 μm.

[0015] The semiconductor layer 13 is a single crystal GaN with a wurtzite structure, and has an n-type impurity concentration of 10 15 cm -3 Over 10 18 cm -3 It is preferable that the n-type impurity is doped with one or more elements selected from the group consisting of Si, Ge, and Sn. The thickness of the semiconductor layer 13 is determined according to the desired breakdown voltage, but is usually within the range of 1 μm to 20 μm. The semiconductor layer 13 is formed by an epitaxial method. Alternatively, it may be formed by a bonding method. When the substrate is 4H-SiC, the bonding method is preferably used.

[0016] The upper electrode 14 is not particularly limited as long as it is a conductive film that forms a Schottky junction with the semiconductor layer 13, but it is preferable to use a material containing one or more elements selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), cobalt (Co) and palladium (Pd), which have excellent Schottky junction characteristics. These materials can be easily formed into a film by sputtering, MOCVD (Metal Organic Chemical Vapour Deposition), thermal evaporation, electron beam evaporation and coating methods. The thickness of the upper electrode 14 is not particularly limited, but may be, for example, 0.1 μm to 10 μm inclusive. If wire bonding is envisaged, the thickness is preferably 1 μm or more.

[0017] The passivation layer 15 has a function of terminating dangling bonds on the semiconductor surface and protecting the semiconductor device 101 from moisture, contaminants, and particles from the environment. 2 ), nitride film (Si 3 N 4 ), and oxynitride film (SiON). Among these, silicon compounds containing nitrogen are particularly preferred because they are dense, have low gas permeability, and have high passivation ability. On the other hand, SiO 2 However, since it is possible to easily and stably form a film with few defects and, moreover, etching and the like are easy, it is preferably used. Methods for forming the passivation layer 15 include a sputtering method, a CVD (Chemical Vapour Deposition) method, and a coating method. The thickness of the passivation layer 15 can be 1 nm or more and 1000 nm or less. If the thickness of the passivation layer 15 is 1 nm, the passivation ability is reduced through defects, etc. If the thickness exceeds 1000 nm, the passivation ability is saturated. The film formation time is also lengthened, which reduces productivity, and problems such as film stress occur.

[0018] The planar shape of the Schottky rectifier (semiconductor device) 101 is a hexagon with sides perpendicular to the m-axis. α The shape of the semiconductor layer 13 (upper surface) is a long hexagon or as shown in FIG. β The shape of the top surface may be either a regular hexagon or a regular hexagon. Here, a long hexagon has the advantage that it is easy to package in a rectangular semiconductor device package while minimizing dead space, and is easy to use and has excellent packing density, while a regular hexagon has the advantage that crystal defects are less likely to occur and a high yield is easily obtained.

[0019] In order to show the effect of the structure of the Schottky rectifier (semiconductor device) 101, the effect of reducing electric field concentration was confirmed by simulation. The parameters were a drift layer thickness of 5 μm, a carrier density of 10 18 cm -3 The surface that forms the reverse taper is {10-1-2}. The taper angle (the angle between the top and side) is 43.2°. Figure 3 shows the results of simulating the electric field distribution and reverse electric field distribution when -200V is applied. It can be seen that the spacing between the equipotential lines widens at the anode end, easing the electric field.

[0020] <Production method> A method for manufacturing Schottky rectifier (semiconductor device) 101 will be described with reference to cross-sectional structural views of FIGS. 4 and 5, a plan view of a pattern layout of a mask layer of FIG. 6, and a flow chart of FIG.

[0021] First, single crystal n + A substrate 11 is prepared (step S11). The substrate 11 may be made of single crystal GaN or single crystal 4H-SiC having a wurtzite structure. Here, when single crystal GaN with a wurtzite structure is used as the substrate 11, it becomes possible to easily form a high-quality semiconductor layer 13 with few crystal defects. For this reason, single crystal GaN with a wurtzite structure is particularly preferably used as the substrate 11. The substrate 11 has a donor impurity concentration of 10 17 cm -3 Over 10 20 cm -3 It is preferably doped with:

[0022] Next, a mask layer 12 having a hexagonal opening 22 with sides perpendicular to the m-axis as shown in FIG. 7 is formed on the first main surface of the substrate 11 (step S12, FIG. 4(a)). The mask layer 12 is made of silicon dioxide (SiO 2 ) can be preferably used as the mask layer 12. In addition, a silicon oxide film (SiO x ), nitride film (Si 3 N4 The material may be one or more selected from the group consisting of silicon oxynitride (SiNO), and one selected from the group consisting of tungsten (W), ruthenium (Ru), molybdenum (Mo), and tantalum (Ta). The film thickness is preferably 50 nm to 1000 nm in view of the subsequent production of the bevel structure of the semiconductor layer 13. The mask layer 12 is preferably formed by sputtering or CVD. The opening 22 in the mask layer 12 can be produced by lithography and etching. Alternatively, lift-off may be applied.

[0023] Thereafter, a semiconductor layer 13' made of GaN and consisting of only c-plane (upper surface) and m-plane (side surface) facets is formed in the opening by selective epitaxial growth (step S13, FIG. 4(b)). This shape is achieved by setting a small V / III ratio in selective epitaxial growth and slowing down the growth rate. For example, Non-Patent Document 3 shows an example of this. It is preferable to introduce impurities in the selective growth. The impurities may be one or more selected from the group consisting of Si, Ge, and Sn, and the concentration of the impurities may be 10 15 cm -3 Over 10 18 cm -3 The following can be mentioned: Although the selective epitaxial growth method has been described here as a method for forming the semiconductor layer 13', a bonding method may be used instead of the selective epitaxial growth method. The thickness of the semiconductor layer 13' may be 1 μm or more and 20 μm or less.

[0024] Thereafter, the mask layer 12 is removed by wet etching (step S14, FIG. 4(c)). Here, the wet etching solution may be a hydrofluoric acid-based etching solution, such as an aqueous hydrofluoric acid solution or a mixture of an ammonium fluoride buffer solution and hydrofluoric acid. This mask layer 12 removal step exposes the edge portion underside 21 of the semiconductor layer 13'. This exposed surface is the -c plane.

[0025] Thereafter, the semiconductor layer 13' is anisotropically wet etched to form the reverse-inclined sidewall semiconductor layer 13 (step S15, FIG. 4(d)). Here, the anisotropic wet etching solution is H 3 PO 4 , H 2 SO 4 , HCl, HNO 3 HF, KOH, NaOH and TMAH (tetramethyammoniuhydroxide), and in particular hot phosphoric acid (H 3 PO 4 ) and KOH can be preferably used. Here, hot phosphoric acid is preferably used at a temperature of 100° C. to 200° C., since this allows etching with high controllability. While the -c plane is rapidly etched by this anisotropic etching, the etching rate of the +c plane, which is the top surface of the semiconductor layer 13', is slow. The side surface of the semiconductor layer 13' is selectively etched along {10-1-2} or {10-1-1}, so that the semiconductor layer 13 made of single crystal GaN is formed in an undercut shape with a side surface inclination angle θ (the angle between the top surface and the side surface) of 43.2±5° or 62.0±5°.

[0026] Incidentally, Non-Patent Document 2 discloses that GaN formed on a sapphire substrate via an AlN buffer layer is selectively etched along the crystal plane by etching the GaN with the anisotropic wet etching solution. A feature of the present invention is that semiconductor layer 13' made of GaN is formed on substrate 11 made of GaN, and an undercut shape of semiconductor layer 13 made of single crystal GaN is formed by utilizing the -c plane formed on underside 21 of an edge portion of the pattern of the semiconductor layer.

[0027] Next, to form an upper electrode, a conductive layer 14' is deposited on the substrate 11 and the semiconductor layer 13 (FIG. 5(a)), and then the conductive layer 14' on the substrate 11 is etched away (side slope) to form a first electrode 14 (anode, upper electrode) on the upper surface of the semiconductor layer 13 (step S16, FIG. 5(b)). Here, the conductive layer 14' is preferably made of a material containing one or more elements selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), cobalt (Co) and palladium (Pd), which have excellent Schottky junction characteristics. These materials can be easily formed into a film by sputtering, MOCVD (Metal Organic Chemical Vapour Deposition), thermal evaporation, electron beam evaporation and coating methods. The thickness of the upper electrode 14 is not particularly limited, but may be, for example, 0.1 μm or more and 10 μm or less.

[0028] Thereafter, at least the exposed surface of the (slant sidewall) semiconductor layer 13 is covered with a passivation layer 15 (step S17, FIG. 5(c)). The passivation layer 15 is a silicon oxide film (SiO 2 ), nitride film (Si 3 N 4 ), and an oxynitride film (SiON) can be preferably used. Methods for forming the passivation layer 15 include a sputtering method, a CVD (Chemical Vapour Deposition) method, and a coating method. The thickness of the passivation layer 15 can be 1 nm or more and 1000 nm or less.

[0029] Thereafter, a second electrode 16 (cathode, lower electrode) is formed on the second main surface of the substrate 11 to produce a Schottky rectifier device (semiconductor device) 101 (step S18, FIG. 5(d)). Here, a material containing one or more selected from the group consisting of nickel (Ni), platinum (Pt), zinc (Zn), aluminum (Al), cadmium (Cd), gold (Au), silver (Ag), tungsten (W), chromium (Cr), copper (Cu), lead (Pb), magnesium (Mg), manganese (Mn), titanium (Ti), iron (Fe), and tin (Sn) can be preferably used as the lower electrode 16. These materials can be easily formed into a film by sputtering, MOCVD (Metal Organic Chemical Vapour Deposition) thermal evaporation, electron beam evaporation, and coating methods, and have the characteristic of having a relatively high electrical conductivity. The thickness of the lower electrode 16 is not particularly limited, but may be, for example, 0.1 μm or more and 1 μm or less.

[0030] The manufactured Schottky rectifier 101 is a Schottky rectifier having a positive bevel termination structure and high withstand voltage, which enables a stable supply of rectifier elements having high withstand voltage suitable for power applications.

[0031] (Embodiment 2) In the second embodiment, a p / n type rectifier device (semiconductor device) 102 will be described.

[0032] <Structure> The p / n type rectifier 102 described in the second embodiment is a semiconductor device conforming to the structure of the Schottky type rectifier 101, except that the semiconductor layer is composed of three semiconductor layers 13a, 13b and 13c, and the upper electrode (anode electrode) 14 is made of a conductive material suitable for making ohmic contact with the semiconductor layer 13c, as shown in FIG. 8. Therefore, like the Schottky rectifier 101, the p / n rectifier 102 has a cross-sectional shape consisting of an inverted taper undercut shape with a cross-sectional inclination angle θ of 43.2±5° or 62.0±5° for the three semiconductor layers 13a, 13b and 13c, and a planar shape that is a hexagon with sides perpendicular to the m-axis (see Figure 2).

[0033] The hexagonal shape may be either a long hexagon as shown in Fig. 2(a) or a regular hexagon as shown in Fig. 2(b), as in the case of the Schottky rectifier 101. Here, a long hexagon has the advantage that it is easy to package in a rectangular semiconductor device package while minimizing dead space, and is easy to use and has excellent packing density, while a regular hexagon has the advantage that crystal defects are less likely to occur and a high yield is easily obtained.

[0034] Here, the semiconductor layer 13a located in the lower layer is n - The semiconductor layer 13b located in the middle is p - The semiconductor layer and the semiconductor layer 13c located above are p + For example, the semiconductor layer 13a is - type GaN, semiconductor layer 13b is p - type GaN, and the semiconductor layer 13c is p + Examples of such GaN include GaN. n - The semiconductor layer 13a has an impurity concentration of 10 15 cm -3 Over 10 18 cm -3 The following is a relatively small n-type semiconductor layer, p - The semiconductor layer 13b has an impurity concentration of 10 15 cm -3 Over 10 18 cm -3 The p-type semiconductor layer is relatively small, and + The semiconductor layer 13c has an impurity concentration of 10 17 cm -3 Over 10 20 cm -3 The following represents the relatively large p-type semiconductor layer. Examples of n-type impurities include Si, Ge, and Sn, and examples of p-type impurities include Zn and Mg. Thus, at least two types of impurities are introduced into the semiconductor layers 13a, 13b, and 13c.

[0035] As a method for introducing impurities, a gas containing these impurities may be used when forming the semiconductor layers 13a, 13b, and 13c by epitaxial growth. The thickness of the semiconductor layer is not particularly limited, but - The semiconductor layer 13a has a thickness of 1 μm or more and 20 μm or less. - The semiconductor layer 13b has a thickness of 1 μm or more and 20 μm or less. + The semiconductor layer 13c may have a thickness of 0.1 μm or more and 10 μm or less.

[0036] The upper electrode (anode electrode) 14 is made of a conductive material suitable for making ohmic contact with the semiconductor layer 13c, and examples of such materials include one or more selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), cobalt (Co) and palladium (Pd). The thickness of the upper electrode 14 is not particularly limited, but may be, for example, 0.1 μm or more and 10 μm or less.

[0037] The p / n type rectifier 102 has a reverse tapered undercut shape (bevel structure) in which the cross-sectional inclination angle θ of the semiconductor layers 13a, 13b, and 13c is 43.2±5° or 62.0±5°, and similarly to the Schottky type rectifier 101 of the first embodiment, the distance between the equipotential lines widens at the anode end which is the upper electrode 14, and the electric field is relaxed. Therefore, according to the second embodiment, it is possible to stably provide a p / n type rectifier with a positive bevel end structure having a high withstand voltage, in particular a rectifier element with a high withstand voltage suitable for power applications, with less damage.

[0038] <Production method> A method for manufacturing the p / n type rectifier device 102 will now be described with reference to cross-sectional structural diagrams FIGS. 9 and 10 and a flow chart diagram FIG.

[0039] First, as in the first embodiment, a single crystal n + A substrate 11 is prepared (step S11). The substrate 11 may be made of single crystal GaN or single crystal 4H-SiC having a wurtzite structure. Here, when single crystal GaN with a wurtzite structure is used as substrate 11, it becomes possible to easily form high quality semiconductor layers 13a, 13b, and 13c with few crystal defects. For this reason, single crystal GaN with a wurtzite structure is particularly preferably used as substrate 11. The substrate 11 has a donor impurity concentration of 10 17 cm -3 Over 10 20 cm -3 It is preferably doped with:

[0040] Next, a mask layer 12 having a hexagonal opening 22 with sides perpendicular to the m-axis as shown in FIG. 7 is formed on the first main surface of the substrate 11 (step S12, FIG. 9(a)). The mask layer 12 is made of silicon dioxide (SiO 2 ) can be preferably used as the mask layer 12. In addition, a silicon oxide film (SiO x ), nitride film (Si 3 N 4 The material may be one or more selected from the group consisting of silicon oxynitride (SiNO), and one selected from the group consisting of tungsten (W), ruthenium (Ru), molybdenum (Mo), and tantalum (Ta). The film thickness is preferably 50 nm to 1000 nm in view of the subsequent production of the bevel structure of the semiconductor layer 13. The mask layer 12 is preferably formed by sputtering or CVD. The opening 22 in the mask layer 12 can be produced by lithography and etching. Alternatively, lift-off may be applied.

[0041] Thereafter, semiconductor layers 13a', 13b', and 13c' made of GaN and consisting only of c-plane (upper surface) and m-plane (side surface) facets are successively formed in the openings by selective epitaxial growth (step S13, FIG. 9(b)). This shape is achieved by setting a small V / III ratio in selective epitaxial growth and slowing down the growth rate, as described above. For example, Non-Patent Document 3 shows an example of this. In this selective growth, impurities are introduced. - The semiconductor layer 13a' has a concentration of 10 15 cm -3 Over 10 18 cm -3 The following n-type impurities are called p - The semiconductor layer 13b' has a concentration of 10 15 cm -3 Over 10 18 cm -3 The following p-type impurities are used: + The semiconductor layer 13c' has a concentration of 10 17 cm -3 Over 10 20 cm -3 The following p-type impurities are introduced. Examples of n-type impurities include Si, Ge, and Sn, and examples of p-type impurities include Zn and Mg. Thus, at least two types of impurities are introduced into the semiconductor layers 13a, 13b, and 13c. The thicknesses of the semiconductor layers 13a', 13b', and 13c' are, for example, 1 μm to 20 μm, 1 μm to 20 μm, and 0.1 μm to 10 μm, respectively.

[0042] Thereafter, the mask layer 12 is removed by wet etching (step S14, FIG. 9(c)). Here, the wet etching solution may be a hydrofluoric acid-based etching solution, such as an aqueous hydrofluoric acid solution or a mixture of an ammonium fluoride buffer solution and hydrofluoric acid. This mask layer 12 removal step exposes the edge portion undersurfaces 21 of the semiconductor layers 13a', 13b', and 13c'. This exposed surface is the -c surface.

[0043] Thereafter, the semiconductor layers 13a', 13b', and 13c' are anisotropically wet etched to form the three-layered semiconductor layers 13a, 13b, and 13c with reversely inclined sidewalls (step S15, FIG. 9(d)). Here, the anisotropic wet etching solution is H 3 PO 4 , H 2 SO 4 , HCl, HNO3 HF, KOH, NaOH and TMAH (tetramethylammonium hydroxide), and in particular hot phosphoric acid (H 3 PO 4 ) and KOH can be preferably used. Here, hot phosphoric acid is preferably used at a temperature of 100° C. to 200° C., since this allows etching with high controllability. The -c plane is rapidly etched by this anisotropic etching, while the etching rate of the +c plane, which is the top surface of semiconductor layer 13c', is slow. The side surfaces of semiconductor layers 13a', 13b', and 13c' are selectively etched along {10-1-2} or {10-1-1}, resulting in the formation of semiconductor layers 13a, 13b, and 13c made of single-crystal GaN with an undercut shape and a side surface inclination angle θ (the angle between the top surface and the side surface) of 43.2±5° or 62.0±5°.

[0044] Next, in order to form the upper electrode 14, the same steps as in the first embodiment are followed to form the first electrode 14 (anode, upper electrode) on the upper surface of the semiconductor layer 13c (step S16, FIG. 10(a)). Here, the upper electrode 14 may be made of a material containing one or more selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), cobalt (Co) and palladium (Pd). These materials can be easily formed into films by sputtering, MOCVD, thermal evaporation, electron beam evaporation and coating methods. The thickness of the upper electrode 14 is not particularly limited, but may be, for example, 0.1 μm or more and 10 μm or less.

[0045] Thereafter, at least the exposed surfaces of the (sloping sidewall) semiconductor layers 13a, 13b and 13c are covered with a passivation layer 15 (step S17, FIG. 10(c)). The passivation layer 15 is a silicon oxide film (SiO 2 ), nitride film (Si 3 N 4 ), and an oxynitride film (SiON) can be preferably used. Methods for forming the passivation layer 15 include a sputtering method, a CVD (Chemical Vapour Deposition) method, and a coating method. The thickness of the passivation layer 15 can be 1 nm or more and 1000 nm or less.

[0046] Thereafter, a second electrode 16 (cathode, lower electrode) is formed on the second main surface of the substrate 11 to produce a p / n type rectifier device 102 (semiconductor device) 102 (step S18, FIG. 10(d)). Here, a material containing one or more selected from the group consisting of nickel (Ni), platinum (Pt), zinc (Zn), aluminum (Al), cadmium (Cd), gold (Au), silver (Ag), tungsten (W), chromium (Cr), copper (Cu), lead (Pb), magnesium (Mg), manganese (Mn), titanium (Ti), iron (Fe), and tin (Sn) can be preferably used as the lower electrode 16. These materials can be easily formed into a film by sputtering, MOCVD (Metal Organic Chemical Vapour Deposition) thermal evaporation, electron beam evaporation, and coating methods, and have the characteristic of having a relatively high electrical conductivity. The thickness of the lower electrode 16 is not particularly limited, but may be, for example, 0.1 μm or more and 1 μm or less.

[0047] The manufactured p / n type rectifier 102 is a Schottky type rectifier with a positive bevel termination structure and high breakdown voltage, which enables a stable supply of rectifier elements with high breakdown voltage suitable for power applications.

[0048] In the first embodiment, a Schottky rectifier element 101 is described, and in the second embodiment, a p / n rectifier device 102 is described. However, the applicable elements of the present invention are not necessarily limited to Schottky rectifier elements and p / n rectifier devices, and the present invention can also be applied to semiconductor devices such as avalanche photodiodes. The essence of the present invention is that the semiconductor layer is made of GaN, its cross section has an inverted taper undercut shape with an inclination angle of 43.2±5° or 62.0±5°, and its plane has a hexagonal shape with sides perpendicular to the m-axis. This shape relaxes the electric field near the edge of the semiconductor layer, improving the breakdown voltage. To obtain a semiconductor device with high breakdown voltage by taking advantage of this electric field relaxation, electrodes of the semiconductor device are arranged above and below the semiconductor layer. Here, the hexagonal planar shape is not directly related to the electric field relaxation, but is a necessary element in manufacturing in order to obtain the cross-sectional shape of the inverse tapered undercut having the angle specified as described above. [Industrial Applicability]

[0049] The present invention provides a semiconductor device having high withstand voltage, in particular a rectifying element having high withstand voltage suitable for power applications, and a method for manufacturing the same. This semiconductor device uses GaN semiconductors, which have both a breakdown voltage and a wide band gap suitable for power applications, and its geometric characteristics also allow for the relaxation of the electric field distribution at the ends, which improves the breakdown voltage, resulting in an extremely high breakdown voltage. Power devices are used in a variety of fields, including powertrains for EVs and hybrid vehicles, power supplies for servers, renewable energy equipment, industrial equipment, and railroad cars, and are considered essential devices for realizing a smart society. For this reason, we believe that this invention will have a large impact on society and a large influence on industry. [Explanation of symbols]

[0050] 11 Substrate (GaN) 12 Mask layer (SiO 2 ) 13 Semiconductor layer 13´ Semiconductor layer 13 α Semiconductor Layer 13 β Semiconductor Layer 13a n - Semiconductor layer (n - GaN) 13a´ n- Semiconductor layer (n - GaN) 13b p - Semiconductor layer (p - GaN) 13b´ p - Semiconductor layer (p - GaN) 13c p + Semiconductor layer (p + GaN) 13c´ p + Semiconductor layer (p + GaN) 14 Upper electrode, first conductive layer, anode electrode 14´ Conductive layer 15 Passivation Layer 16 Lower electrode, second conductive layer, cathode electrode 21 -c plane 22 Aperture 101 Semiconductor devices (Schottky rectifiers) 102 Semiconductor devices (p / n type rectifiers)

Claims

1. A semiconductor device in which a lower electrode, a substrate, a semiconductor layer made of single-crystal GaN with a wurtz structure, and an upper electrode are sequentially stacked, A semiconductor device wherein the semiconductor layer has a hexagonal plane with sides perpendicular to the m-axis, and its cross-section has an inverted tapered undercut shape with an inclination angle of 43.2 ± 5° or 62.0 ± 5°.

2. The semiconductor device according to claim 1, wherein at least the surface of the reverse taper undercut portion of the semiconductor layer that is not in contact with the substrate and the upper electrode is covered with an insulating passivation layer.

3. The semiconductor device according to claim 2, wherein the passivation layer consists of one or more selected from the group consisting of silicon oxide films, nitride films, and oxynitride films.

4. The semiconductor device according to claim 2 or 3, wherein the thickness of the passivation layer is 1 nm or more and 1000 nm or less.

5. The substrate is a wurtz-structured single-crystal GaN or single-crystal 4H-SiC, and the donor impurity is concentrated at a concentration of 10 １７ cm －３ The above 10 ２０ cm －３ A semiconductor device according to any one of claims 1 to 3, which is doped with the following:

6. The semiconductor device according to any one of claims 1 to 3, wherein the lower electrode is made of a material containing one or more selected from the group consisting of nickel (Ni), platinum (Pt), zinc (Zn), aluminum (Al), cadmium (Cd), gold (Au), silver (Ag), tungsten (W), chromium (Cr), copper (Cu), lead (Pb), magnesium (Mg), manganese (Mn), titanium (Ti), iron (Fe), and tin (Sn).

7. The semiconductor device according to any one of claims 1 to 3, wherein the upper electrode is made of a material containing one or more selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), cobalt (Co), and palladium (Pd).

8. The aforementioned semiconductor layer has 10 n-type impurities. １５ cm －３ The above 10 １８ cm －３ A semiconductor device according to any one of claims 1 to 3, which is introduced at the following concentrations.

9. The semiconductor layer has at least two or more types of impurities introduced therein, and an n － layer, a p － layer, and a p ＋ layer are sequentially stacked and formed from bottom to top. The semiconductor device according to any one of claims 1 to 3.

10. The semiconductor device according to any one of claims 1 to 3, wherein the planar shape of the semiconductor layer is a regular hexagon.

11. A mask layer having hexagonal openings with sides perpendicular to the m-axis is formed on the first main surface of a single crystal substrate, A semiconductor layer made of GaN is formed by selectively epitaxially growing GaN in the opening on the substrate, The aforementioned mask layer is removed by wet etching, The semiconductor layer is etched using an anisotropic wet etching solution to form a sidewall gradient semiconductor layer made of GaN with an undercut shape where the angle between the top surface and the side surface is 43.2 ± 5° or 62.0 ± 5°. A first conductive layer is formed on at least a portion of the upper surface of the aforementioned sidewall inclined semiconductor layer, Form an insulating passivation layer such that at least the exposed portion of the sidewall inclined semiconductor layer is covered with the passivation layer, A method for manufacturing a semiconductor device, comprising forming a second conductive layer on the second main surface of the substrate.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the opening is a regular hexagon.

13. The anisotropic wet etching solution is H ３ PO ４ H ２ SO ４ HCl, HNO ３ A method for manufacturing a semiconductor device according to claim 11 or 12, wherein the material is one selected from the group consisting of HF, KOH, NaOH, and TMAH.

14. The method for manufacturing a semiconductor device according to claim 11 or 12, wherein the substrate is a single-crystal GaN with a wurtz structure.

15. The method for manufacturing a semiconductor device according to claim 11 or 12, wherein the mask layer consists of one or more selected from the group consisting of silicon oxide films, nitride films, and oxynitride films.

16. The method for manufacturing a semiconductor device according to claim 11 or 12, wherein the mask layer is made of one selected from the group consisting of tungsten (W), ruthenium (Ru), molybdenum (Mo), and tantalum (Ta).

17. The passivation layer is SiO ２ Si ３ N ４ Al ２ O ３ , and HfO ２ A method for manufacturing a semiconductor device according to claim 11 or 12, comprising one selected from the group consisting of the following.

18. The method for manufacturing a semiconductor device according to claim 11 or 12, wherein the second conductive layer is made of a material comprising one or more selected from the group consisting of nickel (Ni), platinum (Pt), zinc (Zn), aluminum (Al), cadmium (Cd), gold (Au), silver (Ag), tungsten (W), chromium (Cr), copper (Cu), lead (Pb), magnesium (Mg), manganese (Mn), titanium (Ti), iron (Fe), and tin (Sn).

19. The method for manufacturing a semiconductor device according to claim 11 or 12, wherein the first conductive layer is made of a material containing one or more selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), cobalt (Co), and palladium (Pd).

20. The aforementioned semiconductor layer has 10 n-type impurities. １５ cm －３ The above 10 １８ cm －３ A method for manufacturing a semiconductor device according to claim 11 or 12, wherein the following concentrations are introduced.

21. The semiconductor layer has at least two types of impurities introduced into it, and due to these impurities, n － layer, p － Layer and p ＋ A method for manufacturing a semiconductor device according to claim 11 or 12, wherein the layers are sequentially stacked from bottom to top.

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