Battery cluster control

Abstract

To provide a battery cluster controller.SOLUTION: According to some embodiments, a method includes connecting a first cluster controller of a first battery cluster to a serial communication bus, connecting a second cluster controller of a second battery cluster to the serial communication bus, sending synchronization data to the first cluster controller and the second cluster controller over the serial communication bus, controlling a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform, and controlling a second bridge of the second battery cluster to connect a second battery terminal of the second battery cluster to the output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform.SELECTED DRAWING: None

Description

[Technical field]

[0001] Related Applications This application claims priority to U.S. Provisional Patent No. 63 / 536,326, filed September 1, 2023, which is incorporated by reference in its entirety. [Background technology]

[0002] Battery-powered systems, such as electric vehicles, use direct current (DC) battery modules to store power. Some loads in the system may require alternating current (AC) power. Inverters and voltage regulators may be provided to convert the voltage level of the power source, or to convert from a DC power source to an AC power source or from an AC power source to a DC power source. Summary of the Invention [Means for solving the problem]

[0003] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] According to some embodiments, a method includes connecting a first cluster controller of a first battery cluster to a serial communication bus; connecting a second cluster controller of a second battery cluster to the serial communication bus; sending synchronization data to the first cluster controller and the second cluster controller via the serial communication bus; controlling a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform; and controlling a second bridge of the second battery cluster to connect a second battery terminal of the second battery cluster to the output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform.

[0005] According to some embodiments, the system includes means for connecting a first cluster controller of a first battery cluster to a serial communication bus; means for connecting a second cluster controller of a second battery cluster to the serial communication bus; means for sending synchronization data to the first cluster controller and the second cluster controller via the serial communication bus; means for controlling a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform; and means for controlling a second bridge of the second battery cluster to connect a second battery terminal of the second battery cluster to the output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform.

[0006] According to some embodiments, the battery cluster controller comprises a serial interface configured to receive synchronization data via a serial communication bus, a modulation unit configured to generate a bridge configuration signal for controlling a bridge for selectively connecting battery elements to an output terminal to generate a first component of a waveform based on a rank assigned to the battery cluster controller, and a delay unit configured to delay the bridge configuration signal based on the synchronization data to generate a delayed bridge configuration signal, wherein the bridge is controlled based on the delayed bridge configuration signal.

[0007] According to some embodiments, a system includes a first battery cluster including an output terminal, a serial communication bus, a first battery cluster including a first battery element, a first bridge configured to selectively connect the first battery element to the output terminal based on a state of the first bridge, and a first cluster controller coupled to the first bridge and the serial communication bus, a second battery cluster including a second battery element, a second bridge configured to selectively connect the second battery element to the output terminal based on a state of the second bridge, and a second cluster controller coupled to the second bridge and the serial communication bus, and a host processor configured to send synchronization data to the first cluster controller and the second cluster controller via the serial communication bus, wherein the first cluster controller is configured to control a first bridge to connect a first battery element to an output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform, and the second cluster controller is configured to control a second bridge to connect a second battery element to an output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform.

[0008] To the accomplishment of the foregoing and related ends, the following description and the annexed drawings set forth certain illustrative aspects and implementations, which are indicative of but a few of the various ways in which the one or more aspects may be employed. Other aspects, advantages and novel features of the present disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of a battery system, according to some embodiments. [Diagram 2] 1 is a schematic diagram of a battery system illustrating latency mitigation, according to some embodiments. [Diagram 3] FIG. 2 is a schematic diagram of a cluster controller in a battery system, according to some embodiments. [Figure 4] 4 is a waveform diagram illustrating an output waveform generated by a battery system according to some embodiments. [Diagram 5] FIG. 1 is a flow diagram of a method for generating a waveform in a battery system, according to some embodiments. [Figure 6] FIG. 1 illustrates an exemplary embodiment of a computer-readable medium, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The claimed subject matter will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it may be apparent that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of the claimed subject matter.

[0011] Equivalent or similar elements, or elements having equivalent or similar functions, are indicated by equivalent or similar reference numerals in the following description. Note that, in the drawings, identical or functionally equivalent elements are designated by the same reference numerals, and therefore, duplicated descriptions of elements designated by the same reference numerals may be omitted. Therefore, descriptions provided for elements having the same or similar reference numerals can be mutually exchanged.

[0012] In this regard, directional terms such as "top," "bottom," "below," "above," "front," "behind," "back," "leading," "trailing," and the like, may be used with reference to the orientation of the figures being described. Because some of the embodiments can be positioned in several different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. Therefore, the following detailed description is not to be taken in a limiting sense.

[0013] When an element is referred to as being "connected" or "coupled" to another element, it will be understood that it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted similarly (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.).

[0014] In the embodiments described herein or shown in the drawings, any direct electrical connection or coupling, i.e., any connection or coupling without additional intervening elements, may be implemented by an indirect connection or coupling, i.e., a connection or coupling with one or more additional intervening elements, or vice versa, so long as the general purpose of the connection or coupling, for example, to transmit a particular type of signal or transmit a particular type of information, is essentially maintained. Features from different embodiments may be combined to form further embodiments. For example, variations or modifications described with respect to one of the embodiments may be applicable to other embodiments, unless otherwise indicated.

[0015] The term "substantially" may be used herein to account for small manufacturing tolerances (e.g., within 5%) that may be accepted in the industry without departing from the aspects of the embodiments described herein.

[0016] 1 is a schematic diagram of a battery system 100 according to some embodiments. In some embodiments, the battery system 100 comprises battery clusters 102, individually referred to as battery clusters 102A, 102B, 102N-1, 102N, a power management integrated circuit (PMIC) 104 connected to a power supply voltage (e.g., 12V) and a ground reference (e.g., chassis ground), a host processor 106 connected to the PMIC 104 to receive a low voltage (LV) power source, and a serial transceiver 108 connected between the host processor 106 and the battery clusters 102. The battery system 100 may be implemented in an electric vehicle, and the battery clusters 102 may provide power to a load 110, such as an electric motor for moving the electric vehicle or other auxiliary loads in the electric vehicle. The battery system 100 is connected to the load 110 by a high-side output relay 112 and a low-side output relay 114 at output terminals 112T, 114T. Battery clusters 102 are subdivided and separately controlled elements of the main battery.

[0017] In some embodiments, each battery cluster 102 comprises a cluster controller 116, a battery element 118, an H-bridge 120 for selectively connecting the battery element 118 to the output relays 112 and 114, and an H-bridge driver 122 for controlling the state of the H-bridge 120. In some embodiments, the cluster controller 116 is implemented using a programmable system-on-chip (PSoC®) hardware with programmable analog sub-blocks that can be configured to control the battery cluster 102 based on instructions from the host processor 106. The cluster controller 116 may comprise a processing unit 124 including a microcontroller and non-volatile memory (or some other type of memory), and an analog front end 126. In some embodiments, the analog front end 126 provides an interface for sensing characteristics of the battery element 118, such as voltage, temperature, or other parameters. In some embodiments, the host processor 106 uses a controller area network (CAN) protocol for communicating with an external domain controller and a universal asynchronous receiver-transmitter (UART) protocol for communicating with the serial transceiver 108. The serial transceiver 108 may implement an isolated UART protocol (ISO-UART) protocol to communicate with a corresponding serial interface 302 (see FIG. 3) in the cluster controller 116. In some embodiments, the cluster controller 116 sends messages to the H-bridge driver 122 using a serial peripheral interface (SPI) or an inter-integrated circuit (I2C) protocol.

[0018] The H-bridge 120 comprises a set of switches that determine how the battery element 118 is connected to the output relays 112 and 114. In some embodiments, the state of the H-bridge 120 is controlled by the host processor 106 by sending status messages to the cluster controller 116. In some embodiments, the functionality for controlling the state of the H-bridge 120 is split between the host processor 106 and the cluster controller 116. The H-bridge 120 can be configured by an H-bridge driver 122 to isolate the battery element 118 from the output relays 112 and 114, to connect the battery element 118 to the output relays 112 and 114 with positive polarity, or to connect the battery element 118 to the output relays 112 and 114 with negative polarity.

[0019] The number of battery clusters 102 may vary. The battery system 100 in Figure 1 shows an arrangement for one phase of a three-phase system. Additional battery clusters 102 are provided for each phase (e.g., 16 clusters / phase * 3 phases = 48 battery clusters 102).

[0020] The battery clusters 102 may be separately controlled to generate a time-varying waveform at the output terminals 112T or 114T to power the load 110. For example, the state of the H-bridge 120 for the battery clusters 102 may be controlled to generate an AC waveform, such as a sinusoidal signal, at the output terminals 112T or 114T. Controlling the battery clusters 102 in this manner eliminates the need for a separate inverter between the battery system 100 and the load 110 to generate the AC waveform.

[0021] In some embodiments, the cluster controllers 116 are serially connected to a serial communication bus 108B implemented by the serial transceiver 108. The cluster controllers 116 are daisy-chained, and the cluster controller 116 forwards the message to the next cluster controller 116 in the daisy chain until all cluster controllers 116 have received the message. In some embodiments, the serial communication bus 108B is configured in a ring topology where a message for the host processor 106 is forwarded to the cluster controller 116 of the last battery cluster 102N in the daisy chain and then forwarded to the serial transceiver 108. For example, a ring topology message is sent in a counterclockwise direction from the cluster controller 116 of the battery cluster 102A to the cluster controller 116 of the battery cluster 102N. A message originating from one of the cluster controllers 116 is sent in the same direction to the serial transceiver 108 for forwarding to the host processor 106. The ring topology provides redundancy because traffic can be rerouted in the other direction if a wire is cut in the ring.

[0022] In some embodiments, the serial communication bus 108B supports automatic addressing. During system initialization, the serial transceiver 108 identifies the cluster controllers 116 of the battery clusters 102 and assigns an address, such as a ring position, to each cluster controller 116. Initially, after power-up or interface timeout, each cluster controller 116 has an address of "0", and a first bus address is assigned to the cluster controller 116 of the first battery cluster 102A in response to receiving a wake-up message from the serial transceiver 108. The cluster controller 116 of the first battery cluster 102A forwards the wake-up message to the cluster controller 116 of the second battery cluster 102B, which results in the cluster controller 116 of the second battery cluster 102B being assigned an address. The message forwarding and address assignment continues until all of the cluster controllers 116 of the battery clusters 102 have been assigned addresses. The serial transceiver 108 may also communicate the configuration of the serial communications bus 108B and the attached cluster controller 116 to the host processor 106.

[0023] On the serial communication bus 108B, the serial transceiver 108 provides isolation between the host processor 106 and the battery clusters 102 which are in different voltage domains. In an example for a 16-cluster 3-phase system, if the host processor 106 communicates in parallel with the cluster controllers 116 of the battery clusters 102, each connection between the host processor 106 and the cluster controllers 116 requires 16 isolation circuits times 3 phases for a total of 48 isolation circuits. Furthermore, parallel addressing does not support automatic addressing and requires production programming to address the battery clusters 102. The use of a serial topology reduces bill of materials costs, reduces footprint, and reduces programming complexity.

[0024] On the serial communication bus 108B, there is an inherent latency between when the host processor 106 sends a message to a target battery cluster 102 via the associated cluster controller 116 and when the target battery cluster 102 receives the message and can respond or act on it, for example to set the state of the H-bridge 120. The latency also varies depending on the position of the target battery cluster 102 in the chain on the serial communication bus 108B. To generate a 1 kHz waveform, such as a sine wave, the H-bridge state needs to be updated a minimum of every 10 μs, requiring all battery clusters 102 to be synchronized. This update frequency requires a differential latency of less than 500 ns.

[0025] To meet switch rate and latency constraints for generating a waveform to power the load 110, the host processor 106 assigns delays to the various battery clusters 102. When the cluster controller 116 of a target battery cluster 102 receives a command from the host processor 106, for example to set the state of the H-bridge 120, it delays execution of the command based on the configured delay.

[0026] 2 is a schematic diagram of a battery system 100 illustrating latency mitigation, according to some embodiments. In some embodiments, the host processor 106 sends a delay test signal 200 over the serial communication bus 108B and calculates a total propagation delay using a timer 106T. The total propagation delay includes a delay component from the serial transceiver 108 and a total delay resulting from message transfer on the serial communication bus 108B (e.g., for going around the ring). The total propagation delay is distributed evenly across the battery cluster 102 to generate synchronization data for the cluster controller 116. For a given position on the serial communication bus 108B, represented by DeviceNumber, and a measured delay, DELAY, the synchronization data represented by the distributed delay for a given device is:

number

[0027] 3 is a schematic diagram of a cluster controller 116 in the battery system 100 according to some embodiments. In some embodiments, each cluster controller 116 includes a physical layer (PHY) 300 for implementing signaling in a serial protocol (e.g., ISO-UART), a serial interface 302 for extracting data per the serial protocol, a trigger multiplexer 304, pulse width modulation (PWM) units 306 and 308 configured to generate bridge configuration signals ARM1 and ARM2 to control the H-bridge driver 122 to set the state of the H-bridge 120, and delay counters 310 and 312 for delaying the bridge configuration signals ARM1 and ARM2, respectively. The delayed bridge configuration signals ARM1 and ARM2 output by the delay counters 310 and 312 are connected to the H-bridge driver 122. In some embodiments, asserting ARM1 while deasserting the ARM2 signal controls the H-bridge driver 122 to connect the battery element 118 in positive polarity, and asserting ARM2 while deasserting the ARM2 signal controls the H-bridge driver 122 to connect the battery element 118 in negative polarity. Deasserting both ARM1 and ARM2 disconnects the battery element 118. The trigger multiplexer 304 is part of a larger group of programmable multiplexers that allow for the routing of trigger signals from any source to a destination peripheral device.

[0028] In some embodiments, the PWMs 306 and 308 are configured to generate ARM1 and ARM2 signals to control the state of the H-bridge 120. The ARM1 and ARM2 signals are delayed based on values ​​stored in associated delay counters 310 and 312. For the cluster controller 116 in the first position (cluster controller 1), the delay may be (N-1)*Delay / (N+2), and for the cluster controller 116 in the last position (cluster controller 16), the delay may be 0*Delay / (N+2). The host processor 106 sends H-bridge state messages to the cluster controller 116 to control connections with the output terminals 112T, 114T to generate waveforms. By delaying the ARM1 and ARM2 signals based on the assigned loop propagation delay, the relative timing between the changing states of the H-bridge 120 by the cluster controller 116 is controlled.

[0029] FIG. 4 is a waveform diagram illustrating an output waveform 400 generated by the battery system 100, according to some embodiments. In some embodiments, the output waveform 400 may be a sinusoidal signal. The numbers above the output waveform 400 represent the stage number of the switching scheme (e.g., 4*N=64 stages for one period of the waveform), and the numbers below the waveform represent the rank of the battery cluster 102 switching in the current time interval. In some embodiments, the rank does not correspond to the device number or position of the cluster controller 116 on the serial communication bus 108B. For example, the battery clusters 102 may not be switching sequentially. The rank represents the relative position of the cluster controller 116 in the switching scheme to generate the output waveform 400. The host processor 106 may determine the rank based on the load balancing of the battery clusters 102. Additionally, the rank may change over time to provide load balancing.

[0030] 5 is a flow diagram of a method 500 for generating an output waveform 400 in a battery system 100, according to some embodiments. At 502, a first cluster controller 116 of a first battery cluster 102 is connected to a serial communication bus 108B. At 504, a second cluster controller 116 of a second battery cluster 102 is connected to the serial communication bus 108B. Connecting the cluster controller 116 to the serial communication bus 108B means establishing communication with the cluster controller 116, which may include providing a physical connection, addressing, etc. At 506, synchronization data is sent to the first cluster controller 116 and the second cluster controller 116 via the serial communication bus 108B. At 508, the first bridge 120 of the first battery cluster 102 is controlled to connect a first battery terminal of the first battery cluster 102 to either the output terminal 112T or the output terminal 114T based on the synchronization data and the first rank assigned to the first battery cluster 102 to generate a first component of the output waveform 400. At 510, the second bridge 120 of the second battery cluster 102 is controlled to connect a second battery terminal of the second battery cluster 102 to either the output terminal 112T or the output terminal 114T based on the synchronization data and the second rank assigned to the second battery cluster 102 to generate a second component of the output waveform 400.

[0031] FIG. 6 illustrates an exemplary embodiment 600 of a computer-readable medium 602, according to some embodiments. One or more embodiments include a computer-readable medium including processor-executable instructions configured to perform one or more of the techniques presented herein. The embodiment 600 comprises a non-transitory computer-readable medium 602 (e.g., a CD-R, a DVD-R, a flash drive, a platter of a hard disk drive, etc.) having computer-readable data 604 encoded thereon. The computer-readable data 604 includes a set of processor-executable computer instructions 606 that, when executed by a computing device 608 including a reader 610 for reading the processor-executable computer instructions 606 and a processor 612 for executing the processor-executable computer instructions 606, are configured to facilitate operation according to one or more of the principles described herein. In some embodiments, the processor-executable computer instructions 606, when executed, are configured to facilitate execution of a method 614, such as at least some of the methods described above. In some embodiments, the processor-executable computer instructions 606, when executed, are configured to facilitate implementation of a system, such as at least some of the systems described above. Many such computer-readable media configured to operate in accordance with the techniques presented herein may be devised by those of skill in the art.

[0032] By configuring the battery cluster 102 to account for the propagation delay of a serial communication topology, the additional hardware and programming complexity of a parallel communication system is eliminated without exceeding latency requirements. This approach reduces hardware costs, device footprint, and programming costs.

[0033] According to some embodiments, a method includes connecting a first cluster controller of a first battery cluster to a serial communication bus; connecting a second cluster controller of a second battery cluster to the serial communication bus; sending synchronization data to the first cluster controller and the second cluster controller via the serial communication bus; controlling a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform; and controlling a second bridge of the second battery cluster to connect a second battery terminal of the second battery cluster to the output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform.

[0034] According to some embodiments, sending the synchronization data includes determining a propagation delay associated with the serial communications bus, assigning a first delay component to the first cluster controller based on the propagation delay, and assigning a second delay component to the second cluster controller based on the propagation delay; controlling the first bridge includes sending a first bridge state command to the first cluster controller via the serial communications bus based on the first rank and delaying execution of the first bridge state command based on the first delay component; and controlling the second bridge includes sending a second bridge state command to the second cluster controller via the serial communications bus based on the second rank and delaying execution of the second bridge state command based on the second delay component.

[0035] According to some embodiments, connecting the first cluster controller and the second cluster controller to the serial communications bus includes connecting the first cluster controller and the second cluster controller to the serial communications bus using a serial transceiver, and determining a propagation delay associated with the serial communications bus includes determining the propagation delay based on a delay associated with the serial transceiver.

[0036] According to some embodiments, delaying execution of the first bridge state command based on the first delay component includes configuring a programmable delay counter in the first cluster controller with the first delay component; generating a bridge configuration signal in response to the first bridge state command; delaying the bridge configuration signal in the programmable delay counter to generate a delayed bridge configuration signal; and controlling a bridge driver associated with the first bridge based on the delayed bridge configuration signal.

[0037] According to some embodiments, assigning the first delay component to the first cluster controller includes assigning the first delay component to the first cluster controller based on a propagation delay and a position of the first cluster controller within the serial communications bus, and assigning the second delay component to the second cluster controller includes assigning the second delay component to the second cluster controller based on the propagation delay and a position of the second cluster controller on the serial communications bus.

[0038] According to some embodiments, connecting the first cluster controller and the second cluster controller to the serial communication bus includes connecting the first cluster controller and the second cluster controller to the serial communication bus in a ring topology.

[0039] According to some embodiments, connecting the first cluster controller to the serial communication bus includes automatically assigning an address to the first cluster controller according to a protocol of the serial communication bus.

[0040] According to some embodiments, the battery cluster controller comprises a serial interface configured to receive synchronization data via a serial communication bus, a modulation unit configured to generate a bridge configuration signal for controlling a bridge for selectively connecting battery elements to an output terminal to generate a first component of a waveform based on a rank assigned to the battery cluster controller, and a delay unit configured to delay the bridge configuration signal based on the synchronization data to generate a delayed bridge configuration signal, wherein the bridge is controlled based on the delayed bridge configuration signal.

[0041] According to some embodiments, the synchronization data includes a component of the total propagation delay of the serial communications bus, the component being related to the position of the battery cluster controller on the serial communications bus.

[0042] According to some embodiments, the location includes a ring location within a serial communication bus.

[0043] According to some embodiments, the delay unit comprises a programmable delay counter configured on a component basis.

[0044] According to some embodiments, the serial interface is configured to receive an address that is automatically assigned to the battery cluster controller according to a protocol of the serial communication bus.

[0045] According to some embodiments, a system includes a first battery cluster including an output terminal, a serial communication bus, a first battery cluster including a first battery element, a first bridge configured to selectively connect the first battery element to the output terminal based on a state of the first bridge, and a first cluster controller coupled to the first bridge and the serial communication bus, a second battery cluster including a second battery element, a second bridge configured to selectively connect the second battery element to the output terminal based on a state of the second bridge, and a second cluster controller coupled to the second bridge and the serial communication bus, and a host processor configured to send synchronization data to the first cluster controller and the second cluster controller via the serial communication bus, wherein the first cluster controller is configured to control a first bridge to connect a first battery element to an output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform, and the second cluster controller is configured to control a second bridge to connect a second battery element to an output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform.

[0046] According to some embodiments, the host processor is configured to determine a propagation delay associated with the serial communications bus, generate a first delay component in the synchronization data for the first cluster controller based on the propagation delay, generate a second delay component in the synchronization data for the second cluster controller based on the propagation delay, send a first bridge state command to the first cluster controller via the serial communications bus based on the first rank and send a second bridge state command to the second cluster controller via the serial communications bus based on the second rank, the first cluster controller is configured to delay execution of the first bridge state command to configure a state of the first bridge based on the first delay component, and the second cluster controller is configured to delay execution of the second bridge state command to configure a state of the second bridge based on the second delay component.

[0047] According to some embodiments, a system includes a serial transceiver connecting a host processor to a serial communications bus, the host processor configured to determine a propagation delay based on a delay associated with the serial transceiver.

[0048] According to some embodiments, the first cluster controller comprises a serial interface, and the host processor is configured to determine the propagation delay based on a delay associated with the serial interface.

[0049] According to some embodiments, the first cluster controller comprises a first programmable delay counter configured based on a first delay component to delay the first bridge state command, and the second cluster controller comprises a second programmable delay counter configured based on a second delay component to delay the second bridge state command.

[0050] According to some embodiments, the first delay component is based on a propagation delay and a position of the first cluster controller on the serial communications bus, and the second delay component is based on the propagation delay and a position of the second cluster controller on the serial communications bus.

[0051] According to some embodiments, the serial communication bus is configured in a ring topology.

[0052] According to some embodiments, a system includes a serial transceiver configured to connect a host processor to a serial communication bus and to automatically assign a first address to a first cluster controller and a second address to a second cluster controller.

[0053] Various operations of the embodiments are provided herein. The order in which some or all of the operations are described should not be construed as implying that these operations are necessarily order dependent. Alternative orderings will be understood with the benefit of this specification. Furthermore, it will be understood that not all operations are necessarily present in each embodiment provided herein. It will also be understood that not all operations are required in some embodiments.

[0054] Any aspect or design described herein as "example" or the like should not be construed as necessarily advantageous over other aspects or designs. Rather, use of the word "example" is intended to present one possible aspect and / or implementation that may be associated with the technology presented herein. Such an example is not intended to be necessary or limiting of such technology. Various embodiments of such technology may include such an example alone or in combination with other features, and / or may modify and / or omit the illustrated example.

[0055] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the appended claims subject matter is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least a portion of the claims.

[0056] As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or." Furthermore, "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless otherwise specified or unless the singular form is clearly intended from the context. Also, at least one of A and B, etc. generally means A or B or both A and B. Furthermore, to the extent that "includes," "having," "has," "with," or variations thereof are used, such terms are intended to be as inclusive as the term "comprising." Also, unless otherwise specified, "first," "second," etc. are not intended to imply any temporal or spatial aspects, ordering, or the like. Rather, such terms are merely used as identifiers, names, or the like of features, elements, items, and the like. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0057] Also, although the present disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art based on reading and understanding the present specification and the accompanying drawings. The present disclosure includes all such modifications and modifications, and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond to any components that perform the specified function of the described components (e.g., functionally equivalent), even if they are not structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments of the present disclosure shown herein, unless otherwise indicated. Furthermore, although certain features of the present disclosure may be disclosed with respect to only one of several embodiments, such features may be combined with one or more other features of other embodiments as may be desired and advantageous for any given or specific application. Furthermore, to the extent the terms "include," "having," "has," "with," or variations thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in the same manner as the term "comprising."

[0058] Although the subject matter has been described with reference to exemplary embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present disclosure, will be apparent to those skilled in the art upon reference to the description. Accordingly, the appended claims are intended to cover such modifications or embodiments.

Claims

1. connecting a first cluster controller of a first battery cluster to a serial communication bus; connecting a second cluster controller of a second battery cluster to the serial communication bus; sending synchronization data to the first cluster controller and the second cluster controller via the serial communication bus; controlling a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform; controlling a second bridge of the second battery cluster to connect a second battery terminal of the second battery cluster to the output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform; The method includes:

2. Sending the synchronization data includes: determining a propagation delay associated with the serial communication bus; assigning a first delay component to the first cluster controller based on the propagation delay; assigning a second delay component to the second cluster controller based on the propagation delay; Including, Controlling the first bridge includes: sending a first bridge state command to the first cluster controller via the serial communications bus based on the first rank; delaying execution of the first bridge state command based on the first delay component; Including, Controlling the second bridge includes: sending a second bridge state command to the second cluster controller via the serial communications bus based on the second rank; delaying execution of the second bridge state command based on the second delay component; Including, The method of claim 1.

3. Connecting the first cluster controller and the second cluster controller to the serial communication bus includes: connecting the first cluster controller and the second cluster controller to the serial communications bus using a serial transceiver; determining the propagation delay associated with the serial communications bus includes determining the propagation delay based on a delay associated with the serial transceiver. The method of claim 2.

4. Delaying execution of the first bridge state command based on the first delay component comprises: configuring a programmable delay counter in the first cluster controller with the first delay component; generating a bridge configuration signal in response to the first bridge state command; delaying the bridge configuration signal in the programmable delay counter to generate a delayed bridge configuration signal; controlling a bridge driver associated with the first bridge based on the delayed bridge configuration signal; Including, The method of claim 2.

5. assigning the first delay component to the first cluster controller includes assigning the first delay component to the first cluster controller based on the propagation delay and a position of the first cluster controller within the serial communication bus; assigning the second delay component to the second cluster controller includes assigning the second delay component to the second cluster controller based on the propagation delay and a position of the second cluster controller on the serial communication bus. The method of claim 2.

6. Connecting the first cluster controller and the second cluster controller to the serial communication bus includes: connecting the first cluster controller and the second cluster controller to the serial communication bus in a ring topology; The method of claim 1.

7. Coupling the first cluster controller to the serial communication bus includes: automatically assigning an address to the first cluster controller according to a protocol of the serial communication bus; The method of claim 1.

8. A battery cluster controller comprising a serial interface, a modulation unit and a delay unit, the serial interface is configured to receive synchronous data over a serial communications bus; the modulation unit is configured to generate bridge configuration signals for controlling bridges for selectively connecting battery elements to output terminals to generate a first component of a waveform based on ranks assigned to the battery cluster controllers; the delay unit is configured to delay the bridge configuration signal based on the synchronization data to generate a delayed bridge configuration signal; the bridge is controlled based on the delayed bridge configuration signal; Battery cluster controller.

9. the synchronous data includes a component of a total propagation delay of the serial communication bus; the component being associated with the location of the battery cluster controller on the serial communication bus; The battery cluster controller of claim 8.

10. the location includes a ring location within the serial communication bus; The battery cluster controller of claim 9.

11. the delay unit comprises a programmable delay counter configured based on the components; The battery cluster controller of claim 8.

12. the serial interface is configured to receive an address automatically assigned to the battery cluster controller according to a protocol of the serial communication bus; The battery cluster controller of claim 8.

13. An output terminal; A serial communication bus; a first battery cluster; Second Battery Cluster Host processor and A system comprising: The first battery cluster comprises: A first battery element; a first bridge configured to selectively connect the first battery element to the output terminal based on a state of the first bridge; a first cluster controller connected to the first bridge and the serial communication bus; Equipped with The second battery cluster comprises: A second battery element; and a second bridge configured to selectively connect the second battery element to the output terminal based on a state of the second bridge; a second cluster controller connected to the second bridge and the serial communication bus; Equipped with the host processor is configured to send synchronous data to the first cluster controller and the second cluster controller via the serial communication bus; the first cluster controller is configured to control the first bridge to connect the first battery element to the output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform; the second cluster controller is configured to control the second bridge to connect the second battery element to the output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform. system.

14. The host processor: determining a propagation delay associated with the serial communication bus; generating a first delay component in the synchronization data for the first cluster controller based on the propagation delay; generating a second delay component in the synchronization data for the second cluster controller based on the propagation delay; sending a first bridge state command to the first cluster controller via the serial communications bus based on the first rank; configured to send a second bridge state command to the second cluster controller via the serial communication bus based on the second rank; the first cluster controller is configured to delay execution of the first bridge state command to configure the state of the first bridge based on the first delay component; the second cluster controller is configured to delay execution of the second bridge state command to configure the state of the second bridge based on the second delay component. The system of claim 13.

15. the system includes a serial transceiver connecting the host processor to the serial communications bus; the host processor is configured to determine the propagation delay based on a delay associated with the serial transceiver. The system of claim 14.

16. the first cluster controller comprises a serial interface; the host processor is configured to determine the propagation delay based on a delay associated with the serial interface. The system of claim 15.

17. the first cluster controller comprising a first programmable delay counter configured based on the first delay component to delay the first bridge state command; the second cluster controller comprising a second programmable delay counter configured based on the second delay component to delay the second bridge state command. The system of claim 14.

18. the first delay component is based on the propagation delay and a position of the first cluster controller on the serial communication bus; the second delay component is based on the propagation delay and a position of the second cluster controller on the serial communication bus. The system of claim 14.

19. The serial communication bus is configured in a ring topology. The system of claim 13.

20. the system includes a serial transceiver configured to connect the host processor to the serial communications bus and to automatically assign a first address to the first cluster controller and a second address to the second cluster controller; The system of claim 13.

Images