Semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics and a method for manufacturing the same.SOLUTION: A transistor includes: an oxide semiconductor layer formed on an insulation layer; a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer; a gate insulation layer in contact with a part of the oxide semiconductor layer; and a gate electrode layer formed on the gate insulation layer. Parasitic resistance is reduced and on-current characteristics of the transistor is improved by forming buffer layers with n-type conductivity between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer respectively.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. For example, a transistor is a semiconductor device, and a liquid crystal display including the transistor Semiconductor devices include electro-optical devices such as semiconductor devices and light-emitting devices, semiconductor circuits, and electronic equipment. [Background technology]

[0003] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention as other materials. do.

[0004] For example, a semiconductor with an electron carrier concentration of 10 18 / cm 3 is less than Amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) was used. A transistor is disclosed (see Patent Document 1).

[0005] In addition, a transistor using an oxide semiconductor is different from a transistor using amorphous silicon. It operates faster than a digital converter and can be used to configure display device drive circuits and high-speed memory circuits. . [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0007] For example, transistors used in a driver circuit of a display device are required to operate quickly. In particular, the higher the resolution of the display, the shorter the time it takes to write the display image. It is desirable for the transistor used in the circuit to have a high on-state current and be capable of high-speed operation.

[0008] Therefore, one embodiment of the present invention is a transistor which has high on-state current and can operate at high speed, and a method for fabricating the same. Another object of the present invention is to provide a method for manufacturing the transistor. One of the purposes of this organization is to provide [Means for solving the problem]

[0009] One embodiment of the present invention disclosed in this specification is a method for manufacturing an oxide semiconductor device which is a channel formation region of a transistor. A barrier having n-type conductivity between the conductor layer and the metal layer serving as the source electrode or drain electrode. By forming a buffer layer, parasitic resistance is reduced and the on-current characteristics of the transistor are improved. It is meant to raise the

[0010] One embodiment of the present invention disclosed in this specification is a semiconductor device including an oxide semiconductor layer formed over an insulating layer and an oxide A source electrode layer and a drain electrode layer overlapping a part of the semiconductor layer and contacting a part of the oxide semiconductor layer a gate insulating layer formed on the source electrode layer and a gate electrode layer formed on the gate insulating layer; The semiconductor layer and the drain electrode layer and the oxide semiconductor layer are provided with an n-type conductive layer. The semiconductor device is characterized in that a buffer layer is formed to

[0011] The source electrode layer and the drain electrode layer are formed of aluminum, chromium, copper, tantalum, titanium, or the like. A single film or alloy film mainly composed of an element selected from the group consisting of tungsten, molybdenum, and tungsten, or A laminated film of these can be used.

[0012] The buffer layer may be formed of indium oxide, indium tin oxide, indium zinc oxide, or the like. a metal oxide selected from the group consisting of tin oxide, tin oxide, zinc oxide, and tin zinc oxide; or the metal oxide contains one or more elements selected from aluminum, gallium, and silicon. In this structure, the source electrode layer and the drain electrode layer can be made of a material that is known in the art. Parasitic resistance between the electrode layer and the oxide semiconductor layer can be reduced.

[0013] Another embodiment of the present invention disclosed in this specification is a method for forming an insulating layer on a substrate having an insulating surface. An oxide semiconductor layer is formed in an island shape on the insulating layer, and an n-type conductive layer is formed on the oxide semiconductor layer. A buffer layer and a metal layer are formed to form the insulating film, and the buffer layer and the metal layer are selectively etched. A source region including the buffer layer and the metal layer is formed so as to overlap a part of the oxide semiconductor layer. A gate electrode is formed to cover the oxide semiconductor layer, the source region, and the drain region. a gate insulating layer is formed on the gate insulating layer so as to overlap with part of the oxide semiconductor layer; The present invention relates to a method for manufacturing a semiconductor device. Effect of the Invention

[0014] According to one embodiment of the present invention, a semiconductor device using an oxide semiconductor layer as a source electrode layer and a drain electrode layer It is possible to reduce the parasitic resistance between the metal layer and the transistor, which has a high on-current and can operate at high speed. It is possible to provide a semiconductor device including a transistor and a manufacturing method thereof. [Brief description of the drawings]

[0015] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating a semiconductor device. [Diagram 2] 1A to 1C are cross-sectional views illustrating process steps of a manufacturing method of a semiconductor device. [Diagram 3] FIG. 1 is a plan view illustrating one embodiment of a semiconductor device. [Figure 4] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 5] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 6] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7] FIG. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] IV characteristics of transistor before and after negative gate BT stress application. [Figure 10] Scientific calculation model and electric field strength distribution during negative gate BT stress. [Figure 11] Transistor IV characteristics and current density distribution when negative charge is inserted (drain voltage +0.1V). [Figure 12] Transistor IV characteristics and current density distribution when negative charge is inserted (drain voltage +3V). [Figure 13] A cross-sectional TEM photograph of a transistor with a buffer layer and its schematic diagram. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and those skilled in the art will recognize that the present invention may be modified in various ways in form and detail. It will be easily understood. In addition, the present invention is not limited to the description of the embodiment shown below. In explaining the configuration of the invention using the drawings, the same symbols are used The numbers are used commonly across different drawings. Also, when referring to similar objects, the hatch pattern is used. Similarly, there are cases where no particular reference numeral is given.

[0017] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the present specification does not refer to a specific name as a matter for identifying the invention. This does not indicate a title.

[0018] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a method for manufacturing the semiconductor device will be described. Explain.

[0019] As an example of a semiconductor device according to one embodiment of the present invention, a plan view of a top-gate transistor and a A cross-sectional view is shown in FIG. 1. Here, FIG. 1(A) is a top view, and FIG. 1(B) and FIG. 1(C) are These are cross-sectional views taken along lines AB and CD in FIG. The transistor 151 has a source region and a drain region formed in contact with the upper portion of a semiconductor layer. Because of this, it is called the top gate type, and also the top contact type. do.

[0020] The transistor 151 shown in FIG. 1 includes an insulating layer 102, an oxide semiconductor layer 10, and a 6, source electrode layer 108a, drain electrode layer 108b, gate insulating layer 112, gate electrode Here, the oxide semiconductor layer 106, the source electrode layer 108a, and the oxide Between the semiconductor layer 106 and the drain electrode layer 108b, buffer layers 107a and 107b are provided. In this specification, for ease of explanation, the source electrode layer 107b is formed. 08a and the buffer layer 107a are integrated as a source region, and the drain electrode layer 108b and the buffer layer 107b are sometimes integrated and referred to as a drain region. Also, in this embodiment the transistor using the oxide semiconductor layer is an n-channel type.

[0021] Note that the transistor 151 may have a configuration as shown in the cross-sectional views of FIGS. 8(A), (B), and (C). FIG. 8(A) shows a configuration in which the film thickness of the channel formation region in the oxide semiconductor layer 106 is formed thinly. FIG. 8(B) shows a configuration in which the source electrode layer 108a and the drain electrode layer 108b are formed so as to have a step on the buffer layers 107a and 107b. FIG. 8(C) shows a configuration in which FIGS. 8(A) and 8(B) are combined. The transistors having these configurations have electrical characteristics equivalent to those of the transistor having the configuration shown in the cross-sectional view of FIG. 1(B).

[0022] As the material of the insulating layer 102, silicon oxide, silicon oxynitride, Ga x Al 2-x O 3+y (0 ≦ x ≦ 2, 0 < y < 1, where x is a value from 0 to 2 and y is greater than 0 and less than 1 ) such as aluminum oxide, gallium oxide, or gallium aluminum oxide, or a mixed material thereof can be used. Also, the insulating layer 102 may be a laminate of the above-described material and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride or a mixed material thereof. For example, if the insulating layer 102 has a laminated structure of a silicon nitride layer and a silicon oxide layer, mixing of moisture from the substrate or the like into the transistor 151 can be prevented. When the insulating layer 102 is formed in a laminated structure, the oxide semiconductor layer 10 ​ The side in contact with 6 is made of silicon oxide, silicon oxynitride, aluminum oxide, or a mixture of these materials. Note that the insulating layer 102 is preferably an oxide layer such as a base layer of the transistor 151. It works.

[0023] The oxide semiconductor used contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of the transistors added to them, In addition, it is preferable to use gallium (Ga) as a stabilizer. It is preferable that the stabilizer contains hafnium (Hf). It is preferable that the stabilizer contains aluminum (Al). stomach.

[0024] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0025] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn-O based materials, Sn-Zn-O based materials, Al-Zn-O based materials, Zn-Mg-O based materials, Sn-Mg-O based materials, In-Mg-O based materials, In-G aO-based materials, In-Ga-Zn-O-based materials, which are ternary metal oxides (IGZO and (also written as In-Al-Zn-O type materials, In-Sn-Zn-O type materials, Sn- Ga-Zn-O based materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O based materials materials, In-Hf-Zn-O materials, In-La-Zn-O materials, In-Ce-Zn -O-based materials, In-Pr-Zn-O-based materials, In-Nd-Zn-O-based materials, In- Sm-Zn-O based materials, In-Eu-Zn-O based materials, In-Gd-Zn-O based materials materials, In-Tb-Zn-O materials, In-Dy-Zn-O materials, In-Ho-Zn -O-based materials, In-Er-Zn-O-based materials, In-Tm-Zn-O-based materials, In- Materials based on the Yb-Zn-O system, materials based on the In-Lu-Zn-O system, and oxides of quaternary metals, such as I n-Sn-Ga-Zn-O materials, In-Hf-Ga-Zn-O materials, In-Al -Ga-Zn-O based materials, In-Sn-Al-Zn-O based materials, In-Sn-Hf- Zn-O based materials and In-Hf-Al-Zn-O based materials can be used.

[0026] In addition, for example, an In-Ga-Zn-O-based material is a material that contains In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than Ga and Zn may be included.

[0027] The oxide semiconductor layer has the chemical formula InMO3(ZnO) m (m>0 and m must be an integer. The thin film can be formed by using a material represented by the formula (I), where M is Zn, It denotes one or more metallic elements selected from Ga, Al, Mn, and Co. For example, M As the gallium arsenide, Ga, Ga and Al, Ga and Mn, Ga and Co, etc. can be used. do.

[0028] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn-O system with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Materials having the above composition or oxides having similar compositions can be used. 1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3: 1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn-O-based material having an atomic ratio of 1000 or an oxide having a composition close to that.

[0029] The oxide semiconductor may be single-crystalline or non-single-crystalline. In the latter case, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. That's fine too.

[0030] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high quality. Therefore, high mobility can be obtained.

[0031] In addition, in a crystalline oxide semiconductor, bulk defects can be further reduced, and the surface By improving the flatness, it is possible to obtain a mobility equal to or higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form the surface with a thickness of 0.1 nm or less.

[0032] The oxide semiconductor layer and the oxide insulating layer serving as the base are in contact with each other, so that the insulating layer 102 and the oxide semiconductor The interface state with the oxide semiconductor layer 106 and the oxygen vacancies in the oxide semiconductor layer 106 can be reduced. The reduction in the interface states and oxygen vacancies reduces the time-dependent change in the threshold voltage of the transistor 151. The reduction in the amount of noise can be reduced.

[0033] The source and drain regions of the transistor 151 are in contact with the oxide semiconductor layer 106. The side to be connected is formed of buffer layers 107a and 107b having n-type conductivity. By forming the layers, the oxide semiconductor layer 106, the source electrode layer 108a, and the oxide semiconductor The parasitic resistance between the drain electrode layer 106 and the drain electrode layer 108b can be reduced, It is possible to increase the on-state current of the transistor and improve the frequency characteristics of the circuit. The effect is remarkable when the channel length of the MOSFET is 5 μm or less. The reduction in the parasitic resistance is mainly due to the oxide semiconductor layer 106 and the source electrode layer 108a or the drain This occurs due to a reduction in contact resistance with the electrode layer 108b.

[0034] Representative materials that can be used for the buffer layers 107a and 107b having n-type conductivity Examples include indium oxide (In-O-based material), indium tin oxide (In-Sn- O-based materials), indium zinc oxide (In-Zn-O-based materials), tin oxide (Sn-O Zinc oxide (Zn-O-based materials), Tin zinc oxide (Sn-Zn-O-based materials) ), as well as aluminum (Al), gallium (Ga), silicon (Si). Titanium oxide (Ti- O-based materials), titanium niobium oxide (Ti-Nb-O-based materials), molybdenum oxide (M oO-based materials), tungsten oxide (WO-based materials), magnesium oxide (Mg -O-based materials), calcium oxide (Ca-O-based materials), gallium oxide (Ga-O-based materials) The above materials may contain nitrogen (N).

[0035] As the metal layer used for the source electrode layer 108a and the drain electrode layer 108b, for example, An element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. Metal films containing elements, or alloy films containing the above elements (titanium nitride film, molybdenum nitride film, etc.) For example, aluminum oxide, tungsten nitride, or a laminate of these can be used. Titanium, molybdenum, tungsten, etc. are applied to one or both sides of a metal film such as aluminum or copper. Any high melting point metal film or its nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) A laminated structure of a metal film (stainless steel film, etc.) may also be used.

[0036] In addition, in a structure in which the source electrode and the drain electrode are in contact with the gate insulating layer, the withstand voltage of the gate insulating layer is In order to prevent a voltage drop, a metal film with a weak oxygen-removing effect is used as the source electrode and drain electrode. The metal film is preferably made of, for example, molybdenum or tungsten. However, when the source electrode and the drain electrode are laminated, At least, the side in contact with the gate insulating layer should be the metal film.

[0037] The gate insulating layer 112 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or silicon oxynitride. Silicon, Aluminum Oxide, Aluminum Nitride, Aluminum Oxide Nitride, Aluminum Oxide Nitride The material used is nium oxide, hafnium oxide, gallium oxide, lanthanum oxide, or a mixture of these materials. The insulating layer 11 can be formed by a plasma CVD method, a sputtering method, or the like. The gate insulating layer 112 is not limited to a single layer, and may be a laminate of the above-mentioned materials.

[0038] Note that the gate insulating layer 112 is formed using an insulating material containing the same type of component as the oxide semiconductor layer. Such a material is preferably capable of maintaining a good state of the interface with the oxide semiconductor layer. Here, the term "component of the same kind as the oxide semiconductor layer" refers to a component selected from the constituent elements of the oxide semiconductor layer. For example, the oxide semiconductor layer may be an In-Ga-Zn system When the insulating material is made of oxide semiconductor material, the insulating material containing the same component is oxide gas. Lithium, etc.

[0039] The gate electrode layer 114 may include molybdenum, titanium, tantalum, tungsten, aluminum, etc. Metallic materials such as copper, neodymium, and scandium, their nitrides, or materials with these as the main components The gate electrode layer 114 may have a single-layer structure. Alternatively, a laminated structure of the above materials may be used.

[0040] Although not shown, an insulating layer may be provided over the transistor 151. The insulating layer may be made of the same material as the insulating layer 102. In order to electrically connect the gate insulating layer 108a and the drain electrode layer 108b to the wiring, An opening may be formed in the oxide semiconductor layer 106. A second gate electrode may be provided. Note that the oxide semiconductor layer 106 is processed into an island shape. Although it is preferable to be present, it does not have to be processed into an island shape.

[0041] Next, an example of the manufacturing process of the transistor 151 shown in FIG. 1 will be described.

[0042] First, an insulating layer 102 serving as an underlying film is formed on a substrate 100 having an insulating surface (see FIG. 2(A ). The insulating layer 102 has a function of preventing the diffusion of impurity elements from the substrate 100, and can be formed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or a G a x Al 2-x O 3+y (0 ≦ x ≦ 2, 0 < y < 1, x is a value from 0 to 2, y is greater than 0 and less than 1) such as aluminum oxide, gallium oxide, or gallium aluminum oxide selected film. Further, the underlying film is not limited to a single layer, and may be a laminate of the above-mentioned plurality of films.

[0043] Here, as the substrate 100, at least one having heat resistance against subsequent heat treatment can be used. For example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. Also, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can also be used.

[0044] Further, a flexible substrate may be used as the substrate 100. Alternatively, a substrate provided with a release layer may be used. In the latter case, after manufacturing a transistor including an oxide semiconductor layer according to the method disclosed below, it can also be transferred to a flexible substrate.

[0045] ​ Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm to 30 nm, is formed on the insulating layer 102. An oxide semiconductor film having a thickness of 1 nm or less is formed.

[0046] As described above, the oxide semiconductor used in the oxide semiconductor film is an oxide semiconductor represented by the chemical formula InMO3(Z nO) m (m>0 and m is not an integer) can be used, where An In-Ga-Zn-O film is formed by sputtering.

[0047] The film formation target used in the sputtering method has a composition ratio of, for example, In2O3:G Use metal oxides with a molar ratio of a2O3:ZnO = 1:1:1. Also, In2O3 Metal oxides with a molar ratio of Ga2O3:ZnO=1:1:2 may also be used.

[0048] In addition, when using an In-Zn-O-based material as an oxide semiconductor, the composition of the target used The composition ratio is In:Zn=50:1-1:2 in atomic ratio (InO 3:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar In terms of ratio, In2O3:ZnO=10:1 to 1:2), and more preferably In:Zn = 1.5:1 to 15:1 (converted to molar ratio: In2O3:ZnO = 3:4 to 15: For example, the target used for forming an In-Zn-O oxide semiconductor is an atomic When the numerical ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0049] In addition, when using an In-Sn-Zn-O-based material as an oxide semiconductor, the target The composition ratio of In, Sn, and Zn is preferably In:Sn:Zn=2:1:3 in terms of atomic ratio.

[0050] The filling rate of the film forming target is 90% or more and 100% or less, preferably 95% or more and 100% or less. By using a film formation target with a high filling rate, the oxide semiconductor film formed The conductive film may be a dense film.

[0051] The sputtering gas is a rare gas (typically argon), oxygen, or a rare gas and oxygen. The sputtering gas may contain hydrogen, water, hydroxyl or other elements. It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0052] The oxide semiconductor film is preferably formed while the substrate is heated. The substrate is held in the film formation chamber and the substrate temperature is set to 100° C. or higher and 600° C. or lower, preferably 200° C. The concentration of impurities in the oxide semiconductor film is reduced by forming the film at a temperature of 400° C. or higher. It is possible.

[0053] In order to remove residual moisture in the deposition chamber, an adsorption type vacuum pump, for example, a cryostat It is preferable to use a pump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo molecular pump with a cold trap added. The deposition chamber evacuated using a cryopump contains hydrogen atoms, water, and other chemicals that contain hydrogen atoms. Since the oxide semiconductor film formed in the film formation chamber is exhausted, the oxide semiconductor film formed in the film formation chamber is exhausted. The concentration of impurities contained in the film can be reduced.

[0054] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions are: DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed DC power supply is used, the powdery substances (particles, etc.) generated during film formation are reduced. This can reduce the thickness loss (also called the "thinning") and make the film thickness distribution uniform.

[0055] Next, the oxide semiconductor film is divided into islands by a first photolithography step and an etching step. The oxide semiconductor layer 106 is then processed into a crystalline oxide semiconductor layer 106 (see FIG. 2B).

[0056] The resist mask used in the photolithography process is formed by an inkjet method. The inkjet method does not require a photomask, which reduces manufacturing costs. It is possible.

[0057] Here, the oxide semiconductor film is etched by dry etching or wet etching. For example, a wet oxide semiconductor film may be used. The etching solution used for etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO-07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0058] Next, the oxide semiconductor layer 106 is dehydrated or dehydrogenated by a first heat treatment. In the specification, dehydration or dehydrogenation refers only to the desorption of water or hydrogen molecules. This does not only include the elimination of hydrogen atoms and hydroxyl groups, but also includes the elimination of hydrogen atoms and hydroxyl groups.

[0059] Excess hydrogen (including water and a hydroxyl group) is removed by this heat treatment, and the oxide semiconductor layer 106 The impurity level in the energy gap can be reduced. The heat treatment temperature is 250°C. or higher and 650°C or lower, preferably 350°C or higher and 500°C or lower, more preferably 390°C or higher The heat treatment time is about 1 hour if the temperature is within the above-mentioned preferable range. The heat treatment may be performed in an inert gas atmosphere (nitrogen, helium, neon, argon, etc.). In an atmosphere, 500℃ to 750℃ (or a temperature below the distortion point of the glass substrate) RTA (Ra These heat treatment methods may be used. The method for dehydrating or desorbing the oxide semiconductor layer 106 may be appropriately determined by a practitioner. The heat treatment for hydrogenation is not limited to this timing, but may be performed during photolithography and formation. It may be performed several times before and after the film process. In that case, the heat treatment is performed in an atmosphere containing oxygen. may also be carried out.

[0060] In addition, the heat treatment of the oxide semiconductor is performed on the oxide semiconductor film before it is processed into the island-shaped oxide semiconductor layer. In this case, the photolithography process is performed after the heat treatment. In addition, if the heat treatment is performed after the formation of the oxide semiconductor film, the source electrode layer is formed on the island-shaped oxide semiconductor layer. The step may be performed after the drain electrode layer is laminated.

[0061] Next, a buffer layer and a metal layer are formed over the insulating layer 102 and the oxide semiconductor layer 106. The buffer layer and the metal layer can be made of the above-mentioned materials. A single layer of indium tin oxide was formed as the thin film and a single layer of tungsten was formed as the metal layer by sputtering. Complete.

[0062] Next, a resist mask is formed on the metal layer by a second photolithography process, and selective The buffer layer 107a and the source electrode layer 107b that constitute the source region are selectively etched. 8a, and a buffer layer 107b and a drain electrode layer 108b which constitute the drain region are formed. Then, the resist mask is removed (see FIG. 2(C)).

[0063] Note that when the source and drain regions are formed, the oxide semiconductor layer 106 is etched as little as possible. However, it is preferable to etch only the metal layer and the buffer layer. It is difficult to obtain the conditions for etching the metal layer and the buffer layer, and the oxide semiconductor A part of the conductor layer 106 may be etched to have a groove (recess). In addition, the source electrode layer 108a is formed on the buffer layers 107a and 107b so as to have a step. In addition, a drain electrode layer 108b may be formed.

[0064] Next, a gate insulating layer 112 is formed on the source region, the drain region, and the oxide semiconductor layer 106. Here, silicon oxide is used as the gate insulating layer 112 (see FIG. 2D). It is formed by sputtering.

[0065] The gate insulating layer 112 can be formed as a high-quality insulating layer that is dense and has a high dielectric strength. Even if it is formed by high density plasma CVD using microwaves (for example, frequency 2.45 GHz), The oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, which reduces the interface state. It is possible.

[0066] In addition, the quality of the gate insulating layer and the interface characteristics with the oxide semiconductor layer are improved by heat treatment after film formation. In any case, the gate insulating layer 112 has a good film quality. In addition, the interface state density with the oxide semiconductor layer can be reduced to form a good interface. It is preferable that the above-mentioned

[0067] After the gate insulating layer 112 is formed, a second heat treatment is preferably performed. The temperature is 250° C. to 700° C., preferably 350° C. to 600° C. or Less than the strain point.

[0068] The second heat treatment may be performed in an oxidizing gas atmosphere or an inert gas atmosphere. It is preferable that the gas does not contain water, hydrogen, etc. Also, the purity of the gas introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., It is preferable to keep the concentration of impurities at 1 ppm or less, and preferably at 0.1 ppm or less.

[0069] In the second heat treatment, the oxide semiconductor layer 106 and the gate insulating layer 112 containing oxygen are in contact with each other. Therefore, oxygen, which is one of the main components of oxide semiconductors, is removed by heating. The oxide semiconductor layer 106 can be supplied with oxygen from the gate insulating layer 112. Oxygen vacancies in the oxide semiconductor layer 106 and the interface between the oxide semiconductor layer 106 and the gate insulating layer 112 At the same time, the defects in the gate insulating layer 112 can be reduced. can be done.

[0070] The timing of the second heat treatment is not particularly limited as long as it is performed after the gate insulating layer 112 is formed. For example, the second heat treatment may be performed after the gate electrode layer 114 is formed.

[0071] Next, after forming a conductive film, a third photolithography process and an etching process are performed to form a gate. A gate electrode layer 114 is formed (see FIG. 2(E)). In this example, tungsten is used as the conductive film. A laminate of tantalum nitride and silicon nitride is formed by sputtering.

[0072] Although not shown in the drawings, an insulating layer may be formed on the gate insulating layer 112 and the gate electrode layer 114. Examples of the insulating layer include a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, Ga x Al 2-x O 3+y (0 ≤ x ≤ 2, 0 < y < 1, where x is a value from 0 to 2 and y is a value greater than 0 and less than 1), such as aluminum oxide, gallium oxide, or gallium aluminum oxide, and inorganic insulating films can be used.

[0073] Furthermore, a protective insulating layer for improving reliability may be formed on the insulating layer. Examples of the protective insulating layer include inorganic insulating films such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, and an aluminum oxynitride film.

[0074] In addition, a planarizing insulating film may be formed on the insulating layer or the protective insulating layer to reduce surface irregularities caused by the transistor. As the planarizing insulating film, organic materials such as polyimide, acrylic, and benzocyclobutene can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. Note that a planarizing insulating film may be formed by laminating a plurality of insulating films formed of these materials.

[0075] The transistor 151 is formed through the above steps.

[0076] As described above, a semiconductor device with good electrical characteristics can be provided.

[0077] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0078] (Embodiment 2) A semiconductor device having a display function (a display device) using the transistor described in Embodiment 1 as an example In addition, a part or the whole of a driver circuit including a transistor can be manufactured. A system-on-panel can be formed by forming the display panel and the pixel portion on the same substrate.

[0079] In FIG. 3A, a pixel portion 202 provided on a first substrate 201 is surrounded by a A sealant 205 is provided, and the device is sealed with a second substrate 206. In this case, the area other than the area surrounded by the sealant 205 on the first substrate 201 is A scanning line driver circuit 204 and a signal line driver circuit 205 are formed of a single crystal semiconductor or a polycrystalline semiconductor. A signal line driver circuit 203 and a scanning line driver circuit 204 are also mounted. Various signals and potentials are applied to the pixel portion 202 through a flexible printed circuit (FPC). The inputs are provided via externally connected circuits 218a, 218b.

[0080] In FIG. 3B and FIG. 3C, a pixel portion 202 is provided on a first substrate 201. A sealant 205 is provided so as to surround the scanning line driver circuit 204. A second substrate 206 is provided on the display unit 202 and the scanning line driving circuit 204. The element portion 202 and the scanning line driving circuit 204 are formed by a first substrate 201, a sealing material 205, and a second The display element is sealed with the substrate 206. In this case, the area other than the area surrounded by the sealant 205 on the first substrate 201 is A signal line driver circuit 203 formed of a single crystal semiconductor or a polycrystalline semiconductor is mounted on the In FIG. 3B and FIG. 3C, a signal line driver circuit 203 and Various signals and potentials applied to the scanning line driver circuit 204 or the pixel portion 202 are transmitted through the FPC 21. It is supplied via 8a.

[0081] In addition, in FIG. 3B and FIG. 3C, the signal line driver circuit 203 is formed separately. However, the present invention is not limited to this configuration. The circuit may be formed separately and mounted, or may be mounted as part of a signal line driver circuit or a scanning line driver circuit. Alternatively, the first and second electrodes may be separately formed and mounted.

[0082] The method of connecting the separately formed drive circuit is not particularly limited, and may be any of the following: ip On Glass) method, wire bonding method, or TAB (Tape Auto The COG method can be used. In this example, the signal line driver circuit 203 and the scanning line driver circuit 204 are mounted in the same manner as in FIG. 3(C) is an example of mounting the signal line driver circuit 203 by the COG method, and FIG. 3(C) is an example of mounting the signal line driver circuit 203 by the TAB method. In this example, the signal line driver circuit 203 is implemented by using a semiconductor device.

[0083] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to modules with FPC or TAB tape attached, A module with a printed wiring board at the end of the TAB tape, or a display element with a COG method According to the formula, all modules on which ICs (integrated circuits) are directly mounted are also included in the display device. .

[0084] In addition, the pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. For this purpose, the transistor illustrated in Embodiment 1 can be used.

[0085] Examples of display elements provided in the display device include liquid crystal elements (also called liquid crystal display elements), light-emitting elements ( The light-emitting element can be used as a light-emitting display element. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Also includes electronic inks and other electronic devices. A display medium in which the contrast changes due to electrochemical effects can also be used.

[0086] One embodiment of the display device will be described with reference to FIG. 4 to FIG. 6. FIG. 4 to FIG. 6 are the same as FIG. ) corresponds to a cross-sectional view at MN.

[0087] As shown in FIGS. 4 to 6, the semiconductor device has a connection terminal electrode 215 and a terminal electrode 216. The connection terminal electrodes 215 and the terminal electrodes 216 are anisotropically connected to the terminals of the FPC 218. They are electrically connected via a conductive layer 219 .

[0088] The connection terminal electrode 215 is formed of the same conductive layer as the first electrode layer 230, and the terminal electrode 216 is , the source and drain electrodes of transistor 210 and transistor 211 are connected to the same conductor. The insulating layer is formed of a conductive layer.

[0089] In addition, the pixel portion 202 and the scanning line driver circuit 204 provided on the first substrate 201 are 4 to 6, the pixel portion 202 includes a transistor 21. 0 and a transistor 211 included in the scanning line driver circuit 204 are illustrated.

[0090] In this embodiment, the transistors 210 and 211 are the transistors shown in the first embodiment. The transistors 210 and 211 have excellent electrical characteristics. A display device with high display capabilities can be constructed.

[0091] The transistor 210 provided in the pixel portion 202 is electrically connected to a display element, and The display element is not particularly limited as long as it can display, and various display elements can be used. There can be.

[0092] FIG. 4 shows an example of a liquid crystal display device using a liquid crystal element as a display element. The liquid crystal element 213 includes a first electrode layer 230, a second electrode layer 231, and a liquid crystal layer 20. 8. In addition, the liquid crystal layer 208 is sandwiched between insulating layers 232 and 233 which function as alignment layers. The second electrode layer 231 is provided on the second substrate 206 side, and the first electrode The polar layer 230 and the second electrode layer 231 are laminated with the liquid crystal layer 208 interposed therebetween. Also, a color filter 237 for color display is provided on the opposing substrate side. However, it may be provided on the substrate side where the transistor is formed. , the color filter 237 is not necessary.

[0093] Under the transistors 210 and 211, the channels of the transistors are protected from the backlight, etc. Light shielding layers 238a and 238b are provided to shield the formation region from light. There is no restriction on the material that can be used for the layer, and it is sufficient if it is a material with high light-shielding properties. For example, metal When a layer is used, it can function not only as a light shielding layer but also as a second gate electrode. This can be done.

[0094] In addition, on the opposing substrate side, the regions located above the transistors 210 and 211 are also light-shielded. A layer 236 is provided to protect the transistor from light irradiation. 236 also acts as a black matrix in the display area to improve display quality. It is possible.

[0095] As described above, by blocking the light irradiating the transistors 210 and 211, the oxide semiconductor This suppresses the photodegradation phenomenon that is a problem with transistors that use semiconductors, and allows them to be used for a long period of time. This makes it possible to suppress deterioration of the threshold voltage.

[0096] The spacer 235 is a columnar spacer obtained by selectively etching an insulating layer. This is provided to control the layer thickness (cell gap) of the liquid crystal layer 208. Spherical spacers may also be used.

[0097] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials can exhibit cholesteric, smectic, cubic, and chromatic phases depending on the conditions. It exhibits an isotropic phase, an isotropic phase, etc.

[0098] In addition, liquid crystals exhibiting a blue phase, which can eliminate the need for an alignment layer, may be used. It is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, it changes from the cholesteric phase to the isotropic phase. This is the phase that appears just before the transition to the blue phase. Since the blue phase appears only in a narrow temperature range, In order to improve the temperature range, 5% by weight or more of chiral agent and ultraviolet curing resin are mixed. The liquid crystal composition is then irradiated with ultraviolet light to form a liquid crystal layer. This liquid crystal layer exhibits a blue phase over a wide temperature range. The response speed is short, less than 1 msec. In addition, since it is optically isotropic, it can be easily aligned without any alignment treatment. Since no alignment layer is required, the viewing angle dependency is small. This eliminates the need for rubbing, which can prevent electrostatic damage caused by rubbing. Therefore, defects and damages of the liquid crystal display device during the manufacturing process can be reduced. In addition, when a blue phase is used, the composition of FIG. However, the present invention is not limited to the above, and may be applied to a structure in which the second electrode layer 231 and the first electrode layer 230 are formed on the same substrate side. A so-called transverse electric field mode configuration may also be used.

[0099] The specific resistivity of the liquid crystal material is 1×10 9 Ω cm or more, preferably 1×10 11 Ω cm or more, and more preferably 1×10 12 In this specification, the solid The resistivity value is measured at 20°C.

[0100] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. The charge is set to a certain period of time, taking into account the current and other factors. By using a transistor having a semiconductor layer, the liquid crystal capacitance of each pixel is It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0101] The transistor including the highly purified oxide semiconductor layer used in this embodiment is in an off state. Therefore, the current value (off-state current value) at the time of the image signal can be reduced. The signal retention time can be extended, and the write interval can also be set longer when the power is on. This reduces the frequency of refresh operations, which is effective in reducing power consumption. To bear fruit.

[0102] In addition, the transistor including the highly purified oxide semiconductor layer used in this embodiment has a relatively low Since a relatively high field effect mobility can be obtained, high speed driving is possible. By using the above transistor in the pixel portion, a high-quality image can be provided. In addition, a driver circuit portion can be formed over the same substrate using the above transistors. The number of parts in the liquid crystal display device can be reduced.

[0103] There are two types of LCD displays: TN (Twisted Nematic) and IPS (In-P lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (Antiferroelectric Liq. uid Crystal) mode can be used.

[0104] In addition, normally black type liquid crystal display devices, such as those using a vertical alignment (VA) mode, The liquid crystal display device may be a transmission type liquid crystal display device. This is a method of controlling the arrangement of crystal molecules, and it applies a In this method, the liquid crystal molecules are aligned vertically. There are several types of vertical alignment modes: For example, MVA (Multi-Domain Vertical Alignment) nt) mode, PVA (Patterned Vertical Alignment) You can also use the ASV mode, ASV mode, etc. It is a multi-layered device that is divided into regions (sub-pixels) and designed to tilt the molecules in different directions in each region. A method known as domaining or multi-domain design can be used.

[0105] In addition, in display devices, they are used as black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, etc. Optical members (optical substrates) such as a prevention member are provided as appropriate. For example, a polarizing substrate and a retardation substrate Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0106] In addition, multiple light-emitting diodes (LEDs) are used as backlights to display the image in a time-division format. It is also possible to perform a field sequential drive method. By applying the color driving method, it is possible to display colors without using color filters. This can be done.

[0107] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB ( R stands for red, G for green, and B for blue). For example, RGBW (W stands for white) or RGB plus one or more colors such as yellow, cyan, or magenta The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but may be applied to monochrome display devices. It is also possible.

[0108] In addition, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element utilizing electroluminescence is made of a light-emitting material They are classified according to whether they are organic or inorganic compounds. Generally, the former are called organic E The latter is called an inorganic EL element.

[0109] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. These carriers are then injected into a layer containing a light-emitting organic compound, causing a current to flow. When the electrons and holes recombine, the light-emitting organic compound forms an excited state, When the excited state returns to the ground state, light is emitted. This is called a current-excited light-emitting element.

[0110] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0111] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes must be transparent. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the opposite side of the substrate. Top emission, bottom emission where the light is emitted from the surface on the substrate side, or the surface on the substrate side and the opposite side There are light-emitting elements with a double-sided emission structure that extracts light from the outside, and light-emitting elements with any emission structure can be used. It is possible.

[0112] FIG. 5 shows an example of a light-emitting device using a light-emitting element as a display element. The transistor 43 is electrically connected to the transistor 210 provided in the pixel portion 202. The optical element 243 is configured with a first electrode layer 230, an electroluminescent layer 241, and a second electrode layer 231. The laminated structure is not limited to the structure shown in FIG. The configuration of the light emitting element 243 can be appropriately changed depending on the situation.

[0113] The partition 240 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 230 using a material, and the sidewall of the opening has a continuous curvature. It is preferable to form the inclined surface so as to have a slope having a given shape.

[0114] The electroluminescent layer 241 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it's

[0115] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 243, the second electrode layer A protective layer may be formed on the barrier 231 and the partition 240. The protective layer may be a silicon nitride layer, A silicon oxynitride layer, a DLC layer, etc. can be formed. A filler 244 is provided in the space sealed by the second substrate 206 and the sealant 205. In this way, the container is airtight and has little degassing, so that it is not exposed to the outside air. Packaging with protective film (lamination film, UV curing resin film, etc.) and cover material It is preferable to enclose the compound in a container.

[0116] The filler 244 may be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or a heat curing agent. Hardening resin can be used, such as PVC (polyvinyl chloride), acrylic resin, polyimide, etc. Mido resin, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (ethylene vinyl acetate) can be used.

[0117] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is placed on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be installed as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection layer. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0118] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display) and is a paper-based display. It is possible to make a display that is as easy to read as a regular display, consumes less power than other displays, and is thinner and lighter in size. This has the advantage that

[0119] Electrophoretic display devices come in a variety of forms, but generally consist of first particles with a positive charge and second particles with a negative charge. A plurality of microcapsules each including a first particle having a charge and a second particle having a charge are dispersed in a solvent or solute. By applying an electric field to the microcapsules, Particles are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. In addition, the first particles or the second particles contain a dye and do not move in the absence of an electric field. In addition, the color of the first particles and the color of the second particles are different (including colorless). .

[0120] In this way, the electrophoretic display device is a so-called "electrophoretic display" in which a substance with a high dielectric constant moves to an area of ​​high electric field. This is a display that utilizes the dielectrophoretic effect.

[0121] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0122] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, a semiconductor material, or a combination of both. Conductive materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A material selected from magnetochromic materials, magnetophoretic materials, or a composite material of these materials is used. That's good.

[0123] In addition, a display device using a twist ball display method can also be used as electronic paper. The twist ball display method uses black and white spherical particles as the display element. The insulating layer is disposed between a first electrode layer and a second electrode layer, and the first electrode layer and the second electrode layer are electrically connected to each other. This is a method of displaying information by controlling the orientation of spherical particles by generating a potential difference between the electrode layers. do.

[0124] FIG. 6 shows an active matrix electronic paper as one mode of a semiconductor device. The electronic paper is an example of a display device that uses the twisting ball display method.

[0125] A first electrode layer 230 connected to the transistor 210 and a second electrode layer 231 provided on the second substrate 206 Between the second electrode layer 231, there are a black region 255a and a white region 255b, and the liquid is A spherical particle 253 is provided that includes a cavity 252 that is filled with a body, the spherical particle The periphery of the second electrode layer 231 is filled with a filler 254 such as a resin. The second electrode layer 231 corresponds to an electrode (counter electrode). The second electrode layer 231 is electrically connected to a common potential line.

[0126] In addition, in FIG. 4 to FIG. 6, the first substrate 201 and the second substrate 206 are glass substrates. In addition to the plate, a flexible substrate can also be used, for example a light-transmitting plastic substrate. As for plastic, FRP (Fiberglass- Reinforced Plastics) plate, PVF (Polyvinyl Fluoride) film Film, polyester film or acrylic resin film can be used. A sheet with aluminum foil sandwiched between PVF film or polyester film is used. You can also be there.

[0127] The insulating layer 221 can be formed using an inorganic insulating material or an organic insulating material. , acrylic resin, polyimide, benzocyclobutene resin, polyamide, epoxy resin, etc. When the above-mentioned organic insulating material having heat resistance is used, it is suitable for the planarizing insulating layer. In addition to organic insulating materials, low-k materials, siloxane resins, PSG (P BPSG (Boron Pho sphorus silicate glass) can also be used. The insulating layer 221 may be formed by stacking a plurality of insulating layers made of these materials. .

[0128] The method for forming the insulating layer 221 is not particularly limited, and may be a sputtering method, a spin coating method, or the like, depending on the material. method, dipping method, spray coating method, droplet ejection method (inkjet method, screen printing method) printing method, offset printing method, etc.), roll coating method, curtain coating method, A coating method or the like can be used.

[0129] A first electrode layer 230 and a second electrode layer 231 (a pixel electrode layer, commonly referred to as a pixel electrode layer) for applying a voltage to a display element. In the case of the electrode layer, the direction of the light to be extracted is determined by the electrode layer. The light transmission or reflectivity can be selected depending on the location and the pattern structure of the electrode layer.

[0130] The first electrode layer 230 and / or the second electrode layer 231 may include titanium oxide. Indium oxide with tungsten oxide, indium zinc oxide with tungsten oxide, Indium oxide containing titanium, indium tin oxide containing titanium oxide, indium stannate Indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, and indium tin oxide doped with silicon. A light-transmitting conductive material such as an oxide can be used.

[0131] Either the first electrode layer 230 or the second electrode layer 231 is made of tungsten (W). , Molybdenum (Mo), Zirconium (Zr), Hafnium (Hf), Vanadium (V) , Niobium (Nb), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel ( Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag ) or its alloys, or its nitrides, and It can be achieved.

[0132] Either the first electrode layer 230 or the second electrode layer 231 is made of a conductive polymer (conductive The conductive layer can be formed by using a conductive composition containing a conductive polymer. As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline Phosphorus or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer of two or more of aniline, pyrrole and thiophene or Derivatives and the like.

[0133] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0134] As described above, a display device with good display performance can be obtained by using the transistor described in Embodiment 1. Note that the transistor described in Embodiment 1 can be used as an example of the display function. In addition to semiconductor devices having the above, power devices mounted on power supply circuits, LSIs and memories and semiconductor device having an image sensor function for reading information of an object. The present invention can be applied to semiconductor devices having various functions such as the above.

[0135] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0136] (Embodiment 3) The semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), (c) Portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples of electronic devices including the semiconductor device described in the first or second embodiment include: We will explain about this.

[0137] FIG. 7A shows a notebook personal computer, which includes a main body 301, a housing 302, a display It is composed of a display unit 303, a keyboard 304, etc.

[0138] FIG. 7B shows a portable digital assistant (PDA), which has a main body 311 with a display unit 313 and an external interface. The device is provided with an interface 315 and operation buttons 314. There is a stylus 312 as an example.

[0139] FIG. 7C shows an example of an electronic book. For example, an electronic book 320 includes a housing 321 and The housing 321 and the housing 322 are configured with a shaft portion 325. The opening and closing operations can be performed with the shaft portion 325 as an axis. By adopting such a configuration, it becomes possible to handle it like a paper book.

[0140] A display unit 323 is built into the housing 321, and a display unit 324 is built into the housing 322. The display unit 323 and the display unit 324 may be configured to display consecutive images. A configuration in which different images are displayed may be used. By using a configuration in which different images are displayed, For example, a text is displayed on the right display unit (display unit 323 in FIG. 7(C)) and a text is displayed on the left display unit ( In C), photographs and pictures can be displayed on the display unit 324).

[0141] FIG. 7C shows an example in which an operation unit and the like are provided on the housing 321. The control panel 321 includes a power supply 326, operation keys 327, a speaker 328, etc. The page can be turned by pressing the operation key 327. The housing may be provided with a display, a pointing device, etc. It is equipped with an external connection terminal (earphone terminal, USB terminal, etc.), a recording medium insertion part, etc. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary. good.

[0142] The electronic book 320 may be configured to transmit and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0143] FIG. 7D shows a mobile phone, which is composed of two housings, housing 330 and housing 331. The housing 331 includes a display panel 332, a speaker 333, a microphone 334, a pop-up 335, and a microphone. The device includes an imaging device 336, a camera 337, and an external connection terminal 338. The housing 330 also includes a solar cell 340 for charging the portable information terminal, an external memory slot, The housing 331 includes a built-in antenna.

[0144] The display panel 332 is equipped with a touch panel, and in FIG. The voltage output from the solar cell 340 is indicated by a dotted line. A boost circuit is also implemented to boost the voltage required for each circuit.

[0145] The display direction of the display panel 332 changes appropriately depending on the usage mode. A camera 337 is provided on the same surface as the speaker 32, making video calling possible. 333 and microphone 334 are not limited to voice calls, but can also be used for video calls, recording, playback, etc. Furthermore, the housing 330 and the housing 331 can be slid and unfolded as shown in FIG. The device can be folded and folded to an overlapping state, making it possible to miniaturize the device for easy portability.

[0146] The external connection terminal 338 can be connected to various cables such as a charging cable and a USB cable. It is also possible to charge the battery and to communicate data with a personal computer. A recording medium can be inserted into the reslot 341 to accommodate the storage and movement of larger amounts of data.

[0147] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0148] FIG. 7E shows a digital video camera, which includes a main body 351, a display unit (A) 357, and an eyepiece. 353, an operation switch 354, a display unit (B) 355, a battery 356, etc. It has been done.

[0149] FIG. 7F shows an example of a television device. The television device 360 ​​has a housing A display unit 363 is built into the camera 361. The display unit 363 can display images. Also, in this example, a configuration in which the housing 361 is supported by a stand 365 is shown. There are.

[0150] The television device 360 ​​can be operated using an operation switch provided on the housing 361 or a separate remote control. This can be done by the remote control unit. A display unit for displaying the information to be displayed may be provided.

[0151] The television device 360 ​​is configured to include a receiver, a modem, and the like. It can receive general television broadcasts, and can also receive them by wire or wirelessly via a modem. By connecting to a communication network, it can be one-way (from sender to receiver) or two-way ( It is also possible to communicate information between a sender and a receiver, or between receivers themselves.

[0152] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. EXAMPLES

[0153] In this example, a transistor having an n-type buffer layer described in the first embodiment is We fabricated the transistor and described the results of comparing its electrical characteristics and reliability with those of a conventional transistor. Reveal.

[0154] According to the manufacturing method of Embodiment 1, a transistor having a structure corresponding to that shown in FIG. The transistor is configured as a 300 nm thick silicon oxide film as the insulating layer 102, which is the base layer. The oxide semiconductor layer 106 is an In-Ga-Zn The -O film and the buffer layers 107a and 107b are made of 5 nm thick indium containing silicon (Si). Indium tin oxide (ITO) film or indium zinc oxide (IZO) film, source The electrode layer 108a and the drain electrode layer 108b are made of a 100 nm tungsten film, and the gate The insulating layer 112 is a 15 nm silicon oxynitride film, and the gate electrode layer 114 is a gate insulating film. From the edge layer 112 side, a tantalum nitride film of 15 nm and a tungsten film of 135 nm were laminated. .

[0155] Although not shown in FIG. 8A, the gate electrode layer 114 and the gate insulating layer 112 are A 300 nm thick silicon oxide film was formed on the substrate as an interlayer insulating film by sputtering. The source electrode layer 108a and the drain electrode layer 108b are electrically connected to each other through contact holes formed in the interlayer insulating film. As a wiring layer connected to each of the gate electrode layer 114 and the gate electrode layer 115, a 50 nm titanium A 100 nm thick silicon film, a 100 nm thick aluminum film, and a 5 nm thick titanium film were formed. This was formed as an extraction electrode when obtaining the electrical characteristics of the transistor.

[0156] First, we fabricated transistors (L = 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, On-resistance of 0.8μm, 0.9μm, 2μm, 3μm, 5μm, 10μm, W=10μm) Based on the data on the L length dependence of the resistance, the TLM (Transmission Line Mode The parasitic resistance between the semiconductor layer and the source / drain electrodes was calculated using the l) method (transmission line model). In addition, the IV characteristics (drain The field effect mobility was calculated using the following conditions: are shown in Table 1. Here, the field effect mobility indicates the maximum value within the above gate voltage, Three types of transistors (without buffer layer, with ITO or IZO containing Si as buffer layer) Twelve samples of each type were measured, and the median values ​​are shown.

[0157] [Table 1]

[0158] From the results in Table 1, the transistor with an n-type buffer layer has a semiconductor layer and a source / drain The parasitic resistance between the n-type electrodes was reduced by about 40%, demonstrating the effect of having an n-type buffer layer. As a result, the on-current characteristics are improved and the field effect mobility is improved by about 9% to 10%. The results were also confirmed.

[0159] Furthermore, for a transistor with L / W=3μm / 50μm fabricated in the same manner as above, A gate BT (voltage-thermal) stress test was conducted. The test was performed by connecting the source of the transistor to the GN D, +0.1V on the drain, +3V (+2MV / cm) and -3V (-2MV / cm) on the gate m), +9V (+6MV / cm), or -9V (-6MV / cm) at 150°C for 1 hour. The test was performed under the condition that a voltage was applied for a short period of time.

[0160] Among the above tests, applying +3V, -3V, or +9V to the gate was used to measure the effectiveness of the buffer layer. No difference was observed when no voltage was applied, but when -9V was applied, the on-state voltage was The degradation of the current (current when the gate voltage is 3V) is smaller for transistors with a buffer layer. The degradation rate of the on-state current obtained from Figures 9(A), (B), and (C) is shown in 2. Here, the initial on-current is defined as the current value when the gate voltage is 3 V. The on-current after negative gate BT stress is The current is defined as the difference between the threshold voltages after stress.

[0161] [Table 2]

[0162] The results show that the transistor with the buffer layer has a higher It can be seen that the buffer also has the effect of significantly reducing the degradation rate of the on-state current. As a layer, the degradation rate of the on-current is suppressed more by using ITO containing Si than by IZO. It was also found that this could be done.

[0163] Regarding the results of the negative gate BT stress test mentioned above (suppression of the decrease in on-current), We performed scientific calculations to investigate the causes.

[0164] The model used for the scientific calculations is basically the configuration shown in Figure 8(A). Considering the structure, the model without a buffer layer is The amount of the buffer layer is set to 5 nm. The model with the buffer layer is shown in FIG. Based on the results of EM observation, the taper angle of the edge was set to 30°, and the oxide in the channel formation region was The amount of film loss of the semiconductor layer was set to 10 nm. Note that FIG. 13(B) is used to explain FIG. 13(A). This is a schematic diagram.

[0165] The size of the transistor is L / W=3 / 50μm, and the gate insulating film (silicon oxynitride The film thickness of the oxide semiconductor is 15 nm, the band gap (Eg) of the oxide semiconductor is 3.15 eV, and the electron The affinity (χ) is 4.3 eV, the dielectric constant is 15, and the electron mobility is 10 cm 2 It was assumed that / Vs. In addition, the oxide semiconductor layer that becomes the channel formation region is a uniform amorphous, n-type buffer The layer is a high-concentration (1 × 10 20 / cm 3 We assumed an oxide semiconductor containing n-type donors. The band gap and electron affinity of the buffer layer are determined by the oxide semiconductor layer that serves as the channel formation region. The same value is used, and the resistivity is 3×10 -3 The electron mobility was determined to be Ω·cm The work function of the gate metal is 4.9 eV (assuming tungsten), and the source / drain metal The work function of the quartz crystal is 4.5 eV (assuming molybdenum), and the calculation is based on a Synopsys device. The simulator Sentaurus Device was used.

[0166] Figure 10 shows the negative gate BT stress (gate voltage = -9V , drain voltage = +0.1V, 150℃) is applied. As a result of the calculation, it was found that electric field concentration occurs in a part of the oxide semiconductor layer, as shown by the arrow in the figure. In the figure, OS means an oxide semiconductor layer, and GI means a gate insulating layer. .

[0167] Next, we assume that electron traps are formed by negative gate BT stress, and Calculations assuming that a negative charge is fixed at the position where the charge transfer occurs (the interface between the oxide semiconductor layer and the gate insulating layer). The results are shown in Figures 11 and 12.

[0168] The negative charge has a surface density of 1×10 13 cm -2 The charge is set to , and the IV characteristics are calculated with and without a negative charge. Calculate and see if the phenomenon of on-current degradation in the negative gate BT stress test can be reproduced. In addition, a negative charge was also inserted at the same position on the source side to ensure symmetry.

[0169] As a result, as shown in FIG. 11, when the drain voltage was +0.1 V, In this model, the on-current is significantly reduced, and the IV characteristics in Figure 9(A) can be reproduced. A decrease in on-current was also observed in the model with the buffer layer in Figure 11. However, the amount is small, and in this respect, the IV characteristics of Figures 9(B) and 9(C) are reproduced. It can be said that this is the case.

[0170] In the current density distribution diagram of Figure 11 (gate voltage = +3V, drain voltage = +0.1V), In the model without a buffer layer, the negative charge repels electrons at the gate insulating layer interface, It can be seen that a depletion layer is formed around the load. This depletion layer exists in the current path. On the other hand, in the model with a buffer layer, the n-type Since electrons are supplied from the buffer layer, the depletion layer is very small even if negative charges exist. This is believed to suppress the decrease in on-state current.

[0171] In the current density distribution diagram of Figure 12 (gate voltage = +3V, drain voltage = +3V), Even in a model without a buffer layer, it was confirmed that the current flows by bypassing the depletion layer caused by negative charges. When the drain voltage is high (in the saturated region), the gate is pulled by the drain electric field. Since current flows even at positions away from the insulating layer interface, it is believed that the current flows by bypassing the negative charge. Therefore, when the drain voltage is high, the on-state current due to negative gate BT stress is It can be said that a decrease in flow is unlikely to occur.

[0172] As a result of the above, the phenomenon of the decrease in on-current after negative gate BT stress shown in Figure 9 is This could be explained by the results of scientific calculations.

[0173] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. . [Explanation of symbols]

[0174] 100 Substrates 102 Insulating layer 106 Oxide semiconductor layer 107a Buffer layer 107b Buffer layer 108a Source electrode layer 108b Drain electrode layer 112 Gate insulating layer 114 Gate electrode layer 151 Transistor 201 Substrate 202 Pixel section 203 Signal line driver circuit 204 Scanning line driving circuit 205 Sealing material 206 Substrate 208 Liquid crystal layer 210 Transistor 211 Transistor 213 Liquid crystal element 215 Connection terminal electrode 216 Terminal electrode 218 FPC 218a FPC 218b FPC 219 Anisotropic Conductive Layer 221 Insulating layer 230 Electrode layer 231 Electrode layer 232 Insulating layer 233 Insulating Layer 235 Spacer 236 Light blocking layer 237 Color Filter 238a Light blocking layer 238b Light blocking layer 240 Bulkhead 241 Electroluminescent Layer 243 Light-emitting element 244 Filling material 252 Cavity 253 Spherical particles 254 Filling material 255a black area 255b White area 301 Main unit 302 Case 303 Display section 304 Keyboard 311 Main unit 312 Stylus 313 Display section 314 Operation button 315 External Interface 320 e-books 321 Case 322 Case 323 Display section 324 Display section 325 Shaft 326 Power supply 327 Operation Key 328 Speakers 330 Case 331 Case 332 Display Panel 333 Speaker 334 Microphone 335 Operation Key 336 Pointing Device 337 Camera 338 External connection terminal 340 Solar Cells 341 External memory slot 351 Main unit 353 Eyepiece 354 Operation switch 355 Display section (B) 356 Battery 357 Display section (A) 360 Television Equipment 361 Case 363 Display section 365 Stand

Claims

1. a first conductive film having a function as a gate electrode of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a first film having a region in contact with an upper surface of the oxide semiconductor film; a second film having a region in contact with an upper surface of the oxide semiconductor film; a second conductive film having a region in contact with an upper surface of the first film; a third conductive film having a region in contact with an upper surface of the second film; the second conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the third conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the first film contains indium, zinc, and oxygen; the second film contains indium, zinc, and oxygen; the oxide semiconductor film contains indium, gallium, zinc, and oxygen; the first film has a first region that does not overlap with the second conductive film; the second film has a second region that does not overlap with the third conductive film; a side surface of the first region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the first region form a first angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second conductive film form a second angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second region form a third angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the third conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a lower surface of the third conductive film form a fourth angle in a cross-sectional view taken along a channel length direction of the transistor; the first angle is less than the second angle; the third angle is smaller than the fourth angle; the oxide semiconductor film has a recess; The recess does not overlap the first film and does not overlap the second film. Semiconductor device.

2. a first conductive film having a function as a gate electrode of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a first film having a region in contact with a top surface of the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the transistor; a second film having a region in contact with a top surface of the oxide semiconductor film and functioning as the other of the source electrode and the drain electrode of the transistor; a second conductive film having a region in contact with an upper surface of the first film; a third conductive film having a region in contact with an upper surface of the second film; the second conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the third conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the first film contains indium, zinc, and oxygen; the second film contains indium, zinc, and oxygen; the oxide semiconductor film contains indium, gallium, zinc, and oxygen; the first film has a first region that does not overlap with the second conductive film; the second film has a second region that does not overlap with the third conductive film; a side surface of the first region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the first region form a first angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second conductive film form a second angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second region form a third angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the third conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a lower surface of the third conductive film form a fourth angle in a cross-sectional view taken along a channel length direction of the transistor; the first angle is less than the second angle; the third angle is smaller than the fourth angle; the oxide semiconductor film has a recess; The recess does not overlap the first film and does not overlap the second film. Semiconductor device.

3. a first conductive film having a function as a gate electrode of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a first film having a region in contact with an upper surface of the oxide semiconductor film; a second film having a region in contact with an upper surface of the oxide semiconductor film; a second conductive film having a region in contact with an upper surface of the first film; a third conductive film having a region in contact with an upper surface of the second film; the second conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the third conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the first film contains indium, zinc, and oxygen; the second film contains indium, zinc, and oxygen; the oxide semiconductor film contains indium, gallium, zinc, and oxygen; the first film has a first region that does not overlap with the second conductive film; an upper surface of the first region is not in contact with the second conductive film; the second film has a second region that does not overlap with the third conductive film; an upper surface of the second region is not in contact with the third conductive film; a side surface of the first region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the first region form a first angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second conductive film form a second angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second region form a third angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the third conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a lower surface of the third conductive film form a fourth angle in a cross-sectional view taken along a channel length direction of the transistor; the first angle is less than the second angle; the third angle is smaller than the fourth angle; the oxide semiconductor film has a recess; The recess does not overlap the first film and does not overlap the second film. Semiconductor device.

4. a first conductive film having a function as a gate electrode of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a first film having a region in contact with a top surface of the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the transistor; a second film having a region in contact with a top surface of the oxide semiconductor film and functioning as the other of the source electrode and the drain electrode of the transistor; a second conductive film having a region in contact with an upper surface of the first film; a third conductive film having a region in contact with an upper surface of the second film; the second conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the third conductive film includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; the first film contains indium, zinc, and oxygen; the second film contains indium, zinc, and oxygen; the oxide semiconductor film contains indium, gallium, zinc, and oxygen; the first film has a first region that does not overlap with the second conductive film; an upper surface of the first region is not in contact with the second conductive film; the second film has a second region that does not overlap with the third conductive film; an upper surface of the second region is not in contact with the third conductive film; a side surface of the first region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the first region form a first angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second conductive film form a second angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the second region in a region overlapping with the oxide semiconductor film and the first conductive film and a bottom surface of the second region form a third angle in a cross-sectional view taken along a channel length direction of the transistor; a side surface of the third conductive film in a region overlapping with the oxide semiconductor film and the first conductive film and a lower surface of the third conductive film form a fourth angle in a cross-sectional view taken along a channel length direction of the transistor; the first angle is less than the second angle; the third angle is smaller than the fourth angle; the oxide semiconductor film has a recess; The recess does not overlap the first film and does not overlap the second film. Semiconductor device.

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