Semiconductor device and module

Abstract

To provide a semiconductor device capable of reducing generation of noise even when a plurality of semiconductor devices are connected in parallel and used simultaneously, with a simple structure.SOLUTION: A semiconductor device includes: a plurality of transistor cells 18 formed in an SiC epitaxial layer 28; a gate pad 4 for electrical connection for controlling the plurality of transistor cells; a pad peripheral unit 12 formed around the gate pad so as to continuously surround the gate pad; a built-in resistor 21 composed of polysilicon, partially arranged below the gate pad and electrically connecting the gate pad and the pad peripheral unit; and a plurality of source pads 6 for electrical connection. The gate pad is physically separated from the pad periphery unit in the same layer so that space is formed between the gate pad and the pad peripheral unit, and is formed around an edge portion of the epitaxial layer. A connection portion to which a connection member is connected is selectively formed on a surface of the gate pad.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a module including a plurality of such semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a gate pad, a gate connecting wiring made of polysilicon, and a gate metal wiring formed on the gate connecting wiring and integrally connected to the gate pad. When a voltage is applied to the gate pad, power is supplied to a MOSFET formed in an active region via the gate metal wiring and the gate connecting wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-238885 A Summary of the Invention [Problem to be solved by the invention]

[0004] In practice, a module having multiple semiconductor devices (chips) connected in parallel to each other is sometimes used. The module is provided with a gate terminal electrically connected to the gates of each chip at the same time. By applying a control voltage to the gate terminal, a voltage is simultaneously applied to the gates of each built-in chip, thereby performing a switching operation.

[0005] However, such modules have the problem that noise is easily generated when they are turned on. This is because there is variation in gate resistance between multiple chips, and current is concentrated in the chip with a relatively low gate resistance at the beginning of the on control. In addition, the variation in gate resistance is caused by the variation in processing accuracy (etching dimensions, etc.) when manufacturing the chips, so it is difficult to eliminate this variation.

[0006] On the other hand, an external gate resistor having a resistance value larger than that of the gate resistor in each chip may be provided for each chip. However, this causes another problem that the structure of the module becomes complicated and assembly becomes difficult.

[0007] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a semiconductor device having a simple structure that can reduce noise generation even when a plurality of semiconductor devices are connected in parallel and used simultaneously, and a module including a plurality of such semiconductor devices. [Means for solving the problem]

[0008] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer; a plurality of cells formed in the semiconductor layer; a control pad for electrical connection for controlling the plurality of cells; a pad peripheral portion formed around the control pad so as to continuously surround the control pad; and a built-in resistor made of polysilicon partially arranged below the control pad, the built-in resistor electrically connecting the control pad and the pad peripheral portion; and a plurality of source pads for electrical connection, the control pad being physically separated from the pad peripheral portion in the same layer so as to form a space between the control pad and the pad peripheral portion, the control pad being formed around an edge of the semiconductor layer, a connection portion to which a connection member is connected being selectively formed on a surface of the control pad, and the built-in resistor being selectively arranged in an area avoiding the connection portion in a plan view.

[0009] In one embodiment of the present invention, the connection portion occupies more than half of the surface area of ​​the control pad in plan view.

[0010] In one embodiment of the present invention, the semiconductor device further comprises a gate finger extending from the periphery of the pad.

[0011] In one embodiment of the present invention, the gate fingers extend in three directions from the periphery of the pad.

[0012] In one embodiment of the present invention, the gate fingers have portions extending to four corners of the semiconductor device.

[0013] In one embodiment of the present invention, the width of the gate finger is narrower than the width of the built-in resistor.

[0014] In one embodiment of the present invention, the built-in resistor has a rectangular shape in a plan view.

[0015] In one embodiment of the present invention, the control pad is made of a material including aluminum.

[0016] In one embodiment of the present invention, the peripheral portion of the pad is made of a material containing aluminum.

[0017] In one embodiment of the present invention, each of the source pads is made of a material including aluminum.

[0018] In one embodiment of the present invention, the semiconductor device has a rectangular shape in a plan view, and the control pad is provided near the center of one side of the semiconductor device in a plan view.

[0019] In one embodiment of the present invention, the pad periphery has the same thickness as the control pad.

[0020] In one embodiment of the present invention, the built-in resistor is partially disposed in a region below the control pad, and an interlayer film is selectively disposed between the built-in resistor and the control pad.

[0021] In one embodiment of the present invention, the connection portion is formed in a central portion of the control pad.

[0022] The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to one embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view of the area surrounded by the dashed line II in FIG. [Diagram 3] 3a and 3b are enlarged views of the area surrounded by the dashed double-dashed line III in FIG. 2, with FIG. 3a showing a plan view and FIG. 3b showing a cross-sectional view of the semiconductor device taken along the line IIIb-IIIb in FIG. 3a. [Figure 4] FIG. 4 is a diagram showing a modified example of the cell structure. [Diagram 5] FIG. 5 is an electric circuit diagram showing an electric circuit of a module to which a semiconductor device according to one embodiment of the present invention is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0025] Fig. 1 is a schematic plan view of a semiconductor device 1 according to one embodiment of the present invention. For clarity, in Fig. 1, some elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

[0026] The semiconductor device 1 is a semiconductor device that employs SiC, and is formed, for example, in the shape of a quadrangular chip when viewed in a plan view (hereinafter simply referred to as "plan view") of the outermost surface seen from the normal direction.

[0027] The semiconductor device 1 has an active region 2 and a termination region 3 surrounding the active region 2. In this embodiment, the active region 2 is formed in an inner region of the semiconductor device 1 in a generally rectangular shape in plan view, but the shape is not particularly limited. A guard ring (not shown) may be formed between the active region 2 and the termination region 3 to improve the breakdown voltage of the semiconductor device 1.

[0028] In the active region 2, a gate metal 44 as an example of a control pad of the present invention, a source metal 43, and a gate finger 5 as an example of a finger of the present invention are formed. A passivation film 40 is formed on the outermost surface of the semiconductor device 1 so as to cover these. In the passivation film 40, openings 41 and 42 are formed to expose a part of the gate metal 44 and a part of the source metal 43 as the gate pad 4 and the source pad 6, respectively. On the other hand, the gate finger 5 is entirely covered with the passivation film 40.

[0029] The gate metal 44, the gate finger 5 and the source metal 43 are made of metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), Cu (copper), or the like.

[0030] By forming the gate finger 5 with metal wiring having a lower resistance than polysilicon, it is possible to supply gate current in a short time even to the transistor cell 18 (see FIG. 2) located at a relatively distant position (far position) from the gate metal 44. Furthermore, since Al has good workability (is easy to process), the process of forming these wirings can be simplified. On the other hand, AlCu can improve the power cycle resistance of the semiconductor device 1 compared to when Al is used, and can also improve the bonding strength of the bonding wire with respect to the gate pad 4. When Cu is used, there is an advantage that the resistivity can be reduced compared to when Al and AlCu are used.

[0031] Gate metal 44 is selectively formed in a portion of the periphery of active region 2 (near the boundary with termination region 3). Gate fingers 5 extend from the position where gate pad 4 is formed, in two directions, along the periphery of active region 2 and toward the inside of active region 2. As a result, cell regions 7, 45 are formed in the active region 2 in the portion partitioned by multiple gate fingers 5 extending in different directions with gate metal 44 between them and in the outer region of gate fingers 5.

[0032] More specifically, in this embodiment, the gate metal 44 is formed in a quadrangular shape in a plan view, and is selectively disposed in the center of one side 8 of the active region 2. Note that the sides other than the side 8 of the active region 2 (the side on which the gate metal 44 is disposed) are the opposite side 9 of the side 8, and sides 10 and 11 continuing to both ends of the sides 8 and 9, respectively.

[0033] The gate finger 5 includes a pad periphery 12 that surrounds the gate metal 44 with a gap therebetween, and a first finger 13 and a second finger 14 that extend from the pad periphery 12 in a direction along the side 8 of the active area 2 and in a direction perpendicular to the side 8, respectively.

[0034] The pad peripheral portion 12 is formed in a quadrangular ring shape in a plan view along the periphery of the gate metal 44 .

[0035] The first fingers 13 are formed in pairs along the side 8 in the direction toward the side 10 and the opposite side 11 with respect to the pad peripheral portion 12 .

[0036] Second finger 14 includes a linear main portion 15 that crosses active area 2 up to side 9 in a direction perpendicular to first finger 13, and a plurality of branch portions 16 that are integrally connected to main portion 15 and extend from the connection point along first finger 13. In this embodiment, branch portions 16 are connected to two points, the tip portion of main portion 15 and an intermediate portion of main portion 15, to form a total of two pairs of branches, but the number is not particularly limited.

[0037] Thus, in the active region 2, cell regions 7, 45 are defined by the first finger 13 and the second finger 14 (main portion 15 and branch portion 16). In this embodiment, a total of four inner cell regions 7 are formed, one at each corner of the intersection formed by the main portion 15 of the second finger 14 and the central branch portion 16. In addition, an annular outer cell region 45 is formed along the periphery of the active region 2 between the periphery of the active region 2 and the gate finger 5.

[0038] The source metal 43 is formed so as to cover almost the entire inner and outer cell regions 7, 45. A total of four openings 42 are formed in the passivation film 40 so that one source pad 6 is disposed in each of the inner cell regions 7.

[0039] Further, a recess 17 corresponding to the shape of the gate metal 44 is formed in the source metal 43. The gate metal 44 is set back toward the inside of the active region 2 with respect to the first finger 13, and the recess 17 is a dent formed to avoid this gate metal 44.

[0040] Fig. 2 is an enlarged view of the area surrounded by dashed line II in Fig. 1. That is, it is an enlarged view of the gate pad 4 and its neighboring area of ​​the semiconductor device 1. For clarity, in Fig. 2, some elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

[0041] As shown in FIG. 2, a plurality of transistor cells 18 are arranged in inner and outer cell regions 7, 45 defined by gate finger 5 (pad peripheral portion 12, first finger 13, and second finger 14).

[0042] In this embodiment, the multiple transistor cells 18 are arranged in a matrix in plan view in each of the inner and outer cell regions 7, 45. In the vicinity of the gate finger 5, the multiple transistor cells 18 are aligned to match the shape of the gate finger 5. For example, the multiple transistor cells 18 are aligned to bend to match the shape of the corners of the pad peripheral portion 12, and aligned linearly to match the shape of the linear main portion 15 of the second finger 14. The source metal 43 is formed to cover the multiple transistor cells 18.

[0043] 2, for clarity, only a portion of the transistor cells 18 covered with the source metal 43 is shown. The arrangement of the transistor cells 18 is not limited to a matrix, and may be, for example, a stripe or staggered pattern. The planar shape of each transistor cell 18 is not limited to a square, and may be, for example, a circle, a triangle, a hexagon, etc.

[0044] Between adjacent transistor cells 18, a gate electrode 19 as an example of a control electrode of the present invention is formed. In the inner and outer cell regions 7, 45, the gate electrode 19 is disposed between each of the matrix-shaped transistor cells 18, and is formed in a lattice shape in a plan view as a whole. Meanwhile, the gate electrode 19 is formed not only in the inner and outer cell regions 7, 45 but also in the region where the gate fingers 5 are disposed, and the lower portion of the gate finger 5 is in contact with the gate finger 5.

[0045] In this embodiment, a part of the gate electrode 19 is formed in the region below the first finger 13 and the second finger 14, and faces the first finger 13 and the second finger 14 as a contact part. In FIG. 2, for clarity, the part of the gate electrode 19 formed in the region below is shown by a hatched region. As a result, the gate electrodes 19 of the inner cell regions 7 adjacent to each other are continuous through the gate electrode 19 crossing the second finger 14 below. This continuous form of the gate electrode 19 is also the same between the inner cell region 7 and the outer cell region 45 adjacent to the gate metal 44. In other words, the gate electrodes 19 in these regions are continuous through the gate electrode 19 crossing the first finger 13 below.

[0046] Each of the first finger 13 and the second finger 14 is connected to a gate electrode 19 disposed in an underlying region thereof by a gate contact 20. The gate contact 20 is formed linearly along the longitudinal direction of each of the first finger 13 and the second finger 14 in the central portion of the finger spaced apart from each side edge of the finger.

[0047] In this embodiment, the multiple built-in resistors 21 are arranged below the gate metal 44. It is preferable to provide symmetry to the arrangement of the multiple built-in resistors 21 by arranging the multiple built-in resistors 21 at positions that are approximately equidistant from each other from the center of gravity of the planar shape of the gate metal 44. In this embodiment, the multiple built-in resistors 21 are arranged one at each corner of the gate metal 44 that is equidistant from the center of gravity G of the gate metal 44 that is rectangular in plan view. This provides symmetry to the four built-in resistors 21.

[0048] Various such symmetrical patterns are possible, and for example, two built-in resistors 21 may be arranged, one at each of two diagonally opposite corners of gate metal 44, or may be arranged, one at each of two opposite sides of gate metal 44, facing each other. Furthermore, for example, when gate metal 44 has a circular shape in a plan view, two built-in resistors 21 may be arranged, one at each of both ends of the diameter of gate metal 44, and when gate metal 44 has a triangular shape in a plan view, three built-in resistors 21 may be arranged, one at each of three corners of gate metal 44.

[0049] Each built-in resistor 21 is formed so as to cross and straddle the annular gap region 26 between the gate metal 44 and the gate finger 5 (pad peripheral portion 12). As a result, the built-in resistor 21 faces each of the gate metal 44 and the gate finger 5. The gate metal 44 and the gate finger 5 (pad peripheral portion 12) are connected to the built-in resistor 21 arranged in the region below them by a pad-side contact 22 and a cell-side contact 23, which are an example of the contact via of the present invention.

[0050] In this embodiment, the four built-in resistors 21 extend from below each peripheral portion 24 of two opposing sides of the gate metal 44 in an outward direction perpendicular to the sides to below the pad peripheral portion 12. Each built-in resistor 21 is formed in a rectangular shape in a plan view and has a size of, for example, 200 μm□ or less (200 μm×200 μm or less). In practice, if the size of each built-in resistor 21 is 200 μm□ or less, the area of ​​the region on the SiC epitaxial layer 28 (see FIG. 3b) that is sacrificed for the built-in resistors 21 can be reduced, thereby saving space.

[0051] The pad contact 22 and the cell contact 23 are formed in parallel linear shapes along the sides of the gate metal 44 and the pad peripheral portion 12, respectively.

[0052] The built-in resistor 21 is disposed below the peripheral portion 24 avoiding the central portion of the gate metal 44, and further, the region above the region where the built-in resistor 21 is disposed is covered with the passivation film 40, thereby ensuring the gate pad 4 as the wire region of the present invention surrounded by the built-in resistor 21 in the central portion of the gate metal 44. The gate pad 4 is the region to which the bonding wire is connected.

[0053] That is, in this embodiment, each corner of the gate metal 44 on which the built-in resistor 21 is arranged is selectively covered with the passivation film 40, and the other part of the gate metal 44 is exposed from the opening 41. As a result, the gate pad 4 having a rectangular shape in a plan view with each corner recessed inward is exposed on the top surface of the semiconductor device 1. In this way, by covering the region above the region on which the built-in resistor 21 is arranged with the passivation film 40, it is possible to prevent the bonding wire from being erroneously joined to the part of the gate metal 44 that overlaps with the built-in resistor 21 when the bonding wire is joined. As a result, it is possible to prevent the built-in resistor 21 from being damaged or destroyed by an impact such as ultrasonic waves when the bonding wire is joined.

[0054] 3a and 3b are enlarged views of the area surrounded by the two-dot chain line III in FIG. 2, where FIG. 3a shows a plan view and FIG. 3b shows a cross-sectional view of the semiconductor device 1 cut along the line IIIb-IIIb in FIG. 3a. In FIG. 3a and FIG. 3b, for clarity, the scale of each component may differ from that in FIG. 1 and FIG. 2, and the scale of each component may also differ between FIG. 3a and FIG. 3b. In FIG. 3a and FIG. 3b, for clarity, some of the elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

[0055] Next, the configuration of the built-in resistor 21 and its surrounding area will be described in more detail together with the cross-sectional structure of the semiconductor device 1.

[0056] The semiconductor device 1 includes a SiC substrate 27 and a SiC epitaxial layer 28. The SiC epitaxial layer 28 is laminated on the SiC substrate 27, and this laminated structure is shown as an example of the SiC semiconductor layer of the present invention.

[0057] The SiC substrate 27 and the SiC epitaxial layer 28 are each + Type and n - It is a type of SiC. + The impurity concentration of the SiC substrate 27 is, for example, 1×10 17 cm -3 ~1×10 21 cm -3 On the other hand, n - The impurity concentration of the SiC epitaxial layer 28 is, for example, 1×10 14 cm -3 ~1×10 17 cm -3 As the n-type impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used (hereinafter the same).

[0058] In the inner cell region 7, a plurality of transistor cells 18 are formed on a surface portion of the SiC epitaxial layer 28. The plurality of transistor cells 18 are p - Type body region 29 and p -The n-type body region 29 is selectively formed in an inner region spaced from the periphery thereof. + A source region 30 and an n + The p-type source region 30 is selectively formed in an inner region spaced apart from the periphery thereof. + The n-type body contact region 31 of the SiC epitaxial layer 28 is also included. - The mold portion serves as a common drain region for multiple transistor cells 18 .

[0059] As shown in FIG. 3a, in plan view, except for the transistor cells 18 along the pad periphery 12 (gate fingers 5), + The n-type body contact region 31 is surrounded by + A source region 30 is formed, and further, + The p - A mold body region 29 is formed. - In the type body region 29, n + The annular region surrounding the type source region 30 is a channel region 32 in which a channel is formed when the semiconductor device 1 is turned on. Although not shown in Figures 3a and 3b, the multiple transistor cells 18 in the outer cell region 45 also have a similar configuration.

[0060] On the other hand, in the transistor cells 18 along the pad periphery 12 (gate finger 5), p - Type body region 29 and p + The body contact regions 31 are p - Type region 34 and p + It is electrically connected to the mold region 33 .

[0061] p - The impurity concentration of the mold body region 29 is, for example, 1×10 14 cm -3 ~1×10 19 cm -3 and n + The impurity concentration of the source region 30 is, for example, 1×10 17 cm -3 ~1×10 21 cm-3 and p + The impurity concentration of the body contact region 31 is, for example, 1×10 19 cm -3 ~1×10 21 cm -3 It is.

[0062] In order to form these regions 29 to 31, for example, p - The p body region 29 is then formed. - By sequentially implanting n-type impurities and p-type impurities into the surface of the body region 29, + type source region 30 and p + A p-type body contact region 31 is formed. This forms a transistor cell 18 made up of regions 29 to 31. As the p-type impurity, for example, B (boron), Al (aluminum), or the like can be used (the same applies below).

[0063] In the active region 2, in the region other than the inner and outer cell regions 7 and 45, specifically, in the region below the gate metal 44, the gate finger 5 and the gap region 26, p is formed on the surface of the SiC epitaxial layer 28. - A mold region 34 is formed. - The surface of the mold region 34 is + A mold area 33 is formed.

[0064] p + The SiC epitaxial layer 28 has a p - Type region 34 p - The mold part is selectively exposed on the SiC surface, and in other areas, the p + The gate metal 44 and the gate finger 5 are formed over almost the entire area below the gate metal 44 so that the mold portion is selectively exposed on the SiC surface. That is, the gate metal 44 and the gate finger 5 are p - The p +It faces the mold part. + Type region 33 and p - The type regions 34 are formed so as to extend to below the source metal 43, and below the source metal 43 (in this embodiment, the portion outside the source pad 6), + The body contact region 31 and the p - 3a, the p-type body region 29 of the transistor cell 18 along the pad periphery 12 (gate finger 5) is integrally connected to the p-type body region 29. + Type body contact region 31 and p + The mold region 33 is represented by the hatched area. + The body contact region 31 is fixed to the ground potential together with the source metal 43, so that + The type region 33 is stable at 0 V. Therefore, as in this embodiment, most of the gate metal 44 and the gate fingers 5 are p + It is preferable to have it facing the mold area 33 .

[0065] p + Type region 33 and p - The type regions 34 are each + The body contact region 31 and the p - It is formed in the same process as the mold body region 29, and has the same impurity concentration and depth.

[0066] A gate insulating film 35, which is an example of an insulating film of the present invention, is formed on the surface of the SiC epitaxial layer 28. The gate insulating film 35 is made of an insulating material such as silicon oxide and has a thickness of, for example, 0.001 μm to 1 μm. The gate insulating film 35 is a common insulating film for insulating the gate electrode 19 and the built-in resistor 21 from the SiC epitaxial layer 28.

[0067] A gate electrode 19 and an internal resistor 21 are formed on the gate insulating film 35. The gate electrode 19 is formed to face the channel region 32 of each transistor cell 18 with the gate insulating film 35 interposed therebetween. -Exposure p of mold region 34 - The gate insulating film 35 is formed on the mold portion so as to face each other.

[0068] Both the gate electrode 19 and the built-in resistor 21 are made of p-type polysilicon and may be formed in the same process. In this embodiment, the gate electrode 19 and the built-in resistor 21 contain B (boron) as a p-type impurity. B (boron)-containing polysilicon has a higher specific resistance value than phosphorus (P)-containing polysilicon that is generally used in Si semiconductor devices. Therefore, the boron-containing polysilicon (built-in resistor 21) requires a smaller area than the phosphorus-containing polysilicon even when realizing the same resistance value. Therefore, the area occupied by the built-in resistor 21 on the SiC epitaxial layer 28 can be reduced, and the space can be used effectively.

[0069] The concentration of the p-type impurity contained in the polysilicon can be appropriately changed according to the design resistance values ​​of the gate electrode 19 and the built-in resistor 21. In this embodiment, the concentration is set so that the sheet resistance of the built-in resistor 21 is 10Ω / □ or more. In practice, if the sheet resistance of the built-in resistor 21 is 10Ω / □ or more, the resistance value of the entire built-in resistor 21 can be easily made larger than the variation in the resistance value among the plurality of semiconductor devices 1 without increasing the area of ​​the built-in resistor 21. For example, when the variation in the resistance value is 0.1Ω to 20Ω, the resistance value of the built-in resistor 21 can be set to 2Ω to 40Ω with a small area. As a result, the area of ​​the region on the SiC epitaxial layer 28 that is sacrificed for the built-in resistor 21 can be reduced, so that the influence on the layout of other elements is reduced. In this case, the total resistance value of the resistance value of the gate electrode 19 and the resistance value of the built-in resistor 21 is preferably 4Ω to 50Ω.

[0070] Furthermore, the thickness of gate electrode 19 and built-in resistor 21 is preferably 2 μm or less. By making the thickness of built-in resistor 21 2 μm or less, the resistance value of the entire built-in resistor 21 can be easily made larger than the variation in resistance value among multiple semiconductor devices 1. Conversely, if built-in resistor 21 is too thick, its resistance value becomes too low, which is not preferable.

[0071] An interlayer film 36 is formed on the gate insulating film 35 so as to cover the gate electrode 19 and the built-in resistor 21. The interlayer film 36 is made of an insulating material such as silicon oxide, and has a thickness of, for example, 0.1 μm to 5 μm.

[0072] Moreover, the interlayer film 36 is formed so as to extend into a region (first region) on the gate insulating film 35 where the gate electrode 19 and the built-in resistor 21 are not arranged. This allows the distance (insulating film thickness T) between the SiC epitaxial layer 28 and the gate metal 44 to be increased in the region where the built-in resistor 21 is not arranged, thereby reducing the capacitance therebetween.

[0073] The pad side contact 22 and the cell side contact 23 are formed to penetrate this interlayer film 36. The pad side contact 22 and the cell side contact 23 are each made of a metal via formed integrally with the gate metal 44 and the gate finger 5 (pad peripheral portion 12), respectively.

[0074] The interlayer film 36 contains n + type source region 31 and p + A source contact 46 for making contact from the source metal 43 to the body contact region 31 is formed penetrating the body contact region 31. The source contact 46 is a metal via formed integrally with the source metal 43.

[0075] On the interlayer film 36, a gate metal 44, a gate finger 5 and a source metal 43 are formed at intervals from each other.

[0076] A passivation film 40 is formed on the interlayer film 36 so as to cover the gate metal 44, the gate fingers 5, and the source metal 43. The passivation film 40 has openings 41 and 42 that expose parts of the gate metal 44 and the source metal 43.

[0077] As described above, according to the semiconductor device 1, as shown in Figures 3a and 3b, the polysilicon resistor (built-in resistor 21) is interposed between the gate metal 44 and the gate finger 5 (pad peripheral portion 12). In other words, the built-in resistor 21 is interposed in the middle of the current path continuing from the outside to the multiple transistor cells 18.

[0078] By adjusting the resistance value of built-in resistor 21, the resistance value of built-in resistor 21 can be made dominant in the resistance value (gate resistance) which is the sum of the resistance value of gate electrode 19 and the resistance value of built-in resistor 21. Therefore, even when a plurality of semiconductor devices 1 having gate electrodes 19 with variations in resistance value are connected in parallel for use, by making the resistance value of built-in resistor 21 larger than the variations, it is possible to restrict the flow of current into the semiconductor device 1 having gate electrodes 19 with relatively low resistance values. As a result, it is possible to reduce the generation of noise during such use.

[0079] Moreover, the polysilicon constituting built-in resistor 21 is a material whose resistance value can be easily controlled by doping impurities or the like, and its processing has also been established by conventional semiconductor manufacturing technology. Therefore, when introducing built-in resistor 21, it is possible to avoid the structure of semiconductor device 1 itself and the module including it becoming complicated.

[0080] Like gate electrode 19, built-in resistor 21 may vary in size and thickness due to variations in processing accuracy (etching dimensions, etc.) during manufacturing of semiconductor device 1, but its processing dimensions are smaller than those of gate electrode 19. Therefore, variations in built-in resistor 21 rarely lead to noise generation.

[0081] In addition, since the built-in resistor 21 is connected to the gate metal 44 below the gate metal 44, it is possible to limit the inflow of the gate current at the entrance of the current path leading from the outside to the multiple transistor cells 18. This makes it possible to prevent an inrush current from flowing only to a specific transistor cell 18.

[0082] 2, for example, consider a case where built-in resistor 21 is formed in the middle of first finger 13 or second finger 14 of gate finger 5 as a detour for these fingers 13, 14. In this case, on the side closer to gate metal 44 than built-in resistor 21, an inrush current may flow from fingers 13, 14 to gate electrode 19 via gate contact 20 before reaching built-in resistor 21. In contrast, if the gate current can be limited at the entrance of the current path as in this embodiment, the variation in switching speed among multiple transistor cells 18 can be reduced.

[0083] Furthermore, the built-in resistors 21 are arranged symmetrically as shown in Fig. 2. This feature also makes it possible to reduce variations in switching speed among the multiple transistor cells 18.

[0084] As shown in FIG. 3a and FIG. 3b, the area of ​​the SiC epitaxial layer 28 facing the built-in resistor 21 is 1×10 19 cm -3 p with impurity concentration of - The p-type region 34 is a p-type region 34. Therefore, the dielectric breakdown of the gate insulating film 35 can be effectively suppressed. - Since the p-type region is less likely to accumulate carriers than the n-type region, the built-in resistor 21 and the p-type region, which face each other with the gate insulating film 35 interposed therebetween, - The capacitance between the mold region 34 can also be reduced.

[0085] 3a and 3b, the gate metal 44 and the built-in resistor 21 are connected by the pad-side contact 22 made of a metal via. Therefore, the resistance value contributed by the built-in resistor 21 in the current path continuing from the outside to the multiple transistor cells 18 can be easily adjusted by processing such as changing the position of the pad-side contact 22 along the surface of the SiC epitaxial layer 28 or changing the diameter of the via.

[0086] For example, as shown by the dashed line in FIG. 3b, by simply placing the pad side contact 37 closer to the pad peripheral area 12 than the pad side contact 22, the distance from the contact position for the built-in resistor 21 to the pad peripheral area 12 can be reduced by D 1 From D 2 3a, the resistance of the current path toward the built-in resistor 21 can be increased simply by making the via diameter smaller than that of the pad side contact 22, as in the case of the pad side contact 38 shown by the dashed line in FIG. 3a. Conversely, by making the via diameter larger, the resistance of the path can be decreased.

[0087] Moreover, in these processes, when forming the pad side contacts 22 (vias), it is only necessary to use a mask that matches the distance design and via diameter design, so that the manufacturing process can be prevented from becoming complicated.

[0088] Although the embodiment of the present invention has been described above, the present invention can be embodied in other forms.

[0089] For example, in the above embodiment, the transistor cells 18 are MOSFET cells with a planar gate structure, but the transistor cells 18 may be MOSFET cells with a trench gate structure as shown in Fig. 4. In this case, the gate electrode 19 is embedded in a gate trench 39 formed between each of the plurality of transistor cells 18 via a gate insulating film 35.

[0090] The transistor cell 18 may be an IGBT cell having a planar gate structure or a trench gate structure. + Instead of the type SiC substrate 27, + A type SiC substrate 27 may be used.

[0091] Furthermore, built-in resistor 21 does not need to be embedded in interlayer film 36 below gate metal 44. For example, polysilicon wiring connecting gate metal 44 and gate finger 5 may be formed on the surface of interlayer film 36 as the built-in resistor of the present invention.

[0092] Furthermore, instead of polysilicon, the material for built-in resistor 21 may be a material having a resistance value equal to or greater than that of gate metal 44 and gate finger 5 (for example, metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), or Cu (copper)). Even if built-in resistor 21 is made of metal, the distance between gate metal 44 and gate finger 5 can be made long, so that the total resistance value of gate electrode 19 and built-in resistor 21 can be made large.

[0093] Moreover, the built-in resistor 21 does not need to be formed below the gate metal 44 and may be formed below the gate finger 5, for example.

[0094] The built-in resistor 21 may be linear and extend along a portion of the periphery 24 of the gate metal 44 , or may be annular and extend along the entire periphery of the periphery 24 of the gate metal 44 .

[0095] It is also possible to adopt a configuration in which the conductivity type of each semiconductor portion of the above-described semiconductor device 1 is inverted. For example, in the semiconductor device 1, the p-type portion may be n-type, and the n-type portion may be p-type.

[0096] FIG. 5 is an electric circuit diagram showing an electric circuit of a module to which a semiconductor device according to one embodiment of the present invention is applied.

[0097] The module 100 includes a plurality of semiconductor devices (chips) 101-104, a drain terminal 105, a source terminal 106, and a gate terminal 107. Each of the semiconductor devices 101-104 is configured from the semiconductor device 1 shown in Figures 1-3. Each of the semiconductor devices 101-104 may be configured from the semiconductor device shown in Figure 4. The plurality of semiconductor devices 101-104 are connected in parallel.

[0098] Each of the semiconductor devices 101 to 104 includes a plurality of transistor cells 18 connected in parallel (see FIGS. 2, 3a, and 3b) and four built-in resistors 41 connected in parallel (see FIGS. 2, 3a, and 3b). In FIG. 5, the plurality of transistor cells 18 connected in parallel are represented by one transistor cell Tr, and the four built-in resistors 41 connected in parallel are represented by one resistor R.

[0099] A gate electrode of each of the semiconductor devices 101-104 is connected to a gate terminal 107 of the module 100 via a built-in resistor R built into the semiconductor device. A drain electrode of each of the semiconductor devices 101-104 is connected to a drain terminal 105 of the module 100. A source electrode of each of the semiconductor devices 101-104 is connected to a source terminal 106 of the module 100.

[0100] In this module 100, each of the semiconductor devices 101-104 has a built-in resistor R having a resistance value larger than the gate resistance in each of the semiconductor devices 101-104. Therefore, in this module 100, the structure of the module is simpler than when an external gate resistor having a resistance value larger than the gate resistance in each of the semiconductor devices 101-104 is provided in each of the semiconductor devices 101-104.

[0101] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited to these examples, and the scope of the present invention is limited only by the appended claims.

[0102] This application corresponds to Patent Application No. 2013-246474 filed with the Japan Patent Office on November 28, 2013, the entire disclosure of which is incorporated herein by reference.

[0103] Further features of the present invention can be extracted from the specification as follows:

[0104] "A1" SiC semiconductor layer, A plurality of transistor cells formed on a surface side of the SiC semiconductor layer, the transistor cells being on / off controlled by receiving a control voltage input to a control pad at a control electrode thereof; a built-in resistor that is disposed closer to the SiC semiconductor layer than the control pad, electrically connects the control pad and the control electrode, and reduces a variation in on-resistance values ​​of the plurality of transistor cells; a first wire region is selectively formed on a surface of the control pad, the first wire region being exposed from a surface insulating film formed on the outermost surface and to which a bonding wire is connected; the built-in resistor is selectively disposed in a region avoiding the first wire region in a plan view seen from a normal direction of the SiC semiconductor layer; a main electrode pad, which is connected to one main electrode of each of the transistor cells and is different from the control pad, is disposed above the transistor cells; a second wire region, exposed from the surface insulating film and to which a bonding wire is connected, is selectively formed on the surface of the main electrode pad.

[0105] This configuration includes a built-in resistor disposed closer to the SiC semiconductor layer than the control pad, electrically connecting the control pad and the control electrode, and reducing the variation in the on-resistance of the multiple transistor cells. By adjusting the resistance of the built-in resistor, the resistance of the built-in resistor can be made dominant in the total resistance (control resistance) of the control electrode and the built-in resistor. Therefore, even when multiple semiconductor devices having variation in the resistance of the control electrode are connected in parallel for use, the resistance of the built-in resistor can be made larger than the variation to limit the flow of current into the semiconductor device having a relatively low resistance of the control electrode. As a result, the generation of noise during use can be reduced.

[0106] "A2" The control pad is formed independently and surrounded by the surface insulating film, The semiconductor device according to "A1", wherein the built-in resistor is disposed in a region outside the first wire region below the control pad via an interlayer film.

[0107] This configuration makes it possible to restrict the flow of the control current below the control pad, i.e., at the entrance of the current path leading from the outside to the multiple cells. This makes it possible to prevent the inrush current from flowing only to a specific transistor cell. As a result, it is possible to reduce the variation in switching speed between the multiple transistor cells.

[0108] "A3" A portion of the built-in resistor is disposed in a region below the control pad; The semiconductor device according to "A2", wherein the interlayer film is embedded in a first region below the control pad in which the built-in resistor is not arranged.

[0109] "A4" further includes an insulating film disposed between the built-in resistor and the SiC semiconductor layer; The semiconductor device described in "A3", wherein in the first region, a film consisting of an extension of the insulating film is disposed between the interlayer film and the SiC semiconductor layer.

[0110] According to this configuration, in the first region where no built-in resistor is arranged, the distance (thickness of the insulating film) between the SiC semiconductor layer and the control pad can be increased, so that the capacitance between them can be reduced.

[0111] "A5" In the SiC semiconductor layer, in the region facing the built-in resistor across the insulating film, 19 cm -3 The semiconductor device according to "A4", in which an impurity region having the following concentration is selectively formed.

[0112] According to this configuration, the concentration of the impurity region facing the built-in resistor is 1×10 19 cm -3 In this case, the SiC semiconductor layer is an n-type SiC semiconductor layer, and the semiconductor layer has a thickness of 1×10 19 cm -3 The following p - It is preferable that the aryl group has a type region. - Since it is more difficult for carriers to accumulate in the p-type region than in the n-type region, the built-in resistor and the p-type region that face each other with the insulating film in between are - The capacitance between the mold area can also be reduced.

[0113] "A6" The portion of the built-in resistor is disposed below the peripheral edge of the control pad, The semiconductor device according to any one of "A1" to "A5", wherein the first wire region is formed in a central portion of the control pad surrounded by the peripheral portion.

[0114] [A7] The semiconductor device according to any one of [A2] to [A5], further comprising a contact via that penetrates the interlayer film and electrically connects the control pad and the built-in resistor.

[0115] According to this configuration, the resistance value contributed by the built-in resistor in the current path leading from the outside to the multiple transistor cells can be easily adjusted by processing to change the position of the contact via along the surface of the SiC semiconductor layer, processing to change the diameter of the via, etc. Moreover, these processing steps can be performed by simply using a mask that matches the distance design and via diameter design when forming the contact via, which prevents the manufacturing process from becoming complicated.

[0116] "A8" The semiconductor device according to any one of "A1" to "A7", wherein the built-in resistors are arranged symmetrically with respect to each other in a plan view seen from the normal direction of the SiC semiconductor layer.

[0117] According to this configuration, it is possible to prevent an inrush current from flowing only through a specific transistor cell, and therefore it is possible to reduce variations in switching speed among a plurality of transistor cells.

[0118] [A9] The semiconductor device according to any one of [A1] to [A8], wherein the control electrode is made of p-type polysilicon.

[0119] [A10] The semiconductor device according to [A9], wherein the control electrode contains B (boron) as a p-type impurity.

[0120] B (boron)-containing polysilicon has a higher resistivity than P (phosphorus)-containing polysilicon, which is generally used in Si semiconductor devices. Therefore, boron-containing polysilicon (built-in resistor) requires a smaller area than phosphorus-containing polysilicon to achieve the same resistance. Therefore, the area occupied by the built-in resistor on the SiC semiconductor layer can be reduced, allowing for more efficient use of space.

[0121] [A11] The semiconductor device according to any one of [A1] to [A10], wherein the resistance value of the built-in resistor is 2Ω to 40Ω.

[0122] [A12] The semiconductor device according to any one of [A1] to [A11], wherein the total resistance value of the control electrode and the resistance value of the built-in resistor is 4 Ω to 50 Ω.

[0123] [A13] The semiconductor device according to any one of [A1] to [A12], wherein the sheet resistance of the built-in resistor is 10 Ω / □ or more.

[0124] In practice, if the sheet resistance of the built-in resistor is 10 Ω / □ or more, the resistance value of the entire built-in resistor can be easily made larger than the variation in resistance value among multiple semiconductor devices without increasing the area of ​​the built-in resistor. As a result, the area of ​​the region on the SiC semiconductor layer that is sacrificed for the built-in resistor can be reduced, so that the impact on the layout of other elements is reduced.

[0125] [A14] The semiconductor device according to any one of [A1] to [A13], wherein the size of each of the built-in resistors in a plan view seen from a normal direction of the SiC semiconductor layer is 200 μm square or less.

[0126] In practice, if the size of each built-in resistor is 200 μm square or less, the area of ​​the region on the SiC semiconductor layer sacrificed for the built-in resistor can be reduced, resulting in space savings.

[0127] "A15" The semiconductor device according to any one of claims 1 to 14, wherein the built-in resistor has a thickness of 2 µm or less.

[0128] By making the thickness of the built-in resistor 2 μm or less, the resistance value of the entire built-in resistor can be easily made larger than the variation in resistance value between multiple semiconductor devices. Conversely, if the built-in resistor is too thick, its resistance value becomes too low, which is not preferable.

[0129] [A16] The semiconductor device further includes a finger that is disposed on the front side of the semiconductor device similarly to the control pad and extends from the control pad so as to divide the plurality of transistor cell regions into a plurality of regions; The semiconductor device according to any one of "A1" to "A15," wherein the built-in resistor electrically connects the control pad and the finger.

[0130] In this way, the features of the present invention can be effectively applied to devices in which fingers extend from a control pad.

[0131] "A17" The semiconductor device according to "A16", wherein the finger has a portion arranged to surround the periphery of the control pad.

[0132] The semiconductor device according to claim 16, wherein the fingers are made of metal wiring. By forming the fingers from metal wiring having a lower resistance than polysilicon, it is possible to supply a control current in a short time even to a cell located relatively far from the control pad.

[0133] [A19] The semiconductor device according to [A17], wherein the metal wiring is made of any one of Al, AlCu, and Cu.

[0134] When the metal wiring is made of Al, the finger forming process can be simplified because Al is easy to process. When the metal wiring is made of AlCu, the power cycle resistance can be improved compared to when the fingers are made of Al wiring. When the metal wiring is made of Cu, the resistivity can be reduced compared to when the fingers are made of Al wiring or AlCu wiring.

[0135] "A20" The transistor cell constitutes a MOSFET cell, the control pad is connected to a control electrode of the MOSFET cell; the main electrode pad is connected to a source electrode of the MOSFET cell; The semiconductor device according to any one of "A1" to "A19", further comprising a drain electrode formed on a back surface side of the SiC semiconductor layer.

[0136] "A21" The semiconductor device according to "A20", wherein the MOSFET cell includes a planar gate structure.

[0137] "A22" The semiconductor device according to "A20", wherein the MOSFET cell includes a trench gate structure.

[0138] "A23" The transistor cell constitutes an IGBT cell, the control pad is connected to a control electrode of the IGBT cell; the main electrode pad is connected to an emitter electrode of the IGBT cell; The semiconductor device according to any one of "A1" to "A19", further comprising a collector electrode formed on a back surface side of the SiC semiconductor layer.

[0139] [A24] The semiconductor device according to any one of [A1] to [A23], wherein the plurality of transistor cells are arranged in a lattice pattern.

[0140] "A25" semiconductor layer; a plurality of transistor cells formed on a surface side of the semiconductor layer, the transistor cells being turned on / off controlled by receiving a control voltage input to a control pad at a control electrode; a finger extending from the control pad so as to divide an area in which the plurality of transistor cells are formed into a plurality of areas and electrically connected to the control pad; a built-in resistor disposed closer to the semiconductor layer than the control pad and the finger, electrically connecting the control pad and the finger, and made of a material having a resistance value the same as but larger than that of the finger; a first wire region is selectively formed on a surface of the control pad, the first wire region being exposed from a surface insulating film formed on the outermost surface and to which a bonding wire is bonded; the built-in resistor is selectively disposed in a region avoiding the first wire region in a plan view seen from a normal direction of the semiconductor layer, a main electrode pad, which is connected to one main electrode of each of the transistor cells and is different from the control pad, is disposed above the transistor cells; a second wire region, exposed from the surface insulating film and to which a bonding wire is connected, is selectively formed on the surface of the main electrode pad.

[0141] "A26" The semiconductor device according to "A25", wherein the built-in resistor is made of metal.

[0142] [A27] A semiconductor module comprising a plurality of semiconductor devices according to any one of [A1] to [A26] connected in parallel. [Explanation of symbols]

[0143] 1 Semiconductor device 2. Active Area 4 Gate Pad 5 Gate Finger 7 Inner Cell Area 12 Pad Surroundings 13 First Finger 14 Second Finger 15 Main parts 16 Branch 18 Transistor Cell 19 Gate electrode 20 Gate Contact 21 Built-in resistor 22 Pad side contact 23 Cell side contact 24 Periphery 27 SiC substrate 28 SiC epitaxial layer 29 pages - Type Body Area 30n + Type Body Area 31 p + Mold body contact area 32 Channel Area 33 p + type area 34 p -type area 35 Gate insulating film 36 Interlayer Film 37 Pad side contact 38 Pad side contact 39 Gate Trench 44 Gate Metal

Claims

1. The gate metal, a plurality of gate fingers including the gate metal and a pad periphery spaced apart from each other, the gate fingers extending in different directions; a plurality of built-in resistors each located below the gate metal in a plan view and each extending across the gate metal and a periphery of the pad; the plurality of built-in resistors are positioned symmetrically with respect to a planar shape of the gate metal in a plan view and are positioned at approximately the same distance from each other from a center of gravity of the planar shape of the gate metal.

2. The plurality of built-in resistors includes two built-in resistors, 2 . The semiconductor device according to claim 1 , wherein the two built-in resistors are located on two opposite sides of the gate metal in a plan view.

3. The plurality of built-in resistors includes two built-in resistors, 2 . The semiconductor device according to claim 1 , wherein the two built-in resistors are located at two diagonally opposite corners of the gate metal in a plan view.

4. 4. The semiconductor device according to claim 1, wherein each of the plurality of built-in resistors has a quadrangular shape in a plan view.

5. 5. The semiconductor device according to claim 4, wherein each of said plurality of built-in resistors has a size of 200 [mu]m square or less.

6. a passivation film covering the gate metal and the gate fingers and having an opening exposing a portion of the gate metal as a gate pad; 6. The semiconductor device according to claim 1, wherein the passivation film covers an area above which the plurality of built-in resistors are located.

7. 7. The semiconductor device according to claim 6, wherein said passivation film has said openings between areas of said gate metal that overlap said plurality of built-in resistors in a plan view.

8. 8. The semiconductor device according to claim 1, wherein the thickness of the plurality of built-in resistors is 2 μm or less.

9. The semiconductor device according to any one of claims 1 to 8, wherein the gate metal and the gate finger are arranged on a semiconductor layer, and the gate metal and the gate finger face a p-type region formed in the semiconductor layer.

10. 10. The semiconductor device according to claim 9, wherein the p-type region is at the same potential as a source metal.

11. The semiconductor device according to any one of claims 1 to 8, wherein the gate metal and the gate finger are arranged on a semiconductor layer, and the gate metal and the gate finger face a p-type region formed in the semiconductor layer via the multiple built-in resistors.

12. The p-type region is 1×10 １９ cm ―３ 12. The semiconductor device according to claim 11, having the following impurity concentration:

13. A plurality of transistor cells are included.

13. The semiconductor device according to claim 1, wherein the plurality of transistor cells are MOSFET cells having a planar gate structure or MOSFET cells having a trench gate structure.

14. A semiconductor device according to any one of claims 1 to 13, a gate resistor connected to each of the gate metals of the plurality of semiconductor devices; a resistance value of a parallel circuit of the plurality of built-in resistors in each semiconductor device is greater than a gate resistance in the semiconductor device.

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