Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device of which surface smoothness of the upper surface of a wiring layer for external connection is improved.SOLUTION: The semiconductor device according to the present invention includes: a wire substrate with an insulating layer and a wire layer; and a semiconductor element having a first electrode, the semiconductor element being fixed to the wire substrate with the first electrode facing the wire substrate side. The wire layer includes: a first wire pattern arranged on the opposite side to the side where the semiconductor element is arranged across the insulating layer; and a first via wire filled in the first through-hole penetrating the first wire pattern and the insulating layer and exposing the first electrode, the first via wire electrically connecting the first wire pattern and the first electrode. The first via wire is formed of metal sintered material.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A semiconductor device in which a semiconductor element is mounted on a wiring board is known. When manufacturing such a semiconductor device, for example, a through hole is formed in the wiring board, and the semiconductor element is mounted on the wiring board so that the electrode of the semiconductor element is exposed in the through hole. Then, for example, a semi-additive method is used to fill the through hole with metal plating, which is then extended onto the wiring board to form a wiring layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-57771 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the method of filling a through hole with metal plating and then extending it onto a wiring board to form a wiring layer, the upper surface of the wiring layer formed over the through hole may not be flat, resulting in the formation of a recess.

[0005] For example, if a recess is formed on the top surface of a wiring layer for external connection, when other components are joined to the wiring layer with solder or the like, there is an increased risk of voids being generated in the solder or the like in the recess, reducing the reliability of the joint.

[0006] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor device in which the flatness of the upper surface of a wiring layer for external connection is improved. [Means for solving the problem]

[0007] This semiconductor device has a wiring board having an insulating layer and a wiring layer, and a semiconductor element having a first electrode and fixed to the wiring board with the first electrode facing the wiring board, wherein the wiring layer includes a first wiring pattern arranged on the opposite side of the insulating layer to the semiconductor element, and a first via wiring filled in a first through hole that penetrates the first wiring pattern and the insulating layer to expose the first electrode, electrically connecting the first wiring pattern and the first electrode, and the first via wiring is formed from a sintered metal material. Effect of the Invention

[0008] According to the disclosed technique, it is possible to provide a semiconductor device having an improved flatness of the upper surface of a wiring layer for external connection. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Diagram 2] 1A to 1C are views illustrating a manufacturing process of the semiconductor device according to the first embodiment; [Diagram 3] 5A to 5C are views illustrating the manufacturing process of the semiconductor device according to the first embodiment (part 2). [Figure 4] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a comparative example. [Diagram 5] 1 is a cross-sectional view illustrating a semiconductor device according to a first modified example of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated explanations may be omitted.

[0011] First embodiment [Semiconductor Devices] Fig. 1 is a cross-sectional view illustrating a semiconductor device according to the first embodiment. Referring to Fig. 1, the semiconductor device 1 has a lead frame 10, a semiconductor element 20, a wiring board 30, a bonding member 40, and a sealing resin 50. Although the present invention may have one or more semiconductor elements, the first embodiment will be described with reference to an example in which two semiconductor elements 20 are included.

[0012] In this embodiment, for convenience, the wiring board 30 side of the semiconductor device 1 is referred to as the upper side, and the lead frame 10 side is referred to as the lower side. Also, the surface of each part facing the wiring board 30 is referred to as the upper surface, and the surface facing the lead frame 10 is referred to as the lower surface. However, the semiconductor device 1 can be used upside down, or can be placed at any angle. Also, a planar view refers to viewing an object from the normal direction of the upper surface of the wiring board 30, and a planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the wiring board 30.

[0013] The lead frame 10 is formed in a flat plate shape. The lead frame 10 may have any planar shape and any size. In the example of FIG. 1, the planar shape of the lead frame 10 is rectangular. The material of the lead frame 10 may be, for example, copper (Cu), a copper alloy, or a 42 alloy. The thickness of the lead frame 10 may be, for example, 100 μm or more and 250 μm or less.

[0014] The semiconductor device 1 may include a wiring board instead of the lead frame 10. Examples of the wiring board include a direct bonding of copper (DBC) board and an active metal brazing (AMB) board.

[0015] Each semiconductor element 20 is bonded to the upper surface of the lead frame 10 via a conductive bonding member 40. The bonding member 40 may be made of, for example, a metal sintered material. The metal sintered material may be, for example, a sintered material (silver sintered material) mainly composed of silver (Ag) particles or a sintered material (copper sintered material) mainly composed of copper particles. The bonding member 40 may be made of, for example, a conductive paste such as solder or silver paste, or a metal brazing material. The bonding member 40 may have a thickness of, for example, about 20 μm to 60 μm.

[0016] Each of the semiconductor elements 20 is, for example, a power semiconductor element. Each of the semiconductor elements 20 has a control electrode and is an element that is switched by a voltage applied to the control electrode. Examples of the semiconductor elements 20 include an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode, etc.

[0017] In the first embodiment, the semiconductor element 20 is a MOSFET. The planar shape of the semiconductor element 20 can be any shape and any size. The planar shape of the semiconductor element 20 is, for example, rectangular. The thickness of the semiconductor element 20 can be, for example, about 50 μm to 600 μm. The thermal expansion coefficient of the semiconductor element 20 can be, for example, about 3 ppm / °C to 6 ppm / °C.

[0018] The semiconductor element 20 has a semiconductor substrate 21, a first electrode 22, a second electrode 23, and a third electrode 24. The second electrode 23 is a control electrode of the semiconductor element 20. The semiconductor substrate 21 is made of, for example, silicon (Si) or silicon carbide (SiC).

[0019] Each semiconductor substrate 21 includes a first electrode 22. Each semiconductor element 20 may include a second electrode 23 arranged on the same side as the first electrode 22 and spaced apart from the first electrode 22. The first electrode 22 and the second electrode 23 may be arranged, for example, on the upper surface of each semiconductor substrate 21. The first electrode 22 is, for example, a source electrode of a MOSFET. The second electrode 23 is, for example, a gate electrode of a MOSFET.

[0020] Each semiconductor element 20 may include a third electrode 24 arranged on the opposite side to the first electrode 22. The third electrode 24 may be arranged, for example, on the lower surface of each semiconductor substrate 21. The third electrode 24 of each semiconductor substrate 21 is electrically connected to the lead frame 10, which is a metal member, via a bonding member 40. The third electrode 24 is, for example, a drain electrode of a MOSFET.

[0021] In addition, when the semiconductor device 1 includes a wiring board instead of the lead frame 10, the third electrodes 24 of each semiconductor substrate 21 are electrically connected to a metal member (such as a wiring layer) on the wiring board via a bonding member 40.

[0022] The first electrode 22, the second electrode 23, and the third electrode 24 may be made of a metal such as aluminum (Al) or copper (Cu), or an alloy containing at least one metal selected from these metals. If necessary, the above-mentioned surface treatment layer may be formed on the surfaces of the first electrode 22, the second electrode 23, and the third electrode 24.

[0023] The wiring board 30 is disposed on the semiconductor element 20. In other words, the semiconductor element 20 is fixed to the wiring board 30 with the first electrodes 22 facing the wiring board 30 side.

[0024] The wiring board 30 is formed in a flat plate shape. The wiring board 30 can have any planar shape and any size. In the example of FIG. 1, the planar shape of the wiring board 30 is rectangular. The thickness of the wiring board 30 can be, for example, about 200 to 400 μm. The thermal expansion coefficient of the wiring board 30 can be, for example, about 20 ppm / ° C. to 25 ppm / ° C. The wiring board 30 can be provided so that, for example, the entire wiring board 30 overlaps with the lead frame 10 in a planar view.

[0025] The wiring board 30 includes an insulating layer 31, an adhesive layer 32, and a wiring layer 33. The insulating layer 31 is adhered to the semiconductor element 20 by the adhesive layer 32. The insulating layer 31 may be made of an insulating resin such as a polyimide resin or a polyester resin. The insulating layer 31 may have a thickness of, for example, about 30 μm to 50 μm.

[0026] The adhesive layer 32 is formed on the lower surface of the insulating layer 31. The thickness of the adhesive layer 32 can be, for example, about 20 μm to 40 μm. For example, an epoxy-based, polyimide-based, or silicone-based adhesive can be used as the adhesive layer 32. The adhesive layer 32 may be provided so as to incorporate, for example, a part of the semiconductor element 20. In other words, a part of the semiconductor element 20 may be embedded in the adhesive layer 32. For example, the outer peripheral edges of the first electrode 22 and the second electrode 23 of the semiconductor element 20 may be embedded in the adhesive layer 32. In addition, the upper part of the side surface of the semiconductor element 20 may be covered with the adhesive layer 32.

[0027] The wiring layer 33 is formed on one side of the insulating layer 31. The wiring layer 33 is a wiring layer for external connection. The wiring layer 33 includes a first wiring pattern 331 and a first via wiring 333 disposed on the upper surface of the insulating layer 31. The first wiring pattern 331 is disposed on the opposite side to the semiconductor element 20 with the insulating layer 31 in between.

[0028] The first via wiring 333 is disposed in a first through hole 30x that continuously penetrates the first wiring pattern 331, the insulating layer 31, and the adhesive layer 32 and exposes at least a portion of the upper surface of the first electrode 22. The first via wiring 333 is filled in the first through hole 30x and electrically connects the first wiring pattern 331 and the first electrode 22. The upper surface of the first via wiring 333 can be flush with the upper surface of the first wiring pattern 331, for example.

[0029] The wiring layer 33 may include a second wiring pattern 332 disposed on the same side as the first wiring pattern 331 and spaced apart from the first wiring pattern 331. The wiring layer 33 may also include a second via wiring 334.

[0030] The second via wiring 334 is disposed in a second through hole 30y that continuously penetrates the second wiring pattern 332, the insulating layer 31, and the adhesive layer 32 and exposes at least a portion of the upper surface of the second electrode 23. The second via wiring 334 is filled in the second through hole 30y and electrically connects the second wiring pattern 332 and the second electrode 23. The upper surface of the second via wiring 334 can be flush with the upper surface of the second wiring pattern 332, for example.

[0031] The first wiring pattern 331 and the first via wiring 333 connect the first electrodes 22 of the respective semiconductor elements 20 to each other. The first electrodes 22 of the respective semiconductor elements 20 can be connected to each other by, for example, the first wiring pattern 331 that does not appear in the cross section of FIG. 1. The second wiring pattern 332 and the second via wiring 334 connect the second electrodes 23 of the respective semiconductor elements 20 to each other. The lead frame 10 connects the third electrodes 24 of the respective semiconductor elements 20 to each other. Thus, in the example of FIG. 1, the respective semiconductor elements 20 are connected in parallel to each other.

[0032] The first wiring pattern 331 and the second wiring pattern 332 may be made of, for example, copper or a copper alloy. If necessary, the above-mentioned surface treatment layer may be formed on the upper surface of the wiring layer 33. The thermal expansion coefficient of the wiring layer 33 may be, for example, about 15 ppm / °C to 18 ppm / °C. The thickness of the wiring layer 33 may be, for example, about 50 μm to 200 μm.

[0033] The first via wiring 333 and the second via wiring 334 can be formed, for example, from a metal sintered material. For example, a sintered material (silver sintered material) mainly composed of silver (Ag) particles or a sintered material (copper sintered material) mainly composed of copper particles can be used as the metal sintered material. The first via wiring 333 and the second via wiring 334 are, for example, circular in plan view. The diameters of the first via wiring 333 and the second via wiring 334 can be appropriately determined according to the size of the electrodes to be connected.

[0034] The sealing resin 50 seals the semiconductor element 20 provided between the lead frame 10 and the wiring board 30. The material of the sealing resin 50 may be, for example, a non-photosensitive insulating resin mainly composed of a thermosetting resin. Specifically, the material of the sealing resin 50 may be, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which a filler such as silica or alumina is mixed into these resins. The sealing resin 50 may be, for example, a mold resin. The thermal expansion coefficient of the sealing resin 50 may be, for example, about 5 ppm / °C to 18 ppm / °C.

[0035] [Method of manufacturing semiconductor device] Next, a method for manufacturing the semiconductor device 1 will be described. For ease of explanation, the parts that will ultimately become the components of the semiconductor device 1 will be denoted by the reference numerals of the final components. Figures 2 and 3 are diagrams illustrating the manufacturing process of the semiconductor device according to the first embodiment.

[0036] 2(a), a wiring board including an insulating layer and a first wiring pattern disposed on the insulating layer is prepared. In the present embodiment, as an example, a wiring board 30 having an insulating layer 31, an adhesive layer 32, and a wiring layer 33 (a first wiring pattern 331 and a second wiring pattern 332) is prepared. Specifically, for example, a member on which a wiring layer 33 of a predetermined pattern is formed on the upper surface of the insulating layer 31 is purchased, and an adhesive layer 32 is formed on the lower surface of the insulating layer 31. Instead of purchasing a member, the wiring layer 33 may be formed on the upper surface of the insulating layer 31 using various wiring forming methods such as a subtractive method or a semi-additive method.

[0037] Next, in the step shown in FIG. 2(b), a first through hole 30x is formed so as to continuously penetrate the first wiring pattern 331, the insulating layer 31, and the adhesive layer 32. A second through hole 30y is formed so as to continuously penetrate the second wiring pattern 332, the insulating layer 31, and the adhesive layer 32. The first through hole 30x and the second through hole 30y can be formed, for example, by press processing. The first through hole 30x and the second through hole 30y may be formed, for example, by a method combining etching and laser processing. In this case, first, the first wiring pattern 331 at the position where the first through hole 30x is to be formed and the second wiring pattern 332 at the position where the second through hole 30y is to be formed are removed by etching to expose the upper surface of the insulating layer 31. Thereafter, the upper surface of the insulating layer 31 exposed by etching is irradiated with laser light to penetrate the insulating layer 31 and form the first through hole 30x and the second through hole 30y.

[0038] 2(c), a semiconductor element 20 including a first electrode 22, a second electrode 23, and a third electrode 24 is prepared. Then, the semiconductor element 20 is fixed by an adhesive layer 32 so that the first electrode 22 is exposed in the first through hole 30x and the second electrode 23 is exposed in the second through hole 30y on the opposite side to the first wiring pattern 331 across the insulating layer 31 of the wiring board 30.

[0039] Next, in the step shown in FIG. 2(d), the first through hole 30x and the second through hole 30y are filled with a paste-like metal sintering material that becomes the first via wiring 333 and the second via wiring 334 when sintered. Specifically, for example, the paste-like sintering material (sintering paste) can be applied to the first through hole 30x and the second through hole 30y by a printing method or a dispenser method. As the sintering paste, for example, a silver sintering paste in which silver particles are dispersed in an organic solvent can be used. As the printing method, for example, a screen printing method or a stencil printing method can be used.

[0040] 2(d) is then sandwiched between parallel plates from above and below and pressed, so that the upper surface of the paste-like first via wiring 333 can be made flush with the upper surface of the first wiring pattern 331. Also, the upper surface of the second via wiring 334 can be made flush with the upper surface of the paste-like second wiring pattern 332.

[0041] Next, in the step shown in FIG. 3(a), the lead frame 10 and the semiconductor element 20 are bonded. First, a bonding member 40 is formed on the upper surface of the lead frame 10 at a position where the semiconductor element 20 is to be mounted. The bonding member 40 can be formed, for example, by applying a paste-like sintering material (sintering paste) by a printing method or a dispenser method. As the sintering paste, for example, a silver sintering paste in which silver particles are dispersed in an organic solvent can be used. As the printing method, for example, a screen printing method or a stencil printing method can be used.

[0042] Next, the semiconductor element 20 fixed to the wiring board 30 is placed on the upper surface of each of the bonding members 40. Specifically, the third electrode 24 formed on the lower surface of the semiconductor element 20 is placed on the lead frame 10, which is a metal member, with the paste-like bonding member 40 sandwiched therebetween. Next, the paste-like first via wiring 333 and second via wiring 334 and the paste-like bonding member 40 are sintered to form the first via wiring 333 and second via wiring 334 and the bonding member 40.

[0043] As a result, the first wiring pattern 331 and the first via wiring 333, and the second wiring pattern 332 and the second via wiring 334 form a wiring layer 33 for external connection. The first via wiring 333 electrically connects the first wiring pattern 331 and the first electrode 22. The second via wiring 334 electrically connects the second wiring pattern 332 and the second electrode 23. The bonding member 40 electrically connects the third electrode 24 and the lead frame 10.

[0044] In this manner, by simultaneously performing sintering of the paste-like first via wiring 333 and the second via wiring 334 and the paste-like joining member 40, it is possible to shorten the manufacturing process.

[0045] The sintering of the paste-like first via wiring 333 and the second via wiring 334 and the sintering of the paste-like joining member 40 may be performed in separate steps. That is, the paste-like first via wiring 333 and the second via wiring 334 may be sintered in the step shown in Fig. 2(d), and the paste-like joining member 40 may be sintered in the step shown in Fig. 3(a). When the paste-like first via wiring 333 and the second via wiring 334 are sintered in the step shown in Fig. 2(d), the structure shown in Fig. 2(d) may be shipped as a semiconductor device product.

[0046] 3(b), a sealing resin 50 is formed to seal the semiconductor element 20 provided between the lead frame 10 and the wiring board 30. The sealing resin 50 can be formed, for example, so as to expose the upper surface of the wiring layer 33 and the lower surface of the lead frame 10 and cover the rest. The sealing resin 50 can be formed, for example, by a method such as a transfer molding method, a compression molding method, or an injection molding method. Through the above steps, the semiconductor device 1 is completed.

[0047] Comparative Example 4A and 4B are diagrams illustrating a manufacturing process of a semiconductor device according to a comparative example. First, in the process shown in FIG. 4A, a laminate of an insulating layer 31 and an adhesive layer 32 is prepared, and a first through hole 30x and a second through hole 30y penetrating the insulating layer 31 and the adhesive layer 32 are formed. Then, a semiconductor element 20 is bonded to the lower side of the adhesive layer 32. At this time, the semiconductor element 20 is positioned so that at least a part of the upper surface of the first electrode 22 is exposed in the first through hole 30x and at least a part of the upper surface of the second electrode 23 is exposed in the second through hole 30y.

[0048] 4(b), a first wiring pattern 331 and a first via wiring 333, as well as a second wiring pattern 332 and a second via wiring 334 are formed. Specifically, a seed layer is formed on the surface of the insulating layer 31 including the inner walls of the first through hole 30x and the second through hole 30y, and on the surfaces of the first electrode 22 and the second electrode 23 exposed in the first through hole 30x and the second through hole 30y, for example, by electroless plating or sputtering. The seed layer is, for example, a copper layer. A laminated film in which a copper layer is laminated on a titanium layer may be used as the seed layer.

[0049] Next, a plating resist pattern having openings corresponding to the shapes of the first wiring pattern 331 and the second wiring pattern 332 is formed on the seed layer. Next, an electrolytic plating layer is deposited on the seed layer exposed in the openings of the plating resist pattern by electrolytic plating of copper with power supplied from the seed layer. Next, the plating resist pattern is removed using a plating resist stripper. Next, etching is performed using the electrolytic plating layer as a mask to remove the seed layer exposed from the electrolytic plating layer.

[0050] This completes the first wiring pattern 331 and the second wiring pattern 332, and the first via wiring 333 and the second via wiring 334, each having a structure in which an electrolytic plating layer is laminated on a seed layer. The first wiring pattern 331 and the second wiring pattern 332 are integrally formed with the first via wiring 333 and the second via wiring 334. At this time, since it is difficult to sufficiently fill the first via wiring 333 and the second via wiring 334 by the electrolytic plating method, a recess 33x is formed on the upper surface of the first wiring pattern 331 located above the first through hole 30x and the second wiring pattern 332 located above the second through hole 30y.

[0051] If the recesses 33x are formed, there is an increased possibility that voids will occur in the solder in the recesses 33x when, for example, a member such as a bus bar is joined with solder to the first wiring pattern 331 or the second wiring pattern 332. If voids occur in the solder, the joining reliability between the first wiring pattern 331 and the second wiring pattern 332 and the members joined thereto will decrease.

[0052] In contrast, in the semiconductor device 1, the first via wiring 333 and the second via wiring 334 are not formed by electrolytic plating of copper or the like, but are formed by a printing method or the like using a paste-like sintering material, and then sintered. With this method, no recesses are formed on the upper surfaces of the first via wiring 333 and the second via wiring 334, so that the flatness of the upper surface of the wiring layer 33 for external connection can be improved.

[0053] Therefore, there is a low possibility that voids will be generated in the solder when a member such as a bus bar is joined with solder to the first wiring pattern 331 and the first via wiring 333, or the second wiring pattern 332 and the second via wiring 334. This can improve the joining reliability between the wiring layer 33 and the member joined thereto.

[0054] Furthermore, the first via wiring 333 and the second via wiring 334 formed from the sintered material are directly connected to the semiconductor element 20, which is a heat generating body. The via wiring formed from the sintered material has a higher thermal conductivity than the wiring pattern and via wiring formed from copper, and can improve the heat dissipation performance of the semiconductor device 1. The thermal conductivity of copper is approximately 398 W / m·K, and the thermal conductivity when the sintered material is silver is approximately 420 W / m·K.

[0055] In addition, the first via wiring 333 and the second via wiring 334 formed from the sintered material have a lower elastic modulus than copper, and therefore can relax stress more than via wirings formed from copper. For example, the elastic modulus of copper is about 60 to 150 GPa, while the elastic modulus of the sintered silver material is about 10 to 90 GPa.

[0056] Modification of the First Embodiment In the modified example of the first embodiment, an example having a plurality of via wirings connected to one electrode is shown. Note that in the modified example of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0057] 5 is a cross-sectional view illustrating a semiconductor device according to Modification 1 of the first embodiment. Referring to Fig. 5, the semiconductor device 1A differs from the semiconductor device 1 in that a plurality of first via wirings 333 are connected to one first electrode 22.

[0058] Each of the first via wirings 333 has the same volume. Also, each of the first via wirings 333 and the second via wirings 334 has the same volume. That is, each of the first through holes 30x and the second through holes 30y has the same volume. Here, "having the same volume" means that the volumes are substantially the same, and manufacturing variations are allowed.

[0059] As also shown in Figure 5, the first via wiring 333 and the second via wiring 334 have approximately constant widths when viewed in cross-section, regardless of their position in the thickness direction; that is, the cross-sectional areas of the first via wiring 333 and the second via wiring 334 are the same regardless of their position in the thickness direction.

[0060] In the semiconductor device 1A, the first via wiring 333 and the second via wiring 334 are not formed by electrolytic plating of copper or the like, but are formed by a printing method or the like using a paste-like sintering material and then sintered, as in the semiconductor device 1. As a result, the same effects as those of the semiconductor device 1 are achieved.

[0061] In addition, in the semiconductor device 1A, since the first through holes 30x and the second through holes 30y have the same volume, when the paste-like sintering material is filled into the first through holes 30x and the second through holes 30y, the filling degree is unlikely to vary. Therefore, the upper surfaces of the first via wiring 333 and the second via wiring 334 can be easily flattened.

[0062] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0063] 1,1A Semiconductor Device 10 Lead frame 20 Semiconductor elements 21 Semiconductor substrate 22 1st electrode 23 2nd electrode 24 3rd electrode 30 Wiring board 30x 1st through hole 30y 2nd through hole 31 Insulating layer 32 Adhesive layer 33 Wiring layer 40 Joint materials 50 Sealing resin 331 First wiring pattern 332 Second wiring pattern 333 First via wiring 334 2nd via wiring

Claims

1. A wiring board including an insulating layer and a wiring layer; a semiconductor element including a first electrode and fixed to the wiring board with the first electrode facing the wiring board; The wiring layer is a first wiring pattern disposed on the opposite side of the insulating layer from the semiconductor element; a first via wiring that is filled in a first through hole that penetrates the first wiring pattern and the insulating layer to expose the first electrode, and electrically connects the first wiring pattern and the first electrode; The first via wiring is made of a sintered metal material.

2. The semiconductor device according to claim 1 , wherein an upper surface of said first wiring pattern and an upper surface of said first via wiring are flush with each other.

3. the semiconductor element includes a second electrode disposed on the same side as the first electrode and spaced apart from the first electrode; The wiring layer is a second wiring pattern disposed on the same side as the first wiring pattern and spaced apart from the first wiring pattern; a second via wiring that is filled in a second through hole that penetrates the second wiring pattern and the insulating layer to expose the second electrode, and electrically connects the second wiring pattern and the second electrode; The semiconductor device according to claim 1 , wherein the second via wiring is made of a sintered metal material.

4. The semiconductor device according to claim 3 , wherein an upper surface of the second wiring pattern and an upper surface of the second via wiring are flush with each other.

5. the wiring layer includes a plurality of the first via wirings connected to one of the first electrodes; The semiconductor device according to claim 3 , wherein each of the first via wirings and the second via wirings has the same volume.

6. The semiconductor device according to claim 1 , wherein the sintered material has a thermal conductivity higher than that of the first wiring pattern.

7. the semiconductor element includes a third electrode disposed on an opposite side to the first electrode; The semiconductor device according to claim 1 , wherein the third electrode is electrically connected to a metal member via a bonding member.

8. The semiconductor device according to claim 7 , wherein the joining member is made of a sintered metal material.

9. preparing a wiring substrate including an insulating layer and a first wiring pattern disposed on the insulating layer; forming a first through hole penetrating the first wiring pattern and the insulating layer; preparing a semiconductor element having a first electrode, and fixing the semiconductor element on the opposite side of the insulating layer of the wiring board from the first wiring pattern such that the first electrode is exposed in the first through hole; filling the first through holes with a first sintering material, which is a paste-like metal; sintering the first sintering material to form a first via wiring, and forming a wiring layer by the first wiring pattern and the first via wiring.

10. the semiconductor element has a third electrode disposed on an opposite side to the first electrode; disposing the third electrode on a metal member with a second sintering material of a paste metal sandwiched therebetween; The method further includes a step of sintering the second sintering material to form a joining member, and electrically connecting the third electrode and the metal member by the joining member, The method for manufacturing a semiconductor device according to claim 9 , wherein the first sintering material and the second sintering material are sintered simultaneously.

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