Semiconductor device

Abstract

To provide a new semiconductor device or a semiconductor device the area of which is reducible, or a semiconductor device having high versatility.SOLUTION: Provided is a semiconductor device comprising a pixel unit having first to fourth pixels, first and second switches provided outside of the first to fourth pixels, and first wiring provided outside of the first to fourth pixels, the first and second pixels being electrically connected to second wiring, the third and fourth pixels being electrically connected to third wiring, a first terminal of the first switch being electrically connected to the first wiring, a second terminal of the first switch being electrically connected to the second wiring, a first terminal of the second switch being electrically connected to the first wiring, a second terminal of the second switch being electrically connected to the third wiring.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, an imaging device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Another embodiment of the present invention relates to a semiconductor device, a display device, , a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof do. [Background technology]

[0003] A light detection circuit (also called a light sensor) that can generate data according to the illuminance of incident light. Technological development of optical detection devices using NMR is underway.

[0004] An example of a light detection device is an image sensor. Image sensors include CCDs. (Charge Coupled Device) image sensors and CMOS (Compact elementary Metal Oxide Semiconductor) image CMOS image sensors are used as imaging elements in digital cameras and mobile phones. Recently, with the trend towards higher resolution imaging and smaller mobile devices, Due to the need to reduce power consumption, the pixels of CMOS image sensors are becoming increasingly smaller.

[0005] In Patent Document 1, in order to reduce the area of ​​a pixel, a transistor is shared between adjacent pixels. An imaging device having such a configuration is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 11-126895 Summary of the Invention [Problem to be solved by the invention]

[0007] In an image sensor, when multiple pixels share elements such as transistors, However, since the shared element is provided within the pixel region, it occupies a certain area of ​​the pixel region. Therefore, by sharing an element among multiple pixels in the pixel area, There is a limit to how much the area of ​​the pixel region can be reduced.

[0008] In addition, in Patent Document 1, the amplifier and the reset transistor are connected to the same power supply line. Therefore, the voltage of the power supply for amplification and the power supply for reset can be set separately. On the other hand, the power supply line for amplification and the power supply line for resetting are If these are separate wirings, it will be necessary to secure space for two power supply lines within the pixel. This leads to an increase in pixel area and a decrease in aperture ratio.

[0009] An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a semiconductor device whose area can be reduced. Another object of the present invention is to provide a semiconductor device having high versatility. Another object of the present invention is to provide a semiconductor device capable of imaging with high accuracy. Another object of the present invention is to provide a semiconductor device capable of reducing power consumption. An object of the present invention is to provide a semiconductor device capable of high-speed imaging.

[0010] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems. It is sufficient if the invention can solve one of the problems. In addition, the description of the problem above does not necessarily mean that there are other problems. Problems other than these will be obvious from the description, drawings, claims, etc. It is clear that the specification, drawings, claims, etc. do not reveal any other problems. It is possible to extract [Means for solving the problem]

[0011] A semiconductor device according to one embodiment of the present invention includes a pixel portion having first to fourth pixels, A first switch and a second switch are provided outside the fourth pixel, and a second switch is provided outside the first to fourth pixels. a first wiring provided on the first pixel and a second pixel electrically connected to the second wiring. the third pixel and the fourth pixel are electrically connected to the third wiring, and the first switch The first terminal is electrically connected to the first wiring, and the second terminal of the first switch is electrically connected to the second wiring. a first terminal of the second switch electrically connected to the first wiring, and a second terminal of the second switch electrically connected to the first wiring. The second terminal of the second switch is a semiconductor device electrically connected to the third wiring.

[0012] A semiconductor device according to one embodiment of the present invention includes a pixel portion having first to fourth pixels; First and second switches provided outside the first to fourth pixels, and a first wiring provided externally, and the first pixel and the second pixel are electrically connected to the second wiring. the third pixel and the fourth pixel are electrically connected to the third wiring, and the first switch A first terminal of the first switch is electrically connected to the first wiring, and a second terminal of the first switch is electrically connected to the second wiring. a first terminal of the second switch electrically connected to the first wiring; The second terminal of the second switch is electrically connected to the third wiring, and the first to fourth pixels A first step of resetting the first switch and turning the first switch on after the first step. The potential of the first wiring is supplied to the second wiring, and an electric signal is output from the first pixel and the second pixel. A second step of reading out and resetting the first to fourth pixels after the second step. After the third step, the second switch is turned on, and the first wiring A fourth switch supplies a potential to the third wiring and reads out electrical signals from the third pixel and the fourth pixel. and a semiconductor device having a step.

[0013] Furthermore, in the semiconductor device according to one aspect of the present invention, a reset potential is supplied to the first to fourth pixels. A fourth wiring having a function of supplying a potential higher than that of the fourth wiring is provided to the first wiring. It may be possible.

[0014] Furthermore, in the semiconductor device according to one embodiment of the present invention, the first to fourth pixels include a photoelectric conversion The photoelectric conversion element is electrically connected to the transistor. The transistor may have an oxide semiconductor in a channel formation region.

[0015] Furthermore, in the semiconductor device according to one aspect of the present invention, the first switch is a first transistor. the second switch is constituted by a second transistor, and the first switch is constituted by a The first to fourth pixels each have a photoelectric conversion element and a third transistor, and the photoelectric conversion element is a third The first transistor and the second transistor are electrically connected to each other. a first transistor having a single crystal semiconductor in a channel formation region, and a second transistor having an oxide semiconductor in a channel formation region. a third transistor is stacked on the first transistor and the second transistor; It may be possible.

[0016] Furthermore, in the semiconductor device according to one embodiment of the present invention, the photoelectric conversion element includes a first electrode and A second electrode and a photoelectric conversion layer between the first electrode and the second electrode, the photoelectric conversion layer being a cell. The present invention may also include

[0017] Further, an imaging device according to one aspect of the present invention includes a light detection unit having the semiconductor device described above, and a light detection a data processing unit having a function of generating image data based on a signal from the .

[0018] Further, an electronic device according to one embodiment of the present invention includes the semiconductor device or the imaging device, and a lens. , a display unit, operation keys, or a shutter button. Effect of the Invention

[0019] According to one embodiment of the present invention, a novel semiconductor device can be provided. According to the aspect of the present invention, a semiconductor device capable of reducing the area can be provided. According to one embodiment of the present invention, a semiconductor device having high versatility can be provided. In this way, a semiconductor device capable of imaging with high accuracy can be provided. According to one embodiment, a semiconductor device capable of reducing power consumption can be provided. According to one embodiment of the present invention, a semiconductor device capable of high-speed imaging can be provided.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0021] [Figure 1] 1A to 1C illustrate an example of the structure of a semiconductor device. [Diagram 2] FIG. 1 is a circuit diagram illustrating an example of a structure of a semiconductor device. [Diagram 3] FIG. 1 is a circuit diagram illustrating an example of a structure of a semiconductor device. [Figure 4] Timing chart. [Diagram 5] FIG. 2 illustrates an example of the configuration of a pixel. [Figure 6] FIG. 2 is a circuit diagram illustrating an example of the configuration of a pixel. [Figure 7] FIG. 2 is a circuit diagram illustrating an example of the configuration of a pixel. [Figure 8] FIG. 2 is a circuit diagram illustrating an example of the configuration of a pixel. [Figure 9] FIG. 2 is a circuit diagram illustrating an example of the configuration of a pixel portion. [Figure 10] FIG. 1 illustrates an example of the configuration of an imaging apparatus. [Figure 11] 1A to 1C are diagrams illustrating an example of a cross-sectional structure of a semiconductor device. [Figure 12] 1A to 1C are diagrams illustrating an example of a cross-sectional structure of a semiconductor device. [Figure 13] 1A to 1C are diagrams illustrating an example of a cross-sectional structure of a semiconductor device. [Figure 14] FIG. 1 illustrates an example of the configuration of an imaging apparatus. [Figure 15] FIG. 2 illustrates an example of the configuration of a pixel. [Figure 16] 1A to 1C illustrate an example of the structure of a transistor. [Figure 17] 1A to 1C illustrate an example of the structure of a transistor. [Figure 18] 1A to 1C illustrate an example of the structure of a transistor. [Figure 19] 1A to 1C illustrate an example of the structure of a transistor. [Figure 20] 1A to 1C illustrate an example of the structure of a transistor. [Figure 21] 1A to 1C illustrate an example of the structure of a transistor. [Figure 22] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the above embodiment, and the present invention is not limited to the above embodiment without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that various modifications may be made to the form and details of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] In addition to the imaging device, one aspect of the present invention is a radio frequency (RF) tag. This category includes any device that includes a display, a display device, or an integrated circuit. The present invention relates to a liquid crystal display device, a light emitting device having a light emitting element, typically an organic light emitting element, in each pixel, an electronic Paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emissio Display devices having integrated circuits, such as a 3D display, are included in this category.

[0024] In describing the configuration of the invention using the drawings, the same reference numerals will be used in different drawings. But it is sometimes used in common.

[0025] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or text. Any connections other than those shown in the drawings or text are also considered to be described in the drawings or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0026] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0027] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state), allowing current to flow or not. The switch has the function of controlling whether or not the current flows through the circuit. When X and Y are electrically connected, This includes cases where the

[0028] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage source, current source, switching circuit, amplifier circuit (circuit that can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits One or more circuits (e.g., a circuit, a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if there is another circuit between X and Y, the signal output from X will be If the information is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are two cases: when X and Y are directly connected, and when X and Y are is electrically connected.

[0029] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0030] In addition, in the drawings, independent components are shown as being electrically connected to each other. Even in such cases, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrical functions of both components are combined. Effective connection means that one conductive film has the functions of multiple components. are also included in that category.

[0031] (Embodiment 1) In this embodiment, a structure example of a semiconductor device according to one embodiment of the present invention will be described.

[0032] <Configuration Example of Semiconductor Device 10> FIG. 1 shows a configuration example of a semiconductor device 10 according to one embodiment of the present invention. The semiconductor device 10 includes a pixel section 20, a circuit 30, and a circuit 40. The circuit has a wiring VIN and a plurality of switches S.

[0033] The pixel section 20 has a plurality of pixels 21. Here, the pixel section 20 has n rows and m columns (n ​​and m are independent of each other). In the example shown, a pixel number (a natural number) of pixels 21 (pixels 21[1,1] to [n,m]) is provided. The element 21 has a function of converting the irradiated light into an electrical signal (hereinafter, also referred to as an optical data signal). Therefore, the pixel 21 functions as a photodetection circuit in the imaging device. In the pixel 21, light incident on a photoelectric conversion element is converted into an electric signal.

[0034] In addition, each of the pixels 21 is connected to a line SE and a line OUT. The pixels 21 (pixels 21[i,1] to [i,m]) in the i-th row (i is an integer between 1 and n) are , connected to the wiring SE[i], pixel 21 (pixel 21 [1,j] to [n,j]) are connected to the wiring OUT[j]. The optical data signal is output to the circuit 40 via a line OUT.

[0035] The pixel section 20 includes a pixel 21 that receives red light, a pixel 22 that receives green light, and a pixel 23 that receives red light. A pixel 21 that receives blue light and a pixel 21 that receives blue light are provided. A full-color image signal is generated by synthesizing these optical data signals. Alternatively, instead of these pixels 21, or In addition to the pixel 21, the pixel 21 receives light of one or more colors of cyan, magenta, and yellow. A pixel 21 may be provided that emits light of one or more of the colors cyan, magenta, and yellow. By providing the pixel 21 that receives the light, the image based on the generated image signal is reproduced. For example, the number of colors that can be displayed can be increased by setting a pixel 21 to transmit light that exhibits a specific color. A colored layer is provided through which light passes, and light is made incident on the pixel 21 through the colored layer, thereby producing a specific color. In addition, in the pixel 21, an optical data signal corresponding to the amount of light exhibiting the characteristic can be generated. The light to be detected may be visible light or invisible light.

[0036] Moreover, a cooling means may be provided in the pixel 21. By providing the cooling means, noise caused by heat can be reduced. This can suppress the occurrence of noise.

[0037] The circuit 30 is a driving circuit having a function of selecting a specific row of pixels 21 from among n rows of pixels 21. Circuit 30 selects a particular row of pixels 21 to output an optical data signal. Specifically, the circuit 30 outputs control signals to a plurality of switches S (switches S1 to Sn). By controlling the conductive state of a plurality of switches S, pixels 21 in a particular row are selected. The circuit 30 may be constituted by a decoder or the like.

[0038] The circuit 30 may have a function of supplying a reset signal to the pixel 21.

[0039] The circuit 40 is a readout circuit having a function of outputting an optical data signal obtained in the pixel section to the outside. Specifically, the circuit 40 is connected to the pixel 21 via the wiring OUT. A function of outputting an optical data signal input from a specific pixel 21 via a wiring OUT to the outside. The circuit 40 can be configured with a current source, a transistor, and the like.

[0040] The circuit 40 also has a function of supplying a predetermined potential to the wiring OUT. When the signal generated in 21 is output to the outside, the potential of the wiring OUT used for output is reset. The circuit 40 can also be operated as a constant current source. Thus, the circuit 40 supplies a predetermined potential to the wiring OUT in response to a signal input from the pixel 21. can be provided.

[0041] In addition, the semiconductor device 10 includes a plurality of switches S (switches S1 to S n) and a line VIN. A first terminal of the switch Si is connected to a line SE The first terminal is connected to the line VIN. It has the function of controlling the continuity state of wiring SE and wiring VIN according to the control signal input from do.

[0042] The wiring VIN is a power supply line used to output the optical data signal. The switch Si is in the on state. When wiring VIN and wiring SE[i] are in a conductive state, Optical data signals are output from the pixels 21[i,1] to 21[i,m] to the circuit 40.

[0043] For example, optical data signals are read from the pixels 21[1,1] to [1,m] in the first row. At this time, a predetermined control signal is output from the circuit 40 to the switch S1 to turn the switch S1 on. As a result, the wiring SE[1] and the wiring VIN are brought into a conductive state, and the pixel 21[1,1] The potential (power supply potential) of the wiring VIN is supplied to the wirings [1, m] to read out the optical data signal. It can be done.

[0044] Thus, in one aspect of the present invention, the switches S for selecting the pixels 21 are the same. The pixel section 20 is shared by the pixels 21 in the row, and the switch S is provided outside the pixel section 20. For this purpose, the pixel section 20 includes a switch (transistor, etc.) for selecting the pixel 21, and In addition, there is no need to provide a power line connected to the switch, and the area of ​​the pixel section 20 is reduced. It is possible.

[0045] In one aspect of the present invention, a power supply line for reading out an optical data signal from the pixel 21 is A wiring VIN that functions as a transistor is provided outside the pixel section 20. is configured by wiring separate from other power supply lines (such as a reset power supply line) connected to the pixel 21. Even if the pixel section 20 is connected to the line VIN, an increase in the area of ​​the pixel section 20 can be suppressed. It is possible to supply a potential different from that of the other power supply lines connected to element 21. The power supply potential used for reading out the optical data signal can be freely set, and the semiconductor device 10 This improves the design freedom and versatility of the device.

[0046] When reading out optical data signals from a specific row, the wiring It is preferable that the SE and the wiring OUT are in a non-conductive state. This allows the optical data signal to be read. This allows for more accurate delivery.

[0047] <Example of circuit configuration> Next, a specific circuit configuration of the semiconductor device 10 will be described. 1 shows an example of a circuit configuration of a semiconductor device 10 including n-type transistors. Although an example of a n-channel type transistor is shown, each transistor described below is an n-channel type. It may be either p-channel or p-channel.

[0048] First, a configuration example of the pixel 21 will be described.

[0049] The pixel 21 shown in FIG. 2 includes a photoelectric conversion element 101, transistors 102, 103, and 104, a capacitor, and a The first terminal of the photoelectric conversion element 101 is connected to the source or drain of the transistor 102. is connected to one of the drains, and the second terminal is connected to the wiring VPD. The gate of 102 is connected to the wiring TX, and the other of the source and drain is connected to the transistor 10 The gate of the transistor 103 is connected to the wiring PR. One of the source and drain is connected to the gate of the transistor 104, and The other end of the input terminal is connected to the wiring VPR. One end is connected to the wiring SE, and the other end of the source or drain is connected to the wiring OUT. One electrode of the capacitor 105 is connected to the gate of the transistor 104, and the other electrode is connected to the wiring The other of the source and drain of the transistor 102 is connected to VPD. One of the source and drain of the transistor 103, the gate of the transistor 104, and The node connected to one electrode of the capacitor 105 is referred to as a node FN. The gate of the transistor 104 can be formed by a capacitance element or a parasitic capacitance. If the port capacitance is sufficiently large, the capacitor 105 and the line VPD can be omitted.

[0050] In this specification, the source of a transistor is a semiconductor layer that functions as an active layer. The term "source region" refers to a part of the semiconductor, or a source electrode connected to the semiconductor. The drain of a transistor refers to a drain region that is a part of the semiconductor, or The term "gate" refers to a gate electrode connected to a gate electrode connected to the gate electrode.

[0051] The source and drain of the transistor are determined by the conductivity type of the transistor and the terminals. The name is changed depending on the level of the potential that can be applied. In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the In p-channel transistors, the terminal to which the low potential is applied is called the drain. The terminal to which the high potential is applied is called the drain, and the terminal to which the high potential is applied is called the source. For convenience, let us assume that the source and drain are fixed and the connection relationship of the transistor is as follows: However, in reality, the names of source and drain are used according to the above potential relationship. Replaced.

[0052] The wirings VPD and VPR are wirings to which a predetermined potential is supplied and function as power supply lines. The potentials supplied to the wirings VPD and VPR are either a high power supply potential or a low power supply potential. (such as ground potential). In this example, the wiring VPD is a high-potential power supply line. In this case, the wiring VPR is a low-potential power supply line. A high power supply potential VDD is supplied to the wiring VPR, and a low power supply potential VSS is supplied to the wiring VP D and VPR may be shared by all pixels 21.

[0053] The photoelectric conversion element 101 has a function of converting irradiated light into an electrical signal. For the element 101, a device capable of obtaining a photocurrent according to irradiated light can be used. Specific examples of the photoelectric conversion element 101 include a PN type photodiode and a PIN type photodiode. Diodes, avalanche diodes, NPN buried diodes, Schottky diodes Diodes, phototransistors, photoconductors for X-rays, infrared sensors, etc. In addition, the photoelectric conversion element 101 may include an element having selenium in the photoelectric conversion layer. In this embodiment, a photodiode is used as the photoelectric conversion element 101. The anode of the diode is connected to either the source or the drain of the transistor 102. The cathode is connected to the wiring VPD. The low power supply potential VSS is supplied to the wiring VPD. When a high power supply potential VDD is supplied to the wiring VPR, the anode of the photodiode It is preferable to switch the cathode with the cathode.

[0054] The conduction state of the transistor 102 is controlled by the potential of the wiring TX. When the photoelectric conversion element 101 is turned on, the electric signal output from the photoelectric conversion element 101 is provided to the node FN. Therefore, the potential of the node FN is changed according to the amount of light irradiated to the photoelectric conversion element 101. The transistor 102 is on and the transistor 103 is off. During the period in which the photoresist is in the photosensitive state, exposure to light can be performed.

[0055] The conduction state of the transistor 103 is controlled by the potential of the wiring PR. When the potential of the wiring VPR is supplied to the node FN, the potential of the node FN is The potential of the wiring PR is reset so that the transistor 103 is turned on. The period during which the reset signal is supplied to the wiring PR corresponds to the reset period. The potential of the wiring PR may be controlled by the circuit 30 or by another driver circuit. You may control it.

[0056] In this way, the pixel 21 is reset by supplying the potential of the wiring VPR to the node FN. The potential of the wiring VPR for resetting the pixel 21 is also called a reset potential.

[0057] The conduction state of the transistor 104 is controlled by the potential of the node FN. The resistance value between the source and drain of the transistor 104 changes depending on the potential of the node FN. Therefore, in response to the potential of the node FN, The potential supplied to the line OUT is determined.

[0058] In one aspect of the present invention, the potential of the line SE is controlled by the transistor 110 and the line VIN. The gate of the transistor 110 is connected to the wiring CSE, and the source or drain One of the inputs is connected to the wire SE, and the other of the source or drain is connected to the wire VIN. The transistor 110 corresponds to the switch S in FIG. A potential (hereinafter also referred to as a selection signal) that turns on the transistor 110 is supplied to the When this happens, the VIN and SE lines are connected, and the potential of the VIN line is displayed as the power supply potential. This selects the pixel 21 from which the optical data signal is to be read out. It is possible.

[0059] Here, the transistor 110 for selecting the pixel 21 is shared by the pixels 21 in the same row, In addition, the transistor 21 is provided outside the pixel 21. , and the area of ​​the pixel 21 can be reduced.

[0060] Next, the configuration of the circuit 41 will be described.

[0061] The circuit 41 is a circuit included in the circuit 40 in FIG. An example of a configuration in which a pixel is provided for each column will be described.

[0062] The circuit 41 includes a transistor 120. A gate of the transistor 120 is connected to a wiring BR. One of the source or drain is connected to the wiring VO, and the other of the source or drain is connected to the wiring VO. The other side is connected to the OUT wire.

[0063] The conduction state of the transistor 120 is controlled by the potential of the wiring BR. When 0 is turned on, the potential of the wire VO is supplied to the wire OUT, and the potential of the wire OUT is reset. Then, the power supply potential is applied from the line VIN to the line SE via the transistor 110. When the potential of the node FN is supplied, the potential of the node FN is output to the wiring OUT. The transistor 104 constitutes a source follower, and the threshold voltage of the transistor 104 is The potential that is reduced by the value is output to the wiring OUT.

[0064] The wiring VO is a wiring to which a predetermined potential is supplied and functions as a power supply line. The potential supplied to O may be a high power supply potential or a low power supply potential (such as ground potential). Here, as an example, a case where the wiring VO is a low-potential power supply line will be described. That is, the low power supply potential VSS is supplied to the line VO.

[0065] Note that a constant potential was continuously supplied to the wiring BR so that the transistor 120 was turned on. In this case, the transistor 120 functions as a current source. The combined resistance between the source and drain of the transistor 104 and the source and drain of the transistor 105 is The divided potential is output to the wiring OUT.

[0066] In one aspect of the present invention, the line VIN is separated from the line VPR. A potential different from the wiring VPR can be supplied. For example, a low power supply potential VS Even if S is supplied, the high power supply potential VDD can be supplied to the VIN line. Therefore, a source follower is configured by the transistor 104 and the transistor 120. This allows the optical data signal to be read out at high speed. By adjusting the high power supply potential VDD supplied to N, the dynamic output potential of the wiring OUT can be controlled. This makes it possible to change the dynamic range.

[0067] <Example of a read operation> Next, the operation of reading out an optical data signal from the pixel 21 will be described.

[0068] When reading out an optical data signal from the pixel 21 in FIG. 2, the potential of the signal line CSE is set to high level. This causes a current to flow from the line VIN to the line SE A high power supply potential VDD is supplied to the transistor 104. The resistance between the input and output terminals is determined by the potential of the node FN. A potential corresponding to the potential of the node FN is output from the wiring SE through the transistor 104. This makes it possible to read out optical data signals from the pixels 21.

[0069] On the other hand, when the optical data signal is not to be read out from the pixel 21, the potential of the signal line CSE is At this time, the wiring SE is connected to the wiring V Since no power supply potential is supplied from IN, no optical data signal is output to the OUT wiring. .

[0070] During the period when the optical data signal is not being read out, the pixel 21 is in a reset state. Specifically, when the node FN is at a low level and the transistor 1 It is preferable that the line SE and the line OUT are in a non-conductive state. This makes it possible to prevent an unintended potential from being supplied to the wiring OUT. To turn off the transistor 104, the transistor 103 must be turned on. Thus, the low power supply potential VSS of the wiring VPR can be supplied to the node FN.

[0071] By the above operation, the optical data signal can be output to the wiring OUT. The optical data signal output to the UT is input to a circuit 40 and output from the circuit 40 to the outside.

[0072] The materials used for each transistor shown in FIG. 2 are not particularly limited. The transistors 102, 103, and 104 are transistors having an oxide semiconductor, particularly in a channel formation region. In the above-mentioned embodiment, an oxide semiconductor transistor (hereinafter also referred to as an OS transistor) is preferably used. has a wider band gap and a lower intrinsic carrier density than other semiconductors such as silicon. Therefore, the off-state current of the OS transistor is extremely small. By using this, it is possible to maintain a predetermined potential for a long period of time. The conductor and the OS transistor will be described in detail in Embodiments 4 and 7.

[0073] For example, when the transistor 102 is an OS transistor, During the period in which the node FN is in the low-level state, the transfer of electric charges between the node FN and the photoelectric conversion element 101 is suppressed. Therefore, the charge stored in the node FN can be held for an extremely long period of time. This makes it possible to prevent the potential of the node FN from fluctuating.

[0074] In addition, when the transistor 103 is an OS transistor, During the period in which the node FN is in the MOSFET state, the transfer of charge between the node FN and the wiring VPR can be suppressed. Therefore, the charge stored in the node FN can be retained for an extremely long period of time. Therefore, fluctuation in the potential of the node FN can be prevented.

[0075] In addition, when the transistor 104 is an OS transistor, During the period in which the line SE is in the ON state, the transfer of charges between the line SE and the line OUT can be suppressed. Therefore, it is possible to suppress unintended fluctuations in the potential of the wiring OUT. During the period when the transistor 104 is in the off state, other pixels connected to the same wiring OUT When reading out the optical data signal in the element 21, it is possible to perform more accurate reading. do.

[0076] When OS transistors are used as the transistors 102 and 103, Even if the potential of the node FN is extremely small, the potential of the node FN is reliably maintained, and the Therefore, the data signal can be accurately output. This can widen the range of light illuminance that can be used, i.e., the dynamic range.

[0077] In addition, an OS transistor is a transistor that contains silicon in the channel formation region (hereafter, S Since the temperature dependence of the electrical characteristics fluctuation is smaller than that of the conventional transistor, it can be used in a wide range of temperatures. Therefore, a semiconductor device having an OS transistor can be used in a wide range of applications. This makes it possible to realize an imaging device suitable for installation in automobiles, aircraft, spacecraft, etc. can be done.

[0078] In addition, when a device having a photoelectric conversion layer made of a selenium-based material is used for the photoelectric conversion element 101, A relatively high voltage (e.g., 10 V or more) is applied to make the Ranche phenomenon more likely to occur. For example, it is preferable to set the potential of the wiring VPD to 10 V or more and the potential of the wiring VPR to 0 V. Here, it is preferable that the OS transistor has a higher drain withstand voltage than the Si transistor. Since the transistors have high conductivity, they are suitable for use as the transistors 102 to 104. As shown above, by combining OS transistors with photoelectric conversion elements using selenium-based materials, This makes it possible to provide a highly reliable imaging device capable of capturing images with high accuracy. The details of the photoelectric conversion element having a photoelectric conversion layer made of a silicon-based material will be described in the sixth embodiment.

[0079] Note that the transistors 102, 103, and 104 are not limited to OS transistors. For example, the channel formation region is formed in a part of a substrate having a single crystal semiconductor. A transistor having a single crystal semiconductor (hereinafter also referred to as a single crystal transistor) is used for the As a substrate having a single crystal semiconductor, a single crystal silicon substrate or a single crystal germanium substrate can be used. A single crystal transistor has a high current supply capacity, so By configuring the pixel 21 using such a transistor, the operation speed of the pixel 21 can be improved. It can be raised.

[0080] In addition, the transistors 102, 103, and 104 are not OS transistors but have a channel type A transistor having a non-single-crystal semiconductor in a growth region (hereinafter also referred to as a non-single-crystal transistor) As a non-single crystal semiconductor other than the OS transistor, amorphous silicon Non-single-crystal silicon such as silicon, microcrystalline silicon, and polycrystalline silicon, as well as amorphous germanium, Examples include non-single-crystal germanium such as microcrystalline germanium and polycrystalline germanium. .

[0081] The transistors 110 and 120 may be the above-mentioned OS transistors, single crystal transistors, and non-single crystal transistors. A crystalline transistor or the like can be used as appropriate.

[0082] Here, the transistor 110 is connected to a plurality of pixels 21 (m pixels 21 in FIG. 1). Therefore, the transistor 110 is required to have a high current supply capability. It is preferable to use a single crystal transistor having a high current supply capability as the transistor 110 . This makes it possible to easily supply the power supply potential from the wiring VIN to the multiple pixels 21. At this time, the transistors 102 to 104 are stacked on the transistor 110. This is preferable because it can prevent an increase in area due to the provision of the transistor 110. The details of the stacked transistor structure will be described in the fourth embodiment. Reveal.

[0083] The transistor 110 has the same semiconductor material as the transistors 102 to 104. When a transistor that supports this (such as an OS transistor) is used, the channel of the transistor 110 The width of the gate is preferably larger than the channel width of the transistors 102 to 104 . This allows the current supply capability of the transistor 110 to be increased.

[0084] <Operation Example of Semiconductor Device 10> Next, a specific example of the operation of the semiconductor device 10 will be described.

[0085] As an example, pixels 21[1,1] and [1,2] in the first row shown in FIG. Next, an example of the operation of pixels 21[2,1] and [2,2] in the second row will be described. 3, pixels 21[1,1] and [1,2] are connected to pixels 21[2,1] and [2,2] The wirings TX are TX[1] and TX[2], respectively. The transistor 110 connected to the line SE[2] is referred to as the transistor 110[1], Transistor 110[2]. Transistor 110[1], transistor 11 The wiring CSE connected to 0[2] is called wiring CSE[1] and wiring CSE[2], respectively. In addition, the nodes F at the pixels 21[1,1], [1,2], [2,1], and [2,2] N are nodes FN[1,1], FN[1,2], FN[2,1], The node FN[2,2] is connected to the wiring OUT[1] and the wiring OUT[2]. The circuits 41 are referred to as circuit 41[1] and circuit 41[2], respectively.

[0086] FIG. 4 shows a timing chart of the semiconductor device 10 shown in FIG. The period Ta is a period during which the pixels in the first row are reset, exposed, and read out. The interval Tb is a period during which reset, exposure, and readout are performed on the pixels in the second row.

[0087] First, in a period T1, the potential of the wiring PR is set to a high level. In 21, the transistor 103 is turned on, and the potential (low level) of the wiring VPR It is supplied to node FN. Therefore, nodes FN[1,1], [1,2], [2,1], [ 2,2] is reset to a low level. By this operation, the pixels 21[1,1] and 21[1,2] are turned off. ], [2,1], and [2,2] are reset.

[0088] In addition, in the period T1, the potential of the wiring TX[1] becomes high, and the potential of the pixel 21[1,1 ], [1, 2], the transistor 102 is turned on. 01 and node FN are in a conductive state.

[0089] Next, in a period T2, the potential of the wiring PR becomes low level, and in all the pixels 21 The transistor 103 is turned off. This causes the node FN to be in a floating state. The potentials of the nodes FN[1,1] and FN[1,2] are changed by applying a voltage to the photoelectric conversion element 101. In this case, the increase in the potential of node FN[1,1] corresponds to the increase in the potential of node FN[1,2]. The light is converted into an electrical signal, and exposure can be performed at pixels 21[1,1] and [1,2]. The period T2 is also called the exposure period of the pixels 21[1,1] and 21[1,2].

[0090] Next, in a period T3, the potential of the wiring TX[1] becomes low, and the potential of the pixel 21[1,1 ], [1, 2], the transistor 102 is turned off. The potentials of the pixels 21[1,1], [1, The exposure period [2] ends.

[0091] Next, in a period T4, the potential of the wiring BR becomes high, so that the transistor 120 is turned on, and the potential of the wire VO is applied to the wires OUT[1] and OUT[2]. In this case, the potential of the line VO is set to low level, so the line OUT[1] The potential of the wiring OUT[2] becomes low level.

[0092] Next, in a period T5, the potential of the wiring BR becomes low, and the transistor 120 is turned on. In addition, the potential of the wiring CSE[1] becomes high, and the transistor 110 [1] is turned on. This causes the potential of the line VIN to be supplied to the line SE[1], The potential of the line SE[1] becomes high level.

[0093] In this example, the potential of the wiring OUT is controlled by changing the potential of the wiring BR. An arbitrary potential may be constantly supplied to R. In this case, the transistor 120 is a current source. The potential of the wiring OUT is determined according to the potential of the wiring BR.

[0094] Here, the wiring SE[1] functions as a power supply line for the pixels 21[1,1] and 21[1,2]. Specifically, the potential of the wiring SE[1] is applied to the transistor 104 functioning as an amplifying transistor. As a result, the potentials of the wiring OUT[1] and wiring OUT[2] are The value depends on the potential of the node FN[1,1] and the node FN[1,2]. The potentials of the wiring OUT[1] and OUT[2] are the same as those of the pixels 21[1,1] and 21[1,2], respectively. In this manner, during period T5, the transistor 110[1] functions as a selection transistor for selecting the pixel 21 from which the optical data signal is to be read out. Yes.

[0095] During the period T5, the pixels 21[2,1] and 21[2,2] are in a reset state. Specifically, the nodes FN[2,1] and [2,2] are at a low level, and the pixel 21 The transistors 104 of the pixels 21[2,1] and 21[2,2] are in the off state. Therefore, the wiring SE[2] and the wiring OUT[1], [2] are in a non-conductive state. When optical data signals are read from 21[1,1] and [1,2], the potential of the wiring SE[2] is changed. As a result, it is possible to prevent the potentials of the wirings OUT[1] and OUT[2] from fluctuating.

[0096] Next, in a period T6, the potential of the wiring CSE[1] becomes low, and the transistor 1 10[1] is turned off. This stops the supply of power potential to the wiring SE[1]. Then, the reading of the optical data signal is completed.

[0097] Through the above operations, reset, exposure, and readout are performed on the pixels in the first row.

[0098] Next, in a period T7, the potential of the wiring PR becomes high level. In 21, the transistor 103 is turned on, and the potential (low level) of the wiring VPR It is supplied to node FN. Therefore, nodes FN[1,1], [1,2], [2,1], [ 2,2] is reset to a low level. By this operation, the pixels 21[1,1] and 21[1,2] are turned off. ], [2,1], and [2,2] are reset.

[0099] In addition, in the period T7, the potential of the wiring TX[2] becomes high, and the potential of the pixel 21[2,1 ], [2,2], the transistor 102 is turned on. 01 and node FN are in a conductive state.

[0100] Next, in a period T8, the potential of the wiring PR becomes low level, and in all the pixels 21 The transistor 103 is turned off. This causes the node FN to be in a floating state. The potentials of the nodes FN[2,1] and FN[2,2] are changed by applying a voltage to the photoelectric conversion element 101. In this case, the increase in the potential of node FN[2,1] corresponds to the increase in the potential of node FN[2,2]. The light is converted into an electrical signal, and exposure can be performed at pixels 21[2,1] and [2,2]. The period T8 is also called the exposure period of the pixels 21[2,1] and 21[2,2].

[0101] Next, in a period T9, the potential of the wiring TX[2] becomes low, and the potential of the pixel 21[2,1 ], [2,2], the transistor 102 is turned off. The potentials of the pixels 21[2,1], [2, The exposure period [2] ends.

[0102] Next, in a period T10, the potential of the wiring BR becomes high, so that the transistor The capacitor 120 is turned on, and the potential of the wiring VO is applied to the wiring OUT[1] and the wiring OUT[2]. In this case, the potential of the wiring VO is set to a low level, so that the potential of the wiring OUT[1 ] and wiring OUT[2] become low potential.

[0103] Next, in a period T11, the potential of the wiring BR becomes low, and the transistor 120 In addition, the potential of the wiring CSE[2] becomes high, and the transistor 11 0[2] is turned on. This causes the potential of the line VIN to be supplied to the line SE[2]. , the potential of the wiring SE[2] becomes high level.

[0104] In this example, the potential of the wiring OUT is controlled by changing the potential of the wiring BR. An arbitrary potential may be constantly supplied to R. In this case, the transistor 120 is a current source. The potential of the wiring OUT is determined according to the potential of the wiring BR.

[0105] Here, the wiring SE[2] functions as a power supply line for the pixels 21[2,1] and 21[2,2]. Specifically, the potential of the wiring SE[2] is applied to the transistor 104 functioning as an amplifying transistor. As a result, the potentials of the wiring OUT[1] and wiring OUT[2] are The potential of the wiring OU is determined by the potential of the node FN[2,1] and the node FN[2,2]. The potentials of the wiring OUT[1] and OUT[2] are the same as those of the pixels 21[2,1] and 21[2,2], respectively. ] corresponds to the optical data signal of the transistor 110[2 ] functions as a selection transistor for selecting a pixel 21 from which an optical data signal is to be read out. do.

[0106] During the period T11, the pixels 21[1,1] and 21[1,2] are reset. Specifically, the nodes FN[1,1] and [1,2] are at a low level, and the pixel 2 The transistor 104 of pixel 1[1,1] and pixel 21[1,2] is in the off state. Therefore, the wiring SE[1] and the wiring OUT[1], [2] are in a non-conducting state. When reading out optical data signals from elements 21[2,1] and 21[2,2], the potential of the wiring SE[1] is This can prevent the potentials of the wirings OUT[1] and OUT[2] from fluctuating.

[0107] Next, in a period T12, the potential of the wiring CSE[2] becomes low, and the transistor 110[2] is turned off. This stops the supply of power supply potential to the wiring SE[2]. Then, the reading of the optical data signal is completed.

[0108] Through the above operations, the pixels in the second row are reset, exposed, and read out.

[0109] After that, in a period T13, the potential of the wiring PR becomes high. In the pixel 21, the transistor 103 is turned on, and the potential of the node FN becomes low. After that, the exposure of the pixels 21 in the third row and onward is reset by the same operation as above. The light is then exposed to light and read out, and the pixels 21 in the fourth row and onward are reset, exposed to light, and read out. do.

[0110] As described above, in one embodiment of the present invention, the switches for selecting the pixels 21 are the same. It is shared by the pixels 21 in the row and is provided outside the pixel section 20. A switch for selecting a pixel 21 in the pixel section 20 and a power line connected to the switch This eliminates the need to provide a filter, and the area of ​​the pixel section 20 can be reduced.

[0111] In one embodiment of the present invention, a wiring functioning as a power supply line for selecting the pixel 21 VIN is provided outside the pixel section 20. Therefore, the wiring VIN is connected to the pixel 21. Even if the power supply line is made up of a wiring different from the other power supply lines (such as wiring VPR) connected to the pixel section 2 In addition, the wiring VIN is connected to the pixel 21 and other Therefore, it is possible to supply a potential different from that of the power supply line of the optical data signal. This allows the power supply potential to be freely set, and increases the degree of freedom in designing the semiconductor device 10. Versatility can be improved.

[0112] In this embodiment, one embodiment of the present invention has been described. In other words, the present embodiment describes various aspects of the invention, However, one aspect of the present invention is not limited to a specific aspect. For example, one aspect of the present invention is Although an example of a semiconductor device in which a switch shared by pixels in a row is provided outside a pixel portion has been shown, However, one aspect of the present invention is not limited thereto. In one aspect of the invention, the switches may not be shared in the same row, or the switches may be The switch may be provided inside the pixel portion. The power supply line connected to the switch is configured with a wiring different from the power supply line connected to the pixel. However, one embodiment of the present invention is not limited to this. Alternatively, depending on the situation, one aspect of the present invention is that these power supply lines may be the same wiring. good.

[0113] In the present embodiment, the exposure is performed row by row. 21 (up to all pixels 21) are exposed simultaneously, and then read out row by row. A global shutter method can also be used, which obtains images with less distortion. In the global shutter method, the entire process from exposure to readout is performed in a single step. The period during which the charge is held at the node FN differs depending on the pixel 21. When using the global shutter method, the potential of node FN changes over time. Here, by using an OS transistor in the pixel 21, The charge stored in the glow plug can be maintained for an extremely long period of time. Even when using the BAL shutter method, the optical data signal can be read out accurately. .

[0114] This embodiment mode can be appropriately combined with the description of other embodiment modes. The contents (or a part of the contents) described in the embodiment may be different contents described in the embodiment. (or a part of) the contents described in one or more other embodiments. (or even a part of) can be applied, combined, or replaced. The contents described in the embodiments are based on various drawings in each embodiment. The contents described using the phrase "Patent Licensing", or the sentences described in the specification. A figure (or a part thereof) described in a certain embodiment may be different from another part of the figure, Another figure (or a part thereof) and / or one or more other figures described in the embodiment By combining with the figures (or even a part of them) described in the embodiment mode, This also applies to the following embodiments. do.

[0115] (Embodiment 2) In this embodiment, a configuration example of a pixel according to one embodiment of the present invention will be described.

[0116] <Pixel layout example> An example of the layout of the pixel 21 that can be used in the above embodiment is shown in FIG. In FIG. 5, wiring, conductive layers, and semiconductor layers shown with the same hatch pattern are made of the same material. The above-mentioned components can be formed in the same process.

[0117] The pixel 21 shown in FIG. 105. The connection relationship of each element can be seen in the description of FIG. In addition, the photoelectric conversion element 101 is not shown in FIG. The photoelectric conversion element 101 is connected to the conductive layer 250 .

[0118] The semiconductor layer 221 functions as an active layer for the transistors 102 and 103. That is, the semiconductor layer 221 has the transistors 102 and 103. The semiconductor layer 222 also functions as an active layer of the transistor 104. Yes.

[0119] The semiconductor layer 221 is connected to the conductive layer 231 and the conductive layer 232. The conductive layer 231 is The conductive layer 232 is connected to the conductive layer 250 through the opening 251. The semiconductor layer 221 is connected to the conductive layer 212 through the opening 255. It is connected to the conductive layer 243.

[0120] The conductive layer 231 functions as one of the source and drain of the transistor 102. The conductive layer 232 functions as one of the source and drain of the transistor 103. The conductive layer 243 is a layer that serves as the other of the source and drain of the transistor 102. The other of the source or drain of the transistor 103, the gate of the transistor 104, and the capacitance It functions as one of the electrodes of 05.

[0121] The semiconductor layer 222 is connected to a conductive layer 233 and a conductive layer 234. The conductive layer 233 is an open The conductive layer 234 is connected to the conductive layer 202 through an opening 256. 211 and is connected to the conductive layer 211 .

[0122] The conductive layer 233 functions as one of the source and drain of the transistor 104. The conductive layer 234 functions as the other of the source and drain of the transistor 104. Yes.

[0123] Here, the conductive layer 212 corresponds to the wiring VPR, the conductive layer 202 corresponds to the wiring SE, and the conductive layer 211 corresponds to the wiring OUT. Also, a node where the semiconductor layer 221 and the conductive layer 243 are connected The node corresponds to node FN.

[0124] The semiconductor layer 221 and the semiconductor layer 222 may be formed of various single crystal semiconductor layers or non-single crystal semiconductor layers. In this case, a layer of an oxide semiconductor can be used. , transistors 102 to 104 are OS transistors.

[0125] The conductive layer 241 is connected to the conductive layer 203 through the opening 252. The conductive layer 241 functions as a gate of the transistor 102. Here, the conductive layer 203 corresponds to the wiring TX. do.

[0126] The conductive layer 242 is connected to the conductive layer 204 through the opening 254. The conductive layer 242 functions as a gate of the transistor 103. Here, the conductive layer 204 corresponds to the wiring PR. do.

[0127] The conductive layer 201 has a region overlapping with the conductive layer 243 via an insulating layer (not shown). The layer 201 functions as the other electrode of the capacitor 105. Here, the conductive layer 201 is Supports wiring VPD.

[0128] In FIG. 5, the transistors 102, 103, and 104 are of the top gate type. The transistors 102, 103, and 104 may be either top-gate or bottom-gate. It may also be of type T.

[0129] In addition, in FIG. 5, semiconductor layers 221 and 222, conductive layers 231 to 234, and conductive layers 241 to 243, conductive layers 211, 212, conductive layers 201 to 204, and conductive layer 25 The upper and lower layers are stacked in this order, but the upper and lower relationships of the layers are not limited to this and can be freely set. It is possible.

[0130] <Modification of pixel> Next, a modification of the pixel 21 described in the first embodiment will be described.

[0131] The pixel 21 may have a configuration as shown in FIG. The anode of the conversion element 101 is connected to the wiring VPD, and the cathode is connected to the The difference from the configuration in FIG. 2 is that the source or drain is connected to the transistor. In this case, the wiring VPD serves as a low potential power supply line, and the wiring VPR serves as a high potential power supply line.

[0132] In one embodiment of the present invention, the potential of the wiring VPR is applied to the node FN as a reset potential. When this is done, it is preferable that the transistor 104 be in an off state. In A), the transistor 104 is a p-channel type, and the wiring VPR is connected to the node FN. When a high-level potential is supplied to the transistor 104, the transistor 104 is turned off. It is preferable to do so.

[0133] The pixel 21 may have a configuration shown in FIG. 6(B). The pixel 21 shown in FIG. 2 in that it has a plurality of photoelectric conversion elements 101 and transistors 102. The first terminal of the photoelectric conversion element 101a is connected to the source or drain of the transistor 102a. The first terminal of the photoelectric conversion element 101 is connected to one of the inputs, and the second terminal of the photoelectric conversion element 101 is connected to the wiring VPD. The first terminal of the transistor 102b is connected to one of the source and drain of the transistor 102b. The gate of the transistor 102a is connected to the wiring VPD. The gate of the transistor 102b is connected to the wiring TXb. The other of the source or drain of transistor 102a and the other of the source or drain of transistor 102b The other drain is connected to a node FN.

[0134] The gate of the transistor 102a and the gate of the transistor 102b are connected to different wirings. The exposure in the photoelectric conversion element 101a and the exposure in the photoelectric conversion element 101b are different. Each is controlled independently. By using this configuration, two The exposure can be performed using a photoelectric conversion element. The number of children is not particularly limited and may be three or more.

[0135] The pixel 21 may have a configuration as shown in FIG. The transistor 103 in the photoelectric conversion element 101 is omitted. The transistor 102 has a source or a drain connected thereto, and a cathode connected to the wiring VPR. is connected.

[0136] When performing a reset operation of the pixel 21 (for example, corresponding to the operation during periods T1 and T7 in FIG. 4), The potential of the wiring VPR is set to a low level, and the potential of the wiring TX is set to a high level. A forward bias is applied to the photoelectric conversion element 101, and the potential of the node FD is reset to a low level. After the node FD is reset, the potential of the wiring VPR is set to a high level.

[0137] The pixel 21 may have a configuration shown in FIG. 6(D). The pixel 21 shown in FIG. The anode of the photoelectric conversion element 101 is connected to the wiring VPD, and the cathode of the photoelectric conversion element 10 6C in that it is connected to one of the source or drain of become.

[0138] When performing a reset operation of the pixel 21 (for example, corresponding to the operation during periods T1 and T7 in FIG. 4), The potential of the wiring VPR and the wiring TX is set to a high level. A forward bias is applied to node 01, and the potential of node FD is reset to a high level. After the node FD is reset, the potential of the wiring VPR may be set to low level.

[0139] In one embodiment of the present invention, the potential of the wiring VPR is applied to the node FN as a reset potential. It is preferable that the transistor 104 is turned off by supplying the voltage Vcc. In FIG. 6D, the transistor 104 is a p-channel transistor, and the potential of the node FN is high. When the level is reset to the threshold level, the transistor 104 is turned off. It is preferable.

[0140] In addition, the transistor 102 may be omitted in FIG. FIG. 7A shows a configuration in which the transistor 102 is omitted, and FIG. The omitted configuration is shown in FIG.

[0141] In addition, the transistor used in the pixel 21 has a first gate electrode (hereinafter, referred to as a front gate). In addition to the first gate electrode (hereinafter also referred to as the back gate), a second gate electrode (hereinafter also referred to as the back gate) is provided. FIG. 8 shows a configuration in which the transistors 102, 103, and 104 are provided with back gates. Shows.

[0142] FIG. 8A shows a front gate and a second gate in the transistors 102, 103, and 104 shown in FIG. A back gate is connected to the front gate, and the back gate is supplied with the same potential as the front gate. FIG. 8B shows a structure in which the transistor 102 in FIG. A back gate connected to the front gate is provided at 103 and 104, and the back gate is connected to the front gate. The structure is such that the same potential as that of the front gate is supplied to the gate. This makes it possible to increase the on-current of the transistors 102, 103, and 104, and achieve high speed This makes it possible to capture images with high resolution.

[0143] FIG. 8C shows a case where the transistors 102, 103, and 104 in FIG. 2 are connected to the wiring VPR. A back gate is provided so that a constant potential is supplied to the back gate. Here, it is assumed that the wiring VPR is applied with a ground potential. The transistors 102, 103, and 104 in FIG. 6(A) are connected to a buffer connected to the wiring VPD. A gate is provided so that a constant potential is supplied to the back gate. Assume that the wiring VPD is applied with a ground potential. The threshold voltages of 103 and 104 can be controlled, enabling highly reliable imaging. Cut.

[0144] In FIG. 8C, the back gates of the transistors 102, 103, and 104 are connected to the wiring In FIG. 8(D), the back-up of transistors 102, 103, and 104 is connected to VPR. Although the gate is connected to the wiring VPD, the back gate is supplied with a constant potential. 6(B) to (D), 7(A), and 7(B) may be connected to another wiring. ) may also be provided with a back gate in a similar manner.

[0145] In addition, the transistors 102, 103, and 104 each have a back gate and a front gate. A configuration in which the same potential is supplied to the back gate, a constant potential is supplied to the back gate, and The transistor may have any of the configurations not provided. In other words, one pixel 21 may include two or more types of transistors.

[0146] In addition, in FIG. 2 and FIG. 6 to FIG. 8, an element included in the pixel 21 is shared by a plurality of pixels. The transistor 103, the transistor 104, and the capacitor 105 in FIG. FIG. 9 shows the configuration of a pixel section 20 shared by four pixels 21. In FIG. The transistor 102 is connected to a node FN, and the node FN is connected to a transistor 103 and a transistor The pixel section 20 is connected to the transistor 104 and the capacitor 105. The number of elements can be reduced.

[0147] In addition, FIG. 9 shows a configuration in which the pixels 21 in different rows share transistors and capacitances. However, a configuration in which the pixels 21 in different columns share a transistor or a capacitor may be used. In this example, the transistor 103, the transistor 104, and the capacitor 105 are shared by four pixels. However, the number of pixels sharing the element is not limited to this, and may be two pixels, three pixels, or the like. 6 to 8, the pixel 21 may be a pixel having a length of 100 nm or a length of 50 nm or more. A similar configuration can be applied to the above-mentioned.

[0148] The configurations shown in FIG. 2 and FIGS. 6 to 9 can be freely combined.

[0149] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0150] (Embodiment 3) In this embodiment, an imaging device using a semiconductor device according to one embodiment of the present invention will be described. .

[0151] 10 shows an example of the configuration of an image pickup device 300. The image pickup device 300 includes a light detection unit 310, a data It has a processing unit 320.

[0152] The light detection unit 310 includes a pixel unit 20, a circuit 30, a circuit 40, a circuit 50, and a circuit 60. The pixel section 20, the circuit 30, and the circuit 40 may be the same as those described in the above embodiment. can be done.

[0153] The circuit 50 has a function of converting the analog signal input from the circuit 40 into a digital signal. The circuit 50 can be configured with an A / D converter or the like.

[0154] The circuit 60 is a driver circuit having a function of reading out the digital signal input from the circuit 50. The circuit 60 can be configured using a selection circuit or the like. The transistor can be an OS transistor. A transistor or the like can be used.

[0155] The data processing unit 320 includes a circuit 321. The circuit 321 detects the signal generated in the light detection unit 310. The optical data signal thus generated is used to generate image data.

[0156] The pixel section 20 may be provided with a circuit having a function of displaying an image. The imaging device 300 can also function as a touch panel.

[0157] Next, an example of a method for driving the imaging device 300 shown in FIG. 10 will be described.

[0158] First, in the pixel 21, an optical data signal is generated by the method shown in the first embodiment. The optical data signal generated in element 21 is output to circuit 40. Circuit 40 then , converts the optical data signal into an analog signal and outputs it to the circuit 50 .

[0159] The analog signal output from the circuit 40 is converted to a digital signal in the circuit 50, and The digital signal is then output to the circuit 60. The circuit 60 reads out the digital signal. The digital signal read out by is used for processing in circuit 321, etc.

[0160] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0161] (Embodiment 4) In this embodiment, a configuration example of an element that can be used in the semiconductor device 10 will be described. .

[0162] FIG. 11 shows the configuration of a transistor and a photoelectric conversion element that can be used in the semiconductor device 10. In this embodiment, a photodiode is used as the photoelectric conversion element. An example will be described.

[0163] <Configuration example 1> FIG. 11A shows a transistor 801, a transistor 802, and a photodiode 803. A configuration example is shown. A transistor 801 is connected to a transistor through a wiring 819 and a conductive layer 823. The transistor 802 is connected to the photodiode 802 through the conductive layer 830. It is connected to 03.

[0164] The transistors 801 and 802 are the same as those shown in FIGS. 2, 3, 6 to 9 of the semiconductor device. The present invention can be freely applied to the transistors included in the semiconductor device 10. For example, the transistor 801 can be replaced with the transistors 110 and 120 in FIG. 2, 3, 6 to 9, and the like. 2 to 104, etc. It can be used as the photoelectric conversion element 101 shown in FIG. 3 and FIG. 6 to FIG.

[0165] [Transistor 801] First, the transistor 801 will be described.

[0166] The transistor 801 is formed using a semiconductor substrate 810. The semiconductor device has a separation layer 811 and an impurity region 812 formed in a semiconductor substrate 810. Region 812 functions as the source or drain region of transistor 801, and impurity region A channel region is formed between the regions 812. The transistor 801 also includes an insulating layer 813. The insulating layer 813 functions as a gate insulating layer of the transistor 801. The conductive layer 814 functions as a gate electrode of the transistor 801. A sidewall 815 may be formed on the side surface of the conductive layer 814. On the layer 814, an insulating layer 816 having a function as a protective layer and a An insulating layer 817 may also be formed to cover the insulating layer 817 .

[0167] A silicon substrate is used as the semiconductor substrate 810. The substrate material is silicon. In addition, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum Nitrogen gallium arsenide, indium phosphide, gallium nitride, and organic semiconductors can also be used. .

[0168] The element isolation layer 811 is formed by LOCOS (Local Oxidation of Silic on method or STI (Shallow Trench Isolation) method. It can be formed by:

[0169] The impurity region 812 contains an impurity element that imparts electrical conductivity to the material of the semiconductor substrate 810. When a silicon substrate is used as the semiconductor substrate 810, n-type conductivity is imparted to the silicon substrate. Examples of impurities that impart p-type conductivity include phosphorus and arsenic. Examples of impurity elements include boron, aluminum, and gallium. , and is added to a predetermined region of the semiconductor substrate 810 by ion implantation, ion doping, or the like. It is possible.

[0170] The insulating layer 813 is made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, or the like. Silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tungsten oxide The insulating layer 813 can be formed of an insulating material containing one or more of the above materials. The insulating layer may be formed by laminating one or more kinds of insulating layers.

[0171] The conductive layer 814 may be made of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, or the like. Conductive materials such as aluminum, zirconium, molybdenum, silver, manganese, tantalum, and tungsten Alternatively, alloys of the above materials or conductive nitrides of the above materials may be used. In addition, the present invention is directed to a method for manufacturing a semiconductor device using a plurality of materials selected from the group consisting of the above materials, alloys of the above materials, and conductive nitrides of the above materials. It may be a laminate of materials.

[0172] The insulating layer 816 may be made of magnesium oxide, silicon oxide, silicon oxynitride, or silicon oxynitride. Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Contains one or more of tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide. The insulating layer 816 can be an insulating layer containing one or more of the above materials. may be laminated.

[0173] The insulating layer 817 is made of acrylic resin, epoxy resin, benzocyclobutene resin, polyimide, An insulating layer containing an organic material such as polyamide can be used. The insulating layer 817 may be formed by stacking insulating layers containing the above materials. The same materials can also be used.

[0174] Note that the impurity region 812 is connected to a wiring 819 through a conductive layer 818. It is possible.

[0175] [Transistor 802] Next, the transistor 802 will be described. The transistor 802 is an OS transistor. It is.

[0176] The transistor 802 includes an oxide semiconductor layer 824 over an insulating layer 822 and an oxide semiconductor layer 82 A conductive layer 825 on the substrate 824, an insulating layer 826 on the conductive layer 825, and a conductive layer 82 on the insulating layer 826. The conductive layer 825 is a source electrode or a drain electrode of the transistor 802. The insulating layer 826 functions as a gate insulating layer of the transistor 802. The conductive layer 827 functions as a gate electrode of the transistor 802. Further, an insulating layer 828 having a function as a protective layer and a planarizing film Alternatively, an insulating layer 829 having a function as a protective layer can be formed.

[0177] Note that the conductive layer 821 may be formed under the insulating layer 822. The conductive layer 8 functions as a second gate electrode (back gate electrode) of the transistor 802. When forming the wiring 819, an insulating layer 820 is formed on the wiring 819, and a conductive layer 821 is formed on the insulating layer 820. 21 can be formed. In addition, a part of the wiring 819 can be formed as the back gate of the transistor 802. The OS transistor having a back gate electrode can be, for example, as shown in FIG. 8, for example, transistors 102 to 104.

[0178] Note that, like the transistor 802, a transistor T is present with a semiconductor film sandwiched therebetween. If you have a pair of gates that are connected to each other, one gate will have signal A and the other gate will have a fixed A potential Vb may be applied.

[0179] The signal A is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that takes on two types of potential: potential V1 or potential V2 (V1>V2). For example, the potential V1 may be a high power supply potential, and the potential V2 may be a low power supply potential. The signal A may be an analog signal.

[0180] The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of the transistor T. The fixed potential Vb may be the potential V1 or the potential V2. This is preferable because it is not necessary to provide a separate potential generating circuit for generating the fixed potential Vb. The fixed potential Vb may be different from the potential V1 or the potential V2. In some cases, the threshold voltage VthA can be increased. As a result, the gate-source voltage V By reducing the drain current when gs is 0V, the leakage current of the circuit with transistor T is For example, the fixed potential Vb may be lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the potential Vb. Improve the drain current when the gate-source voltage Vgs is VDD, and the transistor T For example, the fixed potential Vb can be set higher than the low power supply potential. It may be made higher.

[0181] Also, a signal A is applied to one gate of transistor T, and a signal B is applied to the other gate. The signal B may be, for example, a signal for controlling the conductive or non-conductive state of the transistor T. Signal B has two types of potentials, potential V3 and potential V4 (V3>V4). For example, potential V3 may be a high power supply potential, and potential V4 may be a digital signal. may be a low power supply potential. Signal B may be an analog signal.

[0182] If signal A and signal B are both digital signals, signal B has the same digital value as signal A. In this case, the on-current of the transistor T is increased, and the transistor T In this case, the potential V1 of the signal A is higher than the potential V2 of the signal B. The potential V2 of the signal A may be different from the potential V3 of the signal B. For example, the gate insulating film corresponding to the gate to which the signal B is input may be If the gate insulating film is thicker than the gate insulating film corresponding to the input gate, the potential amplitude of signal B (V3-V 4) may be made larger than the potential amplitude (V1-V2) of signal A. The effect of signal A on the conductive or non-conductive state of transistor T and the effect of signal B on the conductive or non-conductive state of transistor T are shown in Fig. In some cases, the impact of the proposed amendment can be considered to be the same as that of the proposed amendment.

[0183] If signal A and signal B are both digital signals, signal B will have a different digital value than signal A. In this case, the control of the transistor T is different by the signal A and the signal B. For example, if a transistor T In the case of an n-channel type, when signal A is at potential V1 and signal B is at potential V3, When only signal A is in a conductive state, or when signal B is at potential V4, If the transistor is in a non-conducting state only when the transistor is turned on, a NAND circuit, a NOR circuit, etc. can be formed with one transistor. In addition, the signal B may be used to control the threshold voltage VthA. For example, the signal B may be a signal when the circuit having the transistor T is operating. Signal B may be a signal whose potential differs between a period when the circuit is in operation and a period when the circuit is not in operation. Alternatively, the signal B may have a different potential according to the operation mode of the circuit. The potential may not switch as frequently as in No. A.

[0184] If signal A and signal B are both analog signals, signal B is an analog input with the same potential as signal A. Signal A is an analog signal that multiplies the potential of signal A by a constant, or the potential of signal A is increased by a constant. In this case, the on-current of the transistor T may be This may improve the operating speed of the circuit having the transistor T. In this case, the control of the transistor T is the same as the signal A. This can be done separately by signal B, and higher functionality may be achieved.

[0185] Signal A may be a digital signal and signal B may be an analog signal. Signal B may be a digital signal.

[0186] In addition, one gate of the transistor T is connected to a fixed potential Va, and the other gate is connected to a fixed potential V b may be given. If both gates of the transistor T are given a fixed potential, There are cases where a resistor T can function as an element equivalent to a resistor element. For example, When the transistor T is an n-channel type, the fixed potential Va or the fixed potential Vb is set high (low). By reducing the resistance of the transistor, it may be possible to lower (higher) the effective resistance of the transistor. By making both the fixed potential Va and the fixed potential Vb high (low), the transistor has only one gate. In some cases, the effective resistance obtained is lower (higher) than that obtained by a small transistor. be.

[0187] The insulating layer 822 may be made of magnesium oxide, silicon oxide, silicon oxynitride, or silicon oxynitride. Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Contains one or more of tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide. The insulating layer 822 can be an insulating layer containing one or more of the above materials. Note that the insulating layer 822 may be formed by stacking the insulating layer 822 and the oxide semiconductor layer 824. The oxide semiconductor layer 824 preferably has an oxygen vacancy. This is because even if the oxygen vacancies are large, oxygen vacancies are repaired by oxygen supplied from the insulating layer. The treatment for supplying oxygen includes, for example, heat treatment.

[0188] An oxide semiconductor layer can be used as the oxide semiconductor layer 824. , Indium oxide, Tin oxide, Gallium oxide, Zinc oxide, In-Zn oxide, Sn-Zn Oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Z n-oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide , In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In- Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Z n-oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide , In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In- Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In-H f-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide , In-Sn-Hf-Zn oxide, and In-Hf-Al-Zn oxide. Ga-Zn oxide is preferred.

[0189] Here, In-Ga-Zn oxide refers to an oxide having In, Ga, and Zn as the main components. However, metal elements other than In, Ga, and Zn may be included as impurities. A film made of In-Ga-Zn oxide is also called an IGZO film.

[0190] The conductive layer 825 may be made of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, or the like. Conductive materials such as aluminum, zirconium, molybdenum, silver, manganese, tantalum, and tungsten Alternatively, alloys of the above materials or conductive nitrides of the above materials may be used. In addition, the present invention is directed to a method for manufacturing a semiconductor device using a plurality of materials selected from the group consisting of the above materials, alloys of the above materials, and conductive nitrides of the above materials. Typically, titanium, which is particularly prone to bonding with oxygen, and the following protons are used. Since the process temperature can be made relatively high, it is more convenient to use tungsten, which has a high melting point. It is also preferable to use a laminate of low-resistance copper or copper-manganese alloy and the above-mentioned material. A material that easily bonds to oxygen is used for the conductive layer 825. When the oxide semiconductor layer 824 comes into contact with the oxide semiconductor layer 824, a region having oxygen vacancies is formed in the oxide semiconductor layer 824. The hydrogen contained in the small amount of the material diffuses into the oxygen vacancy, causing the region to become significantly n-type. This n-type region functions as the source or drain region of the transistor. It is possible to do so.

[0191] The insulating layer 826 may be made of aluminum oxide, magnesium oxide, silicon oxide, or silicon oxynitride. Silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tungsten oxide The insulating layer 826 can be formed of one or more of the above materials. The insulating layer may be formed by laminating one or more kinds of insulating layers.

[0192] The conductive layer 827 may be made of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, or the like. Conductive materials such as aluminum, zirconium, molybdenum, silver, manganese, tantalum, and tungsten Alternatively, alloys of the above materials or conductive nitrides of the above materials may be used. In addition, the present invention is directed to a method for manufacturing a semiconductor device using a plurality of materials selected from the group consisting of the above materials, alloys of the above materials, and conductive nitrides of the above materials. It may be a laminate of materials.

[0193] The insulating layer 828 may be made of magnesium oxide, silicon oxide, silicon oxynitride, or silicon oxynitride. Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Contains one or more of tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide. The insulating layer 828 can be an insulating layer containing one or more of the above materials. may be laminated.

[0194] The insulating layer 829 is made of acrylic resin, epoxy resin, benzocyclobutene resin, polyimide, An organic material such as polyamide can be used. The insulating layer 817 can be formed of the above material. The insulating layer 829 may be formed by stacking an insulating layer containing the same material as the insulating layer 828. Fees may also be used.

[0195] [Photodiode 803] Next, the photodiode 803 will be described.

[0196] The photodiode 803 includes an n-type semiconductor layer 832, an i-type semiconductor layer 833, and a p-type semiconductor The i-type semiconductor layer 833 is made of amorphous silicon. In addition, the n-type semiconductor layer 832 and the p-type semiconductor layer 834 are preferably made of a material having electrical conductivity. Amorphous silicon or microcrystalline silicon containing impurities can be used. Photodiodes using CMOS are preferred because they have high sensitivity in the visible light wavelength range. In addition, the p-type semiconductor layer 834 serves as a light receiving surface, thereby increasing the output current of the photodiode. It is possible.

[0197] The n-type semiconductor layer 832 functioning as a cathode is connected to the conductive layer 82 of the transistor 802. 5 through the conductive layer 830. Also, a p-type The semiconductor layer 834 is connected to a wiring 837. It may also be connected to other wirings via the line 831 or the conductive layer 836. Alternatively, an insulating layer 835 having a function as a protective film can be formed.

[0198] As shown in FIG. 11A, a transistor 802 is stacked on a transistor 801. By stacking the diode 803 on the transistor 802, the area of ​​the semiconductor device is reduced. In addition, the transistor 801, the transistor 802, the photodiode By forming a structure having an overlapping region between the electrodes 803, the area of ​​the semiconductor device can be further reduced. can be reduced to

[0199] In FIG. 11A, the impurity region 812 and the conductive layer 825 are connected to each other. That is, one of the source or drain of the transistor 801 and the Although the structure in which either the source or the drain is connected is shown, the transistor 801 and the transistor The connection relationship of the transistor 802 is not limited to this. For example, as shown in FIG. The structure in which the conductive layer 814 and the conductive layer 825 are connected, i.e., the gate of the transistor 801. and one of the source and drain of the transistor 802 may be connected. can.

[0200] Although not shown here, the gate of the transistor 801 and the gate of the transistor 802 A structure in which one of the source or drain of the transistor 801 is connected to the transistor Alternatively, the gate of the transistor 802 may be connected.

[0201] As shown in FIG. 11C, the OS transistor is omitted, and the photodiode 803 The structure shown in FIG. 11C may be configured as follows: For example, when all the transistors in FIG. 2 are single crystal transistors, In this way, by omitting the OS transistor, the fabrication of a semiconductor device can be simplified. This allows for a reduction in the manufacturing process.

[0202] <Configuration example 2> In FIG. 11, a photodiode 803 is stacked on a transistor 802. However, the position of the photodiode 803 is not limited to this. As shown, a photodiode 803 is placed between transistors 801 and 802. It can also be provided in layers.

[0203] As shown in FIG. 12B, a photodiode 803 and a transistor 802 are In this case, the conductive layer 825 may be provided on the source electrode of the transistor 802. The electrode or drain electrode of the photodiode 803 can be used. .

[0204] As shown in FIG. 12C, a photodiode 803 is provided in the same In this case, the function of the gate electrode of the transistor 801 can be provided in the layer. A conductive layer 814 having a function as an electrode of the photodiode 803 and a wiring 831 having a function as an electrode of the photodiode 803 can be made simultaneously using the same materials.

[0205] <Configuration example 3> A plurality of transistors can also be formed using the semiconductor substrate 810. 2. An example in which a transistor 804 and a transistor 805 are formed using a semiconductor substrate 810 Shows.

[0206] The transistor 804 includes an impurity region 842 and an insulating layer 843 having a function as a gate insulating film. The transistor 805 has a gate electrode 843 and a conductive layer 844 having a function as a gate electrode. The gate insulating film 853 is formed of an impurity region 852 and a gate insulating film 853. The transistor 804 and the transistor The structure and material of the transistor 805 are similar to those of the transistor 801, and therefore a detailed description thereof will be omitted.

[0207] Here, the impurity region 842 contains an impurity element that imparts a conductivity type opposite to that of the impurity region 852. That is, the transistor 804 has an opposite polarity to the transistor 805. As shown in FIG. 13A, the impurity region 842 is connected to the impurity region 852. As a result, the transistor 804 and the transistor 805 can be The CMOS (Complementary Metal Oxide Semiconductor) A MOSFET can be used to configure an inverter.

[0208] By using the configuration of FIG. 13A, a transistor using a semiconductor substrate 810 1 and 10, the circuit 30, the circuit 40, the circuit 50, the circuit 60, the data processing unit 320, On these circuits, a pixel section 20 formed of an OS transistor is laminated. This makes it possible to reduce the area of ​​the semiconductor device.

[0209] In addition, as shown in FIG. 13B, a transistor 807 which is an OS transistor is a semiconductor In a structure stacked on a transistor 806 formed using a substrate 810, impurities The region 861 and the conductive layer 862 are connected to each other, i.e., the source of the transistor 806. Either the source or the drain of the transistor 807 is connected to either the source or the drain of the transistor 808. This allows a transistor formed using the semiconductor substrate 810 to be It is possible to construct a CMOS inverter using a gate-type transistor and an OS transistor.

[0210] The transistor 806 formed using the semiconductor substrate 810 has a Therefore, the transistor 806 is a p-channel transistor. and the transistor 807 is an n-channel transistor. As a result, two types of transistors with different polarities are formed on the semiconductor substrate 810. This makes it possible to form a CMOS inverter without any need for a semiconductor device. It is possible.

[0211] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0212] (Embodiment 5) In this embodiment, a configuration example of an imaging device to which a color filter or the like is added will be described.

[0213] FIG. 14A shows one embodiment in which a color filter or the like is added to the configuration shown in FIG. 11 to FIG. 13. FIG. 1 is a cross-sectional view of an example of a pixel circuit including three pixels (pixel 21a, pixel 21b, and pixel 21c). The photodiode 803 formed in the layer 1100 is covered with an insulating layer 1500. The insulating layer 1500 is formed using a silicon oxide film or the like that has high transparency to visible light. In addition, a silicon nitride film can be laminated as a passivation film. Alternatively, a dielectric film such as hafnium oxide may be laminated as the anti-reflection film. Good too.

[0214] A light-shielding layer 1510 is formed on the insulating layer 1500. The light-shielding layer 1510 is formed by The light blocking layer 1510 has a function of preventing the mixing of colors of the light passing through the filter. A metal layer such as tungsten or a dielectric film that functions as an anti-reflective film is laminated on the metal layer. The structure may be layered.

[0215] An organic resin layer 1520 is formed as a planarizing film on the insulating layer 1500 and the light-shielding layer 1510. The color filters 153 are disposed on the pixels 21a, 21b, and 21c, respectively. 0a, color filter 1530b and color filter 1530c are formed in pairs. The color filter 1530a, the color filter 1530b, and the color filter 1530c are The 530c can be assigned colors such as R (red), G (green), and B (blue) , a color image can be obtained.

[0216] Color filter 1530a, color filter 1530b, and color filter 1530c A microlens array 1540 is installed on top, and the light passing through one lens is reflected directly below The light passes through the filter and is then incident on the photodiode.

[0217] A support substrate 1600 is provided in contact with the layer 1400. The support substrate 1600 may be made of: Semiconductor substrates such as silicon substrates, glass substrates, metal substrates, ceramic substrates and other hard substrates In addition, an inorganic material serving as an adhesive layer may be provided between the layer 1400 and the support substrate 1600. An organic insulating layer or an organic resin layer may be formed.

[0218] In the configuration of the imaging device, the color filters 1530a, 1530b, and An optical conversion layer 1550 may be used instead of the color filter 1530c (FIG. 14( By using the optical conversion layer 1550, images in various wavelength regions can be obtained. It is possible to provide an imaging device that can

[0219] For example, if a filter that blocks light with wavelengths shorter than visible light is used for the optical conversion layer 1550, infrared In addition, the optical conversion layer 1550 can be used to block light having wavelengths of infrared rays or less. If a filter having such a structure is used, a far-infrared imaging device can be obtained. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. do.

[0220] In addition, if a scintillator is used for the optical conversion layer 1550, radiation such as medical X-ray imaging devices can be used. It is possible to make an imaging device that can obtain an image that visualizes the strength of lines. When radiation strikes a scintillator, it emits a large amount of light due to a phenomenon called photoluminescence. The light is converted into visible light, ultraviolet light, or other light (fluorescence). The light is then transmitted to a photodiode 8. Image data is obtained by detecting the object at 03.

[0221] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy and The material is made of a substance that emits visible or ultraviolet light or a material that contains such a substance. For example, Gd 2 O 2 S: Tb, Gd 2 O 2 S: Pr, Gd 2 O 2 S:Eu, BaFCl:Eu, NaI, C sI, CaF 2 , BaF2 , CeF 3 , LiF, LiI, ZnO, and other materials. It is known to be dispersed in resins or ceramics.

[0222] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0223] (Embodiment 6) In this embodiment, another configuration example of the semiconductor device 10 will be described.

[0224] 15A shows a configuration example of a pixel 21. The pixel 21 shown in FIG. 15A has the same structure as that shown in FIG. As the photoelectric conversion element 101 in the pixel 21, an element 900 having a selenium-based semiconductor is used. This is the configuration.

[0225] A device that uses a selenium-based semiconductor can convert a single irradiated photon into multiple electrons by applying a voltage. Photoelectric conversion is possible by utilizing the phenomenon of avalanche multiplication, which allows electrons to be extracted. Therefore, in the pixel 21 having the selenium-based semiconductor, the amount of electric current for the amount of incident light is This allows the amplification of the molecules to be increased, making it possible to produce a highly sensitive sensor. In photoelectric conversion elements that use materials as photoelectric conversion layers, the avalanche phenomenon is more likely to occur. It is preferable to apply a relatively high voltage (for example, 10 V or more). It is preferable to use OS transistors having a high drain withstand voltage for the transistors 102 to 104. It is.

[0226] The selenium-based semiconductor may be an amorphous selenium-based semiconductor or a crystalline selenium-based semiconductor. A selenium-based semiconductor having crystallinity can be used. The selenium-based semiconductor can be formed into a film and then heat-treated. By making the crystal grain size of the selenium-based semiconductor smaller than the pixel pitch, the characteristics of each pixel can be This is preferable because it reduces fluctuations and results in uniform image quality.

[0227] Selenium-based semiconductors, especially crystalline selenium-based semiconductors, have a high optical absorption coefficient over a wide wavelength range. Therefore, in addition to visible light and ultraviolet light, it can also detect X-rays and gases. It can be used as an imaging element for a wide range of wavelengths, including X-rays, gamma rays, etc. It is used as a so-called direct conversion element that can directly convert light in a short wavelength band such as It is possible.

[0228] 15B shows a configuration example of an element 900. The element 900 includes a substrate 901, an electrode 902, an optical The transistor 102 includes a power conversion layer 903 and an electrode 904. The electrode 904 is a The photoelectric conversion layer 90 is connected to one of the drains. 3, the electrode 904 is connected to the transistor 102. However, the number of the photoelectric conversion layers 903 and the electrodes 904 is not particularly limited, and may be one or more. Good too.

[0229] Light is incident on the side where the substrate 901 and the electrode 902 are provided toward the photoelectric conversion layer 903. Therefore, it is preferable that the substrate 901 and the electrode 902 have light-transmitting properties. A glass substrate can be used as the substrate 901. An indium substrate can be used as the electrode 902. For example, indium tin oxide (ITO) can be used.

[0230] The photoelectric conversion layer 903 contains selenium. Various selenium-based semiconductors are used for the photoelectric conversion layer 903. It is possible.

[0231] The photoelectric conversion layer 903 and the electrode 902 laminated on the photoelectric conversion layer 903 are arranged for each pixel 21. In either case, the shape can be used without processing. This can reduce the manufacturing cost and improve the manufacturing yield. do.

[0232] An example of a selenium-based semiconductor is a chalcopyrite-based semiconductor. is CuIn 1-x Ga x Se 2 (x is 0 to 1) (abbreviated as CIGS) CIGS can be formed by using a deposition method, a sputtering method, or the like.

[0233] When a chalcopyrite-based semiconductor is used as a selenium-based semiconductor, the voltage is several volts or more (5V to 20 By applying a voltage of about 1000 V, avalanche multiplication can be achieved. By applying a voltage to 903, the linearity of the movement of the signal charge caused by the irradiation of light is In addition, by setting the film thickness of the photoelectric conversion layer 903 to 1 μm or less, In addition, the transistors 102 to 104 are OS transistors. By doing so, even if the above voltage is applied, the pixel 21 can operate normally. It is possible.

[0234] In addition, if the thickness of the photoelectric conversion layer 903 is thin, a dark current may flow when a voltage is applied. A layer to prevent dark current from flowing in the chalcopyrite semiconductor CIGS mentioned above. By providing a hole injection barrier layer, the flow of dark current can be suppressed. FIG. 15B shows a structure in which a hole-injection barrier layer 905 is provided.

[0235] The hole injection barrier layer may be made of an oxide semiconductor. For example, gallium oxide is used. The thickness of the hole injection barrier layer may be smaller than the thickness of the photoelectric conversion layer 903. preferable.

[0236] As described above, by forming a sensor using a selenium-based semiconductor, a highly sensitive sensor can be obtained. Therefore, by combining with one aspect of the present invention, it is possible to realize a more accurate It becomes possible to acquire imaging data.

[0237] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0238] (Embodiment 7) In this embodiment, a structure of a transistor that can be used in the above embodiment will be described. I will explain it below.

[0239] <Transistor configuration example 1> FIG. 16A illustrates a structure of a transistor 400 that can be used in the above embodiment. The transistor 400 is formed on an insulating layer 401 with an insulating layer 402 and an insulating layer 403 interposed therebetween. In this example, the transistor 400 is a top-gate transistor. However, a transistor having a bottom gate structure may also be used.

[0240] The transistor 400 may be an inverted staggered transistor or a forward staggered transistor. It is also possible to sandwich the semiconductor layer in which the channel is formed between two gate electrodes. It is also possible to use a dual-gate transistor with a structure including a single Not limited to a transistor with a gate structure, but a multi-gate transistor having multiple channel formation regions The transistor may be a gate type transistor, for example a double gate type transistor.

[0241] The transistor 400 may be a planar type, a FIN type, or a TRI-GATE type. (Tri-gate type) and other configurations are also possible.

[0242] The transistor 400 includes an electrode 443 that can function as a gate electrode and a source electrode 444 . Electrode 444, which can function as either a source or drain electrode; The other electrode 445 can function as the drain electrode, and the other electrode 446 can function as the gate insulating layer. The semiconductor layer 421 includes an insulating layer 411 that can be used as a semiconductor layer.

[0243] The insulating layer 402 prevents the diffusion of impurities such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals. It is preferable to form the insulating film using an insulating film having a function of preventing the formation of the oxide film. Silicon oxide nitride, silicon nitride, silicon oxide nitride, gallium oxide, hafnium oxide Examples of such oxides include yttrium oxide, aluminum oxide, and aluminum oxide nitride. As insulating films, silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, and oxide By using aluminum or the like, impurities diffused from the insulating layer 401 side are diffused into the semiconductor layer 421 The insulating layer 402 can be formed by sputtering, C The insulating layer 402 can be formed by a method such as a vapor deposition method, a vapor deposition method, or a thermal oxidation method. The materials can be used in a single layer or in a laminate.

[0244] The insulating layer 403 is made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, or the like. gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Oxide materials such as tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as silicon nitride Nitride materials such as silicon oxynitride, aluminum nitride, and aluminum oxynitride The insulating layer 403 can be formed as a single layer or a multilayer. It can be formed by using a D method, a thermal oxidation method, a coating method, a printing method, or the like.

[0245] When an oxide semiconductor is used for the semiconductor layer 421, the insulating layer 402 must have a stoichiometric composition. It is preferable to form the insulating layer by using an insulating layer containing more oxygen than oxygen containing stoichiometric composition. When an insulating layer contains more oxygen than the oxygen required to fill the gap, some of the oxygen is released by heating. Insulating layers that contain more oxygen than is stoichiometric have a higher concentration of oxygen in the oxygen atoms in the TDS analysis. The converted amount of oxygen released is 1.0 x 10 18 atoms / cm 3 Above 3.0, preferably 3.0 ×10 20 atoms / cm 3 The insulating layer is as above. The surface temperature of the layer to be treated is 100°C to 700°C or 100°C to 500°C. The range is preferably:

[0246] In addition, an insulating layer that contains more oxygen than the stoichiometric composition is The treatment of adding oxygen can be carried out under an oxygen atmosphere. Heat treatment, ion implantation equipment, ion doping equipment, or plasma processing equipment is used. The gas for adding oxygen is:16 O 2 or 18 O 2 Acids such as The gas may be, for example, nitrogen gas, nitrous oxide gas, or ozone gas. The process of adding oxygen is also called "oxygen doping process."

[0247] The semiconductor layer 421 is a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a nanocrystalline semiconductor. The insulating film can be formed using a semi-amorphous semiconductor, an amorphous semiconductor, or the like. The material can be, for example, amorphous silicon or microcrystalline germanium. Uses compound semiconductors such as lithium arsenide, oxide semiconductors, and nitride semiconductors, as well as organic semiconductors. It is possible.

[0248] In this embodiment, an example in which an oxide semiconductor is used for the semiconductor layer 421 will be described. In the present embodiment, the semiconductor layer 421 is made up of a semiconductor layer 421a, a semiconductor layer 421b, and A case where a semiconductor layer 421c and a semiconductor layer 421b are laminated will be described.

[0249] The semiconductor layers 421a, 421b, and 421c are made of In or Ga. It can be formed of a material containing either one or both. Typically, In-Ga oxide ( In-Zn oxide (oxide containing In and Ga), In-M- Zn oxide (In, element M, and Zn oxide. Element M is Al, Ti, Ga, Y, One or more elements selected from Zr, La, Ce, Nd, or Hf that are more likely to react with oxygen than In. It is a metallic element with strong bonding strength.

[0250] The semiconductor layer 421a and the semiconductor layer 421c are formed by removing the metal elements constituting the semiconductor layer 421b. In particular, it is preferable that the material is made of a material containing one or more kinds of the same metal element. When the material is used, the interface between the semiconductor layer 421a and the semiconductor layer 421b and the semiconductor layer This can prevent the occurrence of interface states at the interface between the semiconductor layer 421c and the semiconductor layer 421b. This makes it difficult for carriers to be scattered or captured at the interface, and the field effect mobility of the transistor is improved. In addition, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. It becomes.

[0251] The thickness of the semiconductor layer 421a and the semiconductor layer 421c is preferably 3 nm or more and 100 nm or less. The thickness of the semiconductor layer 421b is set to be 3 nm or more and 50 nm or less. 0 nm or less, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm m or less.

[0252] The semiconductor layer 421b is an In-M-Zn oxide, and the semiconductor layer 421a and the semiconductor When the layer 421c is also an In-M-Zn oxide, the semiconductor layer 421a and the semiconductor layer 421 c = In:M:Zn=x 1 :y 1 :z 1 [Atomic ratio], semiconductor layer 421b is In:M:Z n=x 2 :y 2 :z 2 [Atomic ratio], y 1 / x 1 y 2 / x 2 is greater than The semiconductor layers 421a, 421c, and 421b are selected so as to For more information, see y 1 / x 1 y 2 / x2 The semiconductor layer 421a is 1.5 times larger than the , semiconductor layer 421c, and semiconductor layer 421b. More preferably, y 1 / x 1 y 2 / x 2 The semiconductor layer 421a, the semiconductor layer 421c, and the semiconductor layer 421b. More preferably, y 1 / x 1 y 2 / x 2 More than 3 The semiconductor layers 421a, 421c, and 421b are formed so that the At this time, in the semiconductor layer 421b, y 1 x 1 If the transistor This is preferable because it can provide stable electrical properties to y 1 x 1 When it becomes more than three times , the field effect mobility of the transistor is reduced, so y 1 x 1 Less than three times the By configuring the semiconductor layer 421a and the semiconductor layer 421c as described above, The dielectric layer 421a and the semiconductor layer 421c are less susceptible to oxygen deficiency than the semiconductor layer 421b. It can be a layer.

[0253] When the semiconductor layer 421a and the semiconductor layer 421c are made of In-M-Zn oxide, Z The content of In and element M, excluding n and O, is preferably less than 50 atomic % In. More preferably, the element M is 50 atomic % or more, and more preferably, the element In is less than 25 atomic %. The element M is 75 atomic % or more. When the oxide is a Zn-based alloy, the content of In and the element M, excluding Zn and O, is preferably 25% by weight. atomic % or more, element M is less than 75 atomic %, and more preferably In is 34a at least 66 atomic %, and element M is less than 66 atomic %.

[0254] For example, a semiconductor layer 421a containing In or Ga and a semiconductor layer 421c: In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6:4, Or In-Ga-Zn oxide formed using a target with an atomic ratio of 1:9:6, etc. In-Ga oxide formed using a target with an atomic ratio of In:Ga=1:9 In addition, In:Ga can be used as the semiconductor layer 421b. Zn=3:1:2, 1:1:1, 5:5:6, or 4:2:4.1 atomic ratio The In-Ga-Zn oxide formed using a target can be used. The atomic ratios of the inorganic layer 421a and the semiconductor layer 421b are calculated by subtracting the above atomic ratios from the atomic ratios as an error. This includes a fluctuation of plus or minus 20%.

[0255] In order to provide a transistor using the semiconductor layer 421b with stable electrical characteristics, The impurities and oxygen vacancies in the layer 421b are reduced to make the semiconductor layer 421b highly intrinsic. It is preferable that the oxide semiconductor layer be an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. The channel forming region in the semiconductor layer 421b is a semiconductor layer that can be regarded as intrinsic or substantially intrinsic. It is preferable to set the above.

[0256] Note that an oxide semiconductor layer that can be regarded as substantially intrinsic is an oxide semiconductor layer having a carrier density of , 1×10 17 / cm 3 Less than 1×10 15 / cm 3Less than or equal to 1 × 10 13 / cm 3 The term "oxide semiconductor layer" refers to an oxide semiconductor layer having a thickness of less than 100 nm.

[0257] Here, the semiconductor layer 421a, the semiconductor layer 421b, and the semiconductor layer 421c are stacked. The function and effect of the semiconductor layer 421 formed will be described with reference to the energy balance shown in FIG. The following will be explained using a band structure diagram. FIG. 16B is an energy band diagram of the channel of the transistor 400. 1 shows the energy band structure of the core formation region.

[0258] In Figure 16(B), Ec403, Ec421a, Ec421b, Ec421c, Ec411 are the insulating layer 403, the semiconductor layer 421a, the semiconductor layer 421b, and the semiconductor layer 421c, respectively. , indicates the energy of the bottom of the conduction band of the insulating layer 411.

[0259] Here, the difference between the vacuum level and the conduction band minimum energy (also called "electron affinity") is The energy difference between the vacant level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap from the spectroscopic ellipsometer ( It can be measured using HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI) It can be measured using a VersaProbe.

[0260] The In-Ga target with an atomic ratio of In:Ga:Zn=1:3:2 was used. The energy gap of a-Zn oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In addition, the In- The energy gap of Ga-Zn oxide is about 3.4 eV and the electron affinity is about 4.5 eV. In addition, the In was formed using a target with an atomic ratio of In:Ga:Zn=1:3:6. The energy gap of Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV. In addition, the I was formed using a target with an atomic ratio of In:Ga:Zn=1:6:2. The energy gap of n-Ga-Zn oxide is about 3.9 eV, and the electron affinity is about 4.3 eV. In addition, the film was formed using a target with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4.4 e V. In addition, a target with an atomic ratio of In:Ga:Zn=1:6:10 was used. The energy gap of the In-Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4. The energy of the target is 5 eV. The atomic ratio of In:Ga:Zn is 1:1:1. The energy gap of the synthesized In-Ga-Zn oxide is about 3.2 eV, and the electron affinity is about 4 .7 eV. In addition, a target with an atomic ratio of In:Ga:Zn=3:1:2 was used. The energy gap of the formed In-Ga-Zn oxide is about 2.8 eV, and the electron affinity is about It is 5.0 eV.

[0261] Since the insulating layer 403 and the insulating layer 411 are insulators, Ec403 and Ec411 are Closer to the vacuum level (lower electron affinity) than 1a, Ec421b, and Ec421c .

[0262] Also, Ec421a is closer to the vacuum level than Ec421b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0263] Also, Ec421c is closer to the vacuum level than Ec421b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0264] In addition, in the vicinity of the interface between the semiconductor layer 421a and the semiconductor layer 421b, and in the vicinity of the interface between the semiconductor layer 421b and the semiconductor layer 421c, In the vicinity of the interface with the semiconductor layer 421c, a mixed region is formed, so that the energy of the conduction band minimum That is, at these interfaces, the levels are almost nonexistent or nonexistent. stomach.

[0265] Therefore, in the stacked structure having the above energy band structure, the electrons Therefore, the interface between the semiconductor layer 421a and the insulating layer 401, Or, even if a level exists at the interface between the semiconductor layer 421c and the insulating layer 411, the level In addition, the boundary between the semiconductor layer 421a and the semiconductor layer 421b is There is almost no level at the interface between the semiconductor layer 421c and the semiconductor layer 421b. Therefore, the movement of electrons in the region is not hindered. The transistor 400 having a stacked conductor structure can achieve high field-effect mobility. Cut.

[0266] As shown in FIG. 16B, the interface between the semiconductor layer 421a and the insulating layer 403 and the semiconductor In the vicinity of the interface between the semiconductor layer 421c and the insulating layer 411, there are trap levels 49 due to impurities and defects. 0 can be formed, but due to the presence of the semiconductor layer 421a and the semiconductor layer 421c, Therefore, the semiconductor layer 421b can be separated from the trap level.

[0267] In particular, in the transistor 400 exemplified in this embodiment, the upper surface and the side surface of the semiconductor layer 421b are The lower surface of the semiconductor layer 421b is in contact with the semiconductor layer 421a. In this manner, the semiconductor layer 421b is covered with the semiconductor layer 421a and the semiconductor layer 421c. By forming the semiconductor layer in this manner, the influence of the trap levels can be further reduced.

[0268] However, if the energy difference between Ec421a or Ec421c and Ec421b is small, In this case, electrons in the semiconductor layer 421b may exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating layer, The threshold voltage of the transistor is shifted in the positive direction.

[0269] Therefore, the energy difference between Ec421a and Ec421c and Ec421b is When each of these is set to 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage of the transistor is Since the voltage fluctuation is reduced and the electrical characteristics of the transistor can be improved, I wish.

[0270] The band gaps of the semiconductor layer 421a and the semiconductor layer 421c are It is preferable that the band gap is wider than that of b.

[0271] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. Therefore, a semiconductor device with excellent performance can be realized.

[0272] In addition, the band gap of oxide semiconductors is 2 eV or more, so A transistor that uses an oxide semiconductor for a semiconductor layer can have an extremely small off-state current. Specifically, the off-current per 1 μm of channel width is 1×10 -20 A less than 1×10 -22 A, more preferably less than 1×10 -24 Less than A That is, the on / off ratio can be set to 20 digits or more and 150 digits or less.

[0273] According to one embodiment of the present invention, a transistor with low power consumption can be realized. Therefore, it is possible to realize an imaging device or a semiconductor device with low power consumption. According to one embodiment of the present invention, an imaging device or a semiconductor device having high light-receiving sensitivity can be realized. In addition, according to one aspect of the present invention, an imaging device or semiconductor device having a wide dynamic range can be realized. It is possible.

[0274] In addition, since an oxide semiconductor has a wide band gap, a semiconductor device using an oxide semiconductor is not available. According to one aspect of the present invention, an imaging device having a wide operating temperature range is provided. and a semiconductor device.

[0275] The above-mentioned three-layer structure is an example. For example, the semiconductor layer 421a or the semiconductor layer 421c Alternatively, a two-layer structure in which one of the layers is not formed may be used.

[0276] Oxide semiconductors applicable to the semiconductor layers 421a, 421b, and 421c An example of the oxide is an oxide containing indium. When indium is contained, the carrier mobility (electron mobility) increases. In addition, oxide semiconductors have the following properties: It is preferable to include the element M. The element M is preferably aluminum, gallium, yttrium, or the like. Other elements that can be used for element M include boron, silicon, and Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium However, the elements M are tungsten, neodymium, hafnium, tantalum, and tungsten. In some cases, the above elements may be combined. The element M may be, for example, a combination with oxygen. It is an element with high bond energy. Element M, for example, increases the energy gap of oxides. In addition, the oxide semiconductor preferably contains zinc. When an object contains zinc, for example, it becomes easier for the oxide to crystallize.

[0277] However, the oxide semiconductor is not limited to an oxide containing indium. For example, zinc tin oxide, gallium tin oxide, and gallium oxide may be used.

[0278] In addition, oxide semiconductors are made of oxides with a large energy gap. The energy gap is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more. The energy is set to 3.8 eV or less, and more preferably, to 3 eV or more and 3.5 eV or less.

[0279] The effect of impurities in an oxide semiconductor is described below. In order to stabilize the temperature, it is necessary to reduce the impurity concentration in the oxide semiconductor, to lower the carrier density, and It is effective to purify the oxide semiconductor. The carrier density of oxide semiconductor is 1×10 17 pieces / cm 3 Less than 1×10 15 pieces / cm 3 Less than or equal to 1 × 10 13 pieces / cm 3 Less than In particular, the carrier density in oxide semiconductors is 8×10 11 / cm 3 Less than or equal to 1 × 10 11 / cm 3 Less than or equal to 1 × 10 10 / cm 3 Less than or equal to 1×10 -9 / cm 3 In order to reduce the impurity concentration in the oxide semiconductor, It is preferable to also reduce the impurity concentration in adjacent films.

[0280] For example, silicon in an oxide semiconductor can become a carrier trap or a carrier generation source. Therefore, the silicon concentration in the oxide semiconductor is measured by secondary ion mass spectrometry (SIMS). Secondary Ion Mass Spectrometry (1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18 atoms / cm 3 Less than.

[0281] Furthermore, when hydrogen is contained in an oxide semiconductor, the carrier density may be increased. The hydrogen concentration of the oxide semiconductor was 2×10 20 atoms / cm 3 below, Preferably 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atom s / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 The following applies. Also, When nitrogen is contained in an oxide semiconductor, the carrier density may increase. The nitrogen concentration of the semiconductor is 5×10 19 atoms / cm 3 Less than, preferred Or 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0282] In order to reduce the hydrogen concentration in the oxide semiconductor, the insulating layer 403 in contact with the semiconductor layer 421 is It is preferable to reduce the hydrogen concentration in the insulating layer 403 and the insulating layer 411. The hydrogen concentration in the sample was 2×10 20 atoms / cm 3 Less than or equal to 5x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 below , and more preferably 5 × 10 18 atoms / cm 3 In addition, the oxide semiconductor In order to reduce the nitrogen concentration, it is preferable to reduce the nitrogen concentration in the insulating layer 403 and the insulating layer 411. The nitrogen concentration of the insulating layer 403 and the insulating layer 411 is preferably 5×10 1 9 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferred: Or 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0283] In this embodiment, first, a semiconductor layer 421a is formed on an insulating layer 403, and then the semiconductor layer 421 A semiconductor layer 421b is formed on the substrate 421a.

[0284] Note that the oxide semiconductor layer is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used. The sputtering method, or AC sputtering method, can form films with better uniformity than the RF sputtering method. can.

[0285] In the present embodiment, the semiconductor layer 421a is formed using an In-Ga-Zn oxide target (In :Ga:Zn=1:3:2) was used to deposit a 20 nm thick In-Ga The semiconductor layer 421a is formed of a-Zn oxide. The constituent elements and composition applicable to the semiconductor layer 421a are This is not limited to the above.

[0286] In addition, oxygen doping treatment may be performed after the semiconductor layer 421a is formed.

[0287] Next, a semiconductor layer 421b is formed on the semiconductor layer 421a. As the layer 421b, an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 ) to form a 30 nm thick In-Ga-Zn oxide film by sputtering. However, the constituent elements and compositions applicable to the semiconductor layer 421b are not limited to those mentioned above. stomach.

[0288] In addition, oxygen doping treatment may be performed after the semiconductor layer 421b is formed.

[0289] Next, impurities such as moisture or hydrogen contained in the semiconductor layers 421a and 421b are removed. In order to further reduce the amount of fluorine and to highly purify the semiconductor layers 421a and 421b, A heat treatment may be carried out.

[0290] For example, the method may be carried out under a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or an ultra-dry atmosphere. Dry air (measured using a CRDS (cavity ring down laser spectroscopy) type dew point meter The moisture content when the air is cooled should be 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. The semiconductor layer 421a and the semiconductor layer 421b are subjected to a fluorine-containing gas (air) atmosphere of preferably 10 ppb or less. The oxidizing atmosphere is an oxidizing atmosphere such as oxygen, ozone, or nitrogen oxide. An inert atmosphere is an atmosphere containing 10 ppm or more of oxidizing gases. This refers to an atmosphere in which the gas concentration is less than 10 ppm and which is filled with nitrogen or a rare gas.

[0291] In addition, by performing heat treatment, impurities are released and oxygen contained in the insulating layer 403 is also removed. The semiconductor layer 421a and the semiconductor layer 421b are diffused. It is possible to reduce the oxygen vacancy in 421b. In addition, after heat treatment in an inert gas atmosphere, Heat treatment is performed in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. Note that the heat treatment may be performed at any time after the formation of the semiconductor layer 421b. For example, heat treatment may be performed after selective etching of the semiconductor layer 421b.

[0292] The heat treatment is carried out at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. Processing time should be within 24 hours.

[0293] The heat treatment can be performed using an electric furnace, an RTA device, etc. Heat treatment can be performed at temperatures above the distortion point of the substrate for a short period of time. It can save time.

[0294] Next, a resist mask is formed on the semiconductor layer 421b. The insulating layer 421a and the semiconductor layer 421b are selectively etched. A part of the insulating layer 403 may be etched, forming a protrusion on the insulating layer 403 .

[0295] The semiconductor layer 421a and the semiconductor layer 421b can be etched by a dry etching method or a wafer etching method. After etching is completed, the resist mask is removed. Remove.

[0296] In addition, the transistor 400 has a semiconductor layer 421b and a gate insulating film 421c. , electrodes 444 and 445. The electrodes 444 and 445 are made of aluminum. , titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, manganese A single layer of metals such as silver, tantalum, or tungsten, or an alloy with these as the main component. For example, a single-layer structure of a copper film containing manganese can be used. , a two-layer structure in which an aluminum film is laminated on a titanium film, and an aluminum film on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film; Two-layer structure with copper film laminated on titanium film, two-layer structure with copper film laminated on tungsten film A titanium film or a titanium nitride film is laminated on the titanium film or the titanium nitride film by an aluminum film. A three-layer structure in which an aluminum or copper film is laminated and a titanium or titanium nitride film is formed on top of it. Structure, molybdenum film or molybdenum nitride film, and the molybdenum film or molybdenum nitride film An aluminum film or a copper film is laminated on the film, and a molybdenum film or a nitrogen film is further laminated on the aluminum film or a copper film. A three-layer structure is formed by forming a molybdenum oxide film, a copper film is laminated on a tungsten film, and a copper film is laminated on top of that. There are three-layer structures that form a tungsten film. In addition, titanium and tantalum are used on aluminum. tungsten, molybdenum, chromium, neodymium, and scandium. An alloy film or a nitride film having a combination of the above may also be used.

[0297] The transistor 400 also includes a semiconductor layer 421b, an electrode 444, and an electrode 445. The semiconductor layer 421c includes a semiconductor layer 421b, an electrode 444, and a conductor layer 421c. It contacts a portion of each of the electrodes 445 .

[0298] In this embodiment, the semiconductor layer 421c is grown using an In-Ga-Zn oxide target (In:Ga The semiconductor layer 42 is formed by a sputtering method using a metal oxide semiconductor (Zn:Zn=1:3:2). The constituent elements and compositions applicable to 1c are not limited to those described above. For example, a semiconductor layer Gallium oxide may be used as the semiconductor layer 421c. may be carried out.

[0299] The transistor 400 further includes an insulating layer 411 over the semiconductor layer 421c. The insulating layer 411 can function as a gate insulating layer. The insulating layer 411 may be formed by performing oxygen doping treatment. good.

[0300] After the semiconductor layer 421c and the insulating layer 411 are formed, a mask is formed on the insulating layer 411, and the semiconductor The insulating layer 411 and the semiconductor layer 421c are selectively etched to form an island-shaped semiconductor layer 42 1c, and an island-shaped insulating layer 411 may also be used.

[0301] The transistor 400 also has an electrode 443 on the insulating layer 411. The electrodes 444 and 445 are the same as the electrodes 444 and 445. The material and method can be used to form the above-mentioned.

[0302] In this embodiment, an example in which the electrode 443 is a laminate of the electrodes 443a and 443b is shown. For example, the electrode 443a is made of tantalum nitride, and the electrode 443b is made of copper. 443a acts as a barrier layer to prevent the diffusion of copper elements. Therefore, a high-performance semiconductor device can be realized.

[0303] The transistor 400 further includes an insulating layer 412 that covers the electrode 443. The insulating layer 412 can be formed using a material and a method similar to those of the insulating layer 403. An elemental doping process may be performed. Also, the surface of the insulating layer 412 may be subjected to a CMP process.

[0304] In addition, an insulating layer 413 is provided over the insulating layer 412. The insulating layer 413 has the same structure as the insulating layer 403. The insulating layer 413 can be formed by performing a CMP process on the surface of the insulating layer 413. By performing CMP, the unevenness of the sample surface is reduced, and the insulating film formed later is The coverage of the conductive layer can be improved.

[0305] <Transistor configuration example 2> Next, a transistor configuration that can be used in place of the transistor 400 described above is An example will be described with reference to FIGS.

[0306] [Bottom-gate transistor] The transistor 510 illustrated in FIG. 17A1 is a bottom-gate transistor. The transistor 510 is a channel protection transistor having an insulating layer 403. The semiconductor device has an electrode 446 that can function as a gate electrode. In addition, an insulating layer 411 is formed on the electrode 446. The electrode 446 has a semiconductor layer 421 therebetween. The method can be formed by the method.

[0307] In addition, the transistor 510 includes a channel protection layer on a channel formation region of the semiconductor layer 421. The insulating layer 450 can function as a heat sink. The insulating layer 450 can be made of the same material as the insulating layer 411. A part of the electrode 444 and a part of the electrode 445 can be formed by the following method. It is formed on an insulating layer 450 .

[0308] By providing an insulating layer 450 on the channel formation region, the electrodes 444 and 445 are formed. Therefore, the electrode 444 and the electrode 445 can be prevented from being exposed. This can prevent the semiconductor layer 421 from being thinned during the formation of the insulating layer 45. A transistor with good electrical characteristics can be realized.

[0309] The transistor 511 shown in FIG. 17A2 has a back gate electrode over the insulating layer 412. The transistor 510 differs from the transistor 510 in that it has a functioning electrode 451. The electrodes 444 and 445 can be formed using the same materials and methods.

[0310] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can function in the same manner as the gate electrode. Alternatively, the back gate electrode may be set to the GND potential or any other potential. By changing the potential of the gate electrode independently, the threshold voltage of the transistor can be controlled. The pressure can be varied.

[0311] Both the electrode 446 and the electrode 451 can function as a gate electrode. The insulating layer 411, the insulating layer 450, and the insulating layer 412 function as a gate insulating layer. It is possible.

[0312] When one of the electrodes 446 and 451 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 511, the electrode 451 is When referring to a "gate electrode," the electrode 446 may be referred to as a "back gate electrode." When the electrode 451 is used as a “gate electrode”, the transistor 511 is a top gate. In addition, the electrodes 446 and 451 can be considered as a type of transistor. One of them may be called the "first gate electrode" and the other the "second gate electrode." be.

[0313] By providing the electrode 446 and the electrode 451 with the semiconductor layer 421 interposed therebetween, 6 and the electrode 451 are set to the same potential, the region in which carriers flow in the semiconductor layer 421 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 511 increases, the field effect mobility also increases.

[0314] Therefore, the transistor 511 is a transistor having a large on-current relative to its area. That is, the area occupied by the transistor 511 is set to the required on-current. According to one aspect of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0315] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity The back gate electrode is larger than the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0316] In addition, the electrodes 446 and 451 each have a function of blocking an electric field from the outside. Therefore, the electric charges of the charged particles generated on the insulating layer 403 side or above the electrode 451 are transferred to the semiconductor layer 4 As a result, the channel formation region of 21 is not affected. Applying electric charge - GBT (Gate Bias-Temperature) stress test ) degradation is suppressed, and the on-current rise voltage at different drain voltages is This effect is achieved when the electrodes 446 and 451 are of the same voltage. This occurs when the potentials are the same or different.

[0317] The BT stress test is a type of accelerated test that measures the transistor damage caused by long-term use. The change in the characteristics of the BT (i.e., aging) can be evaluated in a short time. The amount of change in the threshold voltage of a transistor before and after a stress test is used to check reliability. The smaller the change in threshold voltage before and after the BT stress test, the Therefore, it can be said that this is a highly reliable transistor.

[0318] In addition, the electrode 446 and the electrode 451 are provided, and the electrode 446 and the electrode 451 are set to the same potential. This reduces the amount of variation in threshold voltage. At the same time, the variation in electrical characteristics caused by the semiconductor device is reduced.

[0319] In addition, a transistor with a back gate electrode is called a +GBT, which applies a positive charge to the gate. The change in threshold voltage before and after the stress test was also observed for transistors without a back gate electrode. Smaller than Sta.

[0320] In addition, when light is incident from the back gate electrode side, the back gate electrode is made of a material having a light blocking property. By forming the semiconductor layer from a conductive film, light is prevented from entering the semiconductor layer from the back gate electrode side. This prevents the semiconductor layer from being photodegraded and the threshold voltage of the transistor is shifted. This can prevent deterioration of electrical characteristics such as the occurrence of

[0321] According to one embodiment of the present invention, a transistor with high reliability can be provided. A highly reliable semiconductor device can be realized.

[0322] The transistor 520 illustrated in FIG. 17B1 is a bottom-gate transistor. The transistor 520 is a channel protection transistor. 0, except that an insulating layer 450 covers the semiconductor layer 421. In addition, a portion of the insulating layer 450 overlapping the semiconductor layer 421 is selectively removed to form an opening. At the opening, the semiconductor layer 421 and the electrode 444 are electrically connected. In the opening formed by selectively removing a portion of the insulating layer 450 overlapping with the semiconductor layer 21, The insulating layer 450 overlaps with the channel forming region. The region can function as a channel protection layer.

[0323] The transistor 521 illustrated in FIG. 17B2 has a back gate electrode over the insulating layer 412. The transistor 520 differs from the transistor 520 in that it has a functioning electrode 451. The electrode 451 can both function as a gate electrode. The insulating layer 450 and the insulating layer 412 can function as gate insulating layers.

[0324] In addition, the transistors 520 and 521 are the same as the transistors 510 and The distance between the electrodes 444 and 446 and the distance between the electrodes 445 and 446 are smaller than the distance between the electrodes 444 and 446. Therefore, the parasitic capacitance between the electrodes 444 and 446 is reduced. In addition, the parasitic capacitance between the electrodes 445 and 446 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.

[0325] [Top-gate transistor] The transistor 530 illustrated in FIG. 18A1 is a top-gate transistor. The transistor 530 has a semiconductor layer 421 on an insulating layer 403. 21 and the insulating layer 403, an electrode 444 in contact with a part of the semiconductor layer 421 and a semiconductor layer The semiconductor layer 421 has an electrode 445 in contact with a part of the electrode 444. 5, an insulating layer 411 is provided on the insulating layer 411, and an electrode 446 is provided on the insulating layer 411.

[0326] Transistor 530 is connected between electrode 446 and electrode 444, and between electrode 446 and electrode 446. Since the electrodes 446 and 444 do not overlap, the parasitic capacitance between the electrodes 446 and 444 and the The parasitic capacitance between the electrode 446 and the electrode 445 can be reduced. After forming the semiconductor layer 421, the electrode 446 is used as a mask to introduce an impurity element 455 into the semiconductor layer 421. By introducing the impurity into the semiconductor layer 421, an impurity region is formed in a self-aligned manner in the semiconductor layer 421. According to one embodiment of the present invention, the electrical characteristics of the A good transistor can be realized.

[0327] The impurity element 455 is introduced by an ion implantation device, an ion doping device, or a plasma The ion doping can be performed using a mass separator. Alternatively, an ion doping device having such a function may be used.

[0328] The impurity element 455 may be, for example, at least one of Group 13 elements or Group 15 elements. In addition, when an oxide semiconductor is used for the semiconductor layer 421, In this case, the impurity element 455 is at least one of a rare gas, hydrogen, and nitrogen. It is also possible to use elements.

[0329] The transistor 531 shown in FIG. 18A2 has an electrode 451 and an insulating layer 417. The transistor 531 is formed on the insulating layer 403. The electrode 451 is provided, and an insulating layer 417 is formed on the electrode 451. The electrode 451 can function as a back gate electrode. The insulating layer 417 can function as a gate insulating layer. and methods.

[0330] Like the transistor 511, the transistor 531 has a large on-current relative to its area. That is, for the required on-current, the transistor 5 According to one aspect of the present invention, the area occupied by the transistor 31 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0331] The transistor 540 illustrated in FIG. 18B1 is a top-gate transistor. The transistor 540 is formed by forming the semiconductor layer 4 after forming the electrodes 444 and 445. The transistor 530 differs from the transistor 530 in that the transistor 21 is formed. The transistor 541 has an electrode 451 and an insulating layer 417. In the transistor 540 and the transistor 541, A portion of the semiconductor layer 421 is formed on an electrode 444 , and another portion of the semiconductor layer 421 is formed on an electrode 445 .

[0332] Like the transistor 511, the transistor 541 has a large on-current relative to its area. That is, for the required on-current, the transistor 5 According to one aspect of the present invention, the area occupied by the transistor 41 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0333] After forming the electrode 446, the transistor 540 and the transistor 541 are also connected to the electrode 44. 6 as a mask to introduce an impurity element 455 into the semiconductor layer 421, According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner in the semiconductor substrate 421. A transistor with favorable electrical characteristics can be realized. This makes it possible to realize a highly integrated semiconductor device.

[0334] [s-channel transistor] In the transistor 550 illustrated in FIG. 19, the upper surface and side surfaces of the semiconductor layer 421b are 19A is a top view of the transistor 550. 19(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 19(A) (channel FIG. 19(C) is a cross-sectional view in the longitudinal direction. 4 is a cross-sectional view (cross-sectional view in the channel width direction) of the portion.

[0335] By providing the semiconductor layer 421 on the protrusions provided on the insulating layer 403, the semiconductor layer 421b The side surface of the transistor 550 can also be covered with the electrode 443. The semiconductor layer 421b can be electrically surrounded by the electric field. In this way, the structure of a transistor in which the semiconductor is electrically surrounded by the electric field of the conductive film is This is called a surrounded channel (s-channel) structure. A transistor with a channel structure is also called an "s-channel transistor." It is also called an "s-channel transistor."

[0336] In the s-channel structure, a channel is formed in the entire semiconductor layer 421b (bulk). In the s-channel structure, the drain current of the transistor is increased. In addition, the electric field of the electrode 443 can be used to obtain a larger on-state current. As a result, the entire channel formation region formed in the semiconductor layer 421b can be depleted. Therefore, in the s-channel structure, the off-state current of the transistor can be further reduced. It is possible.

[0337] In addition, by making the protrusion of the insulating layer 403 high and reducing the channel width, The n-nel structure can increase the on-current and reduce the off-current. In addition, when forming the semiconductor layer 421b, the exposed semiconductor layer 421a may be removed. In this case, the side surfaces of the semiconductor layer 421a and the semiconductor layer 421b may be aligned.

[0338] 20, an insulating layer 40 is provided below a semiconductor layer 421. 20A is a top view of the transistor 551. FIG. 20(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 20(A). FIG. 20(C) is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. 20(A). do.

[0339] In addition, as in the case of a transistor 452 shown in FIG. 21, a layer 414 is provided above an electrode 443. FIG. 21A is a top view of the transistor 452. FIG. FIG. 21(C) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 4A is a cross-sectional view of the portion indicated by the dashed dotted line Y1-Y2 in FIG.

[0340] In FIG. 21, the layer 414 is provided on the insulating layer 413, but it may be provided on the insulating layer 412. By forming the layer 414 using a material having a light-shielding property, the characteristics of the transistor due to light irradiation can be improved. The layer 414 is made of at least the semiconductor layer 4. By forming the layer 414 larger than the semiconductor layer 421b and covering the semiconductor layer 421b, the above effect can be enhanced. The layer 414 can be made of an organic material, an inorganic material, or a metal material. Also, when the layer 414 is made of a conductive material, a voltage can be applied to the layer 414. Alternatively, the capacitor may be in an electrically floating state.

[0341] <Structure of oxide semiconductor> Next, the structure of the oxide semiconductor will be described.

[0342] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. In the specification, when the crystals are trigonal or rhombohedral, they are referred to as hexagonal.

[0343] Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors are divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. do.

[0344] Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors. Crystalline oxide semiconductors include single crystal semiconductors and amorphous oxide semiconductors. crystalline oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, etc. .

[0345] [CAAC-OS] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0346] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0347] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0348] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0349] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, InGaZnO 4 CAAC-OS film with crystals In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak may appear in InGaZnO 4 It is assigned to the (009) plane of the crystal of From this, it can be seen that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0350] In addition, InGaZnO 4 Out-of-plane synthesis of CAAC-OS films with crystallites In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0351] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0352] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0353] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0354] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0355] [Microcrystalline oxide semiconductor film] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0356] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. When this is done, a circular (ring-shaped) area of ​​high brightness may be observed. Nanobeam electron diffraction of the nc-OS film revealed multiple spots within the ring-shaped region. It may be observed.

[0357] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0358] [Amorphous oxide semiconductor film] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0359] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0360] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0361] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Oxide Semiconductor (a-like OS) The conductor membrane is called the endothelium.

[0362] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may be clearly visible in high-resolution TEM images. The a-like OS film has a region in which a crystal part is not observed and a region in which a crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed in TEM observations, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be observed. Almost no crystallization due to electron irradiation was observed.

[0363] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO 4 The crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. 4 Crystal unit cell of The layer has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is therefore the (009) plane. This is approximately the same as the lattice spacing (also called the d value), and crystal structure analysis has determined that this value is 0.29 nm Therefore, we focused on the lattice fringes in high-resolution TEM images and In the region where the distance is between 0.28 nm and 0.30 nm, the lattice fringes are InG aZnO 4 This corresponds to the ab plane of the crystal.

[0364] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the membrane is known, the density can be determined by comparing it with that of a single crystal of the same composition. The structure of the oxide semiconductor film can be estimated. The density of the OS-like film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film was 92.3% or more. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is The film formation itself is difficult.

[0365] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor film that satisfies the [number ratio], single crystal InGaZnO having a rhombohedral crystal structure 4 The density of is 6.357g / cm 3Therefore, for example, In:Ga:Zn=1:1:1 In the oxide semiconductor film that satisfies the atomic ratio, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1: In the oxide semiconductor film that satisfies the atomic ratio of 1, the density of the nc-OS film and the CAAC- The density of the OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0366] In some cases, single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. However, the density should be calculated using as few types of single crystals as possible. It is preferable to perform the calculation in combination.

[0367] Note that the oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a microcrystalline oxide semiconductor film. The semiconductor layer may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0368] By the way, even if the oxide semiconductor film is a CAAC-OS film, it is possible to partially form an nc-OS film. Therefore, the CAAC-OS film is considered to have a good diffraction pattern. The ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (C It can be expressed as the AAC conversion rate. For example, a good quality CAAC-OS In the case of a membrane, the CAAC content is 50% or more, preferably 80% or more, and more preferably 90% or more. It is preferably 0% or more, and more preferably 95% or more.

[0369] <Off-state current> In this specification, unless otherwise specified, the off-state current is the current that flows when a transistor is in an off state (non-conducting state). The drain current when the device is in the on or off state. In the absence of a gate-source voltage Vgs threshold, an n-channel transistor In a p-channel transistor, the gate-source voltage Vth is lower than the threshold voltage Vth. This refers to the state in which the voltage Vgs is higher than the threshold voltage Vth. For example, in an n-channel transistor, The off-state current of a transistor is the time when the gate-source voltage Vgs is lower than the threshold voltage Vth. In some cases, it refers to the drain current when

[0370] The off-state current of a transistor may depend on Vgs. When there exists a Vgs where the off-current is I or less, the off-current of the transistor is I or less. The off-state current of a transistor is the off-state current when Vgs is at a certain value, The off-state current when Vgs is within a certain range, or when Vgs is sufficiently reduced The term "off-state current" may refer to the value at which the off-state current is obtained.

[0371] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The input current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 - 13 A, and the drain current at Vgs of -0.5 V is 1×10 -19 A and V The drain current at gs of -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: Or, when Vgs is in the range of -0.5V to -0.8V, 1×10 -19 Below A Therefore, the off-current of the transistor is 1×10 -19 There are cases where it is less than A. The drain current of the transistor is 1×10 -22 There exists a Vgs below A Therefore, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0372] In this specification, the off-state current of a transistor having a channel width W is expressed as It may be expressed as a current value per a given channel width (e.g., 1 μm). In the latter case, the unit of the off-state current is expressed as current / length (e.g., A / μm). There are cases.

[0373] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the off-state current is measured at room temperature, 60℃, 85℃, 95℃, or 125℃. Or, the reliability of the semiconductor device containing the transistor may be in doubt. or the temperature at which a semiconductor device or the like that includes the transistor is used (for example, For example, the off-state current at room temperature may be expressed as the off-state current at any one of temperatures from 5°C to 35°C. 60℃, 85℃, 95℃, 125℃, reliability of semiconductor devices containing the transistor or the temperature at which a semiconductor device or the like including the transistor is used. (For example, any one of temperatures from 5° C. to 35° C.) When there exists a Vgs below which the off-state current of the transistor is I or less, There is a match.

[0374] The off-state current of a transistor may depend on the voltage Vds between the drain and source. In this specification, unless otherwise specified, the off-state current is measured when the absolute value of Vds is 0.1 V, 0. 8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V or the off-state current at 20 V. Vds that guarantees the reliability of the semiconductor device or semiconductor device that includes the transistor It may also refer to the off-state current at a given Vds used in semiconductor devices. If there exists a Vgs at which the off-state current of the transistor is I or less when It is sometimes said that the off-current of a transistor is equal to or less than I. Here, the predetermined value is, for example, , 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V , 12V, 16V, 20V, the reliability of semiconductor devices containing the transistors is guaranteed. The value of Vds used in a semiconductor device that includes the transistor is the value of Vds.

[0375] In the above description of the off-state current, the drain may be read as the source. may also refer to the current that flows through the source when the transistor is in the off state.

[0376] In this specification, the term "leakage current" may be used to mean the same thing as the off-state current.

[0377] In this specification, the off-state current is, for example, the current that flows through a source when a transistor is in an off state. It can also refer to the current that flows between the source and drain.

[0378] <Film formation method> The various films disclosed in this specification, such as metal films, semiconductor films, and inorganic insulating films, can be formed by sputtering or plating. It can be formed by plasma CVD, but other methods, such as thermal CVD (Chemical Vapor Deposition), can also be used. Alternatively, the insulating layer may be formed by a thermal CVD method. As an example, MOCVD (Metal Organic Chemical Vapor Deposition) deposition) method and ALD (Atomic Layer Deposition) You can use the law.

[0379] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0380] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the pressure inside the chamber is raised to atmospheric pressure. The film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing them on the substrate. It is also possible.

[0381] In addition, in the ALD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially The gas may then be introduced into the chamber, and the gas introduction sequence may be repeated to form a film. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction sequence until a thin film of the desired thickness is formed. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film depends on the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. Suitable for making thin FETs (Field Effect Transistors). is.

[0382] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga In the case of forming a -Zn-O film, trimethylindium, trimethylgallium, and dimethyl Methyl zinc is used. The chemical formula for trimethylindium is In(CH 3 ) 3 is The chemical formula for trimethylgallium is Ga(CH 3 ) 3 Also, dimethyl zinc The chemical formula is Zn(CH 3 ) 2 In addition, the combination is not limited to these, and may be any combination. Instead of triethylgallium, triethylgallium (chemical formula Ga(C 2 H 5 ) 3 ) can also be used. Dimethyl zinc can be replaced by diethyl zinc (chemical formula Zn(C 2 H 5 ) 2 ) can also be used. can.

[0383] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethylamine, etc.) The raw material gas is vaporized hafnium amide (TDMAH, etc.) and oxidized As an agent, ozone (O 3 Two types of gases are used: tetrakisdimethylamide hafnium The chemical formula for nium is Hf[N(CH 3 ) 2 ] 4 In addition, other material liquids include tetrahydrofuran. Examples include kis(ethylmethylamido)hafnium.

[0384] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor compound (e.g., trimethylaluminum (TMA)) The raw gas is oxidized and H 2 Two types of gases are used: trimethylammonia, trimethylphenylacetone, and trimethylphenylacetone. The chemical formula for aluminum is Al(CH 3 ) 3 Other liquid materials include Tris(diisopropyl alcohol, Methylamido)aluminum, triisobutylaluminum, aluminum tris(2, 2,6,6-tetramethyl-3,5-heptanedionate).

[0385] For example, when forming a silicon oxide film using a deposition system that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O 2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0386] For example, when forming a tungsten film using a deposition system that uses ALD, the WF6 G S and B 2 H 6 The gases are introduced repeatedly in sequence to form an initial tungsten film, and then WF 6 Gas and H 2 A tungsten film is formed using gas. 2 H 6 Instead of gas, SiH 4 A gas may also be used.

[0387] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH 3 ) 3 Gas and O 3 Gases were introduced repeatedly in sequence to O layer, and then Ga(CH 3 ) 3 Gas and O 3 A GaO layer is formed using a gas, and Then Zn(CH 3 ) 2 Gas and O 3 The ZnO layer is formed using these gases. The order of layers is not limited to this example. In addition, by mixing these gases, In-Ga-O layers and In-Z layers can be formed. Alternatively, a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer may be formed. 3 Change to gas In addition, H obtained by bubbling water with an inert gas such as Ar 2 O gas may be used, but H Does not contain O 3 It is preferable to use In(CH 3 ) 3 Instead of gas, In (C 2 H 5 ) 3 Gas may also be used. 3 ) 3 Instead of gas, Ga(C 2 H 5 )3 Gas may also be used. 3 ) 2 A gas may also be used.

[0388] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0389] (Embodiment 8) In this embodiment, an example of an electronic device using an imaging device according to one embodiment of the present invention will be described. do.

[0390] Examples of electronic devices using an imaging device according to one embodiment of the present invention include display devices such as televisions and monitors, Lighting equipment, desktop or notebook personal computers, word processors The digital content is stored on a recording medium such as a DVD (Digital Versatile Disc). Image reproducing devices that reproduce still or moving images, portable CD players, radios, tape recorders, etc. Coders, headphone stereos, stereos, navigation systems, table clocks, wall-mounted clocks meters, cordless telephone handsets, transceivers, mobile phones, car phones, portable game consoles, tabs Laptop terminals, large game machines such as pachinko machines, calculators, personal digital assistants, electronic organizers, electronic books Registration terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shakers microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, water heaters, fans Fans, hair dryers, air conditioners, humidifiers, dehumidifiers and other air conditioning equipment, dishwashers , dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, D Freezers for storing NA, flashlights, tools such as chainsaws, smoke detectors, medical equipment such as dialysis machines , fax machines, printers, printer-combined machines, automated teller machines (ATMs), In addition, emergency lights, traffic lights, conveyor belts, elevators, escalators, etc. For calators, industrial robots, power storage systems, power leveling and smart grids In addition, fuel-powered engines and non-aqueous secondary batteries are also examples of Electric motors using electricity from the sun and vehicles propelled by engines using fuel are also electronically The above-mentioned mobile objects include, for example, electric vehicles (EVs), Hybrid vehicles (HEVs) that combine a combustion engine and an electric motor, plug-in hybrid vehicles (P HEVs, tracked vehicles that use these tires and wheels as tracks, and electric-assisted bicycles. Motorbikes, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines , helicopters, airplanes, rockets, satellites, space probes, planetary probes, spacecraft, etc. Some examples include:

[0391] FIG. 22A shows a video camera, which includes a first housing 1041, a second housing 1042, and a display unit 1043. 43, an operation key 1044, a lens 1045, a connection part 1046, etc. 4 and a lens 1045 are provided in a first housing 1041, and a display unit 1043 is provided in a second housing. The first housing 1041 and the second housing 1042 are connected to each other. The first housing 1041 and the second housing 1042 are connected by a portion 1046, and the angle between the first housing 1041 and the second housing 1042 is The image on the display unit 1043 can be changed by the connection unit 1046. 6, the switch is configured to switch according to the angle between the first housing 1041 and the second housing 1042. The imaging device according to one embodiment of the present invention may be provided at the focal position of the lens 1045. This can be done.

[0392] FIG. 22B shows a mobile phone. A housing 1051 includes a display unit 1052, a microphone 1057, and a speaker. Speaker 1054, camera 1059, input / output terminal 1056, operation button 1055, etc. The imaging device of one embodiment of the present invention can be used as the camera 1059.

[0393] FIG. 22C shows a digital camera, which includes a housing 1021, a shutter button 1022, a microphone, and a microphone unit. The lens 1025 has a focus 1023, a light emitting portion 1027, and a lens 1025. The position may be equipped with an imaging device according to one aspect of the present invention.

[0394] FIG. 22D shows a portable game machine, which includes a housing 1001, a housing 1002, a display unit 1003, Display unit 1004, microphone 1005, speaker 1006, operation keys 1007, stylus 1008, and a camera 1009. The portable game machine shown in FIG. The device has two display units 1003 and 1004. The number of units is not limited to this. The camera 1009 uses an imaging device according to one embodiment of the present invention. It is possible.

[0395] FIG. 22E shows a wristwatch-type information terminal, which includes a housing 1031, a display unit 1032, a wristband, and The display unit 1032 may be a touch panel. The imaging device according to one embodiment of the present invention can be used as the camera 1039.

[0396] FIG. 22(F) shows a portable data terminal, which includes a first housing 1011, a display unit 1012, and a camera 10. The display unit 1012 has a touch panel function for inputting and outputting information. The imaging device of one embodiment of the present invention can be used as the camera 1019.

[0397] Note that the electronic device is not limited to the above-described electronic devices as long as it includes the imaging device according to one embodiment of the present invention. Needless to say, this is not possible.

[0398] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes. [Explanation of symbols]

[0399] 10 Semiconductor device 20 Pixel section 21 pixels 30 Circuit 40 Circuits 41 Circuit 50 circuits 60 Circuits 101 Photoelectric conversion element 102 Transistor 103 Transistor 104 Transistor 105 capacity 110 Transistor 120 Transistor 201 Conductive layer 202 Conductive layer 203 Conductive layer 204 Conductive layer 211 Conductive layer 212 Conductive layer 221 Semiconductor layer 222 Semiconductor layer 231 Conductive Layer 232 Conductive Layer 233 Conductive Layer 234 Conductive Layer 241 Conductive Layer 242 Conductive Layer 243 Conductive Layer 250 Conductive Layer 251 Opening 252 Opening 253 Opening 254 Opening 255 opening 256 Openings 257 Opening 300 Imaging device 310 Light detection unit 320 Data Processing Unit 321 Circuit 400 Transistors 401 Insulating layer 402 Insulating layer 403 Insulating layer 411 Insulating layer 412 Insulating layer 413 Insulating Layer 414 layers 417 Insulating Layer 421 Semiconductor Layer 443 Electrode 444 Electrode 445 Electrode 446 Electrode 450 Insulation layer 451 Electrode 452 Transistor 455 Impurity elements 490 Trap Level 510 Transistor 511 Transistor 520 Transistor 521 Transistor 530 Transistor 531 Transistor 540 Transistor 541 Transistor 550 Transistor 551 Transistor 801 Transistors 802 Transistor 803 Photodiode 804 Transistor 805 Transistor 806 Transistor 807 Transistor 810 Semiconductor Substrate 811 Element isolation layer 812 Impurity region 813 Insulating layer 814 Conductive layer 815 Sidewall 816 Insulating layer 817 Insulating layer 818 Conductive layer 819 Wiring 820 Insulating layer 821 Conductive layer 822 Insulating layer 823 Conductive layer 824 Oxide semiconductor layer 825 Conductive Layer 826 Insulating layer 827 Conductive Layer 828 Insulating layer 829 Insulating layer 830 Conductive layer 831 Wiring 832 n-type semiconductor layer 833 i-type semiconductor layer 834 p-type semiconductor layer 835 Insulation Layer 836 Conductive layer 837 Wiring 842 Impurity region 843 Insulation Layer 844 Conductive layer 852 Impurity region 853 Insulation Layer 854 Conductive layer 861 Impurity region 862 Conductive layer 900 elements 901 Board 902 Electrode 903 Photoelectric conversion layer 904 Electrode 905 Hole injection barrier layer 1001 Case 1002 Case 1003 Display section 1004 Display section 1005 Mike 1006 Speaker 1007 Operation key 1008 Stylus 1009 Camera 1011 Case 1012 Display section 1019 Camera 1021 Case 1022 Shutter button 1023 Microphone 1025 Lens 1027 Light emitting part 1031 Case 1032 Display section 1033 Wristband 1039 Camera 1041 Case 1042 Case 1043 Display section 1044 Operation Key 1045 Lens 1046 Connection 1051 Case 1052 Display section 1054 Speaker 1055 Button 1056 Input / output terminal 1057 Mike 1059 Camera 1100 layers 1400 layers 1500 Insulation layer 1510 Light blocking layer 1520 Organic resin layer 1530a Color Filter 1530b Color Filter 1530c Color Filter 1540 Microlens Array 1550 Optical conversion layer 1600 Support Board

Claims

[Claim 1] a pixel portion having first to fourth pixels; first and second switches provided outside the first to fourth pixels; a first wiring provided outside the first to fourth pixels; the first pixel and the second pixel are electrically connected to a second wiring; the third pixel and the fourth pixel are electrically connected to a third wiring, a first terminal of the first switch electrically connected to the first wiring; a second terminal of the first switch electrically connected to the second wiring; a first terminal of the second switch electrically connected to the first wiring; The second terminal of the second switch is electrically connected to the third wiring.

Images