Semiconductor device manufacturing method

Abstract

To provide a thin film transistor which uses an oxide semiconductor layer and achieves stable electric characteristics and excellent reliability.SOLUTION: In a thin film transistor using an oxide semiconductor layer, by controlling a fluctuation range of a threshold voltage of the thin film transistor before and after a BT test to be 2 V or less, favorably 1.5 V or less, more favorably 1.0 V or less, a semiconductor device having high reliability and stable electric characteristics can be manufactured. Particularly, in a display device as one embodiment of the semiconductor device, malfunction such as display unevenness caused by fluctuation in a threshold value can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, thin semiconductor layers (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used The technology of constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as C and electro-optical devices, especially in switching of image display devices. Metal oxides exist in a wide variety of forms and are used for a wide range of purposes. Indium oxide is a well-known material that is needed for applications such as liquid crystal displays. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin-film transistors that use metal oxides as channel formation regions and that exhibit excellent semiconductor properties are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] Thin film transistors with a channel formation region in an oxide semiconductor are made of amorphous silicon. A higher field effect mobility was obtained than in the thin film transistor used.

[0007] Using such oxide semiconductors, thin film transistors can be formed on glass substrates, plastic substrates, etc. The display may be used for liquid crystal displays, electroluminescence displays, electronic paper, etc. It is expected that this technology will be applied to display devices.

[0008] In active matrix display devices, the electrical properties of thin film transistors that make up the circuits are The characteristics are important, and these electrical characteristics determine the performance of the display device. Among the electrical characteristics of , the threshold voltage (Vth) is important. If the threshold voltage is high or negative, the circuit cannot control it. It is difficult to achieve this. In the case of a TFT, when the driving voltage is low, it cannot perform the switching function as a TFT. In addition, if the threshold voltage is negative, the gate voltage Even at 0V, current flows between the source and drain electrodes, making it a so-called normally-on state. stomach.

[0009] In the case of an n-channel thin-film transistor, the channel is turned on only when a positive voltage is applied to the gate. A transistor in which a channel is formed and a drain current flows out is desirable. There are transistors in which a channel does not form unless a negative voltage is applied, and transistors in which a channel forms even under negative voltage conditions. Transistors that allow drain current to flow are not suitable for use as thin-film transistors in circuits. be.

[0010] In addition, the characteristic fluctuation range (amount of change) of the transistors constituting the circuit in the semiconductor device is large. In this case, there is a risk of malfunction occurring due to the fluctuation in the threshold voltage.

[0011] In particular, in a liquid crystal display device, when the variation range between individual elements is large, the threshold voltage There is a risk of malfunctions such as display unevenness due to pressure fluctuations.

[0012] In a display device having a light-emitting element, a constant current is applied to the pixel electrode. On-current of TFT (a TFT that supplies current to a driving circuit or a light-emitting element arranged in a pixel) (I on If the variation in the display brightness is large, the display screen may show irregularities in brightness and other malfunctions. There is a risk of this occurring.

[0013] In view of the above, one embodiment of the present invention provides a thin film transistor which operates stably for a long period of time and a thin film transistor using the same. An object of the present invention is to provide a semiconductor device. [Means for solving the problem]

[0014] One embodiment of the present invention disclosed in this specification is a semiconductor device having a gate electrode layer over a substrate having an insulating surface. a gate insulating layer over a gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a source electrode layer and a drain electrode layer on an oxide semiconductor layer; a source electrode layer and a drain electrode layer; and an insulating layer in contact with a part of the oxide semiconductor layer over the source electrode layer and the drain electrode layer. The semiconductor device is characterized in that

[0015] In addition, one embodiment of the present invention disclosed in this specification is a method for forming a gate electrode layer on a substrate having an insulating surface. a gate insulating layer over the gate electrode layer; and an oxide semiconductor layer over the gate insulating layer. After the oxide semiconductor layer is formed, a first heat treatment is performed to form a soot layer on the oxide semiconductor layer. A gate insulating layer, an oxide semiconductor layer, a source electrode layer and a drain electrode layer are formed. An insulating layer was formed on the drain electrode layer so as to be in contact with a part of the oxide semiconductor layer. A second heat treatment is then performed after the formation of the semiconductor device.

[0016] Note that the first heat treatment is preferably performed in a nitrogen atmosphere or a rare gas atmosphere. The first heat treatment is preferably performed at a maximum temperature of 350° C. or more and 750° C. or less during the treatment. In addition, the maximum temperature in this specification may include so-called overshoot that occurs during temperature adjustment. Part temperatures are not included.

[0017] The second heat treatment is carried out in an air atmosphere, an oxygen atmosphere, a nitrogen atmosphere, or a rare gas atmosphere. The second heat treatment is preferably performed at a temperature of 100° C. or higher and not higher than the maximum temperature in the first heat treatment. It is preferable to carry out the process in the following manner.

[0018] The above configuration solves at least one of the above problems.

[0019] The oxide semiconductor used in this specification is InMO3(ZnO). m (m>0) A thin film is formed, and a thin film transistor is manufactured using the thin film as an oxide semiconductor layer. However, m is not necessarily an integer. M can be selected from Ga, Fe, Ni, Mn, and Co. It denotes a selected metallic element or elements. For example, M can be Ga. In addition, there are cases where the above metal elements other than Ga are included, such as Ga and Ni or Ga and Fe. In addition, in the oxide semiconductor, in addition to the metal element contained as M, an impurity element Contains Fe, Ni or other transition metal elements, or oxides of said transition metals In this specification, InMO3(ZnO) m Acids with structures represented by (m>0) Among the oxide semiconductor layers, the oxide semiconductor with a structure containing Ga as M is called the In-Ga-Zn-O system. This is called an oxide semiconductor, and the thin film is also called an In-Ga-Zn-O non-single crystal layer.

[0020] In addition to the above, In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In -Ga-O, In-O, Sn-O, and Zn-O oxide semiconductors can be used. The oxide semiconductor layer may contain silicon oxide. By including silicon oxide (SiOx(x>0)) which inhibits oxidation during the manufacturing process, When a heat treatment is performed after the formation of the oxide semiconductor layer, crystallization can be suppressed. Note that the oxide semiconductor layer is preferably in an amorphous state, and even if it is partially crystallized, good.

[0021] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), Hydrogenation or dehydrogenation is effective.

[0022] Depending on the conditions of the heat treatment or the material of the oxide semiconductor, the oxide semiconductor layer may become amorphous. In some cases, the layer may become a microcrystalline or polycrystalline layer. Even if the semiconductor device is a thin film transistor, it is possible to obtain switching characteristics as a TFT. Effect of the Invention

[0023] We have fabricated thin-film transistors with small threshold fluctuations and long-term stable electrical characteristics. Therefore, a thin film transistor having good electrical characteristics and high reliability can be provided. It is possible to provide a semiconductor device. [Brief description of the drawings]

[0024] [Figure 1] 2A to 2C illustrate a manufacturing process of a semiconductor device. [Diagram 2] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 3] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 4] 13A and 13B show hydrogen concentrations in oxide semiconductor layers. [Diagram 5] FIG. 13 is a graph showing HO ion intensity and H2O ion intensity in an oxide semiconductor layer. [Figure 6] 13A to 13C show the results of an analysis of the mechanism by which water molecules are released from an oxide semiconductor. [Figure 7] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 8] 1A and 1B are a circuit diagram and a timing chart of a signal line driver circuit. [Figure 9] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 10] 1A and 1B are a circuit diagram and a timing chart of a shift register. [Figure 11] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 12] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 13] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 14]1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 15] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 16] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 17] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 18] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 19] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 20] FIG. 1 is a circuit diagram showing a configuration of a semiconductor device. [Figure 21] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 22] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 23] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 24] FIG. 1 is a circuit diagram showing a configuration of a semiconductor device. [Diagram 25] FIG. 1 is a diagram showing an example of an electronic book. [Figure 26] FIG. 1 shows an example of a television device and a digital photo frame. [Figure 27] FIG. 1 shows an example of a gaming machine. [Figure 28] 1A and 1B are diagrams showing examples of a portable computer and a mobile phone. [Figure 29] FIG. 2 is a diagram showing the definition of Vth. [Diagram 30] FIG. 4 shows the results of a BT test of the thin film transistor of Example 1. [Diagram 31] FIG. 13 is a graph showing the results of a BT test on a conventional thin film transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0026] (Embodiment 1) In this embodiment, one mode of a manufacturing method of the thin film transistor 150 shown in FIG. The process for manufacturing a thin film transistor will be described with reference to cross-sectional views of FIG. 1(A) to FIG. 1(D). The thin film transistor 150 is one of the bottom gate structures called a channel etch type. be.

[0027] First, a photolithography process is performed using a photomask on a substrate 100 having an insulating surface. A gate electrode layer 101 is provided by a roughening process. If the resist mask is formed by the inkjet method, a photomask can be used. Since no additional wiring is required, manufacturing costs can be reduced.

[0028] It is preferable to use a glass substrate as the substrate 100. If the temperature of the subsequent heat treatment is high, the substrate should have a distortion point of 730°C or higher. The substrate 100 may be made of, for example, aluminosilicate glass, aluminoborosilicate glass, or the like. Glass materials such as glass and barium borosilicate glass are used. By containing more barium oxide (BaO) than boron (B2O3), it is more practical. Heat-resistant glass can be obtained. For this reason, it is recommended to use a glass substrate containing more BaO than B2O3. is preferred.

[0029] Instead of the substrate 100, a ceramic substrate, a quartz glass substrate, a quartz substrate, a safa substrate, etc. Alternatively, a substrate made of an insulating material such as a metal substrate may be used. Alternatively, crystallized glass may be used. This can be done.

[0030] In addition, an insulating layer serving as a base layer may be provided between the substrate 100 and the gate electrode layer 101. The layer has a function of preventing the diffusion of impurity elements from the substrate 100, and is made of silicon nitride, silicon oxide, A laminate structure of one or more layers selected from silicon nitride oxide or silicon oxynitride. It can be formed.

[0031] By making the underlayer contain halogen elements such as chlorine and fluorine, impurities from the substrate 100 can be prevented. The function of preventing the diffusion of elements can be further improved. The element concentration is the concentration peak obtained by analysis using SIMS (secondary ion mass spectrometry). In, 1×10 15 cm 3 More than 1×10 20 cm 3 The following would suffice.

[0032] A metal conductive layer can be used as the gate electrode layer 101. The following metals are used: aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti) (Ti), molybdenum (Mo), tungsten (W), or any of the above. It is preferable to use an alloy containing the above elements or a combination of the above elements. For example, a three-layer structure is formed by laminating an aluminum layer on a titanium layer, and a titanium layer on the aluminum layer. or a laminate structure of an aluminum layer on a molybdenum layer and a molybdenum layer on the aluminum layer. Of course, the metal conductive layer may be a single layer or a Alternatively, it may have a two-layer structure or a laminated structure of four or more layers.

[0033] Next, the gate insulating layer 102 is formed on the gate electrode layer 101 .

[0034] The gate insulating layer 102 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer is formed as a single layer or a stacked layer. For example, the deposition gas can be SiH4, oxygen, and nitrogen. The silicon oxynitride layer may be formed by the method D. The thickness of the gate insulating layer 102 is 100 nm. In the case of a multilayer structure, for example, the first layer has a thickness of 50 nm to 200 nm. A first gate insulating layer and a second gate insulating layer having a thickness of 5 nm to 300 nm are formed on the first gate insulating layer. The insulating layer is laminated.

[0035] In addition, before the formation of the oxide semiconductor layer, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400°C or higher but below the distortion point of the substrate) under argon gas or other gases is then performed to remove the The gate insulating layer 102 may be one from which impurities such as hydrogen and water have been removed.

[0036] Next, a film having a thickness of 5 nm to 200 nm, preferably 10 nm, is formed on the gate insulating layer 102. An oxide semiconductor layer having a thickness of 50 nm or less is formed. After the oxide semiconductor layer is formed, dehydration or Since the oxide semiconductor layer is made amorphous even after heat treatment for dehydrogenation, the thickness It is preferable to make the oxide semiconductor layer as thin as 50 nm or less. When a heat treatment is performed after the formation of the semiconductor layer, crystallization can be suppressed.

[0037] The oxide semiconductor layer is an In-Ga-Zn-O non-single crystal layer, an In-Sn-Zn-O layer, or an In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-Ga-O system In this embodiment, a Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor layer is used. For example, a sputtering method is used to form a semiconductor target of In-Ga-Zn-O oxide. The oxide semiconductor layer 130 is formed by oxidizing the oxide semiconductor layer 130 under a rare gas (typically, argon) atmosphere. It is sputtered under a rare gas (typically argon) and oxygen atmosphere. In addition, when the sputtering method is used, the SiO2 content is 2% by weight or more and 10% by weight or less. The film is formed using a target containing less than 1% by weight of Si, which inhibits crystallization of the oxide semiconductor layer. By adding Ox (X>0), the material can be dehydrated or dehydrogenated during the subsequent heat treatment. It is preferable to suppress crystallization. The use of a source is preferable since it reduces dust and provides a uniform thickness distribution.

[0038] The relative density of the oxide semiconductor in the oxide semiconductor target is preferably 80% or more. This makes it possible to reduce the impurity concentration in the formed oxide semiconductor layer, and Therefore, a thin film transistor having excellent thermal properties and high reliability can be obtained.

[0039] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to form insulating layers, while the DC sputtering method is mainly used to form metal layers. It is used in.

[0040] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can laminate different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to form the above-mentioned materials by discharging them simultaneously.

[0041] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0042] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0043] In addition, before the oxide semiconductor film is formed, the inner wall of the sputtering apparatus, the surface of the target, and the It is advisable to perform a preheat treatment to remove any moisture or hydrogen remaining in the material. The preheating process involves heating the deposition chamber to 200℃ to 600℃ under reduced pressure. There are also other methods, such as repeatedly introducing and exhausting nitrogen or inert gas while heating. It is recommended to use oil or fat as a target coolant instead of water. Nitrogen can be introduced and exhausted without heating. Repeating the process will produce a certain effect, but it is even better if you do it while heating. After the sputtering is completed, the substrate or the sputtering apparatus is cooled, and an oxide semiconductor film is formed.

[0044] The substrate may be heated to 400° C. or higher and 700° C. or lower during film formation by sputtering.

[0045] In addition, before, during, or after the formation of the oxide semiconductor film, It is preferable to remove moisture remaining therein using a cryopump.

[0046] In addition, the gate insulating layer 102 and the oxide semiconductor film can be formed in succession without being exposed to air. By forming the film without exposing it to the air, the interface is free from water and hydrocarbons. The interface between each layer is formed without being contaminated by atmospheric components or impurity elements floating in the air, such as fluorine. Since the thin film transistor can be fabricated, the variation in characteristics can be reduced.

[0047] Next, the oxide semiconductor layer is formed into an island-shaped oxide semiconductor layer 103 by a photolithography process. In addition, a laser for forming an island-shaped oxide semiconductor layer 103 is formed. The resist mask may be formed by an inkjet method. Since no photomask is used, the manufacturing cost can be reduced.

[0048] Next, a first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer 103. The temperature of the first heat treatment for dehydration or dehydrogenation is 350°C or higher for 7 days. The temperature is set to 50°C or less, and preferably 425°C or more. If the temperature is 425°C or more, the heat treatment time is The heat treatment time may be less than 1 hour, but if the temperature is less than 425℃, the heat treatment time should be longer than 1 hour. For example, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated. After the heat treatment was performed in a nitrogen atmosphere, the oxide semiconductor The oxide semiconductor layer 103 can be obtained by preventing water or hydrogen from re-entering the layer. In this embodiment, water is again released from the heating temperature T at which the oxide semiconductor layer 103 is dehydrated or dehydrogenated. Use the same furnace until the temperature is high enough that the material cannot enter the furnace. The temperature is gradually cooled in a nitrogen atmosphere until the temperature drops. The atmosphere is not limited to nitrogen, and may be helium, neon, etc. The dehydration or dehydrogenation is carried out under a rare gas such as argon.

[0049] The first heat treatment causes rearrangement at the atomic level of the oxide semiconductor constituting the oxide semiconductor layer 103. The first heat treatment is performed to prevent carrier movement in the oxide semiconductor layer 103. This is important because it can release the distortion that occurs during

[0050] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. The purity of rare gases such as helium, neon, and argon is 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., 1 ppm or less, It is preferable to keep the concentration of the EDTA concentration at 0.1 ppm or less.

[0051] The first heat treatment may be performed using a heating method that uses an electric furnace. The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. The apparatus may be equipped with a device for heating the object to be treated by thermal radiation. For example, the GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Iridium lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a pressure mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0052] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be In some cases, the oxide semiconductor layer is crystallized to become a microcrystalline layer or a polycrystalline layer. In some cases, the oxide semiconductor layer has a crystallinity of 80% or more or 90% or more. Depending on the material, the oxide semiconductor layer may not have crystals.

[0053] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer 103. In this case, the substrate is removed from the heating device after the first heat treatment. Then, the substrate is taken out and subjected to a photolithography process.

[0054] Here, the results of hydrogen concentration analysis depending on whether dehydrogenation has occurred in the oxide semiconductor layer will be described. FIG. 4(A) is a schematic diagram of the cross-sectional structure of the sample used in this analysis. The oxynitride insulating layer 401 is formed by plasma CVD, and In-G The a-Zn-O-based oxide semiconductor layer 402 was formed to a thickness of about 40 nm. The material was divided, one was not dehydrogenated, and the other was heated at 650 The dehydrogenation was performed at 40° C. for 6 minutes. The effect of dehydrogenation by heat treatment was investigated by measuring the degree of dehydrogenation.

[0055] The hydrogen concentration in the oxide semiconductor layer was measured using secondary ion mass spectrometry (SIMS). The results were analyzed by ion mass spectroscopy. This is the result of SIMS analysis showing the hydrogen concentration distribution in the thickness direction of the semiconductor layer. The depth from the top of the oxide semiconductor layer is shown. 4A corresponds to the analysis direction 403 shown in FIG. 4A. The analysis was performed in the direction from the outermost surface of the oxide semiconductor layer toward the glass substrate 400. , the horizontal axis of FIG. 4(B) was from the left end to the right end. shows the hydrogen concentration and oxygen ion intensity in the sample at a specific depth on a logarithmic axis.

[0056] In FIG. 4B, the hydrogen concentration profile 412 is the same as that of the oxide semiconductor that has not been dehydrogenated. The hydrogen concentration profile 413 in the conductor layer is shown. 1 shows a hydrogen concentration profile in an oxide semiconductor layer after dehydrogenation with an acid. The elementary ion intensity profile 411 was acquired simultaneously with the measurement of the hydrogen concentration profile 412. The oxygen ion intensity profile 411 shows no extreme fluctuations. Since almost constant ion intensity was obtained, it was confirmed that the SIMS analysis was performed accurately. Although not shown in the figure, the oxygen concentration profile 413 was also measured. The ionic strength was measured, and it was found to be almost constant. The hydrogen concentration profile 412 and hydrogen concentration profile 413 are the same as the sample, In-Ga-Zn-O The quantitative analysis was performed using a standard sample made of a Zn-type oxide semiconductor layer.

[0057] In principle, SIMS analysis can only measure the area near the sample surface or near the interface between layers of different materials. It is known that it is difficult to obtain accurate data. Accurate data was not obtained from the surface to a depth of about 15 nm. The profile was evaluated from nm onwards.

[0058] From the hydrogen concentration profile 412, it can be seen that hydrogen is present in the oxide semiconductor layer that has not been dehydrogenated. Approximately 3×10 20 atoms / cm 3 That's about 5 x 10 20 atoms / cm 3 below, average Hydrogen concentration is about 4 x 10 20 atoms / cm 3 It can be seen that hydrogen is contained. From the hydrogen concentration profile 413, the average hydrogen concentration in the oxide semiconductor layer was reduced by about 2× 10 19 atoms / cm 3 It can be seen that the noise level has been reduced to .

[0059] This analysis revealed that the hydrogen concentration in the oxide semiconductor layer was reduced by dehydrogenation through heat treatment. It was also confirmed that dehydration was possible in a nitrogen atmosphere at 650°C for 6 minutes using the GRTA method. It was confirmed that the hydrogen concentration in the oxide semiconductor layer can be reduced to 1 / 10 or less by oxidation. .

[0060] In addition, the H+O ions in the oxide semiconductor layer were measured simultaneously during the SIMS analysis shown in Figure 4. The results of the detection of the H2+O ion intensity and H2+O ion intensity are shown in Figure 5. Figure 5 (A1) shows the results of the detection of the H2+O ion intensity after dehydrogenation. FIG. 5A2 shows the H+O ion intensity in the oxide semiconductor layer after dehydrogenation. FIG. 5B1 shows the H+O ion intensity in the oxide semiconductor layer after dehydrogenation. 5B2 shows the H2+O ion intensity in the oxide semiconductor layer that has not been dehydrogenated. The H2+O ion intensity in the oxide semiconductor layer was measured. The on-state strength is small, and the moisture is removed by heat treatment at 650℃ for 6 minutes using the GRTA method. It can be seen that the desorption of OH is efficiently carried out.

[0061] Next, we investigated the mechanism by which water molecules are desorbed from In-Ga-Zn-O oxide semiconductors. The results of the computational chemistry analysis are explained with reference to Figure 6. This analysis was performed using a quantum chemistry calculation program. This was done using Gaussian 03. In oxide semiconductors, not only water molecules but also OH molecules are H and may be desorbed as water molecules. The desorption mechanism was analyzed.

[0062] FIG. 6(A) shows the initial state of the most stable structure in an oxide semiconductor containing OH groups. D) shows the final state in which the OH group becomes a water molecule (HO molecule) and leaves at infinity. 6(B) and 6(C) show the transition and intermediate states from FIG. 6(A) to FIG. 6(D). M1, M2, and M' represent metal atoms, and are assumed to be In, Ga, and Zn. In other words, all combinations of M1-M2 are In-In, Ga-Ga, Zn-Zn In this calculation, M' is water. The calculation was performed on the smallest molecular structure unit by replacing the atoms with elementary atoms. The mechanism of OH group elimination is as follows: We will explain the system step by step.

[0063] First, in the initial state, OH group 701 bonds with M1, and OH group 702 bridges M1 and M2. The ligand forms a coordinate bond so as to form the ligand (see FIG. 6(A)).

[0064] Next, when a certain amount of energy is applied to the oxide semiconductor, the H in the OH group 702 is converted to OH The group 701 rearranges (see FIG. 6B) to generate the H2O molecule 705. forms a coordinate bond with M1 (see FIG. 6(C)). Finally, the H2O molecule 705 forms a coordinate bond with M1. The H2O molecule 710 is released from the atom to infinity (see FIG. 6(D)).

[0065] FIG. 6E shows the states of FIG. 6A to FIG. 6D when M1-M2 are In-Ga. The potential energy value at 711 is shown in FIG. The energy 712 is the energy in the state shown in FIG. Energy 713 is the energy in the state shown in FIG. Energy 714 shows the energy in the state shown in FIG. There are.

[0066] From the results of this analysis, when M1-M2 is In-Ga, the activation energy for water molecule formation is 1. The value was found to be 14 eV. Figure 6(F) shows the results for the six combinations of M1-M2. The calculation results of the activation energy (Ea) of the water production reaction are shown below. Among them, the activation energy is the smallest when M1-M2 is In-Ga, and the activation energy is the smallest when M1-M2 is Zn-Zn. The activation energy was found to be the largest when the M1-M2 combination was Zn When In-Ga-Zn- is included, the activation energy tends to be large. In O-based oxide semiconductors, it is speculated that Zn may be a factor inhibiting the elimination of OH groups. can be.

[0067] From the results of this analysis, it is clear that in In-Ga-Zn-O oxide semiconductors, the OH groups are For efficient desorption, the In and Ga contents (atomic numbers) should be approximately the same, or In should be 100%. It was found that the more the Zn content (atomic number), the better. It is preferable that the content of In is less than the combined content of In and Ga. It turns out that not having one is preferable.

[0068] By optimizing the composition of the oxide semiconductor, dehydration or dehydrogenation by heat treatment can be efficiently performed. It can be done.

[0069] Next, a source electrode layer and a drain electrode layer are formed on the gate insulating layer 102 and the oxide semiconductor layer 103. A conductive layer for forming an electrode layer is formed.

[0070] As a conductive layer for forming a source electrode layer and a drain electrode layer, a gate electrode layer 101 As in the above, a metal conductive layer can be used. The material of the metal conductive layer can be Al, Cr, An element selected from Cu, Ta, Ti, Mo, and W, or an alloy containing the above elements It is preferable to use an alloy or the like that combines the above elements. For example, an aluminum layer is formed on a titanium layer. A three-layer laminate structure in which a titanium layer is laminated on an aluminum layer, or a molybdenum layer is laminated on the aluminum layer. A three-layer stack consisting of an aluminum layer on a molybdenum layer and a molybdenum layer on the aluminum layer. Of course, the metal conductive layer may be a single layer, a two-layer structure, or a four-layer structure. A laminated structure of more than one layer may also be used.

[0071] A source electrode layer and a drain electrode layer are formed by a photolithography process using a photomask. The source electrode layer 105a or the drain electrode layer 105b is formed from a conductive layer for forming a At this time, the oxide semiconductor layer 103 is also partly etched. As a result, the oxide semiconductor layer 103 having a groove (depression) is formed.

[0072] Note that a resist mask for forming the source electrode layer 105a or the drain electrode layer 105b is used. The resist mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0073] In addition, the oxide semiconductor layer 103 and the source electrode layer 105a or the drain electrode layer 105b An oxide conductive layer having a lower resistance than the oxide semiconductor layer 103 may be formed between the oxide semiconductor layer 102 and the oxide conductive layer 104. By adopting such a laminated structure, the breakdown voltage of the thin film transistor can be improved. The carrier concentration of the oxide conductive layer with low resistance is, for example, 1×10 20 / cm 3 1×1 or more 0 21 / cm 3 It is preferable that the content is within the following range.

[0074] Next, the gate insulating layer 102, the oxide semiconductor layer 103, the source electrode layer 105a and the drain electrode layer 105b are An insulating layer 107 is formed to cover the electrode layer 105b and to be in contact with a part of the oxide semiconductor layer 103. See FIG. 1(C). The insulating layer 107 has a thickness of at least 1 nm. A method that does not allow impurities such as water and hydrogen to be mixed into the insulating layer 107, such as a sputtering method, is appropriately used. Here, the insulating layer 107 can be formed by, for example, a type of sputtering method. The oxide semiconductor layer 103 is formed by a reactive sputtering method. The insulating layer 107 formed in contact with the - Does not contain impurities such as In order to prevent these substances from entering the insulating layer from the outside, an inorganic insulating layer is used. layer, silicon nitride oxide layer, silicon nitride layer, aluminum oxide layer, aluminum oxynitride layer or nitride An aluminum nitride layer may be used.

[0075] The insulating layer 107 may be a silicon oxide layer, a silicon nitride oxide layer, an aluminum oxide layer, or an oxynitride layer. A structure in which a silicon nitride layer or an aluminum nitride layer is laminated on an aluminum layer may be used. In particular, the silicon nitride layer is highly resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as This is preferable because it is easier to block intrusion from

[0076] The substrate temperature during the formation of the insulating layer 107 may be set to room temperature or higher and 300° C. or lower. The deposition by the sputtering method is carried out under a rare gas (typically argon) atmosphere or an oxygen atmosphere. Alternatively, it can be carried out under an atmosphere of rare gas (typically argon) and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target is used to perform sputtering in an oxygen and rare gas atmosphere. A silicon carbide can be formed.

[0077] Next, a second heat treatment is performed. The second heat treatment is performed at 100° C. or higher, and the treatment temperature is the same as that of the first heat treatment. For example, the substrate is placed in an electric furnace, which is a type of heat treatment device, and The second heat treatment is performed in a nitrogen atmosphere after the formation of the insulating layer 107. If so, you can go anytime.

[0078] Through the above steps, a gate electrode layer 101 is provided on a substrate 100 having an insulating surface. A gate insulating layer 102 is provided on the gate electrode layer 101. An oxide semiconductor layer 103 is provided on the source electrode layer 105. a or drain electrode layer 105b is provided, and a gate insulating layer 102 and an oxide semiconductor layer 10 3. A semiconductor layer 103 is formed on the source electrode layer 105a and the drain electrode layer 105b. A channel-etched thin-film transistor 15 having an insulating layer 107 in contact with a part of the transistor. 0 can be formed (see Figure 1(D)).

[0079] FIG. 2 is a top view of the thin film transistor 150 shown in this embodiment. The cross-sectional structure of the X1-X2 portion of FIG. 2 is shown. In FIG. 2, L indicates the channel length. where W is the channel width. A is the distance in the direction parallel to the channel width direction. The oxide semiconductor layer 103 does not overlap with the source electrode layer 105a and the drain electrode layer 105b. Ls indicates the length of the region where the source electrode layer 105a and the gate electrode layer 101 overlap. Ld indicates the overlap length of the drain electrode layer 105b and the gate electrode layer 101. is doing.

[0080] In this embodiment, the thin film transistor 150 is a thin film transistor having a single gate structure. However, if necessary, a thin multi-gate structure having a plurality of channel forming regions may be used. a thin-film transistor having a structure in which a second gate electrode layer is formed on the insulating layer 107; It can also be used as a data.

[0081] In this embodiment, a method for manufacturing the channel-etch thin film transistor 150 will be described. However, the configuration of this embodiment is not limited to this. Such a bottom-gate thin-film transistor 160 (also called an inverted coplanar type) and the thin-film transistor 160 shown in FIG. As shown in FIG. 1B, a channel protection type (channel stop type) having a channel protection layer 110 A thin film transistor 170 (also referred to as a thin film transistor 170) can be formed using the same materials and methods. FIG. 3(C) shows another example of a channel-etch type thin-film transistor. In the thin film transistor 180 shown in FIG. 1, the gate electrode layer 101 is disposed at an end of the oxide semiconductor layer 103. The structure extends outward more than that.

[0082] The channel length (L in FIG. 2) of the thin film transistor is determined by the distance between the source electrode layer 105a and the drain electrode layer 105b. The distance between the gate electrode layer 105b and the channel of the channel protection type thin film transistor is defined as The channel length is defined as the width of the channel protection layer in the direction parallel to the carrier flow.

[0083] According to this embodiment, a thin film transistor using an oxide semiconductor as a channel formation region can be fabricated. The threshold voltage can be made close to 0V.

[0084] In addition, the treatment temperature was 150°C, the treatment time was 1 hour, and the electric field strength was 2×10 6 Under V / cm conditions In the BT test, the change in threshold voltage before and after the BT test should be 2V or less, preferably 1. A thin-film transistor having an oxide semiconductor layer with a resistance of 5 V or less, more preferably 1.0 V or less. It is possible to create a data.

[0085] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0086] (Embodiment 2) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0087] The thin film transistors arranged in the pixel portion are formed according to the first embodiment. The thin film transistor shown in the embodiment 1 is an n-channel TFT, so the n-channel A part of the driving circuit that can be configured with a panel-type TFT is the same as the thin-film transistor of the pixel part. It is formed on a substrate.

[0088] An example of a block diagram of an active matrix display device is shown in FIG. On the plate 5300, a pixel section 5301, a first scanning line driver circuit 5302, a second scanning line driver The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. A signal line driver circuit 5304 is extended from the first scanning line driver circuit 5305. 302 and the second scanning line driver circuit 5303. At the intersections with the signal lines, pixels each having a display element are arranged in a matrix. In addition, the display device substrate 5300 is a flexible printed circuit board (FPC). Through the connection part such as the timing control circuit 5305 (controller, control IC (also called the

[0089] In FIG. 7A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. The number of externally provided components such as drive circuits is reduced, which contributes to cost reduction. In the case where a driving circuit is provided outside the substrate 5300, the wiring is extended to connect the driving circuit at the connection portion. The number of connections can be reduced, and the reliability or yield can be improved.

[0090] The timing control circuit 5305 is, for example, A start signal (GSP1) for the first scanning line driver circuit (also called a start pulse) A clock signal (GCK1) for the scan line driver circuit is supplied to the timing control circuit 530. 5 is a second scanning line driver circuit 5302, for example, a second scanning line driver circuit It also supplies a clock signal (GSP2) for the scanning line driver circuit and a clock signal (GCK2) for the scanning line driver circuit. The timing control circuit 5305 supplies a start signal for the signal line driver circuit to the signal line driver circuit 5304. signal (SSP), clock signal for signal line driver circuit (SCK), data for video signal (DAT A) (also called video signal), and latch signal (LAT). The clock signal may be a plurality of clock signals with different periods, or may be an inverted clock signal. The first scanning line driving circuit may be supplied with the signal (CKB). It is possible to omit either the second scanning line driver circuit 5302 or the second scanning line driver circuit 5303.

[0091] In FIG. 7B, circuits with low driving frequencies (for example, the first scanning line driver circuit 5302, the second The scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The circuit 5304 is formed on a substrate different from that of the pixel portion 5301. The thin film transistor has a smaller field effect mobility than a transistor using a single crystal semiconductor. A driver circuit formed on the substrate 5300 can be formed by using transistors. Therefore, it is possible to increase the size of display devices, reduce the number of processes, reduce costs, and improve yields. It is possible.

[0092] The thin film transistor shown in Embodiment 1 is an n-channel TFT. FIG. 8B shows the configuration and operation of a signal line driver circuit made up of an n-channel TFT. An example will be given to explain.

[0093] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a A plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) are provided. The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0094] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are respectively connected to the wiring 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0095] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0096] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k The thin film transistor 56 has a function of supplying the potential to the signal lines S1 to Sk. Each of 03_1 to 5603_k has a function as a switch.

[0097] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0098] Next, the operation of the signal line driver circuit in FIG. 8(A) will be described with reference to the timing chart in FIG. 8(B). 8B, signals Sout_1 to Sout_N and a signal Vda The signals Sout_1 to Sout_N are each an example of 5601. The signals Vdata_1 to Vdata_k are an example of an output signal of the soft register 5601. , are examples of signals input to the wirings 5604_1 to 5604_k. One operation period of the drive circuit corresponds to one gate selection period in the display device. As an example, the period is divided into periods T1 to TN. This is a period for writing video signal data (DATA) to pixels belonging to a selected row.

[0099] In the drawings of the present embodiment, the signal waveforms of the components are not rounded for clarity. Therefore, the scale may not necessarily be limited to the actual scale. It should be noted that

[0100] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0101] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written more quickly. This can prevent under-crowding.

[0102] The shift register 5601 and the switching circuit 5602 may be the same as those described in the first embodiment. In this case, a circuit including a thin film transistor shown in FIG. The polarity of all the transistors in the resistor 5601 is set to N-channel or P-channel. It can be configured with only one polarity.

[0103] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 9 and FIG.

[0104] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. A selection signal is generated by inputting a clock (CK) and a start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Since the transistors of the pixels in one line must be turned on at the same time, a buffer The resistor used is capable of passing a large current.

[0105] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number equal to or greater than 3) (see FIG. 9(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the A first clock signal CK1 is output from the first wiring 11, a second clock signal CK2 is output from the second wiring 12, and a third clock signal CK3 is output from the third wiring 13. The third wiring 13 transmits a third clock signal CK3, and the fourth wiring 14 transmits a fourth clock signal C In the first pulse output circuit 10_1, a start signal from the fifth wiring 15 is supplied. The first start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), The signal from the previous stage (called the previous stage signal OUT(n-1)) (n is a natural number of 2 or more) is input. In the first pulse output circuit 10_1, the third pulse output circuit 10_3, which is two stages behind, Similarly, in the n-th pulse output circuit 10_n in the second stage or later, The signal from the (n+2)th pulse output circuit 10_(n+2) (n+2) of the downstream signal OUT(n+2 Therefore, the pulse output circuit of each stage outputs the pulse to the next stage and / or The first output signal (OUT(1)(SR) to OUT (N)(SR)), the second output signal (OUT(1) to OUT(N However, as shown in Figure 9(A), the last two shift registers Since the next stage signal OUT(n+2) is not input to the second stage, for example, A first start pulse SP2, a second start pulse SP3, and a third start pulse SP4 may be input.

[0106] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The fourth clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is GCK depending on the input drive circuit. It is sometimes called SCK, but here we will use the term CK for explanation.

[0107] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to The fourth wiring 14 is electrically connected to the first wiring 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to a first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the wiring 13 of the first The input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14. do.

[0108] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 9B) In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the second input terminal 23, and a third A third clock signal CK3 is input to the input terminal 23, and a start signal is input to the fourth input terminal 24. A pulse is input to the fifth input terminal 25, a subsequent signal OUT(3) is input to the first output terminal The first output signal OUT(1)(SR) is output from the second output terminal 27. Therefore, the output signal OUT(1) of the second output terminal is output.

[0109] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are each a three-terminal thin-film transistor. In addition to transistors, four-terminal thin-film transistors can be used. The transistor includes a source electrode, a drain electrode, a first gate electrode, and a second gate electrode. A channel of the semiconductor layer is provided between the first gate electrode and the second gate electrode via an insulating layer. FIG. 9C shows a four-terminal thin film transistor 28. The thin film transistor 28 is a first A first control signal G1 is input to the gate electrode of the first gate electrode and a second control signal G2 is input to the gate electrode of the second gate electrode. An element that can perform electrical control between the In and Out terminals using the control signal G2. It is.

[0110] The threshold voltage of the thin film transistor 28 shown in FIG. can be controlled to a desired value by controlling the potential of the second gate electrode.

[0111] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0112] The first pulse output circuit 10_1 includes a first transistor 31 to a thirteenth transistor 43. (See FIG. 9(D)). In addition, the first input terminal 21 to the fifth input terminal 25, a first output terminal 26, a second output terminal 27, and a first high power supply potential VDD A power supply line 51 is supplied with a second high power supply potential VCC, a power supply line 52 is supplied with a low power supply potential V The first transistor 31 to the thirteenth transistor 43 are connected to the power supply line 53 through which the SS is supplied. A signal or a power supply potential is supplied to each of the power supply lines. The relationship is that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential V CC is set to a potential higher than the third power supply potential VSS. ) ~ The fourth clock signal (CK4) is a signal that alternates between H and L levels at regular intervals. When the power supply line 51 is at the H level, it is VDD, and when the power supply line 51 is at the L level, it is VSS. By making the potential VDD of the power supply line 52 higher than the potential VCC of the power supply line 52, the operation of the The potential applied to the gate electrode of the transistor can be kept low without causing a problem. This reduces the shift in the threshold voltage of the transistor and suppresses degradation. As shown in the figure, among the first transistor 31 to the thirteenth transistor 43, the first transistor The transistor 31 and the sixth to ninth transistors 36 to 39 are It is preferable to use a four-terminal thin film transistor 28 shown in FIG. 1. The operation of the sixth transistor 36 to the ninth transistor 39 is performed by the source or drain The potential of the node to which one of the electrodes is connected is switched by the control signal of the gate electrode. The transistor is required to have a high response to a control signal input to the gate electrode. Fast response (sharp rise in on-current) reduces malfunction of pulse output circuits Therefore, the four-terminal thin-film transistor shown in Fig. 9(C) By using the transistor 28, the threshold voltage can be controlled, and malfunctions can be further reduced. In FIG. 9D, the first control signal G1 and the second control signal G2 are However, a configuration in which different control signals are input may be adopted. .

[0113] In FIG. 9D, the first transistor 31 has a first terminal electrically connected to a power supply line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the The first gate electrode and the second gate electrode are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal 9, and a gate electrode of the fourth transistor The third transistor 33 has a first terminal electrically connected to the gate electrode of the first The first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53 and a second terminal The fifth transistor 35 has a first terminal electrically connected to the first output terminal 26. The terminal is electrically connected to the power supply line 53, and the second terminal is the gate electrode of the second transistor 32. and a gate electrode of a fourth transistor 34, the gate electrode of which is electrically connected to the fourth input The sixth transistor 36 has a first terminal electrically connected to the power supply line 52. , and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 33. The gate electrode of the transistor 34 is electrically connected to the gate electrode of the first gate electrode and the second gate electrode of the transistor 34. The seventh transistor 37 has a gate electrode electrically connected to the fifth input terminal 25. The first terminal is electrically connected to the power supply line 52, and the second terminal is the third terminal of the eighth transistor 38. The gate electrodes (first gate electrode and second gate electrode) are electrically connected to the first terminal. The eighth transistor 38 has a first terminal electrically connected to the third input terminal 23. The gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to The gate electrodes (the first gate electrode and the second gate electrode) are connected to the second input terminal 22. The ninth transistor 39 has a first terminal electrically connected to the first transistor a second terminal of the second transistor 31 and a second terminal of the second transistor 32, The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are electrically connected to each other. The gate electrodes (first gate electrode and second gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 21. the second terminal is electrically connected to the second output terminal 27, and the gate electrode is The eleventh transistor 41 is electrically connected to the second terminal of the ninth transistor 39. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. , and the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor The twelfth transistor 42 has a first terminal electrically connected to the gate electrode of the first transistor 34. The second terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the first gate electrode and the second gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 53. the second terminal is electrically connected to the first output terminal 26, and the gate electrode is The gate electrodes (first gate electrode and second gate electrode) of the transistor 37 of is connected to

[0114] In FIG. 9D, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 The connection point of the gate electrode of the ninth transistor 39 and the second terminal of the ninth transistor 39 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the gate electrode of the fifth transistor 35, the second terminal of the sixth transistor 35, the second terminal of the sixth transistor 36, The connection point between the first terminal of the eleventh transistor 38 and the eleventh transistor 41 is referred to as a node B.

[0115] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. An element having terminals, and a channel region between a drain region and a source region, A current can be passed through the drain region, the channel region, and the source region. The source and drain are different depending on the structure and operating conditions of the thin film transistor. It is difficult to determine whether the source or drain is the source or drain. In some cases, the region that functions as a drain is not called a source or drain. As an example, they may be referred to as a first terminal and a second terminal, respectively.

[0116] In addition, the source and drain functions may differ depending on whether transistors with different polarities are used or the circuit operation. In some cases, such as when the direction of the current changes during operation, the positions may be reversed. In this document, the terms source and drain may be used interchangeably.

[0117] In FIG. 9(D) and FIG. 10(A), the node A is set to a floating state, and the bootstrap A capacitor may be provided separately to perform a trapping operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0118] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 10B corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0119] As shown in FIG. 10A, the ninth transistor in which the second power supply potential VCC is applied to the gate electrode By providing the transistor 39, the following can be achieved before and after the bootstrap operation: The advantages are as follows:

[0120] In the absence of the ninth transistor 39, the gate electrode of which is applied with the second power supply potential VCC, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate and the source, between the gate and the drain In both cases, a large bias voltage is applied, which places a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 is increased, but the potential of the second terminal of the first transistor 31 is not increased. That is, by providing the ninth transistor 39, It is possible to reduce the value of the negative bias voltage applied between the gate and source of the transistor 31. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0121] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0122] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. In addition, a transistor using an oxide semiconductor can be used. Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is Since the number of power supply lines can be reduced, the circuit can be made more compact.

[0123] The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 a clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38; A second input terminal 22 supplies a potential to the first gate electrode and the second gate electrode. The clock signal is applied to the gate electrode of the seventh transistor 37 (the gate electrode of the first transistor and the gate electrode of the second transistor). A clock signal is supplied to the gate electrode of the eighth transistor by the second input terminal 22. The gate electrodes (first gate electrode and second gate electrode) of the transistor 38 are connected to the third input terminal 23. Therefore, the same effect can be obtained by switching the wiring so that the clock signal is supplied. In the shift register shown in FIG. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. By turning off the power supply 38, the second input terminal 22 and the third input terminal 23 are turned on. The voltage drop at node B is applied to the gate of the seventh transistor 37. 2 due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, in the shift register shown in FIG. The seventh transistor 37 and the eighth transistor 38 are both in an on state. on, the eighth transistor 38 is off, then the seventh transistor 37 is off, By turning off the eighth transistor 38, the second input terminal 22 and the third input terminal The drop in the potential of the node B caused by the drop in the potential of the input terminal 23 is suppressed by the eighth transistor Therefore, the seventh The gate electrodes (first gate electrode and second gate electrode) of the transistor 37 are connected to the third input terminal. A clock signal CK3 is supplied from the input terminal 23, and the gate electrode ( A clock signal CK2 is input from the second input terminal 22 to the first gate electrode and the second gate electrode. It is preferable to have a wiring relationship in which the potential of node B is supplied. This is because the signal strength can be reduced and noise can also be reduced.

[0124] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0125] The thin film transistor of the driver circuit is manufactured by the manufacturing method of the thin film transistor shown in Embodiment 1. By creating a thin-film transistor, high-speed operation of the driving circuit section was achieved, resulting in power saving. It is possible to achieve this.

[0126] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0127] (Embodiment 3) In this embodiment mode, a thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further In the case of manufacturing a semiconductor device (also called a display device) having a display function by using the device in a driver circuit, In addition, a part or the whole of a driver circuit having a thin film transistor is formed in a pixel region. A system-on-panel can be formed by integrally forming the display and the display device on the same substrate.

[0128] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic ink, etc. A display medium whose contrast changes due to an electrical effect, such as a liquid crystal display, can also be used.

[0129] The display device includes a panel in which a display element is sealed, and a controller for the panel. The display device further includes a module in which an IC or the like including the display device is mounted. In the process of manufacturing the display device, the element substrate corresponds to a form before the display device is completed. The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, only the pixel electrodes of the display element may be formed, or the pixel electrodes and After forming the conductive layer, and before etching to form the pixel electrode, is fine, and all forms apply.

[0130] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0131] In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device which is one embodiment of the present invention. First, the appearance and cross section of a liquid crystal display panel, which corresponds to one embodiment of a semiconductor device, will be described with reference to FIG. FIG. 11 shows an In—Ga—Zn—O based non-crystalline semiconductor layer formed on a first substrate 4001. Highly reliable thin film transistors 4010 and 4011 including a single crystal layer as a semiconductor layer, A liquid crystal element 4013 is sealed between a second substrate 4006 and the liquid crystal element 4013 by a sealant 4005. FIG. 11(B) is a top view of the panel, and FIG. 11(A1) and (A2) are cross-sectional views taken along line MN. Corresponding to the figure.

[0132] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor or a polycrystalline semiconductor is mounted.

[0133] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 11A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0134] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 11B, the thin film transistor included in the pixel portion 4002 is A thin film transistor 4010 and a thin film transistor 401 included in a scanning line driver circuit 4004 The insulating layers 4020 and 4011 are formed on the thin film transistors 4010 and 4011. 21 is provided.

[0135] The thin film transistors 4010 and 4011 are the signal transistors including the oxide semiconductor layer described in Embodiment 1. In this embodiment, a thin film transistor having high reliability can be applied. The transistors 4010 and 4011 are n-channel thin film transistors.

[0136] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the gate insulating film at a position overlapping the channel formation region of the nitride semiconductor layer, In addition, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0137] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0138] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Alternatively, you can use aluminum foil with a PVF film or polyester film. A sheet having a structure sandwiched between films can also be used.

[0139] Also, 4035 is a columnar spacer obtained by selectively etching the insulating layer. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031, A spherical spacer may be used. 1 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 4 to the conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 4 to the common potential line. Included in 005.

[0140] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0141] Note that the liquid crystal display device shown in this embodiment is an example of a transmission type liquid crystal display device. The device can be applied to both a reflective liquid crystal display device and a semi-transmissive liquid crystal display device.

[0142] In the liquid crystal display device shown in this embodiment mode, a polarizing plate is provided on the outer side (the viewing side) of the substrate. In this example, a colored layer and an electrode layer for use in a display element are provided on the side of the substrate in this order. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and the polarizing plate may be provided in the same manner. The thickness may be appropriately set depending on the material of the colored layer and the manufacturing process conditions. A light-shielding layer that functions as a light-shielding matrix may be provided.

[0143] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, It acts as a protective layer and a planarizing insulating layer for thin-film transistors to improve the reliability of the transistors. The insulating layer 4020 and the insulating layer 4021 are formed to cover the insulating layer 4020 and the insulating layer 4021. is intended to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor suspended in the air. The protective layer is preferably a silicon oxide layer or a silicon nitride layer formed by sputtering. , silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer, oxynitride layer The insulating layer 10 may be formed of a single layer of aluminum oxide nitride or a single layer of aluminum nitride oxide. In the embodiment, the protective layer is formed by a sputtering method, but the method is not limited thereto and may be formed by various methods. It is sufficient to form it.

[0144] Here, an insulating layer 4020 having a laminated structure is formed as a protective layer. A silicon oxide layer is formed as the first layer of the first insulating film by sputtering. By using the above, it is possible to prevent hillocks on the aluminum layer used as the source electrode layer and the drain electrode layer. It is effective in stopping.

[0145] In addition, an insulating layer is formed as the second layer of the protective layer. A silicon nitride layer is formed by sputtering. When a silicon nitride layer is used as a protective layer, Mobile ions such as thorium penetrate into the semiconductor region and change the electrical properties of the TFT. can be suppressed.

[0146] After forming the protective layer, the semiconductor layer may be annealed (at 300° C. to 400° C.). stomach.

[0147] In addition, an insulating layer 4021 is formed as a planarizing insulating layer. Heat-resistant resins such as amide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant materials (L ow-k materials), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass) In addition, multiple insulating layers made of these materials can be laminated. In this way, the insulating layer 4021 may be formed.

[0148] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0149] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, In the step of bonding, the semiconductor layer may be annealed (at 300° C. to 400° C.) at the same time. By combining the firing process of the edge layer 4021 with the annealing process of the semiconductor layer, a semiconductor device can be efficiently manufactured. It becomes possible to do so.

[0150] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0151] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0152] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0153] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0154] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive layer as the thin film transistors 4010 and 30. The source electrode layer and the drain electrode layer 11 are formed of the same conductive layer.

[0155] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive layer 4019. The electrodes are electrically connected to each other.

[0156] In FIG. 11, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0157] FIG. 12 shows a liquid crystal display module, which corresponds to one form of a semiconductor device, using a TFT substrate 2600. An example of the configuration is shown in FIG.

[0158] FIG. 12 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0159] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0160] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0161] A thin film transistor in a pixel portion of a liquid crystal display device using the thin film transistor shown in Embodiment 1 By fabricating a thin-film transistor, the variation in the threshold voltage of each pixel is eliminated. Display unevenness can be suppressed.

[0162] In addition, a driver circuit of a liquid crystal display device can be manufactured by using the manufacturing method of a thin film transistor shown in Embodiment 1. By fabricating a thin-film transistor with This can achieve power savings.

[0163] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0164] (Embodiment 4) An example of electronic paper will be shown as one mode of a semiconductor device.

[0165] The thin film transistor of the first embodiment uses an element electrically connected to a switching element. The present invention may be used for electronic paper that drives electronic ink by electrophoretic display. Also called electrophoretic display, it has the same readability as paper and is comparable to other display devices. It has the advantage of being able to consume less power and have a thinner, lighter shape than conventional liquid crystal displays.

[0166] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0167] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0168] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0169] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. If an electric field is applied to the cell, a display can be performed. For example, the thin film transistor of the first embodiment An active matrix substrate obtained by a laser diode can be used.

[0170] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0171] FIG. 13 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in the embodiment mode 1. The thin film transistor includes an oxide semiconductor layer and is highly reliable.

[0172] The electronic paper in FIG. 13 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0173] The thin film transistor 581 formed on the substrate 580 is a bottom-gate thin film transistor. The thin film transistor 581 is covered with an insulating layer 583 that is in contact with the semiconductor layer. The source electrode layer or the drain electrode layer is formed by a first electrode layer 587, an insulating layer 583, and an insulating layer 585. The first electrode layer 587 and the substrate 596 are in contact with each other at the opening to be formed and are electrically connected. Between the second electrode layer 588 formed on the first electrode layer 581 and the second electrode layer 582, a black region 590a and a white region 590b are formed. A spherical particle 589 is provided having a cavity 594 therearound that is filled with liquid. The periphery of the spherical particle 589 is filled with a filler 595 such as resin (see FIG. 13). The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common electrode layer provided over the same substrate as the thin film transistor 581. The common connection portion is electrically connected to the conductive particles disposed between the pair of substrates. The second electrode layer 588 and a common potential line can be electrically connected via the same.

[0174] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element. It has a higher reflectivity than other LEDs, so no auxiliary light is required, it consumes less power, and it is suitable for use in dimly lit areas. The display can be recognized even when the power is not supplied to the display. Even if the image is displayed, it is possible to hold the image once it has been displayed. It will be possible to store it.

[0175] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0176] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0177] (Embodiment 5) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0178] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0179] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0180] FIG. 14 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0181] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0182] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 64 has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate.

[0183] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0184] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as follows: A capacitance may be formed between the gate electrode and the second electrode.

[0185] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is The driving transistor 6402 is in two states, either fully on or fully off. A video signal is inputted, that is, the driving transistor 6402 is operated in a linear region. In order to operate the driving transistor 6402 in a linear region, the voltage of the power supply line 6407 must be higher than that of the driving transistor 6402. A high voltage is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied.

[0186] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 14 can be used.

[0187] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. In addition, the video transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The gate potential of the light emitting element 6402 is set higher than that of the gate of the transistor 6403. Analog gradation drive can be performed by passing a current corresponding to a video signal through 6404.

[0188] Note that the pixel configuration shown in FIG. 14 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0189] Next, the configuration of the light emitting element will be described with reference to FIG. 15. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figure 15(A), (B), and (C). The driving TFTs used in the semiconductor device, TFTs 7001, 7011, and 7021, are The thin film transistor can be fabricated in the same manner as in the first embodiment, and has high reliability including an oxide semiconductor layer. It is a thin film transistor.

[0190] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light-emitting elements with a double-sided emission structure that emits light from the side of the pixel. The present invention can also be applied to optical elements.

[0191] A light emitting element having a bottom emission structure will be described with reference to FIG.

[0192] The driving TFT 7011 is an n-type TFT, and the light emitted from the light-emitting element 7012 is FIG. 15(A) shows a cross-sectional view of a pixel when light is emitted to the TFT 7011 side. A cathode 70 of the light-emitting element 7012 is formed on a light-transmitting conductive layer 7017 electrically connected to the 13 is formed, and an EL layer 7014 and an anode 7015 are laminated in this order on a cathode 7013. Note that the light-transmitting conductive layer 7017 is a conductive film formed in the oxide insulating layer 7031. The drain electrode layer 7030 of the TFT 7011 is electrically connected to the drain electrode layer 7030 through a contact hole. There are.

[0193] The light-transmitting conductive layer 7017 may be formed of indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), Conductive materials with optical transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive layer may be used.

[0194] In addition, the cathode 7013 can be made of various materials. However, it is preferable to use a material having a small work function, e.g. Specifically, alkali metals such as Li and Cs, and alkaline earths such as Mg, Ca, and Sr. In addition to metals and alloys containing these (Mg:Ag, Al:Li, etc.), Yb, Er, etc. Rare earth metals are preferable. In FIG. 15(A), the thickness of the cathode 7013 is set to a level that allows light to pass through. (Preferably, about 5 nm to 30 nm). For example, an aluminum The aluminum layer is used as the cathode 7013.

[0195] After a light-transmitting conductive layer and an aluminum layer are laminated, the conductive layer is selectively etched. In this case, the conductive layer 7017 and the cathode 7013 may be formed on the same substrate. It is preferable to use a etchant.

[0196] The periphery of the cathode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide, alumina, Organic resin layer such as acrylic resin, polyamide, epoxy resin, inorganic insulating layer or organic polysiloxane The partition wall 7019 is formed by using a photosensitive resin material, and the cathode 7013 is formed by using a photosensitive resin material. An opening is formed on the top, and the side wall of the opening becomes an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7019, The step of forming a resist mask can be omitted.

[0197] The EL layer 7014 formed on the cathode 7013 and the partition wall 7019 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7013 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. stomach.

[0198] The stacking order is not limited to the above, and may be a hole injection layer, a hole transport layer, a light emitting layer, etc., on the cathode 7013. However, when comparing power consumption, the cathode may be used in the same manner as the cathode. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7013 in this order. Layering is preferred because it consumes less power.

[0199] In addition, various materials can be used for the anode 7015 formed on the EL layer 7014. However, materials with large work functions, such as titanium nitride, ZrN, Ti, W, Ni, Pt, Cr, etc., and transparent conductive materials such as ITO, IZO (indium zinc oxide), and ZnO. It is preferable to provide a shielding film 7016 on the anode 7015. For example, the shielding film 7016 may be made of a metal that blocks light or a material that reflects light. In this embodiment, an ITO film is used as the anode 7015, and a shielding film 7 A Ti layer is used as 016.

[0200] The region where the EL layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light emitting element 7012. In the case of the element structure shown in FIG. 15A, the light emitted from the light emitting element 7012 is is emitted toward the cathode 7013 as indicated by the arrow.

[0201] Note that FIG. 15A shows an example in which a light-transmitting conductive layer is used as a gate electrode layer. The light emitted from the light emitting element 7012 passes through the color filter layer 7033 and is reflected by the TFT The light is emitted through the gate electrode layer, source electrode layer, drain electrode layer, etc. of 7011. The gate electrode layer, source electrode layer, drain electrode layer, etc. of the TFT7011 can be By using a light-transmitting conductive layer, the aperture ratio can be improved.

[0202] The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0203] The color filter layer 7033 is covered with an overcoat layer 7034, which is a protective insulating layer. In FIG. 15(A), the overcoat layer 7034 is thin. As shown in FIG. 7, the overcoat layer 7034 has irregularities caused by the color filter layer 7033. It has the function of flattening the surface.

[0204] In addition, a protective insulating layer 7035, an overcoat layer 7034, a color filter layer 7033, and A contact hole is formed in the oxide insulating layer 7031 and reaches the drain electrode layer 7030. The partition wall 7019 is disposed at a position overlapping the partition wall 7019. The layout of the cut hole and the partition wall 7019 is designed to overlap each other to improve the aperture ratio. This can be done.

[0205] Next, a light emitting element having a dual emission structure will be described with reference to FIG.

[0206] In FIG. 15B, a light-transmitting conductive layer 7027 electrically connected to a TFT 7021 is A cathode 7023 of the light-emitting element 7022 is formed on the cathode 7023. An EL layer 70 24 and an anode 7025 are laminated in this order. The drain electrode of the TFT 7021 is connected to the contact hole formed in the insulating layer 7041. It is electrically connected to layer 7040.

[0207] The light-transmitting conductive layer 7027 may be formed of indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), Conductive materials with optical transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive layer may be used.

[0208] In addition, the cathode 7023 can be made of various materials. However, it is preferable to use a material with a small work function, e.g. Specifically, alkali metals such as Li and Cs, and alkaline earths such as Mg, Ca, and Sr. In addition to metals and alloys containing these (Mg:Ag, Al:Li, etc.), Yb, Er, etc. Rare earth metals and the like are preferable. In this embodiment, the thickness of the cathode 7023 is set to a level that allows light to pass through. (Preferably, about 5 nm to 30 nm). For example, an aluminum The aluminum layer is used as the cathode 7023.

[0209] After a light-transmitting conductive layer and an aluminum layer are laminated, the conductive layer is selectively etched. In this case, the conductive layer 7027 and the cathode 7023 may be formed on the same substrate. It is preferable to use a etchant.

[0210] The periphery of the cathode 7023 is covered with a partition 7029. The partition 7029 is made of polyimide, alumina, Organic resin layer such as acrylic resin, polyamide, epoxy resin, inorganic insulating layer or organic polysiloxane The partition wall 7029 is formed by using a photosensitive resin material, and the cathode 7023 is formed by using a photosensitive resin material. An opening is formed on the top, and the side wall of the opening becomes an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7029, The step of forming a resist mask can be omitted.

[0211] The EL layer 7024 formed on the cathode 7023 and the partition wall 7029 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7023 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. stomach.

[0212] The stacking order is not limited to the above, and may be a hole injection layer, a hole transport layer, a light emitting layer, etc., on the cathode 7023. However, when comparing power consumption, the cathode may be used in the same manner as the cathode. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7023 in this order. Layering is preferred because it consumes less power.

[0213] In addition, various materials can be used for the anode 7025 formed on the EL layer 7024. However, materials with large work functions, such as transparent conductive materials such as ITO, IZO, and ZnO, are In this embodiment, an ITO film containing silicon oxide is used as the anode 7026.

[0214] The region where the EL layer 7024 is sandwiched between the cathode 7023 and the anode 7025 is the light emitting element 7022. In the case of the element structure shown in FIG. 15B, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0215] Note that FIG. 15B shows an example in which a light-transmitting conductive layer is used as a gate electrode layer. The light emitted from the light emitting element 7022 to the cathode 7023 side is reflected by the color filter layer 7043. and passes through the gate electrode layer, source electrode layer, drain electrode layer, etc. of the TFT7021. The gate electrode layer, source electrode layer, drain electrode layer, By using a conductive layer with light transmission as the anode electrode layer, the aperture ratio and the cathode The aperture ratio on the pole 7023 side can be made almost the same.

[0216] The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0217] The color filter layer 7043 is covered with an overcoat layer 7044, which is a protective insulating layer. Covered by layer 7045 .

[0218] However, when using a light-emitting element with a dual-side emission structure and making both display surfaces full color display, Since the light from the anode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate having a filter layer above the anode 7025.

[0219] In addition, a protective insulating layer 7045, an overcoat layer 7044, a color filter layer 7043, and A contact hole is formed in the oxide insulating layer 7041 and reaches the drain electrode layer 7040. The partition wall 7029 is disposed at a position overlapping the partition wall 7029. By overlapping the cut hole and the partition wall 7029, the aperture ratio on the anode 7025 side is The aperture ratio on the cathode 7023 side can be made substantially the same.

[0220] Next, a light emitting element having a top emission structure will be described with reference to FIG.

[0221] In FIG. 15C, a driving TFT 7001 is an n-type TFT, and a light emitting element 7002 emits light. FIG. 15C shows a cross-sectional view of a pixel in the case where the light incident thereon is guided to the anode 7005 side. A cathode 7003 of a light emitting element 7002 electrically connected to a TFT 7001 is formed. An EL layer 7004 and an anode 7005 are laminated in this order on the cathode 7003 .

[0222] In addition, the cathode 7003 can be made of various materials. However, it is preferable to use a material with a small work function, e.g. Specifically, alkali metals such as Li and Cs, and alkaline earths such as Mg, Ca, and Sr. In addition to metals and alloys containing these (Mg:Ag, Al:Li, etc.), Yb, Er, etc. Rare earth metals and the like are preferred.

[0223] The periphery of the cathode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide, alumina, Organic resin layer such as acrylic resin, polyamide, epoxy resin, inorganic insulating layer or organic polysiloxane The partition wall 7009 is formed by using a photosensitive resin material, and the cathode 7003 is formed by using a photosensitive resin material. An opening is formed on the top, and the side wall of the opening becomes an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7009, The step of forming a resist mask can be omitted.

[0224] In addition, the EL layer 7004 formed on the cathode 7003 and the partition wall 7009 is composed of a single layer. The EL layer 70 may be formed by laminating a plurality of layers. When the cathode 7003 is composed of multiple layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. stomach.

[0225] The stacking order is not limited to the above, and a hole injection layer, a hole transport layer, and a light emitting layer may be stacked on the cathode 7003. The cathode 700 may be laminated in this order, the electron transport layer, and the electron injection layer. 3 will function as the anode.

[0226] In FIG. 15(C), a hole injection is performed on a laminated film in which a Ti layer, an aluminum layer, and a Ti layer are laminated in this order. The dopant layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are laminated in that order, and Mg:A A laminate of a g-alloy thin film and ITO is formed.

[0227] However, when comparing power consumption, the cathode 7003 is provided with an electron injection layer, an electron transport layer, a light emitting layer, It is preferable to laminate the hole transport layer and the hole injection layer in this order, since this reduces power consumption.

[0228] The anode 7005 is formed using a conductive material having light transmitting properties, for example, tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium oxide, Indium tin oxide with titanium oxide, Indium tin oxide, Indium Conductive materials with light-transmitting properties such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive layer may also be used.

[0229] The region where the EL layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light emitting element 7002. In the case of the pixel shown in FIG. 15C, the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0230] In FIG. 15C, a TFT 7001 is an example using a thin film transistor 150. However, the present invention is not limited to the above. A thin film transistor 180 can be used.

[0231] In FIG. 15C, the cathode 7003 is formed by the oxide insulating layer 7051 and the planarizing insulating layer 7052. 7053 and the insulating layer 7055 are formed through contact holes. The planarization insulating layer 7053 is electrically connected to the drain electrode layer 7050. Resin materials such as acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin In addition to the above resin materials, low-k materials, white materials, etc. Xanthane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. In addition, by stacking a plurality of insulating layers made of these materials, a planarized insulating layer can be formed. The method for forming the planarization insulating layer 7053 is not particularly limited. Depending on the material, sputtering, SOG, spin coating, dip, spray coating, droplet ejection printing (inkjet printing, screen printing, offset printing, etc.), doctor knife, roll A coater, a curtain coater, a knife coater, etc. can be used.

[0232] In addition, a partition wall 7009 is provided to insulate the cathode 7003 from the cathode 7008 of the adjacent pixel. The partition wall 7009 is made of a material such as polyimide, acrylic resin, polyamide, or epoxy resin. The partition wall 7009 is formed by using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. A photosensitive resin material is used to form an opening on the cathode 7003, and the side wall of the opening is continuous. It is preferable to form the partition wall 7009 so as to have an inclined surface having a certain curvature. When a photosensitive resin material is used as the resist mask, the step of forming a resist mask can be omitted. can.

[0233] In the structure of FIG. 15C, when a full-color display is performed, for example, the light-emitting element 70 02 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also added, making a total of four. A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0234] In the structure of FIG. 15C, all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By forming a material and combining it with a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0235] Of course, a single-color display may be used. For example, a lighting device may be formed using white light. Alternatively, monochromatic light may be used to form an area color type light emitting device.

[0236] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0237] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0238] In addition, the thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically However, a current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the input / output terminals are connected to each other.

[0239] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 16. FIG. 16(A) shows a thin film formed on a first substrate. A panel in which the film transistor and the light emitting element are sealed between the second substrate and the film transistor and the light emitting element by a sealant. 16(B) is a plan view of the above-mentioned embodiment, and FIG. 16(B) is a cross-sectional view taken along line HI of FIG. 16(A).

[0240] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0241] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 16B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0242] The thin film transistors 4509 and 4510 are the signal transistors including the oxide semiconductor layer described in Embodiment 1. In this embodiment, a thin film transistor having high reliability can be applied. Transistors 4509 and 4510 are n-channel thin film transistors.

[0243] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the channel forming region. By providing the MOSFET in a position overlapping the channel formation region of the semiconductor layer, It is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4509. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a conductive material and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0244] The thin film transistor 4509 is in contact with a semiconductor layer including a channel formation region as a protective insulating layer. The insulating layer 4541 is formed on the insulating layer 10 shown in Embodiment 1. The same materials and methods as those used in the method for forming the thin film transistor 7 may be used. In this embodiment, the insulating layer 4544 is covered with the insulating layer 4544, which functions as a planarizing insulating layer. The insulating layer 4541 was formed by sputtering an oxide film similar to the insulating layer 107 in Embodiment 1. A silicon carbide layer is formed.

[0245] In addition, a protective insulating layer 4543 is formed over the insulating layer 4541. The protective insulating layer 4543 is The protective insulating layer 407 may be formed using a material and a method similar to those of the protective insulating layer 407 described in Embodiment 1. A silicon nitride layer is formed as a protective insulating layer 4543 by a PCVD method.

[0246] In addition, an insulating layer 4544 is formed as a planarizing insulating layer. The insulating layer 4021 may be formed using the same material and method as the insulating layer 4021 described in the third embodiment. The layer 4544 is made of acrylic resin.

[0247] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown in the figure. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0248] The partition 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0249] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0250] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective layer may be formed over 4513 and the partition wall 4520. The protective layer may be a silicon nitride layer, A silicon oxynitride layer, a DLC layer, or the like can be formed.

[0251] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0252] The connection terminal electrode 4515 is a conductive layer that is the same as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive layer.

[0253] The connection terminal electrode 4515 is connected to a terminal of the FPC 4518a via an anisotropic conductive layer 4519. The electrodes are electrically connected to each other.

[0254] The substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In this case, the material may be a glass plate, a plastic plate, a polyester film, or an acrylic resin. A light-transmitting material such as a film is used.

[0255] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of resin or thermosetting resin, and is suitable for PVC (polyvinyl chloride), acrylic resin, etc. Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. Just use it.

[0256] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0257] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driver circuit formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate. Also, only the signal line driver circuit, or a part of the scanning line driver circuit, Only one or a part of the components may be separately formed and mounted, and the configuration is not limited to that shown in FIG.

[0258] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0259] A thin film transistor of a pixel portion of a light-emitting display device can be manufactured by the manufacturing method of the thin film transistor shown in Embodiment 1. By fabricating a transistor, the variation in the threshold voltage of the thin film transistor of each pixel can be eliminated. Therefore, display unevenness caused by the above can be suppressed.

[0260] In addition, a driver circuit of a light-emitting display device can be manufactured by using the manufacturing method of a thin film transistor described in Embodiment 1. By fabricating a thin-film transistor with This can achieve power savings.

[0261] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0262] (Embodiment 6) In this embodiment mode, the thin film transistor described in Embodiment 1 is used as one mode of a semiconductor device. An example of a liquid crystal display device using a liquid crystal element having the above structure will be described with reference to FIGS. 17 to 20. The TFT 628 and the TFT 629 used in the liquid crystal display device of FIG. The thin film transistor shown in FIG. 1 can be applied to the present invention and can be manufactured in the same manner as in the embodiment 1. The TFT628 and TFT629 are thin-film transistors with excellent electrical characteristics and high reliability. 17 to 20 are thin film transistors in which an oxide semiconductor layer is used as a channel formation region. In the case where the thin film transistor shown in FIG. 3C is used as an example of the thin film transistor, However, the present invention is not limited to this.

[0263] A VA (Vertical Alignment) type liquid crystal display device will be described below. A VA type liquid crystal display device is a type of display that controls the alignment of liquid crystal molecules in a liquid crystal display panel. In a VA type liquid crystal display device, when no voltage is applied, the liquid crystal molecules are aligned relative to the panel surface. In this embodiment, the pixels are divided into several regions. The device is designed to divide the image into sub-pixels, each of which tilts the molecules in a different direction. This is called multi-domain or multi-domain design. In the following explanation, multi-domain A liquid crystal display device with carefully designed features will be described.

[0264] 18 and 19 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate side on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. FIG. 17 shows the same. FIG. 19 shows a plan view of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

[0265] FIG. 17 shows a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 630. The substrate 600 and the counter substrate 601 on which the counter electrode 640 and the like are formed are overlapped. , the liquid crystal is injected.

[0266] Although not shown, a protrusion 644 is formed between the substrate 600 and the counter substrate 601. The distance between the pixel electrode 624 and the counter electrode 640 (cell gap) is An alignment film 648 is formed on the pixel electrode 624, and the counter electrode 646 is formed on the pixel electrode 624. An alignment film 646 is also formed on the electrode 640. A liquid crystal layer 650 is formed between them. .

[0267] Although the spacers described here are columnar spacers, bead spacers may be dispersed. Furthermore, the spacers may be formed on the pixel electrodes 624 formed on the substrate 600 .

[0268] On the substrate 600, a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 63 are provided. The pixel electrode 624 includes a TFT 628, a wiring 616, and a storage capacitor 630. A contact hole is formed through an insulating layer 620 covering the insulating layer 620 and an insulating layer 622 covering the insulating layer 620. The TFT 628 is connected to the wiring 618 through a wire 623. The storage capacitor 630 is connected to the gate wiring of the TFT 628. A capacitance wiring 604, which is a first capacitance wiring formed at the same time as 602, and a gate insulating layer 606 The wiring 616 and the wiring 618 are formed at the same time as the second capacitance wiring 617. do.

[0269] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0270] FIG. 18 shows a planar structure on a substrate 600. The pixel electrode 624 is an insulator containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as "IT Indium zinc oxide, indium tin oxide with added silicon oxide, etc. A light-transmitting conductive material can be used.

[0271] In addition, the pixel electrode 624 is made of a conductive material including a conductive polymer. The pixel electrode formed by using the conductive composition can be formed by a sheet Resistance is 10,000Ω / □ or less, and light transmittance at a wavelength of 550nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that there is.

[0272] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0273] The pixel electrode 624 is provided with a slit 625. The slit 625 is used to control the alignment of the liquid crystal. This is for the purpose.

[0274] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode 624, and the storage capacitor 630 can be formed in the same manner. The TFT 628 and the TFT 629 are both connected to the wiring 616. The pixel is composed of a pixel electrode 624 and a pixel electrode 626. The electrode 624 and the pixel electrode 626 are a sub-pixel.

[0275] The planar structure of the opposing substrate side is shown in FIG. 19. The opposing electrode 640 is made of the same material as the pixel electrode 624. On the counter electrode 640, a protrusion 64 for controlling the alignment of the liquid crystal is formed. 4 is formed.

[0276] The equivalent circuit of this pixel structure is shown in Figure 20. TFT628 and TFT629 both have gate The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 are individually controlled. The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0277] When a voltage is applied to the pixel electrode 624 having the slit 625, The electric field is distorted (diagonal electric field). By arranging the 44 in an alternating interdigitated manner, a diagonal electric field is effectively generated to align the liquid crystal. By controlling the orientation, the liquid crystal orientation is made different depending on the location. The multi-domain structure widens the viewing angle of the LCD panel.

[0278] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 21 to 24. do.

[0279] 21 and 22 show the pixel structure of a VA type liquid crystal display panel. FIG. 21 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The following description will refer to both figures.

[0280] In this pixel structure, one pixel has multiple pixel electrodes, each of which is connected to a TFT. Each TFT is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independent. The control circuit has a configuration in which the

[0281] The pixel electrode 624 is connected to the TFT 628 through the contact hole 623 by the wiring 618. The pixel electrode 626 is connected to the TFT through a contact hole 627 by a wiring 619. The gate wiring 602 of the TFT 628 and the gate wiring 629 of the TFT 629 are connected to each other. 603 is separated so that different gate signals can be applied. The wiring 616 that functions as a data line is used in common by the TFT 628 and the TFT 629. The thin film transistors shown in the embodiment mode 1 are appropriately used for the TFT 628 and the TFT 629. In addition, a capacitance line 690 is provided.

[0282] The pixel electrodes 624 and 626 have different shapes. The pixel electrode 624 spreads in a V-shape. The pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624. By applying different voltages to the TFT628 and TFT629, the alignment of the liquid crystal is The equivalent circuit of this pixel structure is shown in Figure 24. 02, and the TFT 629 is connected to the gate wiring 603. The TFT 629 is connected to the wiring 616. The gate wiring 602 and the gate wiring 603 By individually controlling the signals applied to the liquid crystal elements 651 and 652, In other words, the operation of TFT628 and TFT629 can be made different. By controlling them individually, different liquid crystal orientations are achieved in liquid crystal element 651 and liquid crystal element 652. and the viewing angle can be widened.

[0283] A colored layer 636 and a counter electrode 640 are formed on the counter substrate 601. A flattening layer 637 is formed between the electrode 36 and the counter electrode 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 23 shows the structure of the opposing substrate side. The opposing electrode 640 is shared between different pixels. The electrode has a slit 641 formed therein. The slit 641 and the pixel electrode 62 4 and the slit 625 on the pixel electrode 626 side are arranged so as to interdigitate with each other. Therefore, the electric field can be effectively generated to control the alignment of the liquid crystal. The viewing angle can be increased by changing the direction of the light depending on the location. The pixel electrodes 624 and 626 formed on the substrate 600 are indicated by dashed lines. 40, the pixel electrode 624 and the pixel electrode 626 are arranged so as to overlap each other. There are.

[0284] An alignment film 648 is formed on the pixel electrodes 624 and 626. An alignment film 646 is also formed on the substrate 600. A liquid crystal layer 65 is formed between the substrate 600 and the counter substrate 601. 0 is formed.

[0285] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a first liquid crystal element. In addition, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 are overlapped. The second liquid crystal element is formed by the above. The structure is a multi-domain structure in which a first liquid crystal element and a second liquid crystal element are provided in one pixel. do.

[0286] In this embodiment, a liquid crystal display device having the thin film transistor shown in Embodiment 1 is We have explained about A-type liquid crystal display devices, but we have also discussed IPS-type liquid crystal display devices and TN-type liquid crystal display devices. The present invention can also be applied to devices and the like.

[0287] The thin film transistor of the pixel portion of the liquid crystal display device is manufactured by the method for manufacturing the thin film transistor shown in Embodiment 1. By fabricating a thin-film transistor, the variation in the threshold voltage of the thin-film transistor of each pixel can be It is possible to suppress display unevenness caused by the adhesion.

[0288] (Embodiment 7) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train rides, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 25.

[0289] FIG. 25 shows an example of an electronic book. For example, an electronic book 2700 includes a housing 2701 and The housing 2701 and the housing 2703 are The device is integrated with an axis portion 2711, and can be opened and closed with the axis portion 2711 as an axis. This configuration makes it possible to operate like a paper book.

[0290] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 25) and An image can be displayed on the display unit 2707 in FIG.

[0291] FIG. 25 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a display board, a pointing device, etc. On the front side, there is a terminal for external connection (earphone terminal, USB terminal, or AC adapter and USB cable). A terminal that can be connected to various cables such as a USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. Good too.

[0292] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0293] (Embodiment 8) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0294] FIG. 26A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this embodiment, the housing 9601 is supported by a stand 9605. The figure shows a configuration in which

[0295] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0296] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0297] FIG. 26B shows an example of a digital photo frame. In the frame 9700, a display unit 9703 is incorporated in a housing 9701. 3 is capable of displaying various images, for example images taken with a digital camera. By displaying data, it can function just like a normal photo frame.

[0298] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have one as it improves the design. For example, the Digital Photo Frame 9700 Insert a memory that stores image data taken with a digital camera into the recording medium insertion section of the Image data can be captured and the captured image data can be displayed on the display unit 9703. do.

[0299] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0300] FIG. 27(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 27(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and may be at least as described in the present specification. The present invention is not limited to the above, and may be applied to any configuration having the semiconductor device disclosed in the above and other auxiliary equipment. The portable game machine shown in FIG. 27(A) can be used to play a game recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 27(A) has the following functions: The functions are not limited to these, and various functions can be provided.

[0301] FIG. 27(B) shows an example of a slot machine, which is a large gaming machine. Slot Machine 9 The slot machine 900 includes a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in the present specification. The configuration may include appropriate auxiliary equipment.

[0302] FIG. 28A is a perspective view showing an example of a portable computer.

[0303] The portable computer of FIG. 28(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display unit 9303 and a keyboard. The lower housing 9302 having the base 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to type on the keyboard, the hinge unit needs to be opened. The user can perform input operations by looking at the display portion 9303.

[0304] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the touch panel. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the USB communication standard is inserted. There are.

[0305] The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301. 07, it is possible to realize a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display unit.

[0306] The display unit 9303 or the foldable display unit 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses an image display device such as a light-emitting display panel using inorganic light-emitting elements.

[0307] The portable computer shown in FIG. 28A is configured with a receiver and the like, and is also a television. It is possible to receive a broadcast and display the video on the display portion 9303 or the display portion 9307. In addition, the hinge unit connecting the upper housing 9301 and the lower housing 9302 is kept in the closed state. Also, the display unit 9307 can be slid to expose the entire screen, and the user can adjust the screen angle. You can also watch TV broadcasts. In this case, the hinge unit is opened and the display unit 9 303 is not displayed, and only the circuit for displaying the TV broadcast is started. Portable computers with minimal power consumption and limited battery capacity It is useful in.

[0308] FIG. 28(B) shows a portable electronic device that can be worn on the user's arm like a wristwatch. FIG. 13 is a perspective view showing an example of a story.

[0309] This mobile phone is a main body having at least a communication device having a telephone function and a battery. A band part 9204 for attaching the body to the arm, and a fastening state of the band part 9204 to the arm are adjusted. The device is made up of an adjustment unit 9205 for adjusting the temperature, a display unit 9201, a speaker 9207, and a microphone 9208. It has been made.

[0310] The main body also has an operation switch 9203, which serves as a power input switch and a display switching switch. In addition to the camera switch and the camera start switch, there are also other buttons, such as a button that starts an Internet program. It will be launched.

[0311] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 28(B) shows a display button 9202 displayed on a display unit 9201. Input can be made by touching the screen with a finger or other object.

[0312] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0313] The mobile phone shown in FIG. 28(B) is configured with a television broadcast receiver, etc. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in a memory or the like. As a configuration equipped with a storage device, television broadcasts can be recorded in the memory. The mobile phone shown in FIG. 2 may have a function for collecting location information such as GPS.

[0314] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 28(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0315] Although FIG. 28B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around. EXAMPLES

[0316] In this example, a thin film transistor is manufactured by using the manufacturing method shown in Embodiment Mode 1. The results of evaluating the amount of change in Vth before and after the test are shown.

[0317] In this embodiment, a thin film transistor having a channel length L of 3 μm and a channel width W of 20 μm is formed on the same substrate. First, a method for manufacturing a thin film transistor will be described.

[0318] First, a silicon nitride layer is formed as a base layer on a glass substrate by a CVD method. A silicon oxynitride layer was formed on the silicon oxynitride layer as a gate electrode layer by a sputtering method. A tungsten layer was formed. The tungsten layer was then selectively etched to form a gate electrode. A polar layer was formed.

[0319] Next, a 100 nm thick silicon oxynitride layer is formed on the gate electrode layer as a gate insulating layer by the CVD method. A base layer was formed.

[0320] Next, an In-GaN oxide semiconductor with a relative density of 85% was deposited on the gate insulating layer by sputtering. a-Zn-O oxide semiconductor target (molar ratio: In2O3:Ga2O3:ZnO A 30-nm-thick oxide semiconductor layer was formed using a 1:1:1 mixture. The conductor layer was selectively etched to form an island-shaped oxide semiconductor layer.

[0321] Next, the oxide semiconductor layer was subjected to a first heat treatment at 650° C. for 6 minutes in a nitrogen atmosphere by the GRTA method. Processing was carried out.

[0322] Next, a titanium layer (thickness 100 mm) was formed on the oxide semiconductor layer as a source electrode layer and a drain electrode layer. nm), an aluminum layer (200 nm thick), and a titanium layer (100 nm thick) were stacked. The source electrode layer and the drain electrode layer were formed by a sputtering method. The channel length L of the thin film transistor is 3 μm and the channel width W is 20 μm. I did.

[0323] Next, an oxide semiconductor layer was formed by reactive sputtering as a protective insulating layer. Here, the silicon oxide layer, which is a protective layer, is selectively etched to form a gate Openings were formed over the electrode layer, the source electrode layer, and the drain electrode layer. A second heat treatment was performed at 250° C. for 1 hour.

[0324] Through the above steps, a thin film transistor was fabricated.

[0325] Next, a BT test was performed on the thin film transistor fabricated in this example. This is a type of rapid test that measures the changes in the characteristics of thin-film transistors that occur over a long period of time. In particular, the threshold voltage of the thin film transistor before and after the BT test can be evaluated. The amount of change in threshold pressure is an important index for examining reliability. The smaller the change in the value voltage, the more reliable the thin film transistor is.

[0326] Specifically, the temperature of the substrate on which the thin film transistor is formed (substrate temperature) is kept constant. The source and drain of the thin film transistor are set to the same potential, and the gate is connected to the source and drain. A potential different from that of the tester is applied for a certain period of time. The substrate temperature can be set appropriately according to the purpose of the test. The case where the potential applied to the gate is higher than the potentials of the source and drain is called +BT. This is called a -B test, and the case where the potential applied to the gate is lower than the potentials of the source and drain is called a -B test. It's called a T test.

[0327] The test strength of the BT test depends on the substrate temperature, the electric field strength applied to the gate insulating layer, and the electric field application time. The electric field strength applied to the gate insulating layer can be determined by the gate, source and It is determined by dividing the potential difference between the gate and drain by the thickness of the gate insulating layer. If you want to apply a 2MV / cm electric field to a gate insulating layer of 2 nm, you need to set the potential difference to 20V. This can be done as follows.

[0328] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. Generally, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, potential may be read as voltage, Voltage may be read as potential.

[0329] The BT test was performed at a substrate temperature of 150°C, with an electric field strength of 2MV / cm applied to the gate insulating layer. The addition time was set to 1 hour, and both +BT and -BT tests were performed.

[0330] First, the +BT test will be explained. The initial characteristics of the thin film transistor to be subjected to the BT test are For the measurement, the substrate temperature was set at 40°C, and the source-drain voltage (hereafter referred to as drain voltage) was The source-gate voltage (hereafter referred to as gate voltage or Vg) is set to 10 V. The source-drain current (hereafter referred to as drain current) when the voltage was changed from -20V to +20V The change in the gate current (Id), i.e., the Vg-Id characteristic, was measured. The plate temperature is set at 40°C to prevent moisture absorption on the sample surface. If there are no particular problems, the plate temperature can be adjusted It is acceptable to measure the temperature at room temperature (25°C).

[0331] Next, the substrate temperature is raised to 150° C., and then the source and drain of the thin film transistor are The potential at the gate insulating layer was set to 0 V. Then, the electric field strength applied to the gate insulating layer was set to 2 MV / cm. A voltage was applied to the gate so that the thickness of the gate insulating layer of the thin-film transistor was 1 Since the thickness of the gate electrode was 0.00 nm, +20 V was applied to the gate and the gate was held there for 1 hour. Although the application time was set to 1 hour, the time may be changed appropriately depending on the purpose.

[0332] Next, while keeping the voltage applied to the gate, source, and drain, the substrate temperature was lowered to 40°C. If the voltage application is stopped before the substrate temperature drops completely, the residual heat The damage done to the thin film transistor during the BT test is repaired, so the voltage is applied The substrate temperature must be lowered while the voltage is still applied. After the substrate temperature reaches 40°C, the voltage application is stopped. Strictly speaking, the temperature drop time must also be added to the application time, but in practice, it took only a few minutes for the voltage to reach 40 V. Since this was within the margin of error, the temperature drop time was added to the application time. not present.

[0333] Next, measure the Vg-Id characteristics under the same conditions as the initial characteristics measurement, and measure the Vg-Id characteristics after the +BT test. characteristics were obtained.

[0334] Next, we will explain the -BT test. The -BT test is conducted in the same manner as the +BT test, but The difference is that the voltage applied to the gate is set to -20 V after the substrate temperature is raised to 150°C. do.

[0335] In addition, for the BT test, thin-film transistors that have never been subjected to the BT test were used. For example, it is important to use a thin-film transistor that has already undergone a +BT test. If a -BT test is performed using a +BT test, the -BT test results may be inaccurate due to the influence of the +BT test performed earlier. In addition, it is not possible to evaluate the re-use of a thin-film transistor that has already undergone a +BT test. The same applies when a test is conducted for the degree + BT test. However, taking these effects into account, This does not apply when repeating T tests.

[0336] Here, the definition of Vth in this specification will be explained. The voltage is shown on a linear scale, and the vertical axis is the square root of the drain current (hereinafter referred to as √Id). ) on a linear scale. Curve 501 shows the drain current versus the gate voltage. The square root of the current is shown in Fig. 1. The Id of the Vg-Id curve measured with Vd at 10 V is the average This is a curve expressed as a square root (hereinafter referred to as a √Id curve).

[0337] First, obtain the √Id curve (curve 501) from the Vg-Id curve measured with Vd at 10 V. Next, a tangent 504 to the point on the √Id curve where the differential value of the √Id curve is maximum is obtained. Next, the tangent line 504 is extended, and Vg when Id becomes 0 A on the tangent line 504, that is, Vg on the tangent line 504 is The value of the gate voltage axis intercept 505 of 04 is defined as Vth.

[0338] FIG. 30 shows the Vg-Id characteristics of the thin film transistor before and after the BT test. In both Fig. 30(B) and Fig. 30(C), the horizontal axis is the gate voltage (Vg) and the vertical axis is the drain current vs. gate voltage. The in-current (Id) is shown on a logarithmic scale.

[0339] FIG. 30(A) shows the Vg-Id characteristics of a thin-film transistor before and after a +BT test. The initial characteristic 331 is the Vg-Id characteristic of the thin film transistor before the +B T332 is the Vg-Id characteristic of the thin film transistor after the +BT test.

[0340] FIG. 30(B) shows the Vg-Id characteristics of the thin film transistor before and after the -BT test. The initial characteristic 341 is the Vg-Id characteristic of the thin film transistor before the -BT test. T342 is the Vg-Id characteristic of the thin film transistor after the -BT test.

[0341] In FIG. 30(A), +BT332 is a characteristic in which the threshold voltage is positive compared to the initial characteristic 331. In FIG. 30(B), the -BT342 has a change of 0.72 V in the direction of the initial characteristic 34 The threshold voltage has changed by 0.04 V in the positive direction compared to 1. Even if the threshold voltage is changed, the change in the threshold voltage is 1 V or less. The transistor was confirmed to be a highly reliable thin film transistor.

[0342] Here, the results of the BT test of the conventional thin film transistor will be explained. The transistor is a channel-etch type thin film transistor similar to that in the first embodiment. However, in conventional thin-film transistors, a base insulating layer is formed on a glass substrate. A gate electrode layer is formed on the gate electrode layer, and a gate insulating layer is formed on the gate electrode layer by a CVD method. A silicon oxynitride layer with a thickness of 100 nm is formed on the gate insulating layer by sputtering. In-Ga-Zn-O oxide semiconductor target with a relative density of 85% (molar The ratio was In2O3:Ga2O3:ZnO=1:1:1) to form a 20 nm thick oxide semiconductor. A conductor layer is formed, a source electrode and a drain electrode are formed on the oxide semiconductor layer, and a source A CV protective insulating layer was placed on the electrode and drain electrode so as to contact part of the oxide semiconductor layer. The silicon oxynitride layer is formed by the D method. No heat treatment has been performed.

[0343] FIG. 31 shows the Vg-Id characteristics of a conventional thin film transistor before and after a BT test. . In measuring these Vg-Id characteristics, the off region of the thin film transistor used in this embodiment (For N-type transistors, Vg is generally in the negative range from near 0V) and Id is The value was below the lower limit of the measurement. The portion below the lower limit is not shown.

[0344] FIG. 31(A) shows the Vg-Id characteristics of a conventional thin-film transistor before and after a +BT test. The initial characteristic 311 is the Vg-Id characteristic before the +BT test, and the +BT 312 is This is the Vg-Id characteristic after the +BT test.

[0345] FIG. 31(B) shows the Vg-Id characteristics of a conventional thin film transistor before and after the -BT test. The initial characteristic 321 is the Vg-Id characteristic before the -BT test, and the -BT322 is -This shows the Vg-Id characteristics after the BT test.

[0346] In FIG. 31(A), +BT312 is a characteristic in which the threshold voltage is positive compared to the initial characteristic 311. In FIG. 31B, the -BT322 characteristic changes by 5.7 V in the direction of the initial characteristic 321. The threshold voltage has shifted 3.4 V in the negative direction compared to the previous example. [Explanation of symbols]

[0347] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminals 25 Input terminal 26 Output terminal 27 Output terminal 28 Thin-film transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 Substrates 101 Gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 107 Insulating layer 110 Channel protection layer 130 Oxide semiconductor layer 150 Thin-film transistor 160 Thin-film transistor 170 Thin-film transistor 180 Thin Film Transistor 311 Initial Characteristics 312+BT 321 Initial Characteristics 322-BT 331 Initial Characteristics 332+BT 341 Initial Characteristics 342-BT 400 Glass Substrate 401 Oxidation and Nitride Insulation Layer 402 In-Ga-Zn-O oxide semiconductor layer 403 Analysis direction 407 Protective Insulation Layer 411 Oxygen ion intensity profile 412 Hydrogen Concentration Profile 413 Hydrogen Concentration Profile 460 Thin Film Transistor 461 Thin-film transistor 481 Thin Film Transistor 501 curve 504 Tangent line 505 Gate voltage axis intercept 580 Substrate 581 Thin Film Transistor 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 Board 600 Substrates 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate Insulation Layer 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 Insulating layer 622 Insulating layer 623 Contact Hole 624 Pixel electrode 625 Slit 626 Pixel electrode 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 636 Colored layer 637 Planarization layer 640 Counter Electrode 641 Slit 644 Protrusion 646 Orientation Film 648 Orientation Film 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 701 OH group 702 OH group 705 O molecule 710 O molecules 711 Energy 712 Energy 713 Energy 714 Energy 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4501 Board 4502 Pixel section 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive layer 4520 Bulkhead 4540 Conductive layer 4541 Insulation layer 4543 Protective insulation layer 4544 Insulation layer 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing Control Circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin Film Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light emitting element 7003 Cathode 7004 EL layer 7005 Anode 7008 Cathode 7009 Bulkhead 7011 TFT 7012 Light emitting element 7013 Cathode 7014 EL layer 7015 Anode 7016 Shielding membrane 7017 Conductive layer 7019 Bulkhead 7021 TFT 7022 Light emitting element 7023 Cathode 7024 EL layer 7025 Anode 7026 Anode 7027 Conductive layer 7029 Bulkhead 7030 Drain electrode layer 7031 Oxide insulating layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7040 Drain electrode layer 7041 Oxide insulating layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7050 Drain electrode layer 7051 Oxide insulating layer 7053 Planarizing insulating layer 7055 Insulation layer 9201 Display section 9202 Display button 9203 Operation switch 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Mike 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section 105a Source electrode layer 105b Drain electrode layer 4503a Signal line driver circuit 4504a Scanning line driver circuit 4518a FPC 590a black area 590b White area

Claims

[Claim 1] forming a gate electrode layer on a substrate having an insulating surface; forming a gate insulating layer on the gate electrode layer; forming an oxide semiconductor layer on the gate insulating layer; After the oxide semiconductor layer is formed, a first heat treatment is performed; forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer; forming a protective insulating layer on the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer so as to be in contact with a part of the oxide semiconductor layer; A method for manufacturing a semiconductor device, comprising the steps of: forming the protective insulating layer; and performing a second heat treatment.

Images