Nitride semiconductor light-emitting element

Abstract

To provide a method for manufacturing a nitride semiconductor light-emitting element with improved output.SOLUTION: A manufacturing method of a nitride semiconductor light-emitting element 100 includes an n-side layer 10 formation step, an active layer 5 formation step, and a p-side layer 20 formation step. The active layer formation step includes a first stacking portion formation step of forming a first stacking portion including a first well layer containing In and having a first thickness, and a first barrier layer doped with an n-type impurity, in which the first well layer is formed at a first temperature, a second stacking portion formation step of forming a second stacking portion including a second well layer containing In and having a second thickness thicker than the first thickness, and a second barrier layer doped with an n-type impurity, in which the second well layer is formed at a second temperature lower than the first temperature, and a third stacking portion formation step of forming a third stacking portion including a third well layer containing In and having a third thickness thinner than the second thickness, and a third barrier layer doped with a p-type impurity, in which the third well layer is formed at a third temperature higher than the second temperature.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor light emitting device. [Background technology]

[0002] Patent Document 1 discloses a nitride light emitting device including an active layer with a multiple quantum well structure in which well layers and barrier layers are alternately stacked. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-103711 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide a method for manufacturing a nitride semiconductor light emitting device having improved output. [Means for solving the problem]

[0005] A method for manufacturing a nitride semiconductor light-emitting device according to one embodiment of the present invention includes an n-side layer forming step of forming an n-side layer, an active layer forming step of forming an active layer on the n-side layer, and a p-side layer forming step of forming a p-side layer on the active layer, the active layer forming step being a first stacked portion forming step of forming a first stacked portion including a first well layer having a first thickness containing In and a first barrier layer formed on the first well layer and doped with an n-type impurity, the first well layer being formed at a first temperature, and a second thickness containing In and thicker than the first thickness being formed on the first stacked portion. and a second barrier layer formed on the second well layer and doped with an n-type impurity, the second stacking portion forming step being performed to form the second stacking portion at a second temperature lower than the first temperature; and a third stacking portion formed on the second stacking portion, the third stacking portion including a third well layer containing In and having a third thickness thinner than the second thickness, and a third barrier layer formed on the third well layer and doped with a p-type impurity, the third stacking portion forming step being performed to form the third well layer at a third temperature higher than the second temperature. Effect of the Invention

[0006] According to a method for manufacturing a nitride semiconductor light emitting device according to an embodiment of the present invention, a nitride semiconductor light emitting device with improved output can be provided. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing a configuration of a nitride semiconductor light-emitting device according to one embodiment of the present invention. [Diagram 2] 1 is a cross-sectional view showing a configuration of a nitride semiconductor light-emitting device according to one embodiment of the present invention. [Diagram 3] 1 is a process flow diagram showing a process flow of a method for manufacturing a nitride semiconductor light-emitting device according to one embodiment of the present invention. [Figure 4] 1 is a process flow diagram showing a process flow of a method for manufacturing a nitride semiconductor light-emitting device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals. Note that since each drawing is a schematic illustration of the embodiment, the scale, intervals, or positional relationships of each component may be exaggerated, or some components may be omitted. Furthermore, a cross-sectional view may be an end view showing only a cut surface.

[0009] In the following description, components having substantially the same functions are indicated by common reference symbols, and descriptions may be omitted. In addition, terms indicating specific directions or positions (for example, "upper", "lower", and other terms including these terms) may be used. However, these terms are merely used for the purpose of making the relative directions or positions in the referenced drawings easier to understand. As long as the relative directions or positions of the terms "upper", "lower", etc. in the referenced drawings are the same, the arrangement may not be the same in drawings other than the present invention, in actual products, etc. In this specification, the positional relationship expressed as "upper" includes cases where the semiconductor layers are in contact with each other and cases where the semiconductor layers are not in contact but are located above each other. In addition, the thickness of each semiconductor layer is the thickness in the stacking direction of the semiconductor layers.

[0010] Hereinafter, a nitride semiconductor light emitting device obtained by the manufacturing method of this embodiment will be described with reference to the drawings.

[0011] Fig. 1 is a schematic cross-sectional view showing the configuration of the nitride semiconductor light-emitting device of this embodiment. As shown in Fig. 1, the nitride semiconductor light-emitting device 100 includes a substrate 1, an n-side layer 10 and a p-side layer 20 provided on the substrate 1, and an active layer 5 located between the n-side layer 10 and the p-side layer 20. An n-electrode 30 is disposed on the n-side layer 10. A p-electrode 40 is disposed on the p-side layer 20. When a forward voltage is applied between the p-electrode 40 and the n-electrode 30, the active layer 5 emits light.

[0012] (Substrate 1) The substrate 1 may be, for example, an insulating substrate such as sapphire or spinel (MgAl2O4) whose main surface is any one of the C-plane, R-plane, and A-plane. When epitaxially growing a semiconductor layer made of a nitride semiconductor, it is preferable to use a sapphire substrate whose main surface is the C-plane. The nitride semiconductor is In x Al y Ga 1-x-y It includes all semiconductors of compositions in which the composition ratios x and y are changed within the respective ranges in the chemical formula N (0≦x≦1, 0≦y≦1, x+y≦1). Furthermore, SiC (including 6H, 4H, 3C), ZnS, ZnO, GaAs, Si, etc. may be used as the substrate 1. The shape of the substrate 1 as viewed from above may be, for example, rectangular. The length of one side of the substrate 1 is, for example, 100 μm or more and 2000 μm or less, and preferably 500 μm or more and 1000 μm or less. The substrate 1 does not necessarily have to be provided in the end.

[0013] (n side layer 10) 1, the n-side layer 10 includes, in order from the substrate 1 side, an underlayer 2, an n-side contact layer 3, and an n-side superlattice layer 4. The n-side layer 10 includes at least one semiconductor layer including an n-type impurity. The n-type impurity may be, for example, Si (silicon), Ge (germanium), or the like. The n-side layer 10 only needs to have a function of supplying electrons, and may include an undoped layer formed without intentionally doping with n-type or p-type impurities.

[0014] The underlayer 2 is disposed between the substrate 1 and the n-side contact layer 3. By disposing the underlayer 2, the n-side contact layer 3 with high crystallinity can be formed on the upper surface of the underlayer 2. The underlayer 2 may be made of, for example, AlGaN, GaN, or the like. A buffer layer may be formed between the substrate 1 and the underlayer 2. The buffer layer is a layer for reducing lattice mismatch between the substrate 1 and the underlayer 2. The buffer layer may be made of, for example, undoped AlGaN, GaN, or the like. The thickness of the buffer layer is, for example, 20 nm or more and 30 nm or less.

[0015] The n-side contact layer 3 is disposed on the upper surface of the underlayer 2, and at least partially contains an n-type impurity. As shown in Fig. 1, an n-electrode 30 is disposed on the upper surface of the n-side contact layer 3. The n-side contact layer 3 is preferably doped with a relatively high concentration of n-type impurity in order to supply electrons from the n-electrode 30 to the active layer 5. The n-type impurity concentration of the n-side contact layer 3 is, for example, 6 x 10 18 / cm 3 More than 1×10 19 / cm 3 The n-side contact layer 3 may be made of, for example, GaN, AlGaN, or the like. The n-side contact layer 3 may have a laminated structure including multiple semiconductor layers. For example, the n-side contact layer 3 may have a laminated structure in which undoped GaN and GaN doped with n-type impurities are alternately laminated. The thickness of the n-side contact layer 3 is, for example, 5 μm or more and 20 μm or less.

[0016] The n-side superlattice layer 4 is disposed on the upper surface of the n-side contact layer 3. By disposing the n-side superlattice layer 4, the lattice mismatch between the n-side contact layer 3 and the active layer 5 can be reduced, and the crystallinity of the active layer 5 can be improved. The n-side superlattice layer 4 has a laminated structure in which semiconductor layers having different lattice constants are alternately laminated. The n-side superlattice layer 4 includes, for example, n pairs of a single pair including one undoped InGaN layer and one undoped GaN layer. The number of pairs n of the n-side superlattice layer 4 can be, for example, 10 to 40, preferably 15 to 35, more preferably 25 to 35. The n-side superlattice layer 4 does not have to be disposed.

[0017] (active layer 5) FIG. 2 is a schematic cross-sectional view for explaining the detailed structure of the active layer 5. As shown in FIGS. 1 and 2, the active layer 5 has a first stacked portion 51, a second stacked portion 52, and a third stacked portion 53, in that order from the n-side layer 10 side. The active layer 5 further has a fourth stacked portion 54 between the first stacked portion 51 and the second stacked portion 52. The first stacked portion 51 includes a first well layer 51w and a first barrier layer 51b. The second stacked portion 52 includes a second well layer 52w and a second barrier layer 52b. The third stacked portion 53 includes a third well layer 53w and a third barrier layer 53b. The fourth stacked portion 54 includes a fourth well layer 54w and a fourth barrier layer 54b. In this embodiment, the active layer 5 has a plurality of first stacked portions 51, a plurality of second stacked portions 52, one third stacked portion 53, and a plurality of fourth stacked portions 54. The number of the first stacked portions 51 can be, for example, 4 or more and 6 or less. The number of the second stacked portions 52 can be, for example, 4 or more and 8 or less. The number of the fourth stacked portions 54 can be, for example, 1 or more and 4 or less. The active layer 5 may be configured to have a plurality of the third stacked portions 53. The active layer 5 may be configured to have one first stacked portion 51 and one second stacked portion 52. The active layer 5 may not have the fourth stacked portion 54.

[0018] The band gap energy of the first well layer 51w is smaller than the band gap energy of the first barrier layer 51b. The first well layer 51w contains In (indium). The first well layer 51w may be, for example, an undoped InGaN layer. The In composition ratio of the first well layer 51w is, for example, not less than 10% and not more than 15%.

[0019] The first thickness of the first well layer 51w is thinner than the second thickness of the second well layer 52w. This allows more electrons to be supplied to the well layer located closer to the p-side layer 20 than the first well layer 51w, thereby reducing the forward voltage. The first thickness of the first well layer 51w is thinner than the second thickness of the second well layer 52w, and radiative recombination is less likely to occur in the first well layer 51w than in the second well layer 52w. The first thickness can be, for example, 0.5 nm to 4.0 nm, preferably 1.0 nm to 2.5 nm, and more preferably 1.2 nm to 2.0 nm.

[0020] The first barrier layer 51b is disposed on the first well layer 51. The first barrier layer 51b is doped with an n-type impurity. By making the first barrier layer 51b contain the n-type impurity, it becomes easier to supply electrons to the well layer located closer to the p-side layer 20 than the first barrier layer 51b, and the forward voltage can be reduced. For example, a GaN layer containing Si as an n-type impurity can be used for the first barrier layer 51b. The n-type impurity concentration of the first barrier layer 51b may be lower than the n-type impurity concentration of the fourth barrier layer 54b. The n-type impurity concentration of the first barrier layer 51b may be, for example, 1×10 17 / cm 3 More than 3×10 19 / cm 3 Less than or equal to 2×10 17 / cm 3 More than 1×10 19 / cm 3 Less than or equal to 3×10 17 / cm 3 8×10 or more 18 / cm 3 It can be as follows:

[0021] The thickness of the first barrier layer 51b can be set to 5 nm or more and 20 nm or less, preferably 10 nm or more and 18 nm or less. By setting the thickness of the first barrier layer 51b to 5 nm or more, it is possible to reduce a shortage of carriers. By setting the thickness of the first barrier layer 51b to 20 nm or less, it is possible to reduce deterioration of crystallinity caused by an increase in n-type impurities.

[0022] The second well layer 52w is disposed on the first barrier layer 51b. The band gap energy of the second well layer 52w is smaller than the band gap energy of the second barrier layer 52b. The second well layer 52w contains In. The second well layer 52w may be, for example, an undoped InGaN layer.

[0023] The second well layer 52w is the well layer in which radiative recombination is most likely to occur among the multiple well layers included in the active layer 5. The emission peak wavelength of the nitride semiconductor light emitting device 100 is substantially the same as the emission peak wavelength of the second well layer 52w. The second well layer 52w emits, for example, ultraviolet light or visible light. The second well layer 52w can emit, for example, blue light or green light as visible light. The emission peak wavelength of the second well layer 52w can be, for example, 430 nm or more and 570 nm or less, preferably 500 nm or more and 570 nm or less. The In composition ratio of the second well layer 52w can be, for example, 20% or more and 28% or less, preferably 24% or more and 28% or less. The second well layer 52w having an In composition ratio in such a range emits green light.

[0024] The second thickness of the second well layer 52w is thicker than the first thickness of the first well layer 51w. This increases the volume of the second well layer 52w, and improves the probability of radiative recombination of electrons and holes in the second well layer 52w. The second thickness of the second well layer 52w is, for example, 1.5 times or more and 3 times or less than the first thickness of the first well layer 51w. By making the second thickness 1.5 times or more than the first thickness, radiative recombination in the second well layer 52w can occur more easily than in the first well layer 51w. By making the second thickness 3.0 times or less than the first thickness, deterioration of crystallinity due to thickening of the second well layer 52w can be reduced. The second thickness can be, for example, 2.0 nm or more and 5.5 nm or less, preferably 2.5 nm or more and 4.0 nm or less, and more preferably 2.8 nm or more and 3.5 nm or less.

[0025] The second barrier layer 52b is disposed on the second well layer 52w. The second barrier layer 52b is doped with n-type impurities. By making the second barrier layer 52b contain n-type impurities, it becomes easier to supply electrons to the second well layer 52w, and the forward voltage can be reduced. For example, a GaN layer containing Si as an n-type impurity can be used for the second barrier layer 52b. The n-type impurity concentration of the second barrier layer 52b can be, for example, 1×10 17 / cm 3 More than 3×10 19 / cm 3Less than or equal to 2×10 17 / cm 3 More than 1×10 19 / cm 3 Less than or equal to 3×10 17 / cm 3 8×10 or more 18 / cm 3 It can be as follows:

[0026] The thickness of the second barrier layer 52b is preferably thinner than the thickness of the first barrier layer 51b. This allows holes supplied from the third stacking unit 53 side to be easily supplied to the second well layer 52w through the second barrier layer 52b. The thickness of the second barrier layer 52b can be set to 3 nm or more and 15 nm or less, preferably 5 nm or more and 10 nm or less. By setting the thickness of the second barrier layer 52b to 3 nm or more, holes supplied from the third stacking unit 53 side can be easily supplied to the second well layer 52w. By setting the thickness of the second barrier layer 52b to 15 nm or less, deterioration of crystallinity due to an increase in n-type impurities can be reduced.

[0027] The third well layer 53w is disposed on the second barrier layer 52b. The band gap energy of the third well layer 53w is smaller than the band gap energy of the third barrier layer 53b. The third well layer 53w contains In. The third well layer 53w may be, for example, an undoped InGaN layer. The In composition ratio of the third well layer 53w is, for example, not less than 10% and not more than 15%.

[0028] The third thickness of the third well layer 53w is thinner than the second thickness of the second well layer 52w. This allows more holes to be supplied to the second well layer 52w, improving the probability of radiative recombination in the second well layer 52w, thereby improving the light-emitting efficiency of the nitride semiconductor light-emitting device 100. The third thickness of the third well layer 53w is thinner than the second thickness of the second well layer 52w, and radiative recombination is less likely to occur in the third well layer 53w than in the second well layer 52w. The third thickness of the third well layer 53w is thinner than the second thickness of the second well layer 52w. The third thickness of the third well layer 53w can be, for example, 0.5 nm or more and 4.0 nm or less, preferably 1.0 nm or more and 2.5 nm or less, and more preferably 1.2 nm or more and 2.0 nm or less.

[0029] The third barrier layer 53b is disposed on the third well layer 53w. The third barrier layer 53b is doped with a p-type impurity in order to efficiently inject holes into the third well layer 53w or the second well layer 52w. The p-type impurity is, for example, Mg (magnesium). The p-type impurity concentration of the third barrier layer 53b is lower than the p-type impurity concentration of the p-side barrier layer 6 described below. This makes it possible to easily supply holes from the third barrier layer 53b to the second well layer 52w while reducing deterioration of crystallinity caused by increasing the p-type impurity concentration, thereby improving the light emission efficiency of the nitride semiconductor light emitting element 100. The p-type impurity concentration of the third barrier layer 53b is, for example, 1×10 19 / cm 3 5×10 or more 19 / cm 3 Below, 1×10 19 / cm 3 More than 3×10 19 / cm 3 It can be as follows:

[0030] The thickness of the third barrier layer 53b can be, for example, 3 nm to 30 nm, preferably 8 nm to 18 nm, and more preferably 12 nm to 14 nm. By making the thickness of the third barrier layer 53b 3 nm or more, it is possible to reduce deterioration of carrier injection efficiency. By making the film thickness of the third barrier layer 53b 30 nm or less, it is possible to improve the crystallinity of the third barrier layer 53b.

[0031] A first intermediate layer made of an undoped semiconductor layer may be disposed between the third barrier layer 53b and the third well layer 53w. By disposing the first intermediate layer, it is possible to reduce deterioration in reliability caused by the diffusion of p-type impurities contained in the third barrier layer 53b into the second well layer 52w and / or the third well layer 53w. The first intermediate layer may be, for example, an undoped GaN layer.

[0032] The band gap energy of the fourth well layer 54w is smaller than the band gap energy of the fourth barrier layer 54b. The fourth well layer 54w contains In. The fourth well layer 54w may be, for example, an undoped InGaN layer. The In composition ratio of the fourth well layer 54w is, for example, not less than 10% and not more than 15%.

[0033] The fourth thickness of the fourth well layer 54w is thinner than the second thickness of the second well layer 52w. This allows more electrons to be supplied to the well layer located closer to the p-side layer 20 than the fourth well layer 54w, thereby reducing the forward voltage. The fourth thickness of the fourth well layer 54w is thinner than the second thickness of the second well layer 52w, and is less likely to cause radiative recombination than the second well layer 52w. The fourth thickness can be, for example, 0.5 nm to 4.0 nm, preferably 1.0 nm to 2.5 nm, and more preferably 1.2 nm to 2.0 nm.

[0034] The fourth barrier layer 54b is disposed on the fourth well layer 54w. The fourth barrier layer 54b is doped with an n-type impurity. By making the fourth barrier layer 54b contain the n-type impurity, it becomes easier to supply electrons to the well layer located closer to the p-side layer 20 than the fourth barrier layer 54b, and the forward voltage can be reduced. For example, a GaN layer containing Si as an n-type impurity can be used for the fourth barrier layer 54b. The n-type impurity concentration of the fourth barrier layer 54b can be, for example, 1×10 17 / cm 3 More than 1×10 19 / cm 3 Less than or equal to 2×10 17 / cm 3 5×10 or more 18 / cm 3 Less than or equal to 3×10 17 / cm 3 More than 2×10 18 / cm 3 It can be as follows:

[0035] The thickness of the fourth barrier layer 54b can be set to 5 nm or more and 30 nm or less, preferably 10 nm or more and 20 nm or less, and more preferably 13 nm or more and 16 nm or less. By setting the thickness of the fourth barrier layer 54b to 2 nm or more, it is possible to reduce a shortage of carriers. By setting the thickness of the fourth barrier layer 54b to 15 nm or less, it is possible to reduce deterioration of crystallinity caused by an increase in n-type impurities.

[0036] As an example of the thickness of each well layer, the first well layer 51w may be 1.5 nm, the second well layer 52w may be 2.8 nm, and the third well layer 53w may be 1.5 nm. By making the active layer 5 have such a thickness, it is possible to reduce the probability of radiative recombination of electrons and holes in the first well layer 51w and the third well layer 53w, and to facilitate the supply of electrons and holes to the second well layer 52w. Therefore, the luminous efficiency of the nitride semiconductor light emitting device 100 can be improved.

[0037] The first thickness, the third thickness, and the fourth thickness are each thinner than the second thickness. The first thickness, the third thickness, and the fourth thickness may be, for example, the same thickness. Note that the first thickness, the third thickness, and the fourth thickness may not be the same thickness, but may be different thicknesses. For example, the fourth thickness may be thinner than the first thickness. This makes it easier for electrons supplied from the first stacking unit 51 side to be supplied to the second well layer 52w via the fourth well layer 54w.

[0038] In the active layer 5 configured as described above, electrons and holes are efficiently supplied to the second well layer 52w, and radiative recombination occurs more easily in the second well layer 52w than in the other well layers, thereby improving the output of the nitride semiconductor light-emitting element 100.

[0039] (p side layer 20) 1, the p-side layer 20 includes, in order from the active layer 5 side, a p-side barrier layer 6 and a p-side contact layer 7. The p-side layer 20 includes at least one semiconductor layer containing a p-type impurity. The p-type impurity may be, for example, Mg. The p-side layer 20 only needs to have the function of supplying holes, and may include an undoped layer.

[0040] The p-side barrier layer 6 is located closest to the active layer 5 in the p-side layer 20. The p-side barrier layer 6 is arranged to confine electrons. For the p-side barrier layer 6, for example, GaN or AlGaN containing p-type impurities such as Mg can be used. The band gap energy of the p-side barrier layer 6 is larger than the band gap energy of the third barrier layer. The thickness of the p-side barrier layer 6 is, for example, 10 nm or more and 50 nm or less. The p-type impurity concentration of the p-side barrier layer 6 is, for example, 2×10 20 / cm 3 More than 6×10 20 / cm 3 It can be as follows:

[0041] A p-electrode 40 is disposed on the upper surface of the p-side contact layer 7. The p-side contact layer 7 may be made of, for example, GaN or AlGaN containing p-type impurities such as Mg. The thickness of the p-side contact layer 7 is, for example, 10 nm or more and 150 nm or less. The p-type impurity concentration of the p-side contact layer 7 is, for example, 2×10 20 / cm 3 More than 2×10 21 / cm 3 It can be as follows:

[0042] A method for manufacturing the nitride semiconductor light emitting device according to this embodiment will be described below.

[0043] 3, the method for manufacturing the nitride semiconductor light-emitting device according to this embodiment includes an n-side layer forming step, an active layer forming step, a p-side layer forming step, and an electrode forming step. Each semiconductor layer formed in the n-side layer forming step, the active layer forming step, and the p-side layer forming step is formed, for example, by MOCVD (metal organic chemical vapor deposition) in a reaction vessel capable of adjusting the pressure and temperature. Specifically, the n-side layer 10, the active layer 5, and the p-side layer 20 are formed on the substrate 1 by supplying a carrier gas and a raw material gas into the reaction vessel.

[0044] The source gas is appropriately selected according to the semiconductor layer to be formed. For example, trimethylgallium (TMG) gas, triethylgallium (TEG) gas, etc. are used as the source gas containing Ga. For example, ammonia (NH3) gas, etc. are used as the source gas containing N. For example, trimethylaluminum (TMA) gas, etc. are used as the source gas containing Al. For example, trimethylindium (TMI) gas, etc. are used as the source gas containing In. For example, monosilane (SiH4) gas, etc. are used as the source gas containing Si. For example, biscyclopentadienylmagnesium (Cp2Mg) gas, etc. are used as the source gas containing Mg. For example, hydrogen gas, nitrogen gas, etc. are used as the carrier gas.

[0045] (n-side layer formation process) The n-side layer formation step is a step of forming an n-side layer 10 on a substrate 1. The n-side layer formation step includes an underlayer formation step, an n-side contact layer formation step, and an n-side superlattice layer formation step.

[0046] In the underlayer formation step, the underlayer 2 is formed on the substrate 1. Before forming the underlayer 2, a buffer layer may be formed on the substrate 1, and the underlayer 2 may be formed via the buffer layer. The buffer layer is formed by growing an AlGaN layer on the substrate 1 using TMA gas, TMG gas, ammonia gas, or the like as a raw material gas. The temperature when forming the buffer layer is, for example, 600° C. or lower. The underlayer 2 is also formed by growing a GaN layer on the buffer layer using TMG gas and ammonia gas as raw material gas, for example.

[0047] In the n-side contact layer formation step, the n-side contact layer 3 is formed on the underlayer 2 . The n-side contact layer 3 can be formed using, for example, a source gas containing Ga, a source gas containing N, and a source gas containing Si. The n-side contact layer 3 is formed by growing a GaN layer containing n-type impurities using, for example, TMG gas, ammonia gas, monosilane gas, or the like as a source gas. The temperature when forming the n-side contact layer 3 is, for example, 1100°C or higher and 1200°C or higher.

[0048] In the n-side superlattice layer forming step, the n-side superlattice layer 4 is formed on the n-side contact layer 3. The temperature when forming the n-side superlattice layer 4 is preferably lower than the temperature when forming the n-side contact layer 3. The temperature when forming the n-side superlattice layer 4 is, for example, 900°C or more and 950°C or less. The n-side superlattice layer forming step includes, for example, a step of forming an undoped GaN layer using TEG gas, ammonia gas, etc. as a raw material gas, and a step of forming an undoped InGaN layer using TEG gas, TMI gas, ammonia gas, etc. as a raw material gas. The step of forming the undoped GaN layer and the step of forming the undoped InGaN layer are alternately performed multiple times to form the n-side superlattice layer 4 in which the undoped GaN layer and the undoped InGaN layer are alternately stacked. Note that when forming the undoped GaN layer, a gas containing H2 may be used as a carrier gas.

[0049] (Active layer formation process) The active layer forming step is a step of forming an active layer 5 on the n-side layer 10. Fig. 4 is a process flow diagram of the active layer forming step. As shown in Fig. 4, the active layer forming step includes a first stacked portion forming step, a second stacked portion forming step, and a third stacked portion forming step. The active layer forming step further includes a fourth stacked portion forming step after the first stacked portion forming step.

[0050] The first stacked portion forming step is a step of forming a first stacked portion 51 including a first well layer 51w and a first barrier layer 51b formed on the first well layer 51w. The first stacked portion 51 is formed on the n-side layer 10.

[0051] The first well layer 51w can be formed, for example, using a source gas containing In, a source gas containing Ga, and a source gas containing N. The first well layer 51w is formed, for example, by growing an undoped InGaN layer using a source gas such as TEG gas, TMI gas, or ammonia gas. It is preferable that the flow rate ratio of the source gas containing In when forming the first well layer 51w is the same as the flow rate ratio of the source gas containing In when forming the second well layer 52w. This simplifies the manufacturing conditions and makes it easier to form a semiconductor layer having a desired composition.

[0052] The first well layer 51w is formed at a first temperature higher than the second temperature when the second well layer 52w is formed. As a result, the first well layer 51w is formed with good crystallinity, so that the surface state of the semiconductor layer after the first stacking portion forming step can be made closer to flat. As a result, the crystallinity of the second well layer 52w formed on the first stacking portion 51 can be improved. For example, the first temperature is preferably 50° C. or more and 100° C. or less higher than the second temperature. For example, the first temperature is 850° C. or more and 950° C. or less. The first well layer 51w is formed so that the first thickness is thinner than the second thickness of the second well layer 52w. For example, the time when the first well layer 51w is formed is shorter than the time when the second well layer 52w is formed, so that the first thickness of the first well layer 51w can be formed thinner than the second thickness of the second well layer 52w.

[0053] The first barrier layer 51b can be formed using, for example, a source gas containing Ga, a source gas containing Si, and a source gas containing N. The first barrier layer 51b is formed by growing a GaN layer doped with n-type impurities using, for example, TEG gas, monosilane gas, ammonia gas, or the like as a source gas. The temperature when forming the first barrier layer 51b is, for example, 900° C. or more and 1000° C. or less.

[0054] The second stacked section forming step is a step of forming a second stacked section 52 including a second well layer 52w and a second barrier layer 52b formed on the second well layer 52w. The second stacked section 52 is formed on the first stacked section 51. When a fourth stacked section forming step is performed, the second stacked section 52 is formed on the fourth stacked section 54.

[0055] The second well layer 52w can be formed using, for example, a source gas containing In, a source gas containing Ga, and a source gas containing N. The second well layer 52w is formed by growing an undoped InGaN layer using, for example, TEG gas, TMI gas, ammonia gas, or the like as the source gas.

[0056] The second well layer 52w is formed at a second temperature lower than the first temperature when the first well layer 51w is formed. The second temperature is preferably, for example, 50° C. to 100° C. lower than the first temperature. The second temperature is, for example, 750° C. to 850° C. The second well layer 52w is formed to have a second thickness greater than the first thickness of the first well layer 51w. For example, by setting the time for forming the second well layer 52w to be longer than the time for forming the first well layer 51w, the second well layer 52w can be formed to have a second thickness greater than the first thickness of the first well layer 51w.

[0057] The second barrier layer 52b can be formed, for example, using a source gas containing Ga, a source gas containing Si, and a source gas containing N. The second barrier layer 52b is formed, for example, by using TEG gas, monosilane gas, ammonia gas, or the like as a source gas and growing a GaN layer doped with n-type impurities. The temperature when forming the second barrier layer 52b is, for example, 900° C. or more and 1000° C. or less.

[0058] It is preferable to make the growth rate when the second barrier layer 52b is formed slower than the growth rate when the first barrier layer 51b is formed. For example, by making the flow rate ratio of the Ga-containing raw material gas when the second barrier layer 52b is formed smaller than the flow rate ratio of the Ga-containing raw material gas when the first barrier layer 51b is formed, the growth rate when the second barrier layer 52b is formed can be made slower than the growth rate when the first barrier layer 51b is formed. This allows the second barrier layer 52b to be formed with better crystallinity than the first barrier layer 51b. Note that, although the crystallinity can be improved by slowing down the growth rate when the first barrier layer 51b is formed, a heat load tends to be generated on the n-side layer 10 that has already been formed when the first barrier layer 51b is formed. The growth rate when the second barrier layer 52b is formed is, for example, 0.5 to 0.8 times the growth rate when the first barrier layer 51b is formed.

[0059] The third stacked portion forming step is a step of forming a third stacked portion 53 including a third well layer 53w and a third barrier layer 53b formed on the third well layer 53w. The third stacked portion 53 is formed on the second stacked portion 52.

[0060] The third well layer 53w can be formed using, for example, a source gas containing In, a source gas containing Ga, and a source gas containing N. The third well layer 53w is formed by growing an undoped InGaN layer using, for example, TEG gas, TMI gas, ammonia gas, or the like as the source gas.

[0061] The third well layer 53w is formed at a third temperature higher than the second temperature when the second well layer 52w is formed. This allows the third well layer 53w to be formed with good crystallinity, so that the surface state of the semiconductor layer after the third stacking portion forming step can be made closer to flat. As a result, the crystallinity of the third barrier layer 53b formed on the third stacking portion 53 can be improved. The third temperature is preferably, for example, 50° C. to 100° C. higher than the second temperature. The third temperature is, for example, 850° C. to 950° C. The third thickness of the third well layer 53w is formed to be thinner than the second thickness of the second well layer 52w.

[0062] The third barrier layer 53b can be formed, for example, using a source gas containing Ga, a source gas containing Mg, and a source gas containing N. The third barrier layer 53b is formed, for example, by using TEG gas, Cp2Mg gas, ammonia gas, or the like as a source gas and growing a GaN layer doped with p-type impurities. Doping the third barrier layer 53b with p-type impurities makes it easier to supply holes to the second well layer 52w. The temperature when forming the third barrier layer 53b is, for example, 900°C or higher and 1000°C or lower.

[0063] After forming the third well layer 53w, an undoped GaN layer may be formed as a first intermediate layer on the third well layer 53w. When the first intermediate layer is formed, the third barrier layer 53b doped with p-type impurities is formed on the first intermediate layer. By forming the first intermediate layer, it is possible to reduce the deterioration of reliability due to the diffusion of the p-type impurities doped in the third barrier layer 53b to the third well layer 53w side. The third barrier layer 53b may be formed so that the impurity concentration of the third barrier layer 53b is lower than the p-type impurity concentration of the p-side barrier layer 6 by controlling the flow rate ratio of the raw material gas containing Mg.

[0064] The fourth stacked layer portion forming step is a step of forming the fourth stacked layer portion 54 including the fourth well layer 54w and the fourth barrier layer 54b formed on the fourth well layer 54w after the first stacked layer portion forming step. The fourth laminated portion forming step is performed after the first laminated portion forming step and before the second laminated portion forming step. The fourth laminated portion 54 is formed on the first laminated portion 51.

[0065] The fourth well layer 54w can be formed using, for example, a source gas containing In, a source gas containing Ga, and a source gas containing N. The fourth well layer 54w is formed by growing an undoped InGaN layer using, for example, TEG gas, TMI gas, ammonia gas, or the like as the source gas.

[0066] The fourth well layer 54w is formed at a fourth temperature higher than the second temperature when the second well layer 52w is formed. This allows the fourth well layer 54w to be formed with good crystallinity, so that the surface state of the semiconductor layer after the fourth stacking portion forming step can be made closer to flat. As a result, the crystallinity of the second well layer 52w formed on the fourth stacking portion 54 can be improved. The fourth temperature is preferably, for example, 50° C. to 100° C. higher than the second temperature. The fourth temperature is, for example, 850° C. to 950° C. The fourth well layer 54w is formed to have a fourth thickness smaller than the second thickness of the second well layer 52w.

[0067] The fourth barrier layer 54b can be formed, for example, by using a source gas containing Ga, a source gas containing Si, and a source gas containing N. The fourth barrier layer 54b is formed by growing a GaN layer doped with n-type impurities using, for example, TEG gas, monosilane gas, ammonia gas, or the like as a source gas. The temperature when forming the fourth barrier layer 54b is, for example, 900° C. or more and 1000° C. or less.

[0068] It is preferable to make the growth rate when the fourth barrier layer 54b is formed slower than the growth rate when the first barrier layer 51b is formed. For example, by making the flow rate ratio of the Ga-containing source gas when the fourth barrier layer 54b is formed lower than the flow rate ratio of the Ga-containing source gas when the first barrier layer 51b is formed, the growth rate when the fourth barrier layer 54b is formed can be made slower than the growth rate when the first barrier layer 51b is formed. This allows the fourth barrier layer 54b to be formed with better crystallinity than the first barrier layer 51b. The growth rate when the fourth barrier layer 54b is formed is, for example, 0.5 to 0.8 times the growth rate when the first barrier layer 51b is formed.

[0069] It is preferable to perform the second stacking portion forming step multiple times and the third stacking portion forming step once. This allows a plurality of second well layers 52w to be formed, which makes it easier for radiative recombination to occur than when a single second well layer 52w is formed, thereby improving the output. In addition, by providing only one third barrier layer 53b doped with p-type impurities, it is possible to reduce the diffusion of p-type impurities into the second well layer 52w. The second stacking portion forming step can be performed, for example, four to eight times.

[0070] The first laminated portion forming step is preferably performed multiple times. By forming multiple first laminated portions 51 formed with good crystallinity, the surface state of the semiconductor layer after the first laminated portion forming step can be made closer to flat than when one first laminated portion 51 is formed. As a result, the second well layer 52w formed on the first laminated portion 51 can be formed with better crystallinity. The first laminated portion forming step can be performed, for example, four or more times and six or less times. The fourth laminated portion forming step is preferably performed multiple times. By forming multiple fourth laminated portions 54 formed with good crystallinity, the surface state of the semiconductor layer after the fourth laminated portion forming step can be made closer to flat than when one fourth laminated portion 54 is formed. As a result, the second well layer 52w formed on the fourth laminated portion 54 can be formed with better crystallinity. The fourth laminated portion forming step can be performed, for example, two or more times and four or less times.

[0071] In order to reduce decomposition of the InGaN layers constituting the first well layer 51w, the second well layer 52w, and the third well layer 53w, a second intermediate layer may be formed on each well layer after the formation of each well layer. The second intermediate layer can be formed by growing an undoped GaN layer using, for example, TEG gas, ammonia gas, or the like as a source gas.

[0072] The first temperature, the third temperature, and the fourth temperature are each higher than the second temperature. The first temperature, the third temperature, and the fourth temperature may be, for example, the same temperature. The first temperature, the third temperature, and the fourth temperature may not be the same temperature, but may be different temperatures. For example, the first temperature and the fourth temperature may be higher than the third temperature. This improves the crystallinity of the first well layer 51w and the fourth well layer 54w that form the base when the second well layer 52w is formed, and further improves the crystallinity of the second well layer 52w, thereby improving the output of the nitride semiconductor light emitting device 100.

[0073] (p-side layer formation process) The p-side layer forming step is a step of forming the p-side layer 20 on the active layer 5. The p-side layer forming step includes a p-side barrier layer forming step and a p-side contact layer forming step.

[0074] In the p-side barrier layer formation step, a p-side barrier layer 6 is formed on the active layer 5. The p-side barrier layer 6 is For example, the AlGaN layer is formed by growing an AlGaN layer doped with p-type impurities using TEG gas, TMA gas, Cp2Mg gas, and ammonia gas as source gases.

[0075] In the p-side contact layer forming step, the p-side contact layer 7 is formed on the p-side barrier layer 6. For the p-side contact layer, an undoped GaN layer is formed using, for example, TMG gas and ammonia gas as raw material gases. Then, a GaN layer containing p-type impurities is formed on the layer made of undoped GaN using TMG gas, Cp2Mg gas, and ammonia gas as raw material gases. In this way, the p-side contact layer 7 is formed including an undoped GaN layer and a GaN layer containing p-type impurities. From the viewpoint of reducing the forward voltage Vf, it is preferable that the impurity concentration of the p-side contact layer 7 is higher than that of the p-side barrier layer 6.

[0076] After the semiconductor layers are formed by the above steps, the semiconductor layers are subjected to a heat treatment in a reaction vessel, for example, in a nitrogen atmosphere at a temperature of 650 to 800° C.

[0077] (Electrode formation process) After the heat treatment, a part of the p-side layer 20 and a part of the active layer 5 are removed to expose a part of the surface of the n-side contact layer 3. The p-side layer 20 and the active layer 5 can be removed by, for example, reactive ion etching.

[0078] Thereafter, a p-electrode 40 is formed on a part of the upper surface of the p-side contact layer 7, and an n-electrode 30 is formed on a part of the exposed surface of the n-side contact layer 3. Through the above steps, the nitride semiconductor light-emitting device 100 is fabricated. The n-electrode and p-electrode 40 can be formed by, for example, a vapor deposition method, a sputtering method, or the like.

[0079] As described above, electrons and holes are efficiently supplied to the second well layer 52w, and an active layer 5 can be formed in which radiative recombination occurs more easily in the second well layer 52w than in the other well layers. Therefore, according to the method for manufacturing the nitride semiconductor light-emitting device of this embodiment, it is possible to manufacture a nitride semiconductor light-emitting device 100 with improved output.

[0080] <Example> A nitride semiconductor light-emitting device was fabricated by the manufacturing method described below. Each semiconductor layer was formed by MOCVD.

[0081] (Substrate 1) A substrate made of sapphire with a C-plane as the main surface was used as the substrate 1, and first, in a reaction vessel, the sapphire (C-plane) on which the nitride semiconductor was to be formed was cleaned in a hydrogen atmosphere at a temperature of 1050° C. The outer shape of the substrate 1 was a square with each side measuring 650 μm in plan view.

[0082] (Buffer layer) Using TMA gas, TMG gas, and ammonia gas as raw material gases, a buffer layer made of AlGaN was formed to a thickness of about 12 nm on the substrate 1. The temperature when forming the buffer layer was 550°C.

[0083] (base layer 2) Next, the temperature was increased to 1050° C., and TMG gas and ammonia gas were used as the raw material gas to form GaN on the buffer layer to a thickness of about 1 μm. Then, the temperature was increased to 1150° C., and TMG gas and ammonia gas were used as the raw material gas to form GaN to a thickness of about 1 μm. Thus, an underlayer 2 consisting of two layers of GaN was formed.

[0084] (n-side contact layer 3) Next, TMG gas, ammonia gas, and monosilane gas were used at a temperature of 1150° C. to form a layer of silicon having a thickness of 1×10 19 / cm 3 An n-side contact layer 3 made of doped GaN was formed to a thickness of 6 μm.

[0085] (n-side superlattice layer 4) Next, the step of forming an undoped GaN layer and the step of forming an undoped InGaN layer were repeated to form an n-side superlattice layer 4. The step of forming an undoped GaN layer and the step of forming an undoped InGaN layer were regarded as one cycle, and the cycle was repeated 30 times to form an n-side superlattice layer 4 including 30 undoped GaN layers and 30 undoped InGaN layers.

[0086] In the process of forming the undoped GaN layer, the temperature was set to 910°C, TEG gas and ammonia gas were used as the raw material gases, and a layer made of GaN was formed to a thickness of 3 nm.In the process of forming the undoped InGaN layer, the temperature was set to 910°C, TEG gas, TMI gas, and ammonia gas were used as the raw material gases, and a layer made of InGaN was formed to a thickness of 1.5 nm.

[0087] (active layer 5) Next, the temperature was raised to 860°C and In was produced using TEG gas, TMI gas, and ammonia gas as the source gas. 0.15 Ga 0.85 A first well layer 51w having a thickness of 1.5 nm and made of N was formed. Furthermore, a first barrier layer 51b having a thickness of 15 nm and made of GaN doped with n-type impurities was formed on the first well layer 51w at a temperature of 960° C. using TEG gas, monosilane gas, and ammonia gas as raw material gases. The first stacking portion formation step of forming the first well layer 51w and the first barrier layer 51b in this manner was repeated five times.

[0088] Next, the temperature was raised to 860°C and In was produced using TEG gas, TMI gas, and ammonia gas as the source gas. 0.15 Ga 0.85 A fourth well layer 54w having a thickness of 1.5 nm and made of N was formed. Furthermore, a fourth barrier layer 54b having a thickness of 16 nm and made of GaN doped with n-type impurities was formed on the fourth well layer 54w at a temperature of 960° C. using TEG gas, monosilane gas, and ammonia gas as raw material gases. The fourth stacked portion formation step of forming the fourth well layer 54w and the fourth barrier layer 54b in this manner was repeated twice.

[0089] Next, the temperature was raised to 800°C, and In was produced using TEG gas, TMI gas, and ammonia gas as the source gas. 0.25 Ga 0.75A second well layer 52w of 2.8 nm in thickness and made of N was formed. Furthermore, a second barrier layer 52b of 9 nm in thickness and made of GaN doped with n-type impurities was formed on the second well layer 52w at a temperature of 960° C. using TEG gas, monosilane gas, and ammonia gas as source gases. The second stacking portion formation step of forming the second well layer 52w and the second barrier layer 52b in this manner was repeated six times.

[0090] Next, the temperature was raised to 860°C and In was produced using TEG gas, TMI gas, and ammonia gas as the source gas. 0.15 Ga 0.85 A third well layer 53w having a thickness of 1.5 nm and made of N was formed. Furthermore, a first intermediate layer having a thickness of 5.3 nm and made of GaN was formed on the third well layer 53w using TEG gas and ammonia gas as raw material gases. Furthermore, a third barrier layer 53b having a thickness of 13 nm and made of GaN doped with p-type impurities was formed on the first intermediate layer at a temperature of 960° C. using TEG gas, Cp2Mg gas, and ammonia gas as raw material gases. In this manner, the third stacked portion forming step of forming the third well layer 53w and the third barrier layer 53b was performed once.

[0091] (p-side barrier layer 6) Next, the temperature was raised to 960°C, and Mg was added at 2×10 20 / cm 3 Doped Al 0.13 Ga 0.87 A p-side barrier layer 6 made of N was formed to a thickness of 11 nm.

[0092] (p-side contact layer 7) Next, an undoped GaN layer was formed to a thickness of about 80 nm using TMG gas and ammonia gas at a temperature range of 850° C. to 1000° C. Furthermore, Mg was doped at 5×10 on the GaN layer using TMG gas, ammonia gas, and Cp2Mg gas. 20 / cm 3 A layer made of doped GaN was formed to a thickness of about 20 nm. Thus, a p-side contact layer 7 made of two layers of GaN was formed.

[0093] After each semiconductor layer was formed, a heat treatment was performed on each semiconductor layer in a reaction vessel. The heat treatment was carried out in a nitrogen atmosphere at a temperature of 700°C.

[0094] After the heat treatment, a part of the p-side layer 20 and a part of the active layer 5 were removed, and a part of the n-side contact layer 3 was exposed from the p-side layer 20 and the active layer 5.

[0095] Finally, an n-electrode 30 was formed on the upper surface of the n-side contact layer 3, and a p-electrode 40 was formed on the upper surface of the p-side contact layer .

[0096] The nitride semiconductor light emitting device of the example fabricated as described above had a forward voltage Vf of 2.74 V and an output power Po of 115.7 mW. The half width was 26.1 nm. In the example, the forward voltage Vf and the output power Po were values ​​when a current of 100 mA was applied.

[0097] <Reference example> The nitride semiconductor light emitting device according to the reference example was fabricated in the same manner as in the example, except that the active layer 5 was formed under the following conditions.

[0098] (active layer 5) In the reference example, the first well layer 51w, the third well layer 53w, and the fourth well layer 54w were each formed at a temperature of 800° C. The third well layer 53w had a thickness of 3.2 nm, and the fourth well layer 54w had a thickness of 2.8 nm.

[0099] In the nitride semiconductor light emitting device of the reference example fabricated as described above, the forward voltage Vf was 2.73 V and the output power Po was 105.3 mW. The half width was 29.7 nm. In the reference example, the forward voltage Vf and the output power Po were values ​​when a current of 100 mA was applied, as in the example.

[0100] From the above, it is found that, according to the nitride semiconductor light-emitting device of this example, the output is improved by making the second thickness of the second well layer 52w thicker than the first thickness of the first well layer 51w and the third thickness of the third well layer 53w and by making the first temperature and the third temperature higher than the second temperature. Moreover, since the half width of the nitride semiconductor light-emitting device of the example is narrower than the half width of the nitride semiconductor light-emitting device of the reference example, it is presumed that electrons and holes are efficiently supplied to the second well layer 52w and that radiative recombination occurs mainly in the second well layer 52w.

[0101] The embodiments include the following aspects.

[0102] (Appendix 1) an n-side layer forming step of forming an n-side layer; an active layer formation step of forming an active layer on the n-side layer; a p-side layer forming step of forming a p-side layer on the active layer, The active layer forming step includes: a first stacking portion forming step of forming a first stacking portion including a first well layer having a first thickness containing In and a first barrier layer formed on the first well layer and doped with an n-type impurity, the first well layer being formed at a first temperature; a second stacking portion forming step of forming a second stacking portion on the first stacking portion, the second stacking portion including a second well layer containing In and having a second thickness greater than the first thickness, and a second barrier layer formed on the second well layer and doped with an n-type impurity, the second well layer being formed at a second temperature lower than the first temperature; a third stacking portion forming step of forming on the second stacking portion a third stacking portion including a third well layer containing In and having a third thickness thinner than the second thickness, and a third barrier layer formed on the third well layer and doped with a p-type impurity, wherein the third well layer is formed at a third temperature higher than the second temperature.

[0103] (Appendix 2) the active layer forming step further includes, after the first stacking unit forming step, a fourth stacking unit forming step of forming, on the first stacking unit, a fourth well layer having a fourth thickness, and a fourth barrier layer formed on the fourth well layer and doped with an n-type impurity; 2. The method for producing a nitride semiconductor light-emitting device according to claim 1, wherein a growth rate when the fourth barrier layer is formed is slower than a growth rate when the first barrier layer is formed.

[0104] (Appendix 3) In the first stacking portion forming step, a first well layer is formed using a source gas containing In, a source gas containing Ga, and a source gas containing N; In a second stacking portion forming step, a second well layer is formed using a source gas containing In, a source gas containing Ga, and a source gas containing N; 3. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1, wherein a flow rate ratio of the In-containing source gas when forming the first well layer is set to be the same as a flow rate ratio of the In-containing source gas when forming the second well layer.

[0105] (Appendix 4) The second laminated portion forming step is carried out multiple times, 4. The method for producing a nitride semiconductor light-emitting device according to claim 1, wherein the third stacked portion forming step is performed once.

[0106] (Appendix 5) 5. The method for producing a nitride semiconductor light-emitting device according to claim 1, wherein the first stacked portion forming step is performed a plurality of times.

[0107] (Appendix 6) 6. The method for producing a nitride semiconductor light-emitting device according to claim 1, wherein the second thickness of the second well layer is 1.5 to 3 times the first thickness of the first well layer.

[0108] (Appendix 7) 7. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1, wherein the second barrier layer is thinner than the first barrier layer.

[0109] (Appendix 8) 8. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1, wherein the first temperature and the third temperature are higher than the second temperature by 50° C. or more and 100° C. or less.

[0110] (Appendix 9) The In composition ratio of the first well layer is 10% or more and 15% or less, 9. The method for manufacturing a nitride semiconductor light-emitting device according to any one of claims 1 to 8, wherein the In composition ratio of the second well layer is 20% or more and 28% or less. [Explanation of symbols]

[0111] 1 Board 2 Base layer 3. N-side contact layer 4 n-side superlattice layer 5 Active layer 51 First lamination section 51w First well layer 51b First barrier layer 52 Second lamination section 52w 2nd well layer 52b Second barrier layer 53 Third lamination section 53w 3rd well layer 53b Third barrier layer 54 4th lamination section 54w 4th well layer 54b Fourth barrier layer 6 p-side barrier layer 7 p-side contact layer 10 n-side layer 20p side layer 30n electrode 40p electrode 100 Nitride semiconductor light emitting device

Claims

1. an n-side layer forming step of forming an n-side layer; an active layer forming step of forming an active layer on the n-side layer; and forming a p-side layer on the active layer. The active layer forming step includes: a first stacking portion forming step of forming a first stacking portion including a first well layer having a first thickness containing In and a first barrier layer formed on the first well layer and doped with an n-type impurity, the first well layer being formed at a first temperature; a second stacking portion forming step of forming a second stacking portion on the first stacking portion, the second stacking portion including a second well layer containing In and having a second thickness greater than the first thickness, and a second barrier layer formed on the second well layer and doped with an n-type impurity, the second stacking portion forming step being performed to form the second well layer at a second temperature lower than the first temperature; a third stacking portion forming step of forming on the second stacking portion a third stacking portion including a third well layer containing In and having a third thickness thinner than the second thickness, and a third barrier layer formed on the third well layer and doped with a p-type impurity, wherein the third well layer is formed at a third temperature higher than the second temperature.

2. the active layer forming step further includes, after the first stacking portion forming step, a fourth stacking portion forming step of forming, on the first stacking portion, a fourth well layer having a fourth thickness, and a fourth barrier layer formed on the fourth well layer and doped with an n-type impurity, 2. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1, wherein a growth rate when the fourth barrier layer is formed is slower than a growth rate when the first barrier layer is formed.

3. In the first stacking portion forming step, the first well layer is formed using a source gas containing In, a source gas containing Ga, and a source gas containing N; In the second stacking portion forming step, the second well layer is formed using a source gas containing In, a source gas containing Ga, and a source gas containing N; 2. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1, wherein a flow rate ratio of a source gas containing In when forming the first well layer is set to be the same as a flow rate ratio of a source gas containing In when forming the second well layer.

4. The second laminated portion forming step is carried out a plurality of times; The method for manufacturing a nitride semiconductor light-emitting device according to claim 1 , wherein the third stacked portion forming step is performed once.

5. The method for manufacturing a nitride semiconductor light-emitting device according to claim 4 , wherein the first laminated portion forming step is performed a plurality of times.

6. 6. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1, wherein the second thickness of the second well layer is 1.5 to 3 times the first thickness of the first well layer.

7. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1 , wherein the second barrier layer is thinner than the first barrier layer.

8. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1 , wherein the first temperature and the third temperature are higher than the second temperature by 50° C. or more and 100° C. or less.

9. the In composition ratio of the first well layer is 10% or more and 15% or less; The method for manufacturing a nitride semiconductor light-emitting device according to claim 1 , wherein the In composition ratio of the second well layer is not less than 20% and not more than 28%.

Images