Semiconductor device

Abstract

To provide a semiconductor device with less loss.SOLUTION: A semiconductor device includes a semiconductor substrate 10, an emitter electrode 52 provided on an upper surface thereof, an N-type drift region 18, a P-type base region 14 provided between the drift region and an upper surface of the semiconductor substrate, a plurality of trench parts 30, 40, an N-type region 16 provided in mesa parts 60, 61 held between the two trench parts and having higher impurity concentration than the drift region, a P-type region 15 provided in a first mesa part 60 held between the two trench parts and having higher impurity concentration than that of the base region, a trench contact 54 in which a conductive material in contact with at least a part of the semiconductor substrate is provided inside a groove part provided in the mesa part and the conductive material is connected to the N-type region and the emitter electrode, and a P-type first concentration plug region 55 provided below a bottom surface of the groove part and having higher impurity concentration than that of the base region.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices provided with transistors such as insulated gate bipolar transistors (IGBTs) are known (see, for example, Patent Documents 1 to 3). [Prior art document] [Patent documents] Patent Document 1: JP 2010-147381 A Patent Document 2: JP 2012-156564 A Patent Document 3: JP 2010-147380 A Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable that the semiconductor device has low loss. [Means for solving the problem]

[0004] In order to solve the above problem, a first aspect of the present invention provides a semiconductor device including a semiconductor substrate and a first electrode provided on an upper surface of the semiconductor substrate. In the above semiconductor device, the semiconductor substrate may include an N-type drift region, a P-type base region provided between the drift region and the upper surface of the semiconductor substrate, a plurality of trenches, an N-type region provided in a first mesa portion sandwiched between the two trenches and having a higher impurity concentration than the drift region, a P-type region provided in a second mesa portion sandwiched between the two trenches and having a higher impurity concentration than the base region, a trench contact provided in a groove provided in the first mesa portion and having a conductive material that contacts at least a part of the semiconductor substrate, the trench contact being connected to the N-type region and the first electrode, and a P-type first high concentration region provided below a bottom surface of the groove and having a higher impurity concentration than the base region.

[0005] In the semiconductor device described above, the P-type region may also be provided in the first mesa portion. In any of the semiconductor devices described above, a bottom surface of the groove may be located deeper within the semiconductor substrate than a bottom surface of the P-type region.

[0006] In any of the above semiconductor devices, an upper surface of the first high concentration region may be located deeper inside the semiconductor substrate than the P-type region. In any of the above semiconductor devices, the trench portions may be arranged along a first direction in a top view, and a width of the first high concentration region in the first direction may be larger than a width of a bottom surface of the groove portion in the first direction.

[0007] In any of the above semiconductor devices, the N-type region and the P-type region may be provided between the base region and an upper surface of the semiconductor substrate.

[0008] In any of the above semiconductor devices, the trenches may include a gate trench and a dummy trench. In any of the above semiconductor devices, the N-type region may be in contact with the gate trench. In any of the above semiconductor devices, the P-type region may be in contact with the dummy trench.

[0009] In any of the above semiconductor devices, the second mesa portion may be sandwiched between the two dummy trench portions.

[0010] In any of the semiconductor devices described above, the first high concentration region may have an impurity concentration higher than that of the P-type region.

[0011] In any of the above semiconductor devices, the plurality of trench portions may be provided from an upper surface of the semiconductor substrate to the drift region.

[0012] Any of the above semiconductor devices may further include an N-type accumulation region between the drift region and the base region of the first mesa portion. Any of the above semiconductor devices may further include an N-type accumulation region between the drift region and the base region of the second mesa portion.

[0013] In any of the above semiconductor devices, the semiconductor substrate may be a silicon substrate or a compound semiconductor substrate. In any of the above semiconductor devices, the plurality of trench portions may be arranged along a first direction in a top view. In any of the above semiconductor devices, each of the plurality of trench portions may be provided extending in a second direction intersecting the first direction in the top view. In any of the above semiconductor devices, an interlayer insulating film may be provided over the entire upper part of the second mesa portion in a cross section of the semiconductor substrate in a depth direction parallel to the first direction at at least a portion of a position in the second direction. In any of the above semiconductor devices, the second mesa portion may be a floating mesa portion electrically insulated from the first electrode by the interlayer insulating film.

[0014] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2A] FIG. 2 is an enlarged view of an area A in FIG. [Figure 2B] 13 is a diagram showing another example of the arrangement of the cathode regions 82 in a top view. FIG. [Diagram 3] FIG. 2C is a diagram showing an example of the bb cross section in FIGS. 2A and 2B. [Figure 4] 2 is a perspective cross-sectional view showing a structural example of a mesa portion 60. FIG. [Diagram 5] 3 is a cross-sectional view showing an example of the structure of a mesa portion 60. FIG. [Figure 6] 2 is a perspective cross-sectional view showing a structural example of a mesa portion 61. FIG. [Figure 7] 13 is a perspective cross-sectional view showing another example of the structure of the mesa portion 61. FIG. [Figure 8] 4 is a cross-sectional view showing a structural example of an end portion of an active portion 120 in the X-axis direction. FIG. [Figure 9] 2 is an XZ cross-sectional view showing an example of a mesa portion 62 of the semiconductor device 100. FIG. [Figure 10] 2A to 2C are diagrams illustrating some steps in a manufacturing method of the semiconductor device 100. [Figure 11] FIG. 5 is a diagram showing another example of the bb cross section in FIGS. 2A and 2B. [Figure 12] 1 is a diagram comparing the characteristics of the semiconductor device 100 according to the embodiment and a semiconductor device according to a comparative example. [Figure 13] 11 is a diagram showing an example of hole density distribution in the depth direction in a diode section 80 of an example and a comparative example. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0017] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0018] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis. In this specification, the view from the +Z-axis direction may be referred to as a top view.

[0019] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0020] In this specification, the conductivity type of the doped region doped with impurities is described as P type or N type. However, the conductivity type of each doped region may be the opposite polarity. In addition, when described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type, and when described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. In addition, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0021] In this specification, the doping concentration refers to the concentration of an impurity activated as a donor or an acceptor. In this specification, the difference in concentration between the donor and the acceptor may be referred to as the doping concentration. The difference in concentration can be measured by a voltage-capacitance measurement method (CV method). The carrier concentration measured by a spreading resistance measurement method (SR) may be referred to as the doping concentration. When the doping concentration distribution has a peak, the peak value may be referred to as the doping concentration in the region. When the doping concentration in the region where the donor or the acceptor is present is almost uniform, the average value of the doping concentration may be referred to as the doping concentration in the region. In this specification, the concentration of the dopant refers to the respective concentrations of the donor and the acceptor.

[0022] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0023] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has edges 102 in a top view. When the term "top view" is used in this specification, it means that the semiconductor substrate 10 is viewed from the top surface side. The semiconductor substrate 10 of this example has two pairs of edges 102 that face each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to either of the edges 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0024] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in the on state. An emitter electrode is provided above the active portion 120, but is omitted in FIG.

[0025] The active section 120 is provided with a transistor section 70 including a transistor element such as an IGBT. The active section 120 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD).

[0026] In FIG. 1, the region in which the transistor section 70 is arranged is marked with the symbol "I", and the region in which the diode section 80 is arranged is marked with the symbol "F". The transistor section 70 and the diode section 80 are arranged side by side along a predetermined arrangement direction (the X-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may be arranged alternately side by side in the X-axis direction. In this specification, a direction perpendicular to the arrangement direction in a top view may be referred to as an extension direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of the trench section.

[0027] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 in which the diode section 80 is extended in the Y-axis direction to a gate wiring to be described later may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0028] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an end edge 102. The vicinity of the end edge 102 refers to the region between the end edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0029] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to a conductive portion of the gate trench portion of the active portion 120. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0030] The gate wiring in this example has a peripheral gate wiring 130 and an active side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 120 and the edge 102 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 120 in a top view. The area surrounded by the peripheral gate wiring 130 in a top view may be the active portion 120. The peripheral gate wiring 130 is connected to the gate pad 112. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring.

[0031] The active side gate wiring 131 is provided in the active section 120. By providing the active side gate wiring 131 in the active section 120, the variation in wiring length from the gate pad 112 for each region of the semiconductor substrate 10 can be reduced.

[0032] The active side gate wiring 131 is connected to a gate trench portion of the active section 120. The active side gate wiring 131 is disposed above the semiconductor substrate 10. The active side gate wiring 131 may be a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0033] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 is provided extending in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 at approximately the center in the Y-axis direction so as to cross the active portion 120.

[0034] Furthermore, the semiconductor device 100 may include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor section provided in the active section 120.

[0035] The semiconductor device 100 of this example includes an edge termination structure 90 between the peripheral gate wiring 130 and the edge 102. The edge termination structure 90 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has, for example, a guard ring provided in an annular shape surrounding the active portion 120, a field plate, a resurf, or a structure that combines these.

[0036] Fig. 2A is an enlarged view of region A in Fig. 1. Region A is a region including a transistor portion 70, a diode portion 80, and an active side gate wiring 131. In the semiconductor substrate 10 of this example, a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 are provided in contact with the upper surface of the semiconductor substrate 10. In addition, in the semiconductor substrate 10 of this example, a cathode region 82 and a collector region 22 are provided in contact with the lower surface of the semiconductor substrate 10.

[0037] Moreover, an emitter electrode 52 and an active side gate wiring 131 are provided above the semiconductor substrate 10. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10. The emitter electrode 52 is also connected to the dummy conductive portion of the dummy trench portion 30. An interlayer insulating film may be provided between the emitter electrode 52 and the semiconductor substrate 10. A contact hole for connecting the emitter electrode 52 and the semiconductor substrate 10 may be provided in the interlayer insulating film.

[0038] An insulating film such as a thermal oxide film is provided between the active side gate wiring 131 and the semiconductor substrate 10. The active side gate wiring 131 is connected to a gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate 10. The active side gate wiring 131 is not connected to a dummy conductive portion in the dummy trench portion 30. The gate trench portion 40 is provided extending in the Y-axis direction to below the gate wiring such as the active side gate wiring 131. The gate conductive portion of the gate trench portion 40 is connected to the gate wiring.

[0039] A well region 11 is provided below the active side gate wiring 131. The well region 11 has a doping concentration higher than that of the base region 14, is formed in contact with the upper surface of the semiconductor substrate 10, and is formed to a position deeper than the bottom of the base region 14. The width of the well region 11 in the Y-axis direction may be larger than the width of the active side gate wiring 131 in the Y-axis direction.

[0040] The transistor section 70 is provided with a gate trench section 40. The diode section 80 is provided with a dummy trench section 30. The transistor section 70 may also be provided with a dummy trench section 30. The gate trench section 40 functions as a gate electrode to which a gate potential is applied in the transistor section 70. An emitter potential is applied to the dummy trench section 30.

[0041] The gate trench portion 40 and the dummy trench portion 30 have a longitudinal direction in the Y-axis direction in a top view. That is, the gate trench portion 40 and the dummy trench portion 30 are provided extending in the Y-axis direction. The gate trench portion 40 and the dummy trench portion 30 may have a straight line portion parallel to the Y-axis direction.

[0042] The gate trench portions 40 and the dummy trench portions 30 are arranged at a predetermined interval in the X-axis direction. The arrangement pattern of the gate trench portions 40 and the dummy trench portions 30 is not limited to the example of FIG. 2A. A group including one or more gate trench portions 40 and a group including one or more dummy trench portions 30 may be arranged alternately along the X-axis direction.

[0043] At least one trench portion may have two straight portions connected at their ends by a curved end portion. In the example of FIG. 2A, the gate trench portion 40 has two straight portions 39 and one end portion 41. Similarly, the dummy trench portion 30 may have two straight portions 29 and one end portion 31. The dummy trench portion 30 may have only straight portions. The end of each trench portion in the Y-axis direction may be disposed inside the well region 11. This can alleviate electric field concentration at the end of the trench portion.

[0044] In this specification, the region of the semiconductor substrate 10 sandwiched between two straight line portions of the trench portion in the X-axis direction may be referred to as a mesa portion. The transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. The mesa portion is a region of the semiconductor substrate 10 sandwiched between the trench portions, which is located above the deepest bottom of the trench portion.

[0045] A P-type base region 14 is provided in each mesa portion. The base region 14 is exposed on a part of the upper surface of the mesa portion. A contact region 15 and an emitter region 12 are provided on the upper surface of the base region 14 of the transistor portion 70. The contact region 15 in this example is a P+ type having a higher doping concentration than the base region 14. The emitter region 12 in this example is an N+ type having a higher doping concentration than a drift region described later.

[0046] The emitter region 12 is provided in contact with the gate trench portion 40 on the upper surface of the semiconductor substrate 10. The emitter region 12 and the contact region 15 in this example are provided from one trench portion to the other trench portion sandwiching the mesa portion 60. On the upper surface of the mesa portion 60 in this example, the contact regions 15 and the emitter regions 12 are alternately arranged along the Y-axis direction.

[0047] In another example, the contact region 15 and the emitter region 12 may be provided in a stripe shape along the Y-axis direction in the mesa portion 60. For example, the emitter region 12 is provided in a region adjacent to the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12. A base region 14 may be disposed on the upper surface of the mesa portion 60, sandwiching the region in which the contact region 15 and the emitter region 12 are provided in the Y-axis direction.

[0048] The mesa portion 61 of the diode portion 80 may not be provided with the emitter region 12. In this example, a base region 14 is provided on the upper surface of the mesa portion 61. The base region 14 may occupy more than half the area of ​​the upper surface of the mesa portion 61. A contact region 15 may be disposed on the upper surface of the mesa portion 61. The contact region 15 of the mesa portion 61 may be provided at a position overlapping with the end of the trench contact 54 in the Y-axis direction. The base region 14 may be provided on the upper surface of the mesa portion 61, sandwiching the contact region 15 in the Y-axis direction.

[0049] Each of the mesa portions 60 and 61 is provided with a trench contact 54. The trench contact 54 includes a contact trench (groove portion) formed from the upper surface of the semiconductor substrate 10 to the inside of the semiconductor substrate 10, and a conductive portion filled in the trench. The conductive portion may be formed of the same material as the emitter electrode 52 and continuous with the emitter electrode 52, or may be formed of a material different from that of the emitter electrode 52.

[0050] The trench contact 54 penetrates the contact region 15 in the depth direction (Z-axis direction). That is, by providing the trench contact 54, the volume of the contact region 15 is reduced. This makes it possible to suppress hole injection from the contact region 15 when the gate of the transistor section 70 is turned off and the transistor section 70 operates as a diode. This makes it possible to reduce reverse recovery loss in the diode section 80.

[0051] Furthermore, by providing the trench contact 54, it is possible to increase the contact area between the conductive portion and the semiconductor substrate 10. Therefore, even if the widths of the mesa portions 60 and 61 in the X-axis direction are reduced, an increase in the contact resistance between the emitter electrode 52 and the semiconductor substrate 10 can be suppressed.

[0052] The width of the trench contact 54 in the X-axis direction is smaller than the width of each mesa portion in the X-axis direction. Both ends of the trench contact 54 in the Y-axis direction may be provided in the contact regions 15 arranged at both ends in the Y-axis direction, among the contact regions 15 of each mesa portion.

[0053] The trench contact 54 provided in the mesa portion 60 and the trench contact 54 provided in the mesa portion 61 may have the same length in the Y-axis direction or may have different lengths. In the mesa portion 60, the trench contact 54 is provided above the contact region 15 and the emitter region 12. The contact region 15 and the emitter region 12 may be disposed in a range in which the trench contact 54 is provided. The trench contact 54 in this example is not provided in a region corresponding to the base region 14 and the well region 11 of the mesa portion 60. In the mesa portion 61, the trench contact 54 is provided above the contact region 15 and the base region 14. However, the trench contact 54 is not provided above the base region 14 sandwiched between the contact region 15 and the well region 11 in the mesa portion 61.

[0054] In the diode section 80, an N+ type cathode region 82 is provided in a region in contact with the lower surface of the semiconductor substrate 10. A collector region 22 is provided in a region in contact with the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. In the Y-axis direction, the cathode region 82 is disposed away from the well region 11. At least one of the base region 14 and the contact region 15 may be disposed between the cathode region 82 and the well region 11 in a top view. In this example, the distance between the cathode region 82 and the well region 11 in the Y-axis direction is greater than the distance between the trench contact 54 and the well region 11 in the Y-axis direction.

[0055] 2B is a diagram showing another example of the arrangement of the cathode region 82 in a top view. In this example, the position of the end of the cathode region 82 in the Y-axis direction coincides with the position of the end of the trench contact 54. By providing the trench contact 54, it becomes easier to extract carriers, so that even if the cathode region 82 is brought close to the well region 11, it becomes easier to ensure the withstand voltage.

[0056] The position of the end of the cathode region 82 in the Y-axis direction does not have to coincide with the position of the end of the trench contact 54. The end of the cathode region 82 in the Y-axis direction may be provided at a position overlapping with the contact region 15. The end of the cathode region 82 in the Y-axis direction may be disposed between the trench contact 54 and the well region 11.

[0057] 2A and 2B. The bb cross section is an XZ plane passing through the contact region 15. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an emitter electrode 52, and a collector electrode 24.

[0058] The emitter electrode 52 may be in contact with the upper surface 21 of the semiconductor substrate 10 at each mesa portion. In other words, no insulating film is provided between each mesa portion and the emitter electrode 52. The insulating film does not extend directly above each mesa portion, but is embedded in the trench portion. The emitter electrode 52 may be in contact with the upper surface 21 in a range including the multiple mesas and the multiple trench portions. With this configuration, the contact area between the mesa portion and the emitter electrode 52 can be ensured even if the width of the mesa portion in the X-axis direction is reduced.

[0059] The collector electrode 24 may be provided over the entire lower surface 23 of the semiconductor substrate 10. The collector electrode 24 and the emitter electrode 52 may be formed of a metal material such as aluminum.

[0060] A P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in the cross section. A P+ type contact region 15 and a P- type base region 14 are provided in this order from the upper surface 21 of the semiconductor substrate 10 on the upper surface 21 side of the semiconductor substrate 10 in the transistor portion 70 in the cross section. A P- type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in the diode portion 80 in the cross section.

[0061] In each mesa portion, an N+ type accumulation region 16 having a doping concentration higher than that of the drift region 18 may be provided between the base region 14 and the drift region 18. The accumulation region 16 does not have to be provided in the mesa portion 61. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be improved, and the on-voltage in the transistor portion 70 can be reduced.

[0062] In the transistor section 70 and the diode section 80, an N− type drift region 18 is provided below the base region 14. In the transistor section 70 and the diode section 80, an N+ type buffer region 20 is provided below the drift region 18.

[0063] The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0064] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. In the diode section 80, a cathode region 82 is provided below the buffer region 20.

[0065] On the upper surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are provided. Each trench portion is provided so as to reach the drift region 18 from the upper surface 21 of the semiconductor substrate 10 through the base region 14. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions and reaches the drift region 18. The trench portion penetrating the doping region is not limited to a case where the trench portion is formed in the order of forming the doping region and then the trench portion. A case where the trench portion is formed and then the doping region is formed between the trench portions is also included in the case where the trench portion penetrates the doping region.

[0066] The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44 provided on the upper surface 21 side of the semiconductor substrate 10. The gate insulating film 42 is provided to cover the inner wall of the gate trench portion 40. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench portion 40. The gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench portion 40. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0067] The gate conductive portion 44 includes a region facing the base region 14 with the gate insulating film 42 interposed therebetween. The gate conductive portion 44 is insulated from the emitter electrode 52 by the interlayer insulating film 38. The interlayer insulating film 38 is, for example, silicate glass such as PSG or PBSG. At least a portion of the interlayer insulating film 38 may be provided inside the gate trench. At least a portion of the interlayer insulating film 38 may be provided on the upper surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0068] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench provided on the upper surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. In the cross section, the dummy conductive portion 34 may be insulated from the emitter electrode 52 by the interlayer insulating film 38. The dummy conductive portion 34 may be connected to the emitter electrode 52 by a contact hole or the like provided in the interlayer insulating film 38 in a cross section different from that of FIG. 3. At least a portion of the interlayer insulating film 38 may be provided inside the dummy trench. At least a portion of the interlayer insulating film 38 may be provided on the upper surface 21 of the semiconductor substrate 10.

[0069] At least one mesa portion is provided with a trench contact 54 made of a conductive material. The trench contact 54 may be made of the same material as the emitter electrode 52, or may be made of a material such as tungsten. By forming the trench contact 54 from a material containing tungsten, it is possible to easily form a fine trench contact 54. The trench contact 54 is connected to the emitter electrode 52.

[0070] The trench contact 54 is provided to penetrate the contact region 15. That is, the trench contact 54 is provided from the upper surface 21 of the semiconductor substrate 10 to a position reaching the base region 14. The lower end of the trench contact 54 may be at the same position as the lower end of the base region 14, or may be located lower than the lower end of the base region 14. The trench contact 54 may penetrate the emitter region 12 in a cross section different from that in FIG. 3.

[0071] As described above, the trench contact 54 penetrates the contact region 15, thereby reducing the size of the contact region 15. This makes it possible to suppress hole injection from the contact region 15 to the drift region 18.

[0072] A P++-type high-concentration plug region 55 having a higher doping concentration than the contact region 15 is provided in a region in contact with the bottom of the trench contact 54. The high-concentration plug region 55 may cover the entire bottom surface of the trench contact 54. The doping concentration of the high-concentration plug region 55 may be at least twice, at least five times, or at least ten times that of the contact region 15. By providing the high-concentration plug region 55, the contact resistance between the trench contact 54 and the semiconductor substrate 10 can be reduced. In addition, the high-concentration plug region 55 and the trench contact 54 make it easier to extract holes from the semiconductor substrate 10. This can further reduce reverse recovery loss. The thickness of the high-concentration plug region 55 in the depth direction is preferably smaller than the thickness of the contact region 15 in the depth direction.

[0073] The transistor section 70 may have a boundary section 72 that contacts the diode section 80. The boundary section 72 includes one or more mesa sections 60. The mesa section 60 at the boundary section 72 may have the same configuration as the mesa section 60 outside the boundary section 72.

[0074] The trench contact 54 and the high-concentration plug region 55 may be provided in the mesa portion 60 of the boundary portion 72. This makes it possible to reduce holes flowing from the contact region 15 of the boundary portion 72 to the diode portion 80. The trench contact 54 and the high-concentration plug region 55 may be provided only in the boundary portion 72, or may be provided in a portion other than the boundary portion 72.

[0075] The trench contact 54 and the high-concentration plug region 55 may be provided in the mesa portion 60 other than the boundary portion 72. The trench contact 54 and the high-concentration plug region 55 may be provided in all the mesa portions 60 of the transistor portion 70. The trench contact 54 and the high-concentration plug region 55 may be provided in all the mesa portions 60 having the contact region 15 and the emitter region 12. This makes it possible to reduce holes flowing from the entire transistor portion 70 to the diode portion 80.

[0076] The trench contact 54 and the high-concentration plug region 55 may also be provided in the diode portion 80. The trench contact 54 and the high-concentration plug region 55 may be provided in all the mesa portions 61 of the diode portion 80. The trench contact 54 provided in the mesa portion 61 may be formed to the same depth as the trench contact 54 provided in the mesa portion 60, or may be formed to a different depth. In the mesa portion 61 as well, the trench contact 54 may penetrate the contact region 15.

[0077] Fig. 4 is a perspective cross-sectional view showing a structural example of the mesa portion 60. In Fig. 4, the contact trench 57 of the trench contact 54 is shown, and the conductive material filled in the contact trench 57 is omitted.

[0078] In this example, the contact region 15 is provided to a position deeper than the emitter region 12. As shown in Fig. 4, the contact trench 57 is provided to penetrate the contact region 15 and the emitter region 12. When the emitter region 12 is provided to a position deeper than the contact region 15, the contact trench 57 may be provided to a position deeper than the lower end of the emitter region 12, or may be provided to a position shallower than the lower end of the emitter region 12.

[0079] A P++ type high concentration plug region 55 is provided at the bottom of the contact trench 57. The contact region 15, the emitter region 12, and the base region 14 may be exposed at the side of the contact trench 57. The high concentration plug region 55 may be exposed at the bottom of the contact trench 57. The trench contact 54 may be in contact with the contact region 15, the emitter region 12, the base region 14, and the high concentration plug region 55.

[0080] 5 is a cross-sectional view showing a structural example of the mesa portion 60. In this example, in the depth direction of the semiconductor substrate 10, the thickness of the high-concentration plug region 55 is T1, the thickness of the contact region 15 is T2, the protruding length of the contact trench 57 protruding downward from the lower end of the contact region 15 is T3, and the thickness of the base region 14 below the high-concentration plug region 55 is T4. The thickness or length of each member may be the maximum value of the thickness or length of each member.

[0081] In this example, the thickness T1 of the high-concentration plug region 55 is smaller than the thickness T2 of the contact region 15. The thickness T1 may be equal to or less than half, equal to or less than ¼, or equal to or less than 1 / 10 of the thickness T2. This makes it possible to suppress the injection of holes from the high-concentration plug region 55. The product of the thickness T1 and the doping concentration in the high-concentration plug region 55 may be smaller than the product of the thickness T2 and the doping concentration in the contact region 15.

[0082] The lower end of the high-concentration plug region 55 is provided above the lower end of the base region 14. In other words, the high-concentration plug region 55 is disposed within the base region 14 and does not contact the accumulation region 16 or the drift region 18. This prevents the trench contact 54 from being connected to an N-type region via the high-concentration plug region 55.

[0083] The protrusion length T3 of the contact trench 57 is smaller than the thickness T4 of the base region 14. If the protrusion length T3 is large, the distance between the high-concentration plug region 55 and the drift region 18 (or the accumulation region 16) becomes short, resulting in a decrease in the breakdown voltage. The protrusion length T3 may be half or less of the thickness T4, or may be one-quarter or less.

[0084] Furthermore, if the thickness T1 of the high-concentration plug region 55 is large, the distance between the high-concentration plug region 55 and the drift region 18 (or the accumulation region 16) becomes short, resulting in a decrease in the breakdown voltage. The thickness T1 may be half or less of the thickness T4, ¼ or less, or 1 / 10 or less.

[0085] Moreover, the width of the contact trench 57 in the X-axis direction (i.e., the width of the trench contact 54) is defined as W1, and the distance in the X-axis direction between the gate trench portion 40 and the contact trench 57 is defined as W2. In other words, the width W2 is the width of the contact region 15. The width W1 may be half or more of the width W2, or may be equal to or more than one time the width W2. By increasing the width W1, hole injection from the contact region 15 can be suppressed.

[0086] The high-concentration plug region 55 may be formed by injecting P-type impurities from above the upper surface 21 of the semiconductor substrate 10 toward the contact trench 57. In this case, P-type impurities are also injected into the contact region 15 and the emitter region 12 in the region exposed on the side surface of the contact trench 57. The contact region 15 may have a higher impurity concentration in a boundary portion 58 in contact with the contact trench 57 than the impurity concentration in the region in contact with the gate trench portion 40. With this configuration, the contact resistance between the trench contact 54 and the contact region 15 can be further reduced. In addition, the emitter region 12 may have a higher P-type impurity concentration in the region in contact with the contact trench 57 than the P-type impurity concentration in the region in contact with the gate trench portion 40. The emitter region 12 may have a region in contact with the contact trench 57 inverted to P type.

[0087] It is preferable that the width W2 has a thickness such that the P-type impurity implanted from the contact trench 57 into the emitter region 12 does not reach the gate trench portion 40. The width W2 may be 0.2 μm or more, or may be 0.5 μm or more.

[0088] The step of forming the high-concentration plug region 55 is preferably a step subsequent to the steps of forming the emitter region 12, the base region 14, the accumulation region 16, the contact region 15, and each trench portion. This can reduce the thermal history of the high-concentration plug region 55 and the boundary portion 58. This can reduce the thickness T1 of the high-concentration plug region 55, and can prevent the P-type impurity implanted into the boundary portion 58 from reaching the gate trench portion 40.

[0089] Fig. 6 is a perspective cross-sectional view showing a structural example of the mesa portion 61. In Fig. 6, the contact trench 57 of the trench contact 54 is shown, and the conductive material filled in the contact trench 57 is omitted.

[0090] As shown in FIG. 6, the contact trench 57 is provided from the upper surface 21 of the semiconductor substrate 10 to the inside of the base region 14. The contact trench 57 may penetrate the contact region 15. A P++ type high concentration plug region 55 is provided at the bottom of the contact trench 57. The contact region 15 and the base region 14 may be exposed at the side of the contact trench 57. The high concentration plug region 55 may be exposed at the bottom of the contact trench 57. The trench contact 54 may be in contact with the contact region 15, the base region 14, and the high concentration plug region 55.

[0091] 7 is a perspective cross-sectional view showing another structural example of the mesa portion 61. The mesa portion 61 of this example has the same structure as the mesa portion 60 on the upper surface 21 of the semiconductor substrate 10. That is, in the mesa portion 61 of this example, the contact regions 15 and the emitter regions 12 are alternately arranged along the Y-axis direction. Even in this case, the contact trenches 57 may be provided from the upper surface 21 of the semiconductor substrate 10, penetrating the contact regions 15 and the emitter regions 12 to the base region 14.

[0092] Fig. 8 is a cross-sectional view showing a structural example of an end portion of the active portion 120 in the X-axis direction. The cross section of Fig. 8 is an XZ cross section. The active portion 120 of this example is surrounded by the well region 11 in top view. A peripheral gate wiring 130 is provided above the well region 11, but is omitted in Fig. 8.

[0093] The active portion 120 of this example has an end region 78 between the transistor portion 70 (or diode portion 80) arranged at the end furthest in the X-axis direction and the well region 11. The gate trench portion 40 and the dummy trench portion 30 are not arranged in the end region 78. The base region 14 may be exposed on the upper surface 21 of the semiconductor substrate 10 in the end region 78.

[0094] The end region 78 may be provided with one or more pairs of trench contacts 54 and high-concentration plug regions 55. In the end region 78 of this example, a plurality of pairs of trench contacts 54 and high-concentration plug regions 55 are arranged at equal intervals along the X-axis direction. The trench contacts 54 and high-concentration plug regions 55 in the end region 78 may have the same structure as the trench contacts 54 and high-concentration plug regions 55 in the transistor section 70. By providing the end region 78, carriers such as holes flowing to the active section 120 can be extracted from a region outside the active section 120. This makes it possible to suppress carrier concentration in the mesa portion arranged at the end of the active section 120.

[0095] 9 is an XZ cross-sectional view showing an example of a mesa portion 62 of the semiconductor device 100. The mesa portion 62 may be provided in the transistor portion 70 or the diode portion 80. The mesa portion 62 is a floating mesa electrically insulated from the emitter electrode 52 by the interlayer insulating film 38. By providing the mesa portion 62, it is possible to suppress carriers from being drawn into the emitter electrode 52, and to further enhance the IE effect. The mesa portion 62 is not provided with a trench contact 54.

[0096] 10 is a diagram for explaining some steps in the manufacturing method of the semiconductor device 100. FIG. 10 shows a step of forming a trench contact. In FIG. 10, the accumulation region 16 is omitted. Before forming the trench contact, the contact region 15, the emitter region 12, the base region 14, the gate trench portion 40, and the dummy trench portion 30 are formed in the semiconductor substrate 10. In this example, the upper end of the gate conductive portion 44 of the gate trench portion 40 and the upper end of the dummy conductive portion 34 of the dummy trench portion 30 are disposed below the upper surface 21 of the semiconductor substrate 10.

[0097] In S1000, an interlayer insulating film 38 is formed above the conductive portion of each trench portion and on the upper surface 21 of the semiconductor substrate 10. As described above, the conductive portion of each trench portion is disposed below the upper surface 21 of the semiconductor substrate 10, and therefore a portion of the interlayer insulating film 38 is also formed on the conductive portion within each trench portion.

[0098] In S1002, the interlayer insulating film 38 above the upper surface 21 of the semiconductor substrate 10 is etched back and removed, leaving the interlayer insulating film 38 inside each trench, and exposing the upper surfaces of the mesa portion 60 and the mesa portion 61.

[0099] In S1004, a mask pattern 202 is formed on the upper surface 21 of the semiconductor substrate 10, and the upper surface 21 of the semiconductor substrate 10 is etched to form a contact trench 57. The contact trench 57 penetrates the contact region 15.

[0100] In S1006, a high-concentration plug region 55 is formed in contact with the bottom of the contact trench 57. The high-concentration plug region 55 may be formed by implanting the same P-type impurity as the contact region 15. The acceleration energy of the impurity ions in S1006 may be smaller than the acceleration energy when the impurity ions are implanted into the contact region 15. The heat treatment temperature in S1006 may be lower than the heat treatment temperature when the contact region 15 is formed. The heat treatment time in S1006 may be shorter than the heat treatment time when the contact region 15 is formed. The heat treatment may not be performed in S1006.

[0101] As an example, the P-type impurity is boron. As an example, the acceleration voltage of the impurity ions when forming the contact region 15 may be 100 keV or more and 140 keV or less. The implantation amount of the impurity ions is 1×10 15 ( / cm 2 ) or more 5×10 15 ( / cm 2The heat treatment temperature may be 950° C. or more and 1100° C. or less. The heat treatment time may be 20 minutes or more and 40 minutes or less.

[0102] As an example, the acceleration voltage of the impurity ions when forming the high-concentration plug region 55 may be 20 keV or more and 80 keV or less. The implantation amount of the impurity ions is 1×10 15 ( / cm 2 ) or more 5×10 15 ( / cm 2 ) or less. The amount of impurity ions implanted when forming the high-concentration plug region 55 may be less than the amount of impurity ions implanted when forming the contact region 15. However, since the high-concentration plug region 55 has a small thickness, the doping concentration per unit volume is high. The heat treatment temperature may be 800° C. or more and 900° C. or less. The heat treatment time when forming the high-concentration plug region 55 may be one-tenth or less of the heat treatment time when forming the contact region 15. The heat treatment time when forming the high-concentration plug region 55 may be 5 seconds or more and 1 minute or less.

[0103] In S1008, a conductive material is formed inside the contact trenches 57. In this example, a conductive material 204 is also formed above the mask pattern 202. The conductive material formed inside the contact trenches 57 becomes the trench contacts 54.

[0104] In S1010, the mask pattern 202 is removed. This allows the formation of the trench contact 54. After the trench contact 54 is formed, the emitter electrode 52 is formed on the upper surface 21 of the semiconductor substrate 10. If the trench contact 54 is formed of the same material as the emitter electrode 52, in S1008, the mask pattern 202 may be removed and then a conductive material may be deposited.

[0105] After the formation of the high-concentration plug region 55, it is preferable that no process is performed at a temperature higher than the heat treatment temperature used when the high-concentration plug region 55 is formed. This allows the thickness of the high-concentration plug region 55 to be controlled with high precision.

[0106] Fig. 11 is a diagram showing another example of the cross section bb in Fig. 2A and Fig. 2B. In the semiconductor device 100 of this example, the structure of the interlayer insulating film 38 is different from that of the example shown in Fig. 3. The other structures are similar to those of the example shown in Fig. 3.

[0107] In this example, the interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is provided so as to cover each trench portion. In other words, the width of the interlayer insulating film 38 in the X-axis direction is greater than the width of the trench portion. The interlayer insulating film 38 may or may not be provided inside each trench portion.

[0108] Each of the mesa portions 60 and 61 has a portion that is not covered with the interlayer insulating film 38. The interlayer insulating film 38 may be provided with a contact hole 56 that exposes the mesa portion 60 and the mesa portion 61. The contact hole 56 may be provided with a longitudinal direction in the longitudinal direction of each mesa portion 60 (the Y-axis direction).

[0109] In this example, the trench contact 54 is provided on the upper surfaces of the mesa portion 60 and the mesa portion 61 exposed by the contact hole 56. The trench contact 54 may be formed by etching the upper surface of the semiconductor substrate 10 using the interlayer insulating film 38 in which the contact hole 56 is provided as a mask. In this case, the position of the opening of the contact hole 56 coincides with the position of the trench contact 54 on the upper surface 21 of the semiconductor substrate 10. In another example, the position of the opening of the contact hole 56 may be different from the position of the trench contact 54.

[0110] Fig. 12 is a diagram comparing the characteristics of the semiconductor device 100 according to the embodiment and the semiconductor device according to the comparative example. Fig. 12 shows the waveforms of the forward current If in the diode section 80 and the anode-cathode voltage Vr of the diode section 80 when the transistor section 70 is turned off. The structure of the semiconductor device of the comparative example is similar to that of the semiconductor device 100, except that it does not have the trench contact 54.

[0111] 12, the semiconductor device 100 according to the embodiment has a smaller peak current Irp during reverse recovery than the comparative example. Therefore, the semiconductor device 100 can reduce reverse recovery loss. This is believed to be because the trench contact 54 is provided to suppress carrier injection from the contact region 15.

[0112] Fig. 13 is a diagram showing an example of hole density distribution in the depth direction in the diode section 80 of the example and the comparative example. Fig. 13 shows the hole density in the region of the diode section 80 adjacent to the transistor section 70. As shown in Fig. 13, it can be seen that the hole density of the example is reduced, particularly on the upper surface (anode) side, by providing the trench contact 54.

[0113] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0114] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0115] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 44 gate conductive portion, 52 emitter Emitter electrode, 54... trench contact, 55... high-concentration plug region, 56... contact hole, 57... contact trench, 58... boundary portion, 60, 61, 62... mesa portion, 70... transistor portion, 72... boundary portion, 78... end region, 80... diode portion, 81... extension region, 82... cathode region, 90... edge termination structure portion, 100... semiconductor device, 102... end side, 112... gate pad, 120... active portion, 130... peripheral gate wiring, 131... active side gate wiring, 202... mask pattern, 204... conductive material

Claims

1. A semiconductor substrate; A first electrode provided on an upper surface of the semiconductor substrate; Including, The semiconductor substrate is an N-type drift region; a P-type base region provided between the drift region and an upper surface of the semiconductor substrate; A plurality of trench portions; an N-type region having an impurity concentration higher than that of the drift region, the N-type region being provided in a first mesa portion sandwiched between the two trench portions; a P-type region having an impurity concentration higher than that of the base region, the P-type region being provided in a second mesa portion sandwiched between the two trench portions; a trench contact in which a conductive material is provided inside a groove provided in the first mesa portion and contacts at least a part of the semiconductor substrate, the trench contact being connected to the N-type region and the first electrode; a P-type first high concentration region provided below a bottom surface of the groove and having an impurity concentration higher than that of the base region; Semiconductor device.

2. The P-type region is also provided in the first mesa portion. The semiconductor device according to claim 1 .

3. The bottom surface of the trench is located deeper inside the semiconductor substrate than the bottom surface of the P-type region.

3. The semiconductor device according to claim 1 or 2.

4. The upper surface of the first high concentration region is located deeper inside the semiconductor substrate than the P-type region. The semiconductor device according to claim 3 .

5. The plurality of trench portions are arranged along a first direction in a top view, The width of the first high concentration region in the first direction is greater than the width of the bottom surface of the groove in the first direction. The semiconductor device according to claim 1 .

6. The N-type region and the P-type region are provided between the base region and the upper surface of the semiconductor substrate. The semiconductor device according to claim 1 .

7. The plurality of trench portions include a gate trench portion and a dummy trench portion. the N-type region is in contact with the gate trench portion, The P-type region is in contact with the dummy trench portion. The semiconductor device according to claim 1 .

8. The second mesa portion is sandwiched between the two dummy trench portions. The semiconductor device according to claim 7.

9. The first high concentration region has a higher impurity concentration than the P-type region. The semiconductor device according to claim 1 .

10. The plurality of trenches are provided from the upper surface of the semiconductor substrate to the drift region. The semiconductor device according to claim 1 .

11. an N-type accumulation region between the drift region and the base region of the first mesa portion; The semiconductor device according to claim 10.

12. an N-type accumulation region between the drift region and the base region of the second mesa portion; The semiconductor device according to claim 10.

13. The semiconductor substrate is a silicon substrate or a compound semiconductor substrate. The semiconductor device according to claim 1 .

14. The plurality of trench portions are arranged along a first direction in a top view, Each of the plurality of trench portions is provided to extend in a second direction intersecting the first direction in the top view, an interlayer insulating film is provided over the entire upper portion of the second mesa portion in a cross section of the semiconductor substrate in a depth direction parallel to the first direction at at least a portion of the second direction; The semiconductor device according to claim 1 .

15. The second mesa portion is a floating mesa portion electrically insulated from the first electrode by the interlayer insulating film. The semiconductor device according to claim 14.

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