Semiconductor device

Abstract

To provide a semiconductor device in which the voltage withstanding can be improved and the on-state resistance can be reduced.SOLUTION: A semiconductor device includes: a first electrode; a first semiconductor layer of a first conductivity type which is provided on the first electrode, has a plurality of regions, and is connected to the first electrode; a second semiconductor layer of a second conductivity type which is provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type which is provided on a part of the second semiconductor layer; a second electrode which is provided in each of the plurality of regions and faces the first semiconductor layer through an insulator; a third electrode which is disposed along a boundary line between the adjacent regions, is not disposed in a portion farthest from the second electrode in the boundary line, and faces the second semiconductor layer through the insulator; and a fourth electrode which is provided on the third semiconductor layer, connected to the second semiconductor layer, the third semiconductor layer, and the second electrode, and in which a portion disposed at the farthest portion is Schottky barrier-connected with the first semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] A semiconductor device for power control has been proposed in which columnar field plate electrodes (hereinafter also referred to as "FP electrodes") are periodically arranged and a gate electrode is disposed between the FP electrodes. In such a semiconductor device, there is a demand for improving the breakdown voltage and reducing the on-resistance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2012 / 144271 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiment is to provide a semiconductor device capable of improving the breakdown voltage and reducing the on-resistance. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a first electrode, a first semiconductor layer of a first conductivity type provided on the first electrode, having a plurality of regions, and connected to the first electrode, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, a third semiconductor layer of a first conductivity type provided on a portion of the second semiconductor layer, second electrodes arranged in each of the plurality of regions and facing the first semiconductor layer via an insulator, a third electrode arranged along a boundary between adjacent regions, not arranged in a portion of the boundary line farthest from the second electrode, and facing the second semiconductor layer via an insulator, and a fourth electrode provided on the third semiconductor layer, connected to the second semiconductor layer, the third semiconductor layer, and the second electrode, and having a portion arranged in the farthest portion that forms a Schottky barrier junction with the first semiconductor layer. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB' shown in FIG. [Figure 4] FIG. 4 is a partially enlarged cross-sectional view showing a region C in FIG. [Diagram 5] FIG. 5 is a plan view showing a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] <Embodiment> FIG. 1 is a plan view showing a semiconductor device according to the present embodiment. FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. FIG. 3 is a cross-sectional view taken along line BB' shown in FIG. FIG. 4 is a partially enlarged cross-sectional view showing a region C in FIG. It should be noted that each figure is schematic and has been appropriately emphasized and simplified.

[0008] 1 to 4, the semiconductor device 1 according to this embodiment includes a drain electrode 11 (first electrode), a source electrode 12 (fourth electrode), a gate electrode 13 (third electrode), an FP electrode 14 (second electrode), and a semiconductor portion 20. The semiconductor portion 20 is made of a semiconductor material, for example, single crystal silicon (Si), and impurities are introduced into each portion to achieve a predetermined conductivity type and carrier concentration. The semiconductor device 1 also includes a gate insulating film 31, an FP insulating film 32, and interlayer insulating films 33 and 34.

[0009] The drain electrode 11 is disposed over the entire lower surface of the semiconductor portion 20. The interlayer insulating film 33 is disposed on the semiconductor portion 20. The interlayer insulating film 34 is disposed on the interlayer insulating film 33. Openings 35c and 35d are formed in the interlayer insulating films 33 and 34. The source electrode 12 is disposed on the interlayer insulating film 34.

[0010] A plurality of regions R of the same shape are set on the upper surface of the semiconductor portion 20, and are closely spaced from each other. When viewed from above, the shape of the regions R is, for example, a square. When viewed from above, the plurality of square regions R are arranged in a matrix.

[0011] In the upper surface of the semiconductor portion 20, a recess 20c is formed inside each region R. In addition, a recess 20d is formed at the corner of each region R, i.e., at the portion where the four regions R contact each other. The recess 20c is disposed directly below the opening 35c. The recess 20d is disposed directly below the opening 35d.

[0012] In this specification, for convenience of explanation, an XYZ Cartesian coordinate system is adopted. The direction from the drain electrode 11 toward the source electrode 12 is defined as the "Z direction", and the two directions in which the regions R are arranged are defined as the "X direction" (first direction) and the "Y direction" (second direction). The Z direction is also called "up" and the opposite direction to the Z direction is also called "down", but these expressions are also for convenience and are unrelated to the direction of gravity.

[0013] The source electrode 12 includes a lower layer 12a (first metal layer) and an upper layer 12b (second metal layer) provided on the lower layer 12a. The lower layer 12a includes one or more metals selected from the group consisting of titanium (Ti), nickel (Ni), platinum (Pt), and tungsten (W). The upper layer 12b includes one or more metals selected from the group consisting of aluminum (Al) and copper (Cu).

[0014] The source electrode 12 is also disposed inside the openings 35c and 35d formed in the interlayer insulating films 33 and 34, and inside the recesses 20c and 20d formed on the upper surface of the semiconductor portion 20. Of the source electrode 12, the portion disposed in the opening 35c and the recess 20c is referred to as a "source contact 12c," and the portion disposed in the opening 35d and the recess 20d is referred to as a "source contact 12d." Note that in FIG. 1, for ease of viewing, only one source contact 12c is shown, and other portions of the source electrode 12 are omitted.

[0015] The gate electrode 13 and the FP electrode 14 are disposed in the semiconductor portion 20. The gate insulating film 31 covers the lower surface and side surfaces of the gate electrode 13. This insulates the gate electrode 13 from the semiconductor portion 20. The upper surface of the gate electrode 13 is covered by an interlayer insulating film 33. This insulates the gate electrode 13 from the source electrode 12. The FP insulating film 32 covers the lower surface and side surfaces of the FP electrode 14. This insulates the FP electrode 14 from the semiconductor portion 20. The lower end of the FP electrode 14 is located lower than the lower end of the gate electrode 13. The average thickness of the FP insulating film 32 is thicker than the average thickness of the gate insulating film 31.

[0016] When viewed from above, i.e., from the Z direction, the gate electrode 13 is disposed along the boundaries of the multiple regions R. When viewed from above, the gate electrode 13 has a generally lattice-like shape. That is, the gate electrode 13 is provided with a portion 13x extending in the X direction and a portion 13y extending in the Y direction.

[0017] However, at the intersections of the lattice, i.e., at the positions where the four regions R contact each other, the portions 13x and 13y are not provided, but the frame-shaped portion 13z is provided. When viewed from above, the shape of the frame-shaped portion 13z is, for example, a square frame. Both the portions 13x and 13y contact the frame-shaped portion 13z, and the portions 13x and 13y do not contact each other. That is, the gate electrode 13 is disposed along the boundaries of the multiple regions R, and is not disposed at the corners of the regions R.

[0018] The gate electrode 13 is integrally formed by a portion 13x, a portion 13y and a frame-shaped portion 13z, and is connected to a gate pad (not shown) arranged on the interlayer insulating film 34. In this specification, "connection" means electrical connection.

[0019] When viewed from above, one FP electrode 14 is disposed near the center of each region R. The FP electrode 14 is generally cylindrical with a central axis extending in the Z direction. The top surface of the FP electrode 14 is connected to the source contact 12c. Also, when viewed from above, the gate electrode 13 surrounds each FP electrode 14. The corner of the region R is a portion Rc of the boundary between the multiple regions R that is farthest from the FP electrode 14. The portion Rc is located within the frame-shaped portion 13z.

[0020] In the semiconductor portion 20, a drain layer 21, a drift layer 22, a base layer 23, a base contact layer 24, a source layer 25 (third semiconductor layer), and a contact layer 26 (fourth semiconductor layer) are provided.

[0021] The drain layer 21 is disposed on the drain electrode 11 and is connected to the drain electrode 11. The conductivity type of the drain layer 21 is n + The drift layer 22 is disposed on the drain layer 21 and is in contact with the drain layer 21. The conductivity type of the drift layer 22 is n - It is of the type "n + "N-type" means that the carrier concentration is higher than that of "n-type", and "n -"N-type" indicates that the carrier concentration is lower than that of "n-type." The same applies to p-type. The drain layer 21 and drift layer 22 form a first semiconductor layer.

[0022] The base layer 23 is disposed on the drift layer 22 and is in contact with the drift layer 22. The conductivity type of the base layer 23 is p-type. The base contact layer 24 is disposed on a part of the base layer 23, directly below the recess 20c. The conductivity type of the base contact layer 24 is p + The base layer 23 and the base contact layer 24 form a second semiconductor layer.

[0023] The source layer 25 is disposed on another part of the base layer 23. The source layer 25 is disposed along the gate insulating film 31. The lower surface of the source layer 25 is in contact with the base layer 23, the upper surface is in contact with the interlayer insulating film 33, and the side surface is in contact with the gate insulating film 31 and the source contact 12c. The conductivity type of the source layer 25 is n + It is a type.

[0024] The contact layer 26 is disposed in the portion Rc, i.e., the corner of the region R, as viewed from above, and disposed directly below the recess 20d of the semiconductor portion 20. The contact layer 26 contacts the source contact 12d at the bottom surface of the recess 20d. The contact layer 26 also contacts the drift layer 22 and the base layer 23. The conductivity type of the contact layer 26 is p + It is a type.

[0025] The gate electrode 13 faces the upper part of the drift layer 22, the base layer 23, and the source layer 25 via the gate insulating film 31. This makes it possible to form an inversion layer in a region of the base layer 23 that contacts the gate insulating film 31. As a result, a MOSFET is realized in the semiconductor device 1.

[0026] The FP electrode 14 is disposed in region R when viewed from above, and faces the upper part of the drift layer 22, the base layer 23, and the base contact layer 24 via the FP insulating film 32. This compensates for the charges of ionized donors in the drift layer 22, making it possible to increase the carrier concentration of the drift layer 22, thereby improving the source-drain breakdown voltage in the semiconductor device 1 and reducing the on-resistance.

[0027] The multiple FP electrodes 14 and the multiple contact layers 26 are parallel to the XY plane including the X and Y directions, and are alternately arranged along the W direction (third direction) that intersects with the X and Y directions. When the shape of the region R is square, the W direction is inclined at 45° with respect to the X and Y directions.

[0028] At the lower part of the side surface of the recess 20d, a part of the side surface of the source contact 12d is in contact with the drift layer 22. This forms a Schottky barrier junction between the lower layer 12a of the source electrode 12 and the drift layer 22. As a result, a Schottky barrier diode S is realized in the portion Rc when viewed from above.

[0029] Next, the operation of this embodiment will be described. 1, in the semiconductor device 1 according to this embodiment, an FP electrode 14 is disposed at the center of each region R. The FP electrode 14 compensates for the charge of the ionized donors in the drift layer 22, so that it is possible to increase the carrier concentration of the drift layer 22, thereby improving the breakdown voltage of the semiconductor device 1 and reducing the on-resistance.

[0030] In this embodiment, the gate electrode 13 is not arranged in the portion Rc of the boundary line of the region R that is the farthest from the FP electrode 14, i.e., the corner of each region R, but the source contact 12d is arranged. The lower layer 12a of the source contact 12d is formed of a material that forms a Schottky barrier junction with the drift layer 22. As a result, the source contact 12d arranged in the portion Rc of the source electrode 12 forms a Schottky barrier junction with the drift layer 22. As a result, a Schottky barrier diode S can be realized in the portion Rc.

[0031] Next, the effects of this embodiment will be described. In this embodiment, by arranging the source contact 12d in the portion Rc that is the farthest from the FP electrode 14 on the boundary line of the region R, it is possible to avoid a decrease in the withstand voltage in the portion Rc and improve the withstand voltage of the semiconductor device 1. In other words, while ensuring the withstand voltage required for the semiconductor device 1, it is possible to improve the carrier concentration of the drift layer 22 and reduce the on-resistance.

[0032] Generally, there is a trade-off between improving the breakdown voltage and reducing the on-resistance, but this embodiment can improve the balance between the two. Therefore, depending on the characteristics required for the semiconductor device 1, it is possible to improve the breakdown voltage while keeping the on-resistance constant, or to reduce the on-resistance while keeping the breakdown voltage constant, thereby achieving both an improvement in the breakdown voltage and a reduction in the on-resistance.

[0033] Furthermore, an SBD is provided in the portion Rc in the semiconductor device 1. Since the SBD has a lower forward voltage than a pn junction diode, the recovery loss (Qrr) of the parasitic diode can be reduced.

[0034] As described above, in this embodiment, in order to avoid a decrease in the breakdown voltage, the gate electrode 13 is not disposed in the portion Rc. Therefore, the portion Rc is a dead space as a MOSFET. In this embodiment, this dead space is utilized as an SBD. As a result, the area ratio of the MOSFET portion in the semiconductor device 1 can be increased and the on-resistance can be reduced, compared to the case where an SBD portion is provided separately from the MOSFET portion.

[0035] In this embodiment, the shape of the region R as viewed from above is a square, but the shape is not limited to this. The shape of the region R may be any shape that can be tiled without gaps, and may be, for example, a polygon, such as a rectangle. The shape of the region R may be an equilateral triangle or a regular hexagon.

[0036] In the present embodiment, the gate electrode 13 is continuously arranged by the portion 13x, the portion 13y, and the frame-shaped portion 13z, but the present invention is not limited to this. The gate electrode 13 may be arranged at any position other than the furthest from the FP electrode 14 in the region R. For example, when the portion 13x and the portion 13y are connected to the gate pad by an upper wiring, the frame-shaped portion 13z may not be provided.

[0037] Furthermore, in the present embodiment, the source electrode 12 has a two-layer structure in which the lower layer 12a and the upper layer 12b are laminated, but the present invention is not limited to this. At least the portion of the source electrode 12 in contact with the drift layer 22 may be formed of a material that forms a Schottky barrier junction with the drift layer 22. For example, the entire source electrode 12 may be formed of a material that forms a Schottky barrier junction with the drift layer 22.

[0038] <Comparative Example> FIG. 5 is a plan view showing a semiconductor device according to this comparative example. As shown in FIG. 5, in the semiconductor device 101 according to this comparative example, the gate electrode 13 is also disposed in a portion Rc on the boundary line of the region R that is farthest from the FP electrode 14.

[0039] The distance D between the portion 13c arranged in the portion Rc of the gate electrode 13 and the center 14c of the FP electrode 14 is the longest distance between the gate electrode 13 and the center 14c of the FP electrode 14. Therefore, the effect of alleviating electric field concentration by the FP electrode 14 is small in the portion 13c, and the withstand voltage is low. As a result, the semiconductor device 101 has a lower withstand voltage than the semiconductor device 1. If the semiconductor device 101 is to achieve the same withstand voltage as the semiconductor device 1, the carrier concentration of the drift layer 22 needs to be lowered, and the on-resistance becomes high.

[0040] In addition, since no SBD is provided in the semiconductor device 101, the recovery loss (Qrr) of the parasitic diode is large. Although an SBD section can be provided separately from the MOSFET section, in this case, the area ratio of the MOSFET section in the semiconductor device 101 decreases, and the on-resistance increases.

[0041] According to the embodiment described above, a semiconductor device capable of improving the breakdown voltage and reducing the on-resistance can be realized.

[0042] Although the embodiment of the present invention has been described above, this embodiment is presented as an example and is not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0043] The present invention includes the following aspects.

[0044] (Appendix 1) A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode, having a plurality of regions, and connected to the first electrode; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on a portion of the second semiconductor layer; a second electrode disposed in each of the plurality of regions and facing the first semiconductor layer via an insulator; a third electrode that is disposed along a boundary line between adjacent regions, is not disposed at a portion of the boundary line farthest from the second electrode, and faces the second semiconductor layer via an insulator; a fourth electrode provided on the third semiconductor layer, connected to the second semiconductor layer, the third semiconductor layer, and the second electrode, and having a portion disposed at the farthest portion that forms a Schottky barrier junction with the first semiconductor layer; A semiconductor device comprising:

[0045] (Appendix 2) The shape of the region is a polygon; 2. The semiconductor device of claim 1, wherein the furthest portion is a corner of the polygon.

[0046] (Appendix 3) 3. The semiconductor device according to claim 1, wherein the shape of the region is a square.

[0047] (Appendix 4) 4. The semiconductor device according to claim 1, further comprising a fourth semiconductor layer of a second conductivity type provided in the farthest portion and in contact with the first semiconductor layer and the fourth electrode.

[0048] (Appendix 5) A plurality of the second electrodes are arranged in a matrix along a first direction and a second direction perpendicular to the first direction, 5. The semiconductor device according to claim 4, wherein the plurality of second electrodes and the fourth semiconductor layers are alternately arranged along a third direction intersecting the first direction and the second direction.

[0049] (Appendix 6) 6. The semiconductor device according to claim 1, wherein the third electrode surrounds the second electrode.

[0050] (Appendix 7) The fourth electrode is a first metal layer forming a Schottky barrier junction with the first semiconductor layer; a second metal layer provided on the first metal layer; 7. The semiconductor device according to claim 1, further comprising:

[0051] (Appendix 8) the first metal layer comprises one or more metals selected from the group consisting of titanium, nickel, platinum, and tungsten; 8. The semiconductor device according to claim 7, wherein the second metal layer contains one or more metals selected from the group consisting of aluminum and copper. [Explanation of symbols]

[0052] 1 Semiconductor device 11 Drain electrode 12 Source electrode 12a lower layer 12b upper layer 12c, 12d Source Contact 13 Gate electrode 13c part 13x part 13y part 13z frame part 14 FP electrode 14c center 20 Semiconductor part 20c, 20d recess 21 Drain layer 22 Drift Layer 23 Base Layer 24 Base contact layer 25 Source Layer 26 Contact layer 31 Gate insulating film 32 FP insulating film 33, 34 Interlayer insulating film 35c, 35d opening 101 Semiconductor device D Distance R region Rc The part of the boundary of region R that is farthest from the FP electrode S Schottky barrier diode

Claims

1. A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode, having a plurality of regions, and connected to the first electrode; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on a portion of the second semiconductor layer; a second electrode disposed in each of the plurality of regions and facing the first semiconductor layer via an insulator; a third electrode that is disposed along a boundary line between adjacent regions, is not disposed at a portion of the boundary line farthest from the second electrode, and faces the second semiconductor layer via an insulator; a fourth electrode provided on the third semiconductor layer, connected to the second semiconductor layer, the third semiconductor layer, and the second electrode, and a portion disposed at the furthest portion forms a Schottky barrier junction with the first semiconductor layer; A semiconductor device comprising:

2. The shape of the region is a polygon; 2. The semiconductor device of claim 1, wherein said furthest portion is a corner of said polygon.

3. The semiconductor device according to claim 1 , wherein the shape of the region is square.

4. The semiconductor device according to claim 1 , further comprising a fourth semiconductor layer of the second conductivity type provided at the farthest portion and in contact with the first semiconductor layer and the fourth electrode.

5. A plurality of the second electrodes are arranged in a matrix along a first direction and a second direction perpendicular to the first direction, The semiconductor device according to claim 4 , wherein the plurality of second electrodes and the fourth semiconductor layers are alternately arranged along a third direction intersecting the first direction and the second direction.

6. The semiconductor device according to claim 1 , wherein the third electrode surrounds the second electrode.

7. The fourth electrode is a first metal layer forming a Schottky barrier junction with the first semiconductor layer; a second metal layer provided on the first metal layer; The semiconductor device according to claim 1 ,

8. the first metal layer comprises one or more metals selected from the group consisting of titanium, nickel, platinum, and tungsten; The semiconductor device according to claim 7 , wherein the second metal layer contains one or more metals selected from the group consisting of aluminum and copper.

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