Photodiode

Abstract

To provide a photodiode in which dark current is reduced.SOLUTION: A photodiode 1 includes a substrate 10 and a semiconductor multilayer body 12. The substrate 10 has a main surface 10a. The semiconductor multilayer body 12 is disposed on the main surface 10a. The semiconductor multilayer body 12 includes a buffer layer 13 disposed on the main surface 10a, and a light absorption layer 14 disposed on the buffer layer 13. The light absorption layer 14 is formed of InxGa1-xAsyP1-y, in which x and y are more than 0 and less than 1. The buffer layer 13 is formed of InzGa1-zAs, in which z is more than 0 and less than 1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to photodiodes. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 11-54785 (Patent Document 1) discloses a light receiving element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-54785 [Summary]

[0004] It is an object of the present disclosure to provide a photodiode with reduced dark current.

[0005] The photodiode of the present disclosure includes a substrate and a semiconductor stack. The substrate has a primary surface. The semiconductor stack is disposed on the primary surface of the substrate. The semiconductor stack includes a buffer layer disposed on the primary surface of the substrate and a light absorbing layer disposed on the buffer layer. The light absorbing layer is made of In x Ga 1-x As y P 1-y where x and y are greater than 0 and less than 1. The buffer layer is made of In z Ga 1-z As, where z is greater than 0 and less than 1. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view of a photodiode according to an embodiment. [Diagram 2] FIG. 2 is a schematic partial plan view of the photodiode according to the embodiment, seen from the direction of arrow II shown in FIG. [Diagram 3] FIG. 3 is a diagram showing the relationship between the lattice constant and the bandgap energy of InGaAsP. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a step of a method for manufacturing a photodiode according to an embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 4 in the method for manufacturing a photodiode according to the embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 5 in the method for manufacturing a photodiode according to the embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 6 in the method for manufacturing a photodiode according to the embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 7 in the method for manufacturing the photodiode according to the embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 8 in the method for manufacturing the photodiode according to the embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 9 in the method for manufacturing the photodiode according to the embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 10 in the method for manufacturing the photodiode according to the embodiment. [Figure 12] FIG. 12 is a diagram showing the results of a simulation of the relationship between the bias voltage applied to the photodiode and the dark current of the photodiode. [Figure 13] FIG. 13 is a diagram showing the results of a simulation of the relationship between the arsenic composition of the light absorption layer and the dark current of the photodiode at a bias voltage of −1 V. [Figure 14] FIG. 14 is a diagram showing a SEM photograph of a partial cross section of the photodiode of the first embodiment. [Figure 15] FIG. 15 is a diagram showing a SEM photograph of a partial cross section of the photodiode of the first comparative example. [Figure 16]FIG. 16 is a diagram showing an experimental example of the relationship between the bias voltage and the dark current of the photodiode in the photodiode of the example and the photodiode of the comparative example. [Figure 17] 17 is a diagram showing the results of a simulation of the relationship between the distance between the edge of the opening in the insulating layer that defines the p-type diffusion region and the side surface of the mesa structure, and the dark current of the photodiode at a bias voltage of −1 V. [Detailed Description]

[0007] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are given the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be arbitrarily combined.

[0008] A photodiode 1 according to an embodiment of the present disclosure will be described with reference to Figures 1 and 2. The photodiode 1 includes a substrate 10, a semiconductor stack 12, a p-type contact layer 18, an insulating layer 21, an anti-reflection film 22, an n-electrode 25, a p-electrode 26, and a conductive pad 27.

[0009] The substrate 10 has a principal surface 10a and a principal surface 10b opposite to the principal surface 10a. The principal surface 10a and the principal surface 10b are both end surfaces in the thickness direction of the substrate 10. The substrate 10 is, for example, a semiconductor substrate such as an InP substrate.

[0010] The semiconductor stack 12 is disposed on the major surface 10a of the substrate 10. The semiconductor stack 12 has a top surface 12a and a bottom surface 12b. The bottom surface 12b is in contact with the major surface 10a. The side surface 12s is connected to the top surface 12a and the bottom surface 12b. The semiconductor stack 12 includes a buffer layer 13, a light absorbing layer 14, and a p-type dopant diffusion region 16. The semiconductor stack 12 may further include a window layer 15. The semiconductor stack 12 includes a plurality of stacked semiconductor layers. For example, in the semiconductor stack 12, the buffer layer 13, the light absorbing layer 14, and the window layer 15 are stacked.

[0011] The buffer layer 13 is disposed on the major surface 10a of the substrate 10. The buffer layer 13 is in contact with the substrate 10. The bottom surface of the buffer layer 13 is the bottom surface 12b of the semiconductor laminate 12. The buffer layer 13 is, for example, an i-type semiconductor layer. The thickness of the buffer layer 13 is, for example, 10 nm or more. The thickness of the buffer layer 13 may be 100 nm or more. Therefore, the buffer layer 13 can reduce crystal defects in the light absorption layer 14 and make the top surface of the light absorption layer 14 flatter. The thickness of the buffer layer 13 is smaller than the thickness of the light absorption layer 14. The thickness of the buffer layer 13 is, for example, 1000 nm or less. The thickness of the buffer layer 13 may be 800 nm or less, 600 nm or less, 400 nm or less, or 200 nm or less. Therefore, the voltage drop in the buffer layer 13 can be reduced, and the reverse bias voltage applied to the light absorption layer 14 can be increased.

[0012] The buffer layer 13 is In z Ga 1-z The buffer layer 13 is made of As, where z is greater than 0 and less than 1. The buffer layer 13 is lattice-matched to the substrate 10 (e.g., an InP substrate). As shown in FIG. 3, the buffer layer 13 can be lattice-matched to the InP substrate by adjusting z. In this specification, the buffer layer 13 lattice-matched to the substrate 10 means that the difference between the lattice constant of the buffer layer 13 and the lattice constant of the substrate 10 is 0.1% or less of the lattice constant of the substrate 10.

[0013] The light absorbing layer 14 is disposed on the buffer layer 13. The light absorbing layer 14 is in contact with the buffer layer 13. The light absorbing layer 14 is separated from the substrate 10 by the buffer layer 13. The light absorbing layer 14 is, for example, an i-type semiconductor layer. The light absorbing layer 14 absorbs light incident on the photodiode 1. The photodiode 1 detects the intensity of the light.

[0014] The light absorbing layer 14 is In x Ga 1-x As y P 1-yThe photodiode 1 is formed by the formula (1), where x and y are greater than 0 and less than 1. For example, x is equal to or greater than 0.70 and less than 1.00. x is determined according to the wavelength of light detected by the photodiode 1, i.e., the wavelength of light absorbed by the photoabsorption layer 14. The wavelength of light detected by the photodiode 1 is, for example, 1690 nm or less. The thickness of the photoabsorption layer 14 is, for example, 3000 nm or more and 5000 nm or less. The photoabsorption layer 14 is lattice-matched to the substrate 10 (for example, an InP substrate). As shown in FIG. 3, by adjusting x and y, the photoabsorption layer 14 can be lattice-matched to the InP substrate while changing the band gap energy of the photoabsorption layer 14. In this specification, the photoabsorption layer 14 is lattice-matched to the substrate 10 means that the difference between the lattice constant of the photoabsorption layer 14 and the lattice constant of the substrate 10 is 0.1% or less of the lattice constant of the substrate 10.

[0015] The window layer 15 is disposed on the light absorbing layer 14. The window layer 15 may be, for example, an n-type semiconductor layer. The thickness of the window layer 15 is, for example, 100 nm or more and 2000 nm or less. The top surface of the window layer 15 may be the top surface 12a of the semiconductor stack 12. The band gap energy of the window layer 15 is larger than the band gap energy of the light absorbing layer 14. The window layer 15 is transparent to the light detected by the photodiode 1. The band gap wavelength of the window layer 15 is shorter than the wavelength of the light detected by the photodiode 1. The window layer 15 is, for example, an n-InP layer.

[0016] The p-type dopant diffusion region 16 is a region in which a p-type dopant such as zinc (Zn) is diffused, and is a p-type semiconductor region. The p-type dopant diffusion region 16 extends from the top surface 12a of the semiconductor laminate 12 to the inside of the light absorbing layer 14. In this embodiment, the p-type dopant diffusion region 16 is formed by doping the light absorbing layer 14 and the window layer 15 with a p-type dopant. The p-type dopant diffusion region 16 is in contact with the light absorbing layer 14 and the window layer 15. The p-type dopant diffusion region 16 is away from the bottom surface 12b of the semiconductor laminate 12.

[0017] The semiconductor laminate 12 has a mesa structure 5. A side surface 12s of the semiconductor laminate 12 is a side surface 5s of the mesa structure 5. In the present embodiment, the mesa structure 5 is formed in the window layer 15, the light absorption layer 14, and the buffer layer 13. At least a part of the side surface 12s of the semiconductor laminate 12 may be the side surface 5s of the mesa structure 5. For example, the mesa structure 5 may not be formed in the buffer layer 13, but the mesa structure 5 may be formed in the window layer 15 and the light absorption layer 14.

[0018] The p-type contact layer 18 is disposed on the top surface 12a of the semiconductor laminate 12. The p-type contact layer 18 is in contact with the p-type dopant diffusion region 16. The p-type contact layer 18 is disposed in an opening 21a of the insulating layer 21. The p-type contact layer 18 is in contact with the insulating layer 21. The thickness of the p-type contact layer 18 is, for example, 10 nm or more and 200 nm or less. The p-type contact layer 18 is, for example, a p-InGaAs layer. An opening 18a is provided in the p-type contact layer 18. The p-type dopant diffusion region 16 is exposed from the p-type contact layer 18 at the opening 18a. Light detected by the photodiode 1 enters the light absorption layer 14 through the opening 18a.

[0019] The insulating layer 21 is disposed on the semiconductor laminate 12. The insulating layer 21 is in contact with the top surface 12a of the semiconductor laminate 12. The insulating layer 21 has a thickness of, for example, 10 nm or more and 500 nm or less. The insulating layer 21 is, for example, a silicon nitride layer. An opening 21a is provided in the insulating layer 21. In a plan view of the main surface 10a, the opening 21a defines the p-type dopant diffusion region 16. The insulating layer 21 functions as a mask that defines an implantation region of the p-type dopant for the p-type dopant diffusion region 16. In a plan view of the main surface 10a, the minimum distance d2 between the edge of the opening 21a and the side surface 5s of the mesa structure 5 is 20 μm or more. The minimum distance d2 may be 30 μm or more, 40 μm or more, or 50 μm or more.

[0020] The antireflection film 22 reduces the reflectance of light on the incident surface of the photodiode 1. The antireflection film 22 is disposed on the insulating layer 21, the p-type contact layer 18, and the semiconductor stack 12 (more specifically, the p-type dopant diffusion region 16). The antireflection film 22 is, for example, an insulating layer. The antireflection film 22 is, for example, a silicon nitride layer. The antireflection film 22 is provided with a through hole 22a. The p-type contact layer 18 is exposed from the antireflection film 22 at the through hole 22a.

[0021] The n-electrode 25 is disposed on the main surface 10b of the substrate 10. The p-electrode 26 is disposed on the anti-reflection film 22, in the through-hole 22a, and on the p-type contact layer 18 exposed from the through-hole 22a. The p-electrode 26 is in contact with the p-type contact layer 18. The p-electrode 26 is electrically connected to the p-type dopant diffusion region 16 through the p-type contact layer 18. In a plan view of the main surface 10a, the p-electrode 26 has an outer edge 26e. The conductive pad 27 is disposed on the anti-reflection film 22 and is connected to the p-electrode 26. The n-electrode 25, the p-electrode 26, and the conductive pad 27 are, for example, a laminate of a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer, and the gold layer is the outermost layer of the laminate.

[0022] In a plan view of the primary surface 10a, the minimum distance d1 between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 is 18 μm or more. The minimum distance d1 may be 28 μm or more, 38 μm or more, or 48 μm or more. The minimum distance d1 between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 may be smaller than the minimum distance d2 between the edge of the opening 21a of the insulating layer 21 and the side surface 5s of the mesa structure 5. In a plan view of the primary surface 10a, the maximum distance d3 between the outer edge 26e of the p-electrode 26 and the edge of the opening 21a of the insulating layer 21 is 2 μm or less.

[0023] The operation of the photodiode 1 of this embodiment will be described. A reverse bias voltage is applied between the p electrode 26 and the n electrode 25. That is, a bias voltage is applied between the p electrode 26 and the n electrode 25 so that the potential of the n electrode 25 is higher than the potential of the p electrode 26. Light passes through the opening 18a and enters the light absorbing layer 14. Electrons and holes are generated in the light absorbing layer 14. The electrons move to the p electrode 26 and the holes move to the n electrode 25 due to the reverse bias voltage. A photocurrent is generated according to the intensity of the light incident on the photodiode 1. The intensity of the light incident on the photodiode 1 is detected from the photocurrent generated in the photodiode 1.

[0024] An example of a method for manufacturing the photodiode 1 of the present embodiment will be described with reference to FIGS.

[0025] 4, a buffer layer 13 is formed on a main surface 10a of a substrate 10. For example, an InP substrate is formed with an In z Ga 1-z A buffer layer 13 made of As is formed. The buffer layer 13 is lattice-matched to the substrate 10 (for example, an InP substrate).

[0026] The light absorbing layer 14 is formed on the buffer layer 13 by, for example, MOCVD. x Ga 1-x As y P 1-y where x and y are greater than 0 and less than 1. For example, x is greater than or equal to 0.70 and less than 1.00. The light absorbing layer 14 is lattice-matched to the substrate 10 (for example, an InP substrate).

[0027] A window layer 15 is formed on the light absorption layer 14 by, for example, an MOCVD method. The window layer 15 is, for example, an n-InP layer. In this manner, a semiconductor stack 12 is formed on the primary surface 10a of the substrate 10. The semiconductor stack 12 has a top surface 12a and a bottom surface 12b.

[0028] 4, a semiconductor layer 17 is formed on the top surface 12a (on the window layer 15) of the semiconductor laminate 12 by, for example, an MOCVD method. The semiconductor layer 17 is formed in a region of the top surface 12a (window layer 15) that overlaps with the p-type dopant diffusion region 16 (see FIGS. 1 and 2) in a plan view of the main surface 10a. The semiconductor layer 17 is made of, for example, InGaAs.

[0029] 5, the semiconductor layer 17 is etched by a dry etching method such as a reactive ion etching (RIE) method. In a plan view of the main surface 10a, a part of the top surface 12a of the semiconductor stack 12 or a part of the window layer 15 is exposed from the semiconductor layer 17.

[0030] Referring to FIG. 6, a mesa structure 5 is formed in the semiconductor laminate 12 (S8). Specifically, the buffer layer 13, the light absorption layer 14, and the window layer 15 are etched by a dry etching method. The dry etching method is, for example, an RIE method using an etching gas such as a chlorine-based gas. Since the mesa structure 5 is formed by a dry etching method rather than a wet etching method, the side surface 5s of the mesa structure 5 is prevented from being excessively etched. Therefore, in a plan view of the main surface 10a, the distance between the side surface 5s of the mesa structure 5 and the p-type dopant diffusion region 16 (see FIGS. 1 and 2) and the distance between the side surface 5s of the mesa structure 5 and the outer edge 26e of the p-electrode 26 (see FIGS. 1 and 2) can be prevented from being excessively small.

[0031] Referring to FIG. 7, a p-type dopant is injected into the semiconductor stack 12 and the semiconductor layer 17 to form a p-type dopant diffusion region 16 and a p-type contact layer 18. Specifically, an insulating layer 21 is formed on the top surface 12a of the semiconductor stack 12 or a portion of the window layer 15 that is exposed from the semiconductor layer 17, for example, by a plasma CVD method. The semiconductor layer 17 is disposed in an opening 21a of the insulating layer 21. Then, a p-type dopant such as zinc (Zn) is injected into the semiconductor layer 17, the window layer 15, and the light absorption layer 14 using the insulating layer 21 as a mask. The p-type dopant is doped into the semiconductor layer 17, the window layer 15, and the light absorption layer 14 through the opening 21a of the insulating layer 21. The p-type dopant is injected into the semiconductor layer 17 to form a p-type contact layer 18. The p-type dopant is injected into the window layer 15 and the light absorption layer 14 to form a p-type dopant diffusion region 16.

[0032] 8, an opening 18a is formed in the p-type contact layer 18. For example, the opening 18a is formed in the p-type contact layer 18 by an RIE method using an etching gas such as a chlorine-based gas. A part of the p-type dopant diffusion region 16 is exposed from the p-type contact layer 18 in the opening 18a.

[0033] 9, an anti-reflective film 22 having a through hole 22a is formed on the insulating layer 21, the p-type contact layer 18, and the p-type dopant diffusion region 16. For example, the anti-reflective film 22 is formed by a plasma CVD method. A part of the anti-reflective film 22 is etched by a dry etching method such as an RIE method using an etching gas such as carbon tetrafluoride (CF4) gas, thereby forming the through hole 22a in the anti-reflective film 22. A part of the p-type contact layer 18 is exposed from the anti-reflective film 22 through the through hole 22a.

[0034] 10, the p-electrode 26 and the conductive pad 27 (see FIG. 2) are formed. For example, the p-electrode 26 and the conductive pad 27 are formed by depositing a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer in this order. The p-electrode 26 is formed on the anti-reflection film 22, in the through-hole 22a, and on the p-type contact layer 18 exposed from the through-hole 22a. The conductive pad 27 is formed on the anti-reflection film 22 and is connected to the p-electrode 26.

[0035] 11, the main surface 10b of the substrate 10 is ground to thin the substrate 10. Then, an n-electrode 25 is formed on the main surface 10b of the substrate 10. For example, the n-electrode 25 is formed by evaporating a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer in this order. In this manner, the photodiode 1 shown in FIGS. 1 and 2 is obtained.

[0036] The action of the photodiode 1 of this embodiment will be described below. The dark current of the photodiode 1 is reduced for the following three reasons.

[0037] First, the light absorption layer 14 is formed of InGaAsP, not InGaAs. As shown in FIG. 3, as the composition ratio of As in InGaAsP increases, the band gap energy of InGaAsP increases. The band gap energy of InGaAsP is larger than that of InGaAs. As the band gap energy of the light absorption layer 14 increases, the reverse bias voltage (negative bias voltage V b The current due to minority carriers diffusing into the depletion layer generated when a voltage is applied and the current due to trap levels in the depletion layer are reduced. The dark current I d Therefore, as shown in FIGS. 12 and 13, as the band gap energy of the light absorbing layer 14 increases, the dark current I d 12 and 13 is lattice-matched to the substrate 10, which is an InP substrate.

[0038] Secondly, the light absorbing layer 14 made of InGaAsP is formed on the buffer layer 13 made of InGaAs. Therefore, as shown in FIG. 14, crystal defects in the light absorbing layer 14 are reduced and the top surface of the light absorbing layer 14 is flattened. In contrast, as shown in FIG. 15, in a comparative example in which the light absorbing layer 14 made of InGaAsP is formed directly on an InP substrate, an InAs region that is lattice mismatched to the InP substrate is formed in the light absorbing layer 14, and as a result, crystal defects in the light absorbing layer 14 increase. In addition, in the comparative example, the top surface of the light absorbing layer 14 becomes rough. The crystal defects and surface roughness of the light absorbing layer 14 affect the dark current I of the photodiode. d Therefore, as shown in FIG. 16, the light absorption layer 14 made of InGaAsP is formed on the buffer layer 13 made of InGaAs, thereby increasing the dark current I d With reference to FIG. 16, the dark current I d is the dark current I of the photodiode of the comparative example d It will decrease to one third of that.

[0039] Thirdly, in a plan view of the primary surface 10a, the minimum distance d1 between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 is 18 μm or more. Therefore, the distance between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 increases. b ), an electric field is concentrated at the outer edge 26e of the p-electrode 26, and the outer edge 26e of the p-electrode 26 becomes a region of high electric field in the photodiode 1, but the region of high electric field in the photodiode 1 is prevented from reaching the side surface 5s of the mesa structure 5. Thus, the dark current I d is reduced.

[0040] In a plan view of the main surface 10a, the minimum distance d2 between the edge of the opening 21a of the insulating layer 21 and the side surface 5s of the mesa structure 5 is 20 μm or more. Therefore, the distance between the p-type dopant diffusion region 16 defined by the opening 21a of the insulating layer 21 and the side surface 5s of the mesa structure 5 increases. When a reverse bias voltage (negative bias voltage V b 17, the dark current I d In contrast, when the minimum distance d2 between the edge of the opening 21a of the insulating layer 21 and the side surface 5s of the mesa structure 5 is 10 μm, the strong electric field region in the photodiode 1 reaches the side surface 5s of the mesa structure 5, and the dark current I d increases.

[0041] In a plan view of the main surface 10a, the maximum distance d3 between the outer edge 26e of the p-electrode 26 and the edge of the opening 21a of the insulating layer 21 is 2 μm or less. Therefore, the distance between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 and the distance between the p-type dopant diffusion region 16 and the side surface 5s of the mesa structure 5 are increased. b ) is applied, the strong electric field region in the photodiode 1 is prevented from reaching the side surface 5s of the mesa structure 5. Thus, the dark current I d is reduced.

[0042] The effects of the photodiode 1 of this embodiment will be described.

[0043] The photodiode 1 of this embodiment includes a substrate 10 and a semiconductor stack 12. The substrate 10 has a major surface 10a. The semiconductor stack 12 is disposed on the major surface 10a of the substrate 10. The semiconductor stack 12 includes a buffer layer 13 disposed on the major surface 10a of the substrate 10, and a light absorbing layer 14 disposed on the buffer layer 13. The light absorbing layer 14 is made of In xGa 1-x As y P 1-y where x and y are greater than 0 and less than 1. The buffer layer 13 is formed of In z Ga 1-z As, where z is greater than 0 and less than 1.

[0044] The light absorbing layer 14 is made of InGaAsP, not InGaAs. The band gap energy of InGaAsP is larger than that of InGaAs. Since the light absorbing layer 14 made of InGaAsP is formed on the buffer layer 13 made of InGaAs, crystal defects in the light absorbing layer 14 are reduced and the top surface of the light absorbing layer 14 is flattened. This reduces the dark current of the photodiode 1.

[0045] In the photodiode 1 of the present embodiment, the substrate 10 is an InP substrate. The light absorption layer 14 and the buffer layer 13 are lattice-matched to the InP substrate.

[0046] This reduces crystal defects in the light absorption layer 14 and the buffer layer 13. The dark current of the photodiode 1 is reduced.

[0047] In the photodiode 1 of the present embodiment, y is equal to or greater than 0.70 and less than 1.00.

[0048] Therefore, the photodiode 1 can be used to detect the intensity of light in the wavelength range from 1400 nm to 1690 nm with high accuracy.

[0049] The photodiode 1 of the present embodiment further includes a p-electrode 26. The semiconductor stack 12 further includes a p-type dopant diffusion region 16, and has a mesa structure 5. The p-type dopant diffusion region 16 is in contact with the light absorption layer 14, and is electrically connected to the p-electrode 26. In a plan view of the main surface 10a of the substrate 10, the minimum distance d1 between an outer edge 26e of the p-electrode 26 and a side surface 5s of the mesa structure 5 is 18 μm or more.

[0050] This increases the distance between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5. When a reverse bias voltage is applied to the photodiode 1, an electric field is concentrated at the outer edge 26e of the p-electrode 26, and the outer edge 26e of the p-electrode 26 becomes a strong electric field region in the photodiode 1, but the strong electric field region in the photodiode 1 is prevented from reaching the side surface 5s of the mesa structure 5. The dark current of the photodiode 1 is reduced.

[0051] The photodiode 1 of the present embodiment further includes an insulating layer 21 disposed on the semiconductor stack 12. An opening 21a is provided in the insulating layer 21. In a plan view of the main surface 10a of the substrate 10, the opening 21a in the insulating layer 21 defines a p-type dopant diffusion region 16. In a plan view of the main surface 10a, the minimum distance d2 between an edge of the opening 21a in the insulating layer 21 and the side surface 5s of the mesa structure 5 is 20 μm or more.

[0052] This increases the distance between the p-type dopant diffusion region 16 and the side surface 5s of the mesa structure 5. When a reverse bias voltage is applied to the photodiode 1, the p-type dopant diffusion region 16 becomes a strong electric field region in the photodiode 1, but the strong electric field region in the photodiode 1 is prevented from reaching the side surface 5s of the mesa structure 5. The dark current of the photodiode 1 is reduced.

[0053] In photodiode 1 of the present embodiment, in a plan view of main surface 10a of substrate 10, maximum distance d3 between outer edge 26e of p-electrode 26 and the edge of opening 21a of insulating layer 21 is 2 μm or less.

[0054] This increases the distance between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 and the distance between the p-type dopant diffusion region 16 and the side surface 5s of the mesa structure 5. When a reverse bias voltage is applied to the photodiode 1, the strong electric field region in the photodiode 1 is prevented from reaching the side surface 5s of the mesa structure 5. The dark current of the photodiode 1 is reduced.

[0055] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) A substrate having a major surface; a semiconductor laminate disposed on the main surface, the semiconductor laminate includes a buffer layer disposed on the primary surface and a light absorbing layer disposed on the buffer layer, The light absorbing layer is In x Ga 1-x As y P 1-y where x and y are greater than 0 and less than 1, The buffer layer is In z Ga 1-z A photodiode formed of As, where z is greater than 0 and less than 1. (Appendix 2) the substrate is an InP substrate, 2. The photodiode of claim 1, wherein the light absorption layer and the buffer layer are lattice-matched to the InP substrate. (Appendix 3) 3. The photodiode of claim 1, wherein y is greater than or equal to 0.70 and less than 1.00. (Appendix 4) Further comprising a p-electrode, The semiconductor stack further includes a p-type dopant diffusion region and has a mesa structure; the p-type dopant diffusion region is in contact with the light absorbing layer and is electrically connected to the p-electrode; 4. The photodiode according to claim 1, wherein in a plan view of the principal surface, a minimum distance between an outer edge of the p-electrode and a side surface of the mesa structure is 18 μm or more. (Appendix 5) Further comprising an insulating layer disposed on the semiconductor laminate, An opening is provided in the insulating layer, In the plan view of the main surface, the opening defines the p-type dopant diffusion region, 5. The photodiode of claim 4, wherein in the planar view of the main surface, a minimum distance between an edge of the opening and the side surface of the mesa structure is 20 μm or more. (Appendix 6) 6. The photodiode according to claim 5, wherein in the planar view of the principal surface, a maximum distance between the outer edge of the p-electrode and the edge of the opening is 2 μm or less.

[0056] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0057] 1 photodiode, 5 mesa structure, 5s side surface, 10 substrate, 10a, 10b main surfaces, 12 semiconductor laminate, 12a top surface, 12b bottom surface, 12s side surface, 13 buffer layer, 14 light absorption layer, 15 window layer, 16 p-type dopant diffusion region, 18 p-type contact layer, 18a opening, 21 insulating layer, 21a opening, 22 anti-reflection film, 22a through hole, 25 n electrode, 26 p electrode, 26e outer edge, 27 conductive pad.

Claims

1. A substrate having a major surface; a semiconductor laminate disposed on the main surface, the semiconductor laminate includes a buffer layer disposed on the primary surface and a light absorbing layer disposed on the buffer layer, The light absorbing layer is In ｘ G １－ｘ A.S. ｙ P １－ｙ where x and y are greater than 0 and less than 1; The buffer layer is In ｚ G １－ｚ A photodiode formed of As, where z is greater than 0 and less than 1.

2. the substrate is an InP substrate, The photodiode of claim 1 , wherein the light absorption layer and the buffer layer are lattice-matched to the InP substrate.

3. The photodiode of claim 1 , wherein y is equal to or greater than 0.70 and less than 1.

00.

4. Further comprising a p-electrode; The semiconductor stack further includes a p-type dopant diffusion region and has a mesa structure, the p-type dopant diffusion region is in contact with the light absorbing layer and is electrically connected to the p-electrode; 4. The photodiode according to claim 1, wherein in a plan view of the principal surface, a minimum distance between an outer edge of the p-electrode and a side surface of the mesa structure is 18 μm or more.

5. Further comprising an insulating layer disposed on the semiconductor laminate, An opening is provided in the insulating layer, In the plan view of the main surface, the opening defines the p-type dopant diffusion region, The photodiode according to claim 4 , wherein in the plan view of the principal surface, a minimum distance between an edge of the opening and the side surface of the mesa structure is 20 μm or more.

6. The photodiode according to claim 5 , wherein in the plan view of the principal surface, a maximum distance between the outer edge of the p-electrode and the edge of the opening is 2 μm or less.

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