Semiconductor device

Abstract

To provide a semiconductor device having an isolation type trench structure capable of improving the degree of design.SOLUTION: A semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a second electrode having a contact portion that is in contact with the second semiconductor region and the third semiconductor region at a contact portion, a plurality of field plate electrodes that are provided in the first semiconductor region via an insulating film and extends along a first direction, and a plurality of gate electrodes extending along a second direction different from the first direction. The plurality of gate electrodes include a first conductive portion provided in the second semiconductor region via a gate insulating film, and a second conductive portion that is connected to the first conductive portion and provided on the insulating film.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In vertical metal-oxide-semiconductor field-effect transistors (MOSFETs), it is desirable to have a high degree of design freedom. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5580150 [Patent Document 2] JP 2004-14858 A [Patent Document 3] Japanese Patent Application Publication No. 10-294456 [Patent Document 4] JP 2005-116985 A [Patent Document 5] JP 2018-152386 A [Patent Document 6] JP 2003-303967 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device having an isolation trench structure that allows for improved design freedom. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a second electrode having a contact portion contacting the second semiconductor region and the third semiconductor region at a contact portion, a plurality of field plate electrodes provided in the first semiconductor region via an insulating film and extending along a first direction, and a plurality of gate electrodes extending along a second direction different from the first direction. The plurality of gate electrodes include a first conductive portion provided in the second semiconductor region via a gate insulating film, and a second conductive portion connected to the first conductive portion and provided on the insulating film. [Brief description of the drawings]

[0006] [Figure 1] 1 is a plan view showing a semiconductor device according to an embodiment; [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along line CC in FIG. [Diagram 5] FIG. 2 is a cross-sectional view taken along line DD in FIG. [Figure 6A] 1 is a view (line BB) for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 6B] 1 is a view (line DD) for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 7A] 6B is a view (taken along line BB) illustrating the method for manufacturing the semiconductor device according to the embodiment, subsequent to FIG. 6A. [Figure 7B] 6B, is a view (taken along line DD) for explaining the method for manufacturing the semiconductor device according to the embodiment. [Figure 8A] 7B is a view (taken along line BB) illustrating the method for manufacturing the semiconductor device according to the embodiment, subsequent to FIG. 7A. [Figure 8B]7B, is a view (taken along line DD) for explaining the method for manufacturing the semiconductor device according to the embodiment. [Figure 9A] 8B is a view (taken along line BB) for explaining the method for manufacturing the semiconductor device according to the embodiment, subsequent to FIG. 8A. [Figure 9B] 8C is a view (taken along line DD) for explaining the method for manufacturing the semiconductor device according to the embodiment, following FIG. 8B. [Figure 10A] 9B is a view (taken along line BB) illustrating the method for manufacturing the semiconductor device according to the embodiment, subsequent to FIG. 9A. [Figure 10B] 9C is a view (taken along line DD) for explaining the method for manufacturing the semiconductor device according to the embodiment, following FIG. 9B. [Figure 11A] 10B is a view (taken along line BB) for explaining the method for manufacturing the semiconductor device according to the embodiment, following FIG. 10A. [Figure 11B] 10C is a view (taken along line DD) for explaining the method for manufacturing the semiconductor device according to the embodiment, following FIG. 10B. [Figure 12] FIG. 1 is a plan view showing a semiconductor device according to a first modified example of the embodiment. [Figure 13] FIG. 14 is a cross-sectional view taken along line EE in FIG. [Figure 14] FIG. 11 is a diagram for explaining a second modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, elements similar to those already described are given the same reference numerals, and detailed description will be omitted as appropriate.

[0008] In the following description, n + , n, n - , and p + , p, p - The notation n may be used.+ has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + Shape and n - The p-type is an example of the first conductivity type in the claims. + Shape and p - The above-mentioned type is an example of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. In other words, the first conductivity type may be the p-type and the second conductivity type may be the n-type.

[0009] The impurity concentration can be measured by, for example, secondary ion mass spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, scanning capacitance microscopy (SCM).

[0010] The depth of the impurity region, the thickness of the insulating layer, etc. can be measured on images of, for example, SIMS or a TEM (Transmission Electron Microscope).

[0011] In the description of the embodiment, an XYZ Cartesian coordinate system is used. The direction from the drain electrode toward the source electrode is the Z axis. Two axes that are perpendicular to the Z axis and perpendicular to each other are the X axis and the Y axis. As will be described later, the gate electrode extends along the X axis, and the field plate electrode extends along the Y axis. For convenience of description, the direction from the drain electrode toward the source electrode is called "up" and the opposite direction is called "down". These directions are based on the relative positional relationship between the drain electrode and the source electrode and are unrelated to the direction of gravity.

[0012] A semiconductor device 1 according to an embodiment will be described with reference to Fig. 1 to Fig. 5. Fig. 1 is a plan view showing a part of the semiconductor device 1. Figs. 2, 3, 4 and 5 are cross-sectional views taken along lines AA, BB, CC and DD in Fig. 1, respectively. Note that a source electrode 50 is only shown in Fig. 2.

[0013] The semiconductor device 1 is configured as a vertical MOSFET. The semiconductor device 1 includes a semiconductor layer 10, a plurality of field plate electrodes (FP electrodes) 20 provided in the semiconductor layer 10, a plurality of gate electrodes 30 provided above the FP electrodes 20, a source electrode 50 provided on the upper surface side of the semiconductor layer 10, and a drain electrode 60 provided on the lower surface side of the semiconductor layer 10.

[0014] 5, the semiconductor layer 10 has a source region 11, a base region 12, a drift region 13, and a drain region 14. In this embodiment, the semiconductor layer 10 is made of silicon (Si), and an n-type impurity such as arsenic (As), phosphorus (P), or antimony (Sb) is used. An example of a p-type impurity is boron (B).

[0015] The semiconductor layer 10 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. The semiconductor layer 10 may be an epitaxial layer or a semiconductor substrate in which each semiconductor region is formed by ion implantation and thermal diffusion. The semiconductor layer 10 may be made of a compound semiconductor such as silicon carbide (SiC) or gallium arsenide (GaAs).

[0016] The source region 11 is a semiconductor region that functions as a source region of the MOSFET, and is provided on the base region 12 as shown in FIG. + The n-type impurity concentration is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3The source region 11 is an example of a third semiconductor region in the claims.

[0017] The base region 12 is a semiconductor region that functions as a base region of the MOSFET, and is provided on the drift region 13 as shown in Figures 2 and 5. The base region 12 is a p-type semiconductor region, and the p-type impurity concentration is, for example, 1 × 10 16 cm -3 More than 1×10 20 cm -3 The base region 12 is an example of a second semiconductor region in the claims.

[0018] The drift region 13 is a semiconductor region that functions as a drift region of the MOSFET, and is provided on the drain region 14. The drift region 13 is an n - The n-type impurity concentration is, for example, 1×10 15 cm -3 More than 2×10 16 cm -3 The drift region 13 is an example of a first semiconductor region in the claims.

[0019] The drain region 14 is a semiconductor region that functions as a drain region of the MOSFET and is provided on the drain electrode 60. The drain region 14 is an n + The n-type impurity concentration is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The drain region 14 is an example of a first semiconductor region in the claims. The first semiconductor region in the claims may be the drift region 13 and / or the drain region 14.

[0020] As shown in Figs. 1 to 4, the multiple field plate electrodes 20 extend in a stripe shape along the Y-axis direction. Note that Fig. 1 shows an FP insulating film 42 located directly above the field plate electrode 20. Also, as shown in Figs. 2 to 4, the multiple field plate electrodes 20 are embedded in the semiconductor layer 10 via the FP insulating films 41, 42. More specifically, each field plate electrode 20 is provided in the drift region 13 of the semiconductor layer 10 via the FP insulating films 41, 42. The FP insulating films 41, 42 are made of an insulating material such as silicon oxide or silicon nitride. Note that the FP insulating film 41 may be a thermal oxide film such as a silicon thermal oxide film. The FP insulating films 41, 42 are an example of an insulating film in the claims.

[0021] 2 and 4, each field plate electrode 20 is electrically connected to a source electrode 50 via a source contact 51. Each field plate electrode 20 is made of, for example, conductive polysilicon.

[0022] 1, the multiple gate electrodes 30 extend in a stripe shape along the X-axis direction. Each gate electrode 30 is electrically connected to a gate pad (not shown) of the semiconductor device 1. The direction in which the multiple gate electrodes 30 extend is perpendicular to the direction in which the multiple field plate electrodes 20 extend. Note that the angle at which the field plate electrode 20 and the gate electrode 30 intersect does not have to be strictly a right angle, and may be an angle other than a right angle.

[0023] 3, the multiple gate electrodes 30 are provided above the multiple field plate electrodes 20. Between the gate electrodes 30 and the field plate electrodes 20, only FP insulating films 41, 42 are interposed.

[0024] As shown in FIG. 3, each gate electrode 30 has conductive portions 30a (first conductive portions) and conductive portions 30b (second conductive portions) connected to the conductive portions 30a, which are arranged alternately. As shown in FIG. 5, the conductive portions 30a are provided in the base region 12 via a gate insulating film 43 (second insulating region). As shown in FIG. 3 and FIG. 4, the conductive portions 30b are provided on the FP insulating films 41 and 42. In this embodiment, the conductive portions 30b are provided so as to straddle the FP insulating films 41 and 42. The gate insulating film 43 is made of an insulating material, such as silicon oxide or silicon nitride.

[0025] The gate electrodes 30 are insulated from each other except for ends (not shown) of the gate electrodes 30. For example, as shown in FIG. 1, no wiring is provided between at least adjacent conductive portions 30b to electrically connect the gate electrodes 30 to each other.

[0026] The source electrode 50 is provided on the source region 11 via the interlayer insulating film 44. The source electrode 50 is an example of a second electrode in the claims.

[0027] The source electrode 50 has a source contact 51 and a source contact 52. As shown in Fig. 2 and Fig. 4, the source contact 51 electrically connects the field plate electrode 20 and the source electrode 50. As shown in Fig. 5, the source contact 52 is provided so as to penetrate the source region 11 and reach the base region 12, and is electrically connected to the source region 11 and the base region 12. The source electrode 50 contacts the source region 11 and the base region 12 at the source contact 52. The source contact 52 is an example of a contact portion in the claims.

[0028] The drain electrode 60 is provided so as to be in contact with the drain region 14 of the semiconductor layer 10. The drain electrode 60 is an example of a first electrode in the claims.

[0029] The source electrode 50 and the drain electrode 60 are made of a metal such as titanium (Ti), tungsten (W), or aluminum (Al).

[0030] As described above, in the semiconductor device 1 according to this embodiment, the gate electrode 30 extends in a direction perpendicular to the extension direction of the field plate electrode 20, and has the conductive portion 30a and the conductive portion 30b. The conductive portion 30a is provided in the base region 12 via the gate insulating film 43, and the conductive portion 30b is provided on the FP insulating films 41, 42 in which the field plate electrode 20 is embedded. In other words, no semiconductor region is interposed between the multiple field plate electrodes 20 and the multiple gate electrodes 30, and only the FP insulating films 41, 42 are provided. Thus, in this embodiment, the gate electrode 30 is configured to extend in the X-axis direction without being divided by the field plate electrode 20 (FP insulating film 41).

[0031] The effect of the semiconductor device 1 according to this embodiment will be described. Vertical MOSFETs include an integrated trench structure in which the gate electrode and the field plate electrode are arranged in one trench, and a separate trench structure in which the gate electrode and the field plate electrode are arranged in separate trenches. In the case of the integrated trench structure, the insulating film in which the field plate electrode is embedded must be thickened to satisfy the desired breakdown voltage, which may restrict the cell pitch. On the other hand, in the case of the separate trench structure, it is relatively easy to avoid the restriction on the cell pitch.

[0032] The separated trench structure includes a structure in which the gate electrode is arranged to intersect with the field plate electrode. With such a structure, restrictions on the gate electrode are relaxed, so that it is possible to increase the channel density and reduce the on-resistance. However, either the gate electrode or the field plate electrode is divided at the intersection. When the gate electrode is divided, it is necessary to provide new wiring to electrically connect the gate electrodes. On the other hand, when the field plate electrode is divided, it becomes difficult to ensure the breakdown voltage, and it becomes difficult to miniaturize the semiconductor device. Thus, in either case, the design freedom of the semiconductor device is reduced.

[0033] According to the semiconductor device 1 of this embodiment, it is possible to provide a semiconductor device 1 having an isolated trench structure that can improve the degree of freedom in design. For example, restrictions on the width, number, and spacing of the gate electrodes 30 are relaxed. Furthermore, since the gate electrodes 30 are not divided by the field plate electrode 20 (FP insulating film 41), there is no need to provide wiring for electrically connecting the gate electrodes 30 together. As a result, the gate capacitance (the capacitance C between the gate electrode and the drain electrode) is reduced. GD Although the gate electrode 30 of the present embodiment includes the conductive portion 30b, the conductive portion 30b is disposed on the FP insulating films 41 and 42, and therefore the conductive portion 30b does not have a capacitance C GD The impact on

[0034] Furthermore, in the semiconductor device 1 of this embodiment, since the field plate electrode 20 is not divided by the gate electrode 30, it is relatively easy to ensure the breakdown voltage of the semiconductor device 1. Therefore, the semiconductor device 1 can be miniaturized.

[0035] <Method of Manufacturing Semiconductor Device 1> An example of a manufacturing method of the semiconductor device 1 will be described with reference to Figures 6A to 11B. Figures 6A, 7A, 8A, 9A, 10A, and 11A are cross-sectional views of a region corresponding to line BB in Figure 1. Figures 6B, 7B, 8B, 9B, 10B, and 11B are cross-sectional views of a region corresponding to line DD in Figure 1.

[0036] First, an n-type semiconductor substrate 2 is prepared. The impurity concentration of the semiconductor substrate 2 may be the same as the impurity concentration of the drift region 13. On the semiconductor substrate 2, a mask (not shown) having a plurality of openings extending in the Y-axis direction is formed.

[0037] Next, as shown in FIGS. 6A and 6B, the semiconductor substrate 2 exposed in the openings of the mask is etched by reactive ion etching (RIE) or the like to form a plurality of trenches extending in the Y-axis direction. Then, an insulating film such as a silicon oxide film or a silicon nitride film is formed so as to fill each trench by thermal oxidation or chemical vapor deposition (CVD) or the like. Then, a part (central part) of the formed insulating film is removed in a groove shape by RIE or the like. In this manner, the FP insulating film 41 is formed. Then, a conductive material such as polysilicon is deposited in the FP insulating film 41 by CVD or the like, and the excess conductive material is etched back to form the field plate electrode 20.

[0038] 7A and 7B, an insulating material is deposited on the semiconductor substrate 2 by thermal oxidation, CVD, or the like to form an FP insulating film 42 that covers the upper surface of the semiconductor substrate 2 and embeds the field plate electrode 20. The FP insulating film 42 is made of, for example, a silicon oxide film or silicon nitride. After the FP insulating film 42 is formed, a resist R having an opening extending in the X-axis direction is formed on the FP insulating film 42 as shown in FIG. 7B.

[0039] Next, the FP insulating film 42 that is not covered with the resist R is removed by etching. The FP insulating film 42 that is removed is the portion that exists on the semiconductor substrate 2, and the FP insulating film 42 in which the field plate electrode 20 is embedded remains.

[0040] 8A and 8B, the semiconductor substrate 2 is removed by etching to form a gate trench GT. Here, the FP insulating films 41 and 42 are not removed by selective etching, and only the semiconductor substrate 2 (silicon) is removed. The FP insulating films 41 and 42 may be removed by etching to an extent that the field plate electrode 20 is not exposed. For example, the upper surfaces of the FP insulating films 41 and 42 may be made substantially flush with the upper surface of the semiconductor substrate 2.

[0041] 9A and 9B, a gate insulating film 43 is formed on the inner wall of the gate trench GT by thermal oxidation, CVD (Chemical Vapor Deposition), etc. The gate insulating film 43 is made of, for example, a silicon oxide film or silicon nitride.

[0042] 10A and 10B, a conductive material such as polysilicon is deposited in the gate trench GT and on the FP insulating films 41 and 42 by a CVD method or the like. This forms the gate electrode 30 having the conductive portion 30a and the conductive portion 30b. Alternatively, a metal material may be deposited by a sputtering method or the like to form the gate electrode 30 made of the metal material.

[0043] 11A and 11B, the FP insulating film 42 between the gate trenches GT is removed, and the base region 12 and the source region 11 are formed in the semiconductor substrate 2. In detail, n-type impurities are ion-implanted into the semiconductor substrate 2 between the gate trenches GT to form the source region 11. Thereafter, p-type impurities are ion-implanted to form the base region 12 on the source region 11.

[0044] Thereafter, an insulating material is deposited by a CVD method or the like so as to cover the upper surface of the semiconductor substrate 2 and bury the gate electrode 30, thereby forming an interlayer insulating film 44. Thereafter, the FP insulating film 42 and the interlayer insulating film 44 on the field plate electrode 20 are removed to form contact holes. In addition, contact holes are formed that penetrate the interlayer insulating film 44 and the source region 11 to reach the base region 12. Source contacts 51 and 52 are formed by filling these contact holes with a metal material. Thereafter, a metal material is deposited on the interlayer insulating film 44 to form a source electrode 50.

[0045] Through the above steps, the semiconductor device 1 according to the embodiment is manufactured.

[0046] Next, two modified examples of the embodiment will be described.

[0047] (Variation 1) A first modified example of the embodiment will be described with reference to FIG. 12 and FIG.

[0048] In addition to the components of the semiconductor device 1 described above, the semiconductor device 1A according to the first modification further includes an inter-gate electrode wiring 31 that electrically connects the multiple gate electrodes 30. As shown in FIG. 12, the inter-gate electrode wiring 31 is provided between adjacent conductive portions 30b.

[0049] 13, the gate electrode inter-wiring 31 is disposed on the drift region 13 via a gate insulating film 43, similar to the gate electrode 30. The gate electrode inter-wiring 31 can be formed together with the gate electrode 30. That is, when the gate trench GT is formed, the trench for the gate electrode inter-wiring 31 is also formed. Thereafter, the gate insulating film 43 is formed in the trench, and a metal material is deposited to form the gate electrode 30 and the gate electrode inter-wiring 31.

[0050] 13, the gate electrode inter-wiring 31 extends in the Y-axis direction and is perpendicular to the gate electrode 30. However, the present invention is not limited to this, and the gate electrode 30 and the gate electrode inter-wiring 31 do not have to be perpendicular to each other. The number of gate electrode inter-wirings 31 is not limited to one, and multiple gate electrode inter-wirings may be provided.

[0051] According to this modification, since the gate electrode wiring 31 is provided, it is possible to reduce the gate resistance and improve the flexibility of the contact with the gate electrode 30. For example, the gate electrode 30 can be electrically accessed not only from the lateral direction (left and right sides) of FIG. 12 but also from the vertical direction (upper and lower sides).

[0052] (Variation 2) A second modified example of the embodiment will be described with reference to Fig. 14. The diagram on the left side of Fig. 14 is a cross-sectional view taken at a position corresponding to line CC in Fig. 1. The diagram on the right side of Fig. 14 is a cross-sectional view taken at a position corresponding to line DD in Fig. 1.

[0053] 14, in this modification, the upper end T of the field plate electrode 20 is located above the lower end L of the base region 12. The position of the upper end of the field plate electrode 20 can be adjusted, for example, by changing the conditions for etching back the conductive material filled in the FP insulating film 41.

[0054] According to this modification, the on-resistance can be reduced by the RESURF effect. Also, the effect of the field plate electrode 20 (the effect of reducing the concentration of the reverse electric field between the gate electrode 30 and the drain electrode 60) is enhanced, so that the breakdown voltage of the semiconductor device 1, 1A can be improved.

[0055] According to the semiconductor device of the embodiment and the modified example described above, a plurality of gate electrodes 30 each having a conductive portion 30a provided in the base region 12 via the gate insulating film 43 and a conductive portion 30b connected to the conductive portion 30a and provided on the FP insulating films 41, 42 are provided above a plurality of field plate electrodes 20. As a result, neither the plurality of field plate electrodes 20 nor the plurality of gate electrodes 30 are divided, thereby improving the degree of freedom in designing the semiconductor device.

[0056] Although the embodiment of the present invention has been described, the embodiment and examples are presented as examples and are not intended to limit the scope of the invention. The embodiment and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and examples and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and gist of the invention. [Explanation of symbols]

[0057] 1,1A Semiconductor Device 2. Semiconductor Substrate 10 Semiconductor layer 11 Source Area 12 Base Area 13 Drift Region 14 Drain Region 20 Field plate electrode 30 Gate electrode 30a,30b Conductive part 31 Gate electrode wiring 41,42 FP insulating film 43 Gate insulating film 44 Interlayer insulating film 50 Source electrode 51,52 Source Contact 60 Drain electrode GT Gate Trench L Bottom edge (of the base area) R Resist T (Top of FP electrode)

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode contacting the second semiconductor region and the third semiconductor region at a contact portion; a plurality of field plate electrodes provided in the first semiconductor region via an insulating film and extending along a first direction; a plurality of gate electrodes extending along a second direction different from the first direction, the gate electrodes having a first conductive portion provided in the second semiconductor region via a gate insulating film, and a second conductive portion connected to the first conductive portion and provided on the insulating film; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein only said insulating film is provided between said plurality of gate electrodes and said plurality of field plate electrodes, with no semiconductor region interposed therebetween.

3. The semiconductor device according to claim 1 , wherein the second conductive portion is provided so as to straddle the insulating film in which the field plate electrode is embedded.

4. 2. The semiconductor device according to claim 1, wherein said insulating film is a thermal oxide film.

5. The semiconductor device according to claim 1 , wherein the first direction and the second direction are perpendicular to each other.

6. The semiconductor device according to claim 1 , wherein an upper end of said field plate electrode is located higher than a lower end of said second semiconductor region.

7. 7. The semiconductor device according to claim 1, wherein no wiring is provided between adjacent second conductive portions to electrically connect said plurality of gate electrodes to each other.

8. 7. The semiconductor device according to claim 1, further comprising inter-gate electrode wiring that electrically connects the plurality of gate electrodes to each other between adjacent second conductive portions.

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