Solid-state imaging device
The solid-state imaging device addresses the challenge of proper chip-to-analog front end connection by incorporating a chip with a pixel array and multiple signal lines, resulting in efficient signal output and adaptable design for various applications.
JP2025045862APending Publication Date: 2025-04-02KK TOSHIBA +1
5 Cites 0 Cited by
Patent Information
- Application Number
- JP2023153867
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-09-20
- Publication Date
- 2025-04-02
AI Technical Summary
Technical Problem
Existing solid-state imaging devices face challenges in ensuring proper connection between the chip and the analog front end, which affects the efficient output of image signals.
Method used
The solid-state imaging device is designed with a chip that includes a pixel array, multiple signal lines, output circuits, and output terminals, allowing for proper connection and signal transfer between the chip and the analog front end.
Benefits of technology
This configuration enables efficient signal output and flexible adaptation to different application requirements, such as speed-first or cost-first applications, while standardizing the design and reducing manufacturing costs.
✦ Generated by Eureka AI based on patent content.
Abstract
To provide a solid-state imaging device suitable for appropriately connecting a chip and an analog front end.SOLUTION: A solid-state imaging device having a chip is provided. The chip has a pixel array, a plurality of signal lines, a plurality of output circuits, and a plurality of output terminals. The pixel array has a plurality of pixel groups arranged at least in a column direction. Each of the plurality of pixel groups includes two or more pixels. The plurality of signal lines correspond to the plurality of pixel groups. Each of the plurality of signal lines is connected to a corresponding pixel group. The plurality of output circuits correspond to the plurality of signal lines. Each of the plurality of output circuits is connected to a corresponding signal line. The plurality of output terminals correspond to the plurality of output circuits. Each of the plurality of output terminals is connected to a corresponding output circuit.SELECTED DRAWING: Figure 2
Need to check novelty before this filing date? Find Prior Art