Power conversion device

Abstract

To provide a power conversion device in which both inductance reduction and inductance equalization are achieved.SOLUTION: A power conversion device includes a wiring board on which a plurality of upper arm semiconductor elements and a plurality of lower arm semiconductor elements are connected in parallel, and a plurality of wiring layers are provided. The plurality of wiring layers include positive electrode wiring extending along the arrangement direction of the plurality of upper arm semiconductor elements, negative electrode wiring extending along the arrangement direction of the plurality of lower arm semiconductor elements, and output wiring connecting the plurality of upper arm semiconductor elements and the plurality of lower arm semiconductor elements. The positive electrode wiring and the negative electrode wiring form a first positive-negative electrode wiring pair in which the positive electrode wiring and negative electrode wiring are disposed in parallel and each layered on the output wiring and a second positive-negative electrode wiring pair in which the positive electrode wiring and the negative electrode wiring are layered on each other.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a power conversion device. [Background technology]

[0002] For card-type inverters that incorporate small semiconductor packages, parallel mounting of multiple small semiconductor packages is required to improve productivity and expand the output lineup. At the same time, reduction in inductance that occurs when a large current is generated by parallel mounting of multiple small semiconductor packages is also required. For example, the following Patent Document 1 describes the configuration of a semiconductor module that reduces inductance by changing the wiring structure in the wiring board along the arrangement direction of the semiconductor elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6269296 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the objective of reducing inductance is achieved, but the focus is only on reducing the inductance of the short-circuit loop path of the upper and lower arms of the semiconductor element, and there is a problem in that the inductance variation when multiple semiconductor chips are parallelized is not considered. In addition, in order to achieve the objective of miniaturizing the main circuit board on which the small semiconductor package is mounted, it is difficult to make the wiring lengths connecting the film capacitor and each semiconductor device equal, and this configuration has a problem in that the current of each semiconductor device varies due to the inductance difference. In view of this, the present invention aims to provide a power conversion device that achieves both low inductance and equal inductance. [Means for solving the problem]

[0005] A power conversion device having a wiring board having multiple wiring layers on which a plurality of upper arm semiconductor elements and a plurality of lower arm semiconductor elements are connected in parallel, the plurality of wiring layers including positive wiring extending along the arrangement direction of the plurality of upper arm semiconductor elements, negative wiring extending along the arrangement direction of the plurality of lower arm semiconductor elements, and output wiring connecting the plurality of upper arm semiconductor elements and the plurality of lower arm semiconductor elements, the positive wiring and the negative wiring forming a first positive and negative wiring pair each arranged in parallel and stacked on the output wiring, and a second positive and negative wiring pair each arranged stacked on top of each other. Effect of the Invention

[0006] It is possible to provide a power conversion device that achieves both low inductance and uniform inductance. [Brief description of the drawings]

[0007] [Figure 1] Circuit diagram of the power conversion device of the present invention. [Diagram 2] 1 is an overall external view of a power conversion device according to the present invention; [Diagram 3] 1 is a cross-sectional view of a wiring board according to an embodiment of the present invention; [Figure 4] 1 is a diagram of a semiconductor device according to an embodiment of the present invention; [Diagram 5] FIG. 1 is a diagram of a wiring board having second to fourth layers according to an embodiment of the present invention. [Figure 6] FIG. 1 is a diagram of a wiring board on which a second capacitor is disposed according to an embodiment of the present invention;

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0009] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0010] (One embodiment of the present invention and overall configuration) (Figure 1) The power conversion device 1 is composed of three-phase semiconductor devices having U, V, and W phases. Each semiconductor device is composed of an upper arm semiconductor element 4 and a lower arm semiconductor element 5. For the upper arm semiconductor element 4 and the lower arm semiconductor element 5, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used.

[0011] A plurality of upper-arm semiconductor elements 4 and lower-arm semiconductor elements 5 are formed and connected in parallel to each other to increase the output current of the power conversion device 1. In a power conversion circuit for one of the U-phase, V-phase, and W-phase, an upper-arm semiconductor element 4 and a lower-arm semiconductor element 5 that are connected in series are paired with a capacitor 8. In addition, a small ceramic capacitor 7 is connected in parallel for each phase.

[0012] The output wiring 6 of each phase is connected to a load such as a motor (not shown). The output wiring 6 also connects the multiple upper arm semiconductor elements 4 and the multiple lower arm semiconductor elements 5. The capacitors 8 are, for example, film capacitors or electrolytic capacitors with large capacitance. By arranging such capacitors 8 in the vicinity of the upper arm semiconductor elements 4 and the lower arm semiconductor elements 5, the wiring inductance of the positive electrode wiring 2 and the negative electrode wiring 3 is reduced.

[0013] The positive wiring 2 is connected to a positive terminal of a DC power source such as a battery (not shown), and the negative wiring 3 is connected to a negative terminal of the DC power source such as a battery, etc. This allows a DC voltage to be supplied to the power conversion circuit of each phase.

[0014] (Figure 2) The power conversion device 1 includes a wiring board 13 on which a plurality of upper arm semiconductor elements 4 and a plurality of lower arm semiconductor elements 5 are connected in parallel, and which has a plurality of wiring layers. The capacitor 8 is connected to a positive electrode wiring 2 and a negative electrode wiring 3 provided on the wiring board 13. The capacitor 8 is disposed adjacent to one side (side) of the wiring board 13 and electrically connected thereto, which facilitates fixing the capacitor 8 to a housing (not shown) of the power conversion device 1. This can improve vibration resistance.

[0015] The output terminal 6a is arranged on the other side of the wiring board 13 opposite to the side on which the capacitor 8 is arranged, and is electrically connected to the output wiring 6. By arranging the upper arm semiconductor element 4 and the lower arm semiconductor element 5 side by side and extending them from the capacitor 8 toward the output terminal 6a, it is possible to shorten the positive electrode wiring 2, the negative electrode wiring 3, and the output wiring 6, and to miniaturize the power conversion device 1. By arranging the multiple upper arm semiconductor elements 4 and the multiple lower arm semiconductor elements 5 in a row, it becomes easy to attach a cooler (not shown) to this portion, and it is also possible to miniaturize the cooler.

[0016] Three-phase semiconductor devices, namely, U-phase, V-phase, and W-phase, are arranged on wiring board 13. Positive wiring 2 and negative wiring 3 are formed in parallel between the respective semiconductor devices. A plurality of capacitors 8 are arranged on wiring board 13 along the arrangement of the U-phase, V-phase, and W-phase semiconductor devices.

[0017] (Figure 3) Between the row of upper arm semiconductor elements 4 and the row of lower arm semiconductor elements 5, wiring board 13 has a plurality of wiring layers. The plurality of wiring layers include positive wiring 2 extending along the arrangement direction of the plurality of upper arm semiconductor elements 4, negative wiring 3 extending along the arrangement direction of the plurality of lower arm semiconductor elements 5, and output wiring 6 connecting the plurality of upper arm semiconductor elements 4 and the plurality of lower arm semiconductor elements 5.

[0018] The wiring board 13 is configured by stacking four layers of wiring. If the layers are designated as the first layer, the second layer, etc. from the top in FIG. 3, the first layer has the positive electrode wiring 2 and the negative electrode wiring 3 arranged in parallel. The second layer has the output wiring 6 arranged. The third layer has the negative electrode wiring 3 arranged between the output wirings 6. The fourth layer has the positive electrode wiring 2 arranged between the output wirings 6. An insulating material such as resin is filled between each layer of the wiring board 13, and thus the wirings 2, 3, and 6 formed on each layer are electrically insulated from each other.

[0019] A wiring pair in which the positive wiring 2 and the negative wiring 3 are formed in parallel and stacked on the output wiring 6 is referred to as a first positive / negative wiring pair 13a, and a wiring pair in which the positive wiring 2 and the negative wiring 3 are stacked on top of each other is referred to as a second positive / negative wiring pair 13b.

[0020] In this way, based on a structure in which the chips on the upper and lower arms are arranged in multiple parallel rows, two types of stacked wiring pair structures with different opposing partners are provided for the positive wiring 2 and negative wiring 3 that run along the arrangement direction of the multiple upper arm semiconductor elements 4 and lower arm semiconductor elements 5 arranged in parallel, thereby making it possible to achieve both low inductance and equal inductance.

[0021] (Figure 4) By widely opposing the current flowing from capacitor 8 (see FIG. 2) located on the upper side of the page to each semiconductor device (upper arm semiconductor element 4, lower arm semiconductor element 5), an increase in inductance caused by extending wiring 2, 3, 6 is suppressed. Furthermore, by achieving both low inductance and equal inductance, it is possible to realize a large current by driving a large number of semiconductor devices arranged in parallel in parallel.

[0022] Wiring board 13 is electrically connected to terminals of upper arm semiconductor element 4 and lower arm semiconductor element 5. Control terminals 10 of upper arm semiconductor element 4 and lower arm semiconductor element 5 are connected to a control circuit (not shown), and are turned on or off based on a signal input from a higher-level control device such as a microcomputer, thereby outputting an AC voltage to a load such as a motor.

[0023] The terminals of the upper arm semiconductor element 4 and the lower arm semiconductor element 5 will be described. The upper arm semiconductor element 4 has three terminals, a main circuit high voltage side terminal 12, a main circuit low voltage side terminal 12a, and a control terminal 10. The lower arm semiconductor element 5 has three terminals, a main circuit high voltage side terminal 11, a main circuit low voltage side terminal 11a, and a control terminal 10. In the upper arm semiconductor element 4 and the lower arm semiconductor element 5 connected to the wiring board 13, the main circuit high voltage side terminals 11, 12 and the main circuit low voltage side terminals 11a, 12a are alternately arranged and electrically connected to the wiring board 13.

[0024] The main circuit high voltage side terminals 11, 12 are collector terminals for an IGBT and drain terminals for a MOSFET. The main circuit low voltage side terminals 11a, 12a are emitter terminals for an IGBT and source terminals for a MOSFET. The control terminal 10 is a gate terminal or the like.

[0025] The high-voltage side terminal 12 and low-voltage side terminal 12a for the main circuit of the upper arm semiconductor element 4, the high-voltage side terminal 11 and low-voltage side terminal 11a for the main circuit of the lower arm semiconductor element 5, and the control terminal 10 are connected to the positive wiring 2 and negative wiring 3 formed on the first layer (outermost layer) of the wiring board 13 via a bonding material such as solder.

[0026] The positive electrode wiring 2, the negative electrode wiring 3 and the output wiring 6 formed in the first layer are electrically connected to other layers stacked on the wiring board 13 by interlayer connectors 9 formed by through-hole vias or the like.

[0027] A plurality of interlayer connections 9 are formed on the positive wiring 2 and the negative wiring 3 along the arrangement direction of the plurality of upper arm semiconductor elements 4 and the plurality of lower arm semiconductor elements 5. The interlayer connections 9 electrically connect the positive wirings 2 and the negative wirings 3 of the first positive / negative wiring pair 13a and the second positive / negative wiring pair 13b, thereby increasing the cross-sectional area of ​​the current flowing in the cross-sectional direction of the wiring board 13 (the direction in which the wiring is stacked). This reduces electrical resistance, and reduces heat generation in the positive wiring 2 and the negative wiring 3. Furthermore, the interlayer connections 9 improve the heat transfer in the cross-sectional direction of the wiring board 13, thereby suppressing an increase in the wiring temperature.

[0028] The positive terminal of capacitor 8 is connected to the main circuit high voltage side terminal 12 of the upper arm semiconductor element 4 by a positive wiring 2. The negative terminal of capacitor 8 is connected to the main circuit low voltage side terminal 11a of the lower arm semiconductor element 5 by a negative wiring 3. The main circuit low voltage side terminal 12a of the upper arm semiconductor element 4 is connected to the main circuit high voltage side terminal 11 of the lower arm semiconductor element 5 by output wiring 6 of each phase.

[0029] In addition, the positive wiring 2 is connected to the positive terminal of the capacitor 8 of the other phase and to the high voltage side terminal 11 for the main circuit of the upper arm semiconductor element 4 of the other phase. The negative wiring 3 is connected to the negative terminal of the capacitor 8 of the other phase and to the low voltage side terminal 11a for the main circuit of the lower arm semiconductor element 5 of the other phase. This makes it possible to configure a multi-phase circuit.

[0030] (Figure 5) Fig. 5(a) is a diagram explaining the second layer of wiring board 13, Fig. 5(b) is a diagram explaining the third layer of wiring board 13, and Fig. 5(c) is a diagram explaining the fourth layer of wiring board 13. As described above, wiring board 13 has a plurality of wiring layers in the thickness direction of wiring board 13. For example, when wiring board 13 is a four-layer board, the first layer is disposed on the front surface of the board, and the fourth layer is disposed on the back surface of the board.

[0031] The output wiring 6 is arranged in the second layer. This makes it possible to shorten the length of the wiring connecting the main circuit low-voltage side terminal 12a of the upper arm semiconductor element 4 and the main circuit high-voltage side terminal 11 of the lower arm semiconductor element 5, thereby reducing the wiring inductance.

[0032] In the third layer, the positive wire 2 is disposed between the output wires 6. The capacitor 8 is disposed on one side (upper side of the drawing) of the wiring board 13, and is electrically connected to the second positive and negative wire pair 13b (see FIG. 3). The second positive and negative wire pair 13b including the positive wire 2 in the third layer is formed along an extension direction perpendicular to one side of the wiring board 13, and the more distant it is from the capacitor 8, the smaller its cross-sectional area (conductive cross-sectional area) in the direction perpendicular to the extension direction.

[0033] The output wiring 6 is formed along an extension direction perpendicular to the other side of the wiring board 13. The output wiring 6 is configured such that the cross-sectional area in the direction perpendicular to the extension direction becomes smaller the farther away from the output terminal 6a the wiring 6 is. This makes it possible to adjust the balance of the current density on the DC side and the AC side, to equalize the current density of each wiring, and to suppress a local temperature rise in the wiring board 13.

[0034] (Figure 6) In the first layer (outermost layer) of wiring board 13, a ceramic capacitor 7 (second capacitor) is disposed between positive electrode wiring 2 and negative electrode wiring 3 formed in parallel. Ceramic capacitor 7 is a second capacitor provided separately from capacitor 8, and is disposed at an equal distance from each semiconductor device. A wiring layer is formed between ceramic capacitor 7 and upper arm semiconductor element 4 and lower arm semiconductor element 5, so that the direction of current is determined.

[0035] The distance between the capacitor 8 and each semiconductor device is different, and the positive wire 2 and the negative wire 3 of the second positive / negative wire pair 13b connecting the capacitor 8 to each semiconductor device are laminated. By opposing the switching transient current flowing from the ceramic capacitor 7 to each semiconductor device between the layers of the second positive / negative wire pair 13b, the inductance can be reduced and the transient current supplied from the capacitor 8 is suppressed. Furthermore, with the above configuration, the current flowing from the capacitor 8 to each semiconductor device is widely opposed, thereby suppressing the inductance difference due to unequal length wires.

[0036] Ceramic capacitors 7 are disposed at equal distances from corresponding elements among the large number of upper arm semiconductor elements 4 and lower arm semiconductor elements 5 connected in parallel, thereby suppressing variations in wiring inductance.

[0037] Since the ceramic capacitor 7 is connected to the upper arm semiconductor element 4 and the lower arm semiconductor element 5 by the positive wiring 2 and negative wiring 3 which realize low inductance, the current supplied from the capacitor 8 during switching is reduced, and therefore the effect of the inductance difference on the positive wiring 2 and negative wiring 3 which connect the capacitor 8 to the upper arm semiconductor element 4 and the lower arm semiconductor element 5 can be reduced.

[0038] By arranging ceramic capacitor 7 in the vicinity of upper arm semiconductor element 4 and lower arm semiconductor element 5, transient current during switching is supplied not only from capacitor 8 but also from ceramic capacitor 7. In addition, first positive / negative wiring pair 13a causes currents flowing through positive wiring 2 and negative wiring 3 connecting ceramic capacitor 7 to upper arm semiconductor element 4 and lower arm semiconductor element 5 to oppose each other. This cancels out the magnetic flux, reducing the inductance of the wiring connecting ceramic capacitor 7 to upper arm semiconductor element 4 and lower arm semiconductor element 5, and enabling the transient current supplied from ceramic capacitor 7 to be increased.

[0039] In the first positive / negative wiring pair 13a, which is a closed loop path passing through the ceramic capacitor 7, the positive wiring 2, the negative wiring 3 and the output wiring 6 are arranged in a stacked manner, and transient currents flow in opposite directions, reducing inductance. Also, the main circuit current flowing from the capacitor 8 cancels out magnetic fluxes in the positive wiring 2 and the negative wiring 3, reducing the inductance difference depending on the position between the semiconductor devices.

[0040] Since the increase in wiring inductance due to wiring extension is suppressed, the wiring inductance difference is small and current variation is suppressed even for semiconductor devices arranged far from capacitor 8. By opposing the switching transient current flowing from ceramic capacitor 7 to each semiconductor device between layers, the inductance is reduced and the transient current supplied from capacitor 8 can be suppressed.

[0041] According to the embodiment of the present invention described above, the following advantageous effects are obtained.

[0042] (1) A power conversion device 1 in which a plurality of upper arm semiconductor elements 4 and a plurality of lower arm semiconductor elements 5 are connected in parallel and which includes a wiring board 13 having a plurality of wiring layers, the plurality of wiring layers including positive wiring 2 extending along the arrangement direction of the plurality of upper arm semiconductor elements 4, negative wiring 3 extending along the arrangement direction of the plurality of lower arm semiconductor elements 5, and output wiring 6 connecting the plurality of upper arm semiconductor elements 4 and the plurality of lower arm semiconductor elements 5. The positive wiring 2 and the negative wiring 3 form a first positive / negative wiring pair 13a which are respectively arranged in parallel and stacked with respect to the output wiring 6, and a second positive / negative wiring pair 13b which are respectively stacked with each other. In this way, a power conversion device that achieves both low inductance and equal inductance can be provided.

[0043] (2) The capacitor 8 is disposed on one side of the wiring board 13 and is electrically connected to the second positive and negative wiring pair 13b, and the second positive and negative wiring pair 13b is formed along an extension direction perpendicular to the one side of the wiring board 13, and the cross-sectional area in the direction perpendicular to the extension direction becomes smaller the farther away from the capacitor 8. In this way, the balance of the current densities on the DC side and AC side can be adjusted, the current densities of the wirings are made uniform, and local temperature rises in the wiring board 13 can be suppressed.

[0044] (3) The output terminal 6a is disposed on the other side of the wiring board 13 opposite to the one side and is electrically connected to the output wiring 6, and the output wiring 6 is formed along an extension direction perpendicular to the other side of the wiring board 13, and the cross-sectional area in the direction perpendicular to the extension direction becomes smaller the farther away from the output terminal 6a the wiring 6 is. In this way, the balance of the current density on the DC side and the AC side can be adjusted, the current density of each wiring can be made uniform, and local temperature rise of the wiring board 13 can be suppressed.

[0045] (4) On the outermost layer of the wiring board 13, the positive wiring 2 and the negative wiring 3 are formed in parallel, and a second capacitor is disposed between the positive wiring 2 and the negative wiring 3. This suppresses variation in wiring inductance.

[0046] (5) The drain terminals and source terminals, or collector terminals and emitter terminals of the plurality of upper arm semiconductor elements 4 and the plurality of lower arm semiconductor elements 5 are alternately arranged and connected to wiring board 13. In this manner, the configuration of the present invention can be realized in either the IGBT or MOSFET system.

[0047] (6) Wiring board 13 has a plurality of wiring layers between the arrangement of a plurality of upper arm semiconductor elements 4 and a plurality of lower arm semiconductor elements 5. This makes it possible to achieve low inductance.

[0048] (7) The wiring board 13 has through holes 9 for electrically connecting the first positive and negative wiring pair 13a and the second positive and negative wiring pair 13b, and a plurality of through holes 9 are formed along the arrangement direction of the upper arm semiconductor elements 4 and the lower arm semiconductor elements 5, and connect the positive wirings 2 and the negative wirings 3 of the first positive and negative wiring pair 13a and the second positive and negative wiring pair 13b of the wiring board 13. This reduces electrical resistance and reduces heat generation in the positive wiring 2 and the negative wiring 3.

[0049] The present invention is not limited to the above-described embodiment, and various modifications and other configurations can be combined without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiment, and includes those in which some of the configurations are omitted. [Explanation of symbols]

[0050] 1 Power conversion device 2 Positive Wiring 3 Negative Wiring 4 Upper arm semiconductor element 5 Lower arm semiconductor element 6 Output wiring 6a Output terminal 7. Ceramic Capacitors 8 Capacitors 9 Interlayer connection (through hole) 10 Control terminal 11 High voltage terminal for main circuit (lower arm semiconductor device) 11a Low voltage side terminal for main circuit (lower arm semiconductor element) 12 High voltage terminal for main circuit (upper arm semiconductor element) 12a Low voltage terminal for main circuit (upper arm semiconductor element) 13 Wiring board 13a First positive / negative wiring pair 13b Second positive / negative wiring pair

Claims

1. A power conversion device including a wiring board having a plurality of upper arm semiconductor elements and a plurality of lower arm semiconductor elements connected in parallel and a plurality of wiring layers, the plurality of wiring layers include positive wiring extending along an arrangement direction of the plurality of upper arm semiconductor elements, negative wiring extending along an arrangement direction of the plurality of lower arm semiconductor elements, and output wiring connecting the plurality of upper arm semiconductor elements and the plurality of lower arm semiconductor elements, The positive and negative wirings form a first pair of positive and negative wirings that are arranged in parallel and stacked with respect to the output wiring, and a second pair of positive and negative wirings that are stacked with each other. Power conversion equipment.

2. The power conversion device according to claim 1, a capacitor disposed on one side of the wiring board and electrically connected to the second positive and negative wiring pair; The second positive and negative wiring pairs are formed along an extension direction perpendicular to the one side of the wiring board, and the cross-sectional area in a direction perpendicular to the extension direction becomes smaller as the position is farther from the capacitor. Power conversion equipment.

3. The power conversion device according to claim 2, an output terminal disposed on the other side of the wiring board opposite to the one side and electrically connected to the output wiring; The output wiring is formed along an extension direction perpendicular to the other side of the wiring board, and a cross-sectional area in a direction perpendicular to the extension direction becomes smaller as the output wiring is positioned farther away from the output terminal. Power conversion equipment.

4. The power conversion device according to claim 1, The positive wiring and the negative wiring are formed in parallel on the outermost layer of the wiring board, A second capacitor is disposed between the positive and negative wiring. Power conversion equipment.

5. The power conversion device according to claim 1, The upper arm semiconductor elements and the lower arm semiconductor elements are connected to the wiring board with their drain terminals and source terminals, or collector terminals and emitter terminals, alternately arranged. Power conversion equipment.

6. The power conversion device according to claim 4, The wiring board has the plurality of wiring layers between the arrangement of the plurality of upper arm semiconductor elements and the arrangement of the plurality of lower arm semiconductor elements. Power conversion equipment.

7. The power conversion device according to claim 1, the wiring board has through holes for electrically connecting the first positive and negative wiring pair and the second positive and negative wiring pair, The through holes are formed in a plurality of locations along an arrangement direction of the upper arm semiconductor elements and the lower arm semiconductor elements, and connect the positive wires of the first positive / negative wiring pair and the second positive / negative wiring pair of the wiring board to each other and the negative wires of the first positive / negative wiring pair and the second positive / negative wiring pair of the wiring board to each other. Power conversion equipment.

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