Circuit device, electro-optical device and electronic apparatus

Abstract

To provide a circuit device, etc., capable of reducing power consumption of an amplifier circuit which drives a capacitive load at high speed.SOLUTION: A circuit device 100 includes: a D / A conversion circuit 111 which outputs a first voltage; a first amplifier circuit 121 consisting of a transistor of first breakdown voltage; a second amplifier circuit 122 consisting of a transistor of a second breakdown voltage lower than the first breakdown voltage; an output capacitor CQ disposed between an output terminal of the second amplifier circuit 122 and an output terminal of the first amplifier circuit 121; a first feedback capacitor Cfa disposed between an inverted input terminal of the second amplifier circuit 122 and the output terminal of the first amplifier circuit 121; and a second feedback capacitor Cfb disposed between the inverted input terminal of the second amplifier circuit 122 and a predetermined potential node. The first voltage is inputted to the first amplifier circuit 121. A second voltage lower than the first voltage is inputted to a non-inverted input terminal of the second amplifier circuit 122.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit device, an electro-optical device, an electronic device, and the like. [Background technology]

[0002] Patent Document 1 discloses a driver including a capacitive driving circuit and an amplifier circuit, which drives an electro-optical panel. After the capacitive driving circuit starts capacitive driving of the electro-optical panel, the amplifier circuit performs voltage driving to output a data voltage corresponding to grayscale data to a data voltage output terminal. As a result, the amplifier circuit compensates for the voltage drop of the data line after the source line switch of the electro-optical panel changes from off to on, thereby suppressing a decrease in accuracy of the data voltage in capacitive driving. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-80807 A Summary of the Invention [Problem to be solved by the invention]

[0004] Some types of liquid crystal panels require high voltages to drive them, and so operational amplifiers made up of high-voltage transistors are used in the driving circuits that drive such liquid crystal panels. However, because high-voltage transistors have low mobility, it is difficult to achieve both the gain and frequency response characteristics of the operational amplifier. For example, when the resolution of an electro-optic panel is increased, the driving time of one pixel becomes shorter, so it is necessary to converge to the target voltage quickly. In order to shorten the convergence time, it is necessary to increase the frequency response characteristics of the operational amplifier, but if the frequency response characteristics are increased while maintaining the gain of the operational amplifier, the power consumption of the operational amplifier increases. The above-mentioned problems arise not only when an amplifier circuit drives a liquid crystal panel, but also when an amplifier circuit drives a capacitive load. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device including: a D / A conversion circuit that outputs a first voltage by D / A converting input data; a first amplifier circuit to which the first voltage is input and which is constituted by transistors with a first withstand voltage; a second amplifier circuit to which a second voltage corresponding to the D / A converted voltage of the input data and lower than the first voltage is input to a non-inverting input terminal and which is constituted by transistors with a second withstand voltage lower than the first withstand voltage; an output capacitor arranged between an output terminal of the second amplifier circuit and an output terminal of the first amplifier circuit; a first feedback capacitor arranged between an inverting input terminal of the second amplifier circuit and an output terminal of the first amplifier circuit; and a second feedback capacitor arranged between the inverting input terminal of the second amplifier circuit and a predetermined potential node.

[0006] Another aspect of the present disclosure relates to an electro-optical device including the above-mentioned circuit device and an electro-optical panel.

[0007] Yet another aspect of the present disclosure relates to an electronic device including the above circuit device. [Brief description of the drawings]

[0008] [Figure 1] 1 shows a first configuration example of a circuit device. [Diagram 2] 5A and 5B are diagrams illustrating voltage relationships in a circuit device. [Diagram 3] 4 shows an example of a signal waveform in the first configuration example. [Figure 4] 2 shows a second configuration example of a circuit device. [Diagram 5] 3 shows a third configuration example of a circuit device. [Figure 6] 13 shows an example of a signal waveform in the third configuration example. [Figure 7] FIG. 4 is a diagram for explaining a dead zone of a first amplifier circuit. [Figure 8] 4 shows a fourth configuration example of a circuit device. [Figure 9] 5 shows a fifth example configuration of a circuit device. [Figure 10] 13 shows an example of a signal waveform in the fifth configuration example. [Figure 11] 13 shows a second detailed configuration example of the second drive circuit. [Figure 12] 13 is a first signal waveform example when a second driving circuit of the second detailed configuration example is used. [Figure 13] 13 is a second signal waveform example when a second driving circuit of the second detailed configuration example is used. [Figure 14] 13 is a third signal waveform example when the second driving circuit of the second detailed configuration example is used. [Figure 15] 13 is a fourth signal waveform example when the second driving circuit of the second detailed configuration example is used. [Figure 16] 6 shows a sixth example configuration of a circuit device. [Figure 17] 1 shows an example of the configuration of an electro-optical device. [Figure 18] 13 is a detailed configuration example of a circuit device as a driver. [Figure 19] Example of electronic device configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A preferred embodiment of the present disclosure will be described in detail below. Note that the embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the embodiment are not necessarily essential configurations.

[0010] 1. First configuration example 1 shows a first configuration example of a circuit device. The circuit device 100 includes a D / A conversion circuit 111, a first drive circuit 131, a second drive circuit 132, and a voltage dividing circuit 140. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate.

[0011] The circuit device 100 drives a capacitive load 1 connected to an output node NVQ. The capacitive load 1 includes a resistor RP and a capacitor CP connected in series between the output node NVQ and a ground node or the like. The resistor RP is a parasitic resistance of a wiring, or a resistor or the like as a circuit element. The capacitor CP is a parasitic capacitance of a wiring, or a capacitor or the like as a circuit element. The capacitive load 1 may be either inside or outside the circuit device 100. As an example, the circuit device 100 is a driver that drives a data line of an electro-optical panel. For example, the input resistance of the electro-optical panel corresponds to the resistor RP, and the parasitic capacitance of the data line and the pixel capacitance correspond to the capacitance CP.

[0012] The D / A conversion circuit 111 performs D / A conversion on the input data DI and outputs the result as a first voltage DAH to an output node NDAH. The D / A conversion circuit 111 includes, for example, a ladder resistor circuit that generates a plurality of voltages corresponding to each value of the input data DI, and a selection circuit that selects a voltage corresponding to the input data DI from the plurality of voltages. The voltage selected by the selection circuit is output as the first voltage DAH. However, the configuration of the D / A conversion circuit 111 is not limited to this.

[0013] The first driving circuit 131 amplifies the first voltage DAH and outputs the amplified voltage to the output node NVQ. The first driving circuit 131 includes a first amplifier circuit 121 which is an operational amplifier. The first driving circuit 131 is, for example, a voltage follower circuit. That is, the inverting input terminal of the first amplifier circuit 121 is connected to the output terminal, and the output terminal is connected to the output node NVQ. The non-inverting input terminal of the first amplifier circuit 121 is connected to the output node NDAH of the D / A conversion circuit 111.

[0014] The voltage dividing circuit 140 divides the first voltage DAH and outputs the result as a second voltage DAL to the output node NDAL. That is, the second voltage DAL is lower than the first voltage DAH. The voltage dividing ratio of the voltage dividing circuit 140 is the inverse of the gain of the second driving circuit 132. The voltage dividing circuit 140 includes, for example, a first voltage dividing capacitor Cda and a second voltage dividing capacitor Cdb. One end of the first voltage dividing capacitor Cda is connected to the output node NDAH of the D / A conversion circuit 111, and the other end is connected to the output node NDAL of the voltage dividing circuit 140. One end of the second voltage dividing capacitor Cdb is connected to the output node NDAL of the voltage dividing circuit 140, and the other end is connected to a low potential side power supply node. The low potential side power supply node is a node to which a low potential side power supply voltage VSS is supplied from a low potential side power supply. The other end of the second voltage dividing capacitor Cdb may be connected to a predetermined potential node to which a constant potential is supplied.

[0015] The second driving circuit 132 amplifies the second voltage DAL and outputs the amplified voltage to an output node NVQ. The second driving circuit 132 includes a second amplifier circuit 122 which is an operational amplifier, a switch SWLV, a first feedback capacitor Cfa, a second feedback capacitor Cfb, and an output capacitor CQ.

[0016] A non-inverting input terminal of the second amplifier circuit 122 is connected to an output node NDAL of the voltage divider circuit 140. A switch SWLV controlled to be turned on or off by an enable signal LVEN is provided between the output terminal of the second amplifier circuit 122 and the output node NLVQ. When the switch SWLV is off, the output node NLVQ is set to a high impedance state. Note that the switch SWLV may not be provided and the second amplifier circuit 122 may switch the output to an output state or a high impedance state according to the enable signal LVEN. An inverting input terminal of the second amplifier circuit 122 is connected to a feedback node NVFB of a feedback voltage VFB.

[0017] One end of the output capacitor CQ is connected to the output node NVQ of the second amplifier circuit 122, and the other end is connected to the output node NVQ. One end of the first feedback capacitor Cfa is connected to the feedback node NVFB, and the other end is connected to the output node NVQ. One end of the second feedback capacitor Cfb is connected to the feedback node NVFB, and the other end is connected to the node of the low-potential power supply voltage VSS. The other end of the second feedback capacitor Cfb may be connected to a predetermined potential node to which a constant potential is supplied. The first feedback capacitor Cfa and the second feedback capacitor Cfb divide the output voltage VQ of the output node NVQ, and output the result as the feedback voltage VFB. As a result, the gain of the second drive circuit 132 is the reciprocal of the voltage division ratio of the feedback capacitor. The voltage division ratio of the feedback capacitor is the same as the voltage division ratio of the voltage division circuit 140. That is, the capacitance ratio is Cda:Cdb=Cfa:Cfb.

[0018] The circuit device 100 is composed of circuit elements of a high-voltage process and circuit elements of a low-voltage process. The high-voltage is also called a first withstand voltage, and the low-voltage is also called a second withstand voltage. The second withstand voltage may be a lower withstand voltage than the first withstand voltage. As an example, the withstand voltage of the low-voltage process is about 1 / 2 to 1 / 10 of the withstand voltage of the high-voltage process, but is not limited thereto. The source-drain distance in a transistor of a high-voltage process is longer than the source-drain distance in a transistor of a low-voltage process. Or, the thickness of the gate insulating film in a transistor of a high-voltage process is thicker than the thickness of the gate insulating film in a transistor of a low-voltage process.

[0019] The D / A conversion circuit 111 and the first driving circuit 131 operate on a first high-potential power supply voltage VDH and are made of circuit elements of a high-voltage process. When the D / A conversion circuit 111 is made of, for example, a ladder resistor circuit and a selection circuit, the selection circuit is made of transistors of a high-voltage process. The transistors making up the first amplifier circuit 121 are transistors of a high-voltage process. The second driving circuit 132 operates on a second high-potential power supply voltage VDL lower than the first high-potential power supply voltage VDH and are made of circuit elements of a low-voltage process. VDL is about 1 / 2 to 1 / 10 of VDH, but is not limited thereto. It is sufficient that VDH is a power supply voltage compatible with a high-voltage process and VDL is a power supply voltage compatible with a low-voltage process. The transistors making up the second amplifier circuit 122 are transistors of a low-voltage process. The second amplifier circuit 122 is DC-isolated from the high-voltage circuit by a capacitor, and can be made of circuit elements of a low-voltage process.

[0020] The input data DI and the enable signal LVEN are output, for example, from the control circuit 40 in Fig. 18. However, although Fig. 18 shows an example in which the circuit device 100 is a driver, the circuit device 100 in Fig. 1 is not limited to a driver.

[0021] 2 is a diagram for explaining the voltage relationships in the circuit device. Here, an example is shown in which the input data DI is 11 bits, VDH is 15 V, VDL is 1.8 V, the amplitude of the output voltage VQ is 10 V, and the gain of the second driving circuit 132 is 10.

[0022] The D / A conversion circuit 111 converts input data DI from 0 to 2047 into a first voltage DAH in the voltage range of 10 V. Here, the lower limit of the first voltage DAH is set to 2.5 V and the upper limit is set to 12.5 V. Since the first drive circuit 131 is a voltage follower circuit with a gain of 1, the voltage output by the first drive circuit 131 is the same as the first voltage DAH.

[0023] The voltage divider circuit 140 divides the voltage range of the first voltage DAH by 10, and outputs the second voltage DAL with a voltage range of 1V. Here, an example is shown in which the voltage itself is divided by 10, and the lower limit of the second voltage DAL is 0.25V and the upper limit is 1.25V. However, since DC is cut by the capacitor, it is sufficient that the voltage range is 1 / 10, and the second voltage DAL may have a DC offset. For example, the lower limit of the second voltage DAL may be 0.4V and the upper limit may be 1.4V.

[0024] The second drive circuit 132 amplifies the voltage range of the second voltage DAL by 10 times and outputs a voltage with a voltage range of 10 V. Here, an example is shown in which the voltage itself is multiplied by 10, with a lower limit of 2.5 V and an upper limit of 12.5 V. The first drive circuit 131 and the second drive circuit 132 output the same voltage in response to the input data DI, which becomes the output voltage VQ.

[0025] 3 shows an example of signal waveforms in the first configuration example. At time ta, the value of the input data DI changes. Here, an example is shown in which the input data DI changes in a direction in which the output voltage VQ increases. Also, at time tb after time ta, the enable signal LVEN turns the switch SWLV of the output of the second amplifier circuit 122 from off to on. The interval between time ta and time tb can be set arbitrarily, and is set, for example, in a register or non-volatile memory (not shown). The interval between time ta and time tb may be determined in advance by circuit simulation, sample evaluation, or the like.

[0026] The first voltage DAH and the second voltage DAL start to change from time ta and gradually approach the target voltage corresponding to the input data DI. The first amplifier circuit 121 increases the output voltage VQ in response to the rise of the first voltage DAH. The first amplifier circuit 121 changes the output in response to the voltage difference of the differential input, so the output voltage VQ rises with a slight delay from the rise of the first voltage DAH. When the first voltage DAH approaches the target voltage and the rise becomes gentle, the output voltage VQ exceeds the first voltage DAH and overshoots. When the voltage difference of the differential input becomes a certain level or more due to the overshoot, the first amplifier circuit 121 lowers the output voltage VQ in response. As a result, the output voltage VQ falls below the first voltage DAH and undershoots. Such repeated overshooting and undershooting is called ringing, and the ringing converges and the output voltage VQ converges to the target voltage.

[0027] The waveform of the voltage VQ_nonLV shows the waveform of the output voltage VQ when the switch SWLV of the output of the second amplifier circuit 122 remains off after time tb. Since the low-voltage second amplifier circuit 122 does not function, only the high-voltage first amplifier circuit 121 converges the ringing. Since the mobility of a transistor made with a high-voltage process is smaller than that of a transistor made with a low-voltage process, it takes time to converge to the target voltage.

[0028] In this embodiment, the switch SWLV of the output of the second amplifier circuit 122 is turned on at time tb. After time tb, the second amplifier circuit 122, which has a low breakdown voltage and a high transistor mobility, causes the ringing to converge. This speeds up the convergence of the output voltage VQ to the target voltage.

[0029] The time tb is set, for example, within the overshoot period when the output voltage VQ exceeds the first voltage DAH for the first time. For example, the time tb is set near the peak of the output voltage VQ within the overshoot period. When the output voltage VQ changes downward, the ringing starts with an undershoot. Therefore, the time tb is set, for example, within the undershoot period when the output voltage VQ falls below the first voltage DAH for the first time. The reason for delaying the enabling of the second amplifier circuit 122 from the change in the input data DI is as follows.

[0030] Suppose that the capacitive load 1 is driven only by the low-voltage second amplifier circuit 122 from time ta. At this time, the capacitance CP of the capacitive load 1 must be charged only by the second amplifier circuit 122. However, since the output of the second amplifier circuit 122 is coupled to the output node NVQ by the output capacitor CQ, it is difficult to greatly change the output voltage VQ. If the capacitance of the feedback capacitor is ignored for simplicity, the change in the output voltage VQ is determined by the ratio of CQ:CP and the change in the output voltage LVQ of the second amplifier circuit 122. Since the low-voltage second amplifier circuit 122 cannot greatly change the output voltage LVQ, it is necessary to increase CQ, which results in a large circuit area. For example, if the second amplifier circuit 122 moves its output voltage LVQ by 1 V and thereby tries to move the output voltage VQ by 10 V, CQ needs to be about 10 times CP.

[0031] In this embodiment, the high-voltage first amplifier circuit 121 connected to the output node NVQ supplies charge to the capacitive load 1 to greatly change the output voltage VQ. Then, the low-voltage second amplifier circuit 122 starts driving after the output voltage VQ approaches the target voltage, so that the second amplifier circuit 122 only needs to supply a small charge and can quickly converge ringing.

[0032] In this embodiment, the circuit device 100 includes a D / A conversion circuit 111, a first amplifier circuit 121, a second amplifier circuit 122, an output capacitor CQ, a first feedback capacitor Cfa, and a second feedback capacitor Cfb. The D / A conversion circuit 111 outputs a first voltage DAH by D / A converting the input data DI. The first voltage DAH is input to the first amplifier circuit 121. The first amplifier circuit 121 is composed of transistors with a first withstand voltage. A second voltage DAL corresponding to the D / A conversion voltage of the input data DI and lower than the first voltage DAH is input to a non-inverting input terminal of the second amplifier circuit 122. The second amplifier circuit 122 is composed of transistors with a second withstand voltage lower than the first withstand voltage. The output capacitor CQ is disposed between the output terminal of the second amplifier circuit 122 and the output terminal of the first amplifier circuit 121. The first feedback capacitor Cfa is arranged between the inverting input terminal of the second amplifier circuit 122 and the output terminal of the first amplifier circuit 121. The second feedback capacitor Cfb is arranged between the inverting input terminal of the second amplifier circuit 122 and a predetermined potential node.

[0033] According to this embodiment, since the second withstand voltage is lower than the first withstand voltage, the mobility of the transistor of the second withstand voltage constituting the second amplifier circuit 122 is higher than the mobility of the transistor of the first withstand voltage constituting the first amplifier circuit 121. As a result, the second amplifier circuit 122 has a higher response frequency characteristic than the first amplifier circuit 121, and it is possible to quickly converge the ringing of the output voltage VQ when driving the capacitive load 1. In addition, since the second amplifier circuit 122 is DC-isolated from the output node NVQ by the output capacitor CQ or the like, the output voltage VQ cannot be moved significantly. In this respect, the first amplifier circuit 121 can change the output voltage VQ significantly. In this way, the first amplifier circuit 121, which has a low response frequency characteristic but moves the voltage significantly, cooperates with the second amplifier circuit 122, which does not move the voltage significantly but has a high response frequency characteristic, to drive the capacitive load 1 at high speed.

[0034] According to this embodiment, the convergence time of ringing is shortened by combining two amplifier circuits, so there is no need to improve the frequency response characteristics of the high-voltage first amplifier circuit 121. As described above, there is a problem that power consumption increases when attempting to achieve both the gain and frequency response characteristics of an amplifier circuit, but according to this embodiment, power consumption can be reduced.

[0035] In this embodiment, the second amplifier circuit 122 is set from the disabled state to the enabled state with a delay from the change timing of the input data DI. In the examples of Figures 1 and 3, the switch SWLV is turned from off to on at time tb, and the second amplifier circuit 122 is set from the disabled state to the enabled state.

[0036] According to this embodiment, it is possible to set the second amplifier circuit 122 in a disabled state until the output voltage VQ approaches the target voltage, and set the second amplifier circuit 122 in an enabled state when the output voltage VQ approaches the target voltage. As a result, when the output voltage VQ approaches the target voltage, the low-withstand voltage second amplifier circuit 122 starts driving, so that the second amplifier circuit 122 only needs to supply a small charge, and ringing can be quickly converged.

[0037] In this embodiment, the circuit device 100 further includes a first voltage dividing capacitor Cda and a second voltage dividing capacitor Cdb. The first voltage dividing capacitor Cda is disposed between the output node NDAH of the D / A conversion circuit 111 and the non-inverting input terminal of the second amplifier circuit 122. The second voltage dividing capacitor Cdb is disposed between the non-inverting input terminal of the second amplifier circuit 122 and a predetermined potential node.

[0038] According to this embodiment, the first voltage dividing capacitor Cda and the second voltage dividing capacitor Cdb divide the first voltage DAH, and the result is input as the second voltage DAL to the non-inverting input terminal of the second amplifier circuit 122. As a result, the second voltage DAL, which corresponds to the D / A converted voltage of the input data DI and is lower than the first voltage DAH, is input to the non-inverting input terminal of the second amplifier circuit 122.

[0039] In this embodiment, the voltage division ratio between the first voltage division capacitor Cda and the second voltage division capacitor Cdb is the same as the voltage division ratio between the first feedback capacitor Cfa and the second feedback capacitor Cfb.

[0040] According to this embodiment, the gain of the second drive circuit 132, which is composed of the second amplifier circuit 122, the output capacitor CQ, the first feedback capacitor Cfa, and the second feedback capacitor Cfb, is the reciprocal of the voltage division ratio of the first feedback capacitor Cfa and the second feedback capacitor Cfb. As a result, the second voltage DAL is increased by the reciprocal of the voltage division ratio of the first voltage division capacitor Cda and the second voltage division capacitor Cdb, and a voltage equal to the first voltage DAH is output to the output node NVQ.

[0041] 2. Second and third configuration examples 4 shows a second configuration example of the circuit device. The circuit device 100 includes a D / A conversion circuit 111, a second D / A conversion circuit 112, a first drive circuit 131, and a second drive circuit 132. Components already described are given the same reference numerals, and descriptions of those components will be omitted.

[0042] The second D / A conversion circuit 112 performs D / A conversion on the input data DI and outputs the result as a second voltage DAL to the output node NDAL. The second D / A conversion circuit 112 operates on a second high potential power supply voltage VDL. The second D / A conversion circuit 112 includes, for example, a ladder resistor circuit that generates a plurality of voltages corresponding to each value of the input data DI, and a selection circuit that selects a voltage corresponding to the input data DI from the plurality of voltages. The voltage selected by the selection circuit is output as the second voltage DAL. However, the configuration of the second D / A conversion circuit 112 is not limited to this. The signal waveform is the same as that in FIG. 3.

[0043] 5 shows a third configuration example of the circuit device. The circuit device 100 includes a D / A conversion circuit 111, a second D / A conversion circuit 112, a first drive circuit 131, and a second drive circuit 132. Components already described are given the same reference numerals, and descriptions of those components will be omitted.

[0044] The number of bits of the input data is 11, and the input data is represented as DI[10:0]. The D / A conversion circuit 111 D / A converts the upper 8 bits DI[10:3] of the input data DI[10:0], and outputs the result as a first voltage DAH. The second D / A conversion circuit 112 D / A converts the 11-bit input data DI[10:0], and outputs the result as a second voltage DAL. The number of bits of the input data may be n, where n is an integer equal to or greater than 2. The D / A conversion circuit 111 may D / A convert the upper m bits of the n-bit input data, where m is an integer equal to or greater than 1 and equal to or less than n-1.

[0045] Figure 6 shows an example of signal waveforms in the third configuration example. Note that the (11bit) attached to the signal name means that the signal is obtained when 11-bit input data DI is D / A converted, and (8bit) means that the signal is obtained when the upper 8 bits of the input data are D / A converted. DAL(8bit) is written for reference, and the waveform of the second voltage DAL in Figure 5 is DAL(11bit).

[0046] The first voltage DAH is a voltage obtained by D / A converting the upper 8 bits of the input data. Therefore, there is a difference ΔV corresponding to the lower 3 bits between the voltage to which the first voltage DAH converges and the target voltage corresponding to the 11-bit input data. A difference ΔV also occurs in the voltage output by the first amplifier circuit 121, but the difference Δ is eliminated by the second amplifier circuit 122 supplying charges. That is, the second voltage DAL is a voltage obtained by D / A converting the 11-bit input data. Therefore, the second drive circuit 132 tries to output a target voltage corresponding to the 11-bit input data. As a result, the output voltage VQ approaches the target voltage.

[0047] The D / A conversion circuit 111 has a large circuit area because it uses a high-voltage process. In this embodiment, the circuit area of ​​the D / A conversion circuit 111 can be reduced by making the number of bits of the D / A conversion circuit 111 smaller than the number of bits of the second D / A conversion circuit 112. The voltage difference ΔV caused by reducing the number of bits can be eliminated by the circuit on the low-voltage side. Since the second D / A conversion circuit 112 uses a low-voltage process, it can be realized with a relatively small circuit area even if the number of bits is large.

[0048] FIG. 7 is a diagram for explaining the dead zone of the first amplifier circuit. The first amplifier circuit 121 may have a dead zone. The dead zone is a range of differential input voltages in which the current capability of the output of the amplifier circuit is zero. The center of the dead zone is when the differential input voltage is zero, which corresponds to when the first voltage DAH and the output voltage VQ are the same. The least significant bit of the upper 8 bits DI[10:3] of the input data is DI[3]. This is the LSB of the upper 8 bits DI[10:3]. The width WFK of the dead zone is wider than the change width of the first voltage DAH when this LSB changes.

[0049] If the first amplifier circuit 121 did not have a dead zone, even if the second drive circuit 132 tried to output a target voltage, the first drive circuit 131 would output a voltage different from the target voltage, which could hinder the asymptotic approach to the target voltage. By having the first amplifier circuit 121 have a dead zone of width WFK, the first drive circuit 131 can mainly handle large voltage changes for the upper 8 bits. Then, the second drive circuit 132 handles voltage changes for the lower 3 bits, and the output of the first drive circuit 131 and the output of the second drive circuit 132 do not interfere with each other.

[0050] In this embodiment, the circuit device 100 includes a second D / A conversion circuit 112. The second D / A conversion circuit 112 outputs a second voltage DAL by D / A conversion of the input data DI. The D / A conversion circuit 111 is composed of transistors with a first voltage resistance. The second D / A conversion circuit 112 is composed of transistors with a second voltage resistance.

[0051] According to this embodiment, the second D / A conversion circuit 112 D / A converts the input data DI, and the result is input as a second voltage DAL to the non-inverting input terminal of the second amplifier circuit 122. As a result, the second voltage DAL, which corresponds to the D / A converted voltage of the input data DI and is lower than the first voltage DAH, is input to the non-inverting input terminal of the second amplifier circuit 122.

[0052] In this embodiment, the D / A conversion circuit 111 performs D / A conversion on the upper m bits of the n-bit input data DI[n-1:0]. n is an integer equal to or greater than 1. m is an integer equal to or greater than 1 and equal to or less than n-1. The second D / A conversion circuit 112 performs D / A conversion on the n-bit input data DI[n-1:0].

[0053] According to this embodiment, the number of bits m of the D / A conversion circuit 111 configured with high-voltage transistors is smaller than the number of bits n of the second D / A conversion circuit 112 configured with low-voltage transistors. This makes it possible to reduce the number of bits of the D / A conversion circuit 111, which has a large transistor size, and save the circuit area. In addition, since the second D / A conversion circuit 112, which has a small transistor size, has an n-bit precision, an output voltage VQ corresponding to n-bit input data can be obtained.

[0054] Furthermore, in this embodiment, the first amplifier circuit 121 has a dead band wider than the variation range of the first voltage DAH corresponding to the LSB of the upper m bits of the n-bit input data DI[n-1:0].

[0055] According to this embodiment, the dead zone is wider than the variation width of the first voltage DAH corresponding to the LSB of the upper m bits, so that the large voltage variation for the upper m bits can be mainly handled by the first amplifier circuit 121. Also, the voltage variation for the lower nm bits can be handled by the second amplifier circuit 122, and the driving by the first amplifier circuit 121 and the driving by the second amplifier circuit 122 do not interfere with each other.

[0056] 3. Fourth and fifth configuration examples 8 shows a fourth configuration example of a circuit device. The circuit device 100 includes a D / A conversion circuit 111, a voltage dividing circuit 140, a first drive circuit 131, a second drive circuit 132, first to third adjustment capacitors CJ1 to CJ3, and an adjustment capacitor drive circuit 150. Components that have already been described are given the same reference numerals, and descriptions of those components will be omitted.

[0057] The D / A conversion circuit 111 D / A converts the upper 8 bits DI[10:3] of the input data DI[10:0] and outputs the result as a first voltage DAH. The number of bits of the input data may be n, where n is an integer equal to or greater than 2. The D / A conversion circuit 111 may D / A convert the upper q bits of the n-bit input data, where q is an integer equal to or greater than 1 and equal to or less than n-1.

[0058] One end of the first adjustment capacitor CJ1 is connected to the non-inverting input terminal of the second amplifier circuit 122. The adjustment capacitor driving circuit 150 outputs a first voltage VJ1 corresponding to the first bit DI[0] of the input data to the other end of the first adjustment capacitor CJ1. When DI[0] is at a low level, VJ1 is the low potential side power supply voltage VSS, and when DI[0] is at a high level, VJ1 is the second high potential side power supply voltage VDL. Similarly, one ends of the second adjustment capacitor CJ2 and the third adjustment capacitor CJ3 are connected to the non-inverting input terminal of the second amplifier circuit 122. The adjustment capacitor driving circuit 150 outputs a second voltage VJ2 and a third voltage VJ3 corresponding to the second bit DI[1] and the third bit DI[2] of the input data to the other ends of the second adjustment capacitor CJ2 and the third adjustment capacitor CJ3. When DI[1] and DI[2] are at low level, VJ2 and VJ3 are the low potential power supply voltage VSS, and when DI[1] and DI[2] are at high level, VJ2 and VJ3 are the second high potential power supply voltage VDL. The adjustment capacitor driving circuit 150 includes, for example, a buffer circuit that buffers the input first to third bits and outputs them as the first to third voltages VJ1 to VJ3.

[0059] The upper 8 bits of the input data DI[10:0] are converted to the second voltage DAL by the voltage divider circuit 140 dividing the first voltage DAH. When the lower 3 bits cause the first to third voltages VJ1 to VJ3 to change, charge redistribution occurs between the first to third adjustment capacitors CJ1 to CJ3 and the first and second voltage dividing capacitors Cda and Cdb, causing the second voltage DAL to change. The capacitance values ​​of the first to third adjustment capacitors CJ1 to CJ3 are set so that the gradation of the second voltage DAL for the upper 8 bits and the gradation of the second voltage DAL for the lower 3 bits are linear. The signal waveforms are the same as those in FIG. 6.

[0060] An example of the capacitance values ​​of CJ1 to CJ3 is shown below. The amplitude of the first voltage DAH is 10V, the amplitude of the second voltage DAL is 1V, and VDL=1.8V. Since the 11-bit input data has 2048 gradations, the voltage change per LSB at 10V amplitude is about 5mV. Since the lower 3 bits have 8 gradations, CJ1 to CJ3 as a whole only need to cause a voltage change of 5mV×8=40mV. If CJ=CJ1+CJ2+CJ3, then 1.8V×CJ / (CJ+Cda+Cdb)=40mV. Rearranging this, we get 44×CJ=Cda+Cdb. Since Cdb≒10×Cda from the voltage division ratio, CJ≒1 / 4×Cda. If we assume that Cda=2pF, then CJ=0.5pF. This is divided by 8 to get 62.5fF, which is the capacitance value for one tone. Therefore, CJ1 ≒ 62.5fF, CJ2 ≒ 125fF, and CJ3 ≒ 250fF. However, the above is just an example, and the capacitance value of the adjustment capacitor is set including the parasitic capacitance.

[0061] In this embodiment, the circuit device 100 includes first to q-th adjustment capacitors CJ1 to CJq and an adjustment capacitor driving circuit 150. One ends of the first to q-th adjustment capacitors CJ1 to CJq are connected to a non-inverting input terminal of a second amplifier circuit 122. The adjustment capacitor driving circuit 150 outputs first to q-th voltages VJ1 to VJq corresponding to the lower q bits of the n-bit input data DI[n-1:0] to the other ends of the first to q-th adjustment capacitors CJ1 to CJq. n is an integer equal to or greater than 1. q is an integer equal to or greater than 1 and equal to or less than n-1. The D / A conversion circuit 111 D / A converts the upper nq bits of the n-bit input data DI[n-1:0].

[0062] According to this embodiment, the D / A conversion circuit 111 performs D / A conversion on the upper nq bits of the input data DI[n-1:0], and the voltage division circuit 140 divides the first voltage DAH. As a result, a second voltage DAL corresponding to the upper nq bits of the input data DI[n-1:0] is output. In addition, the adjustment capacitor driving circuit 150 drives the other ends of the first to q-th adjustment capacitors CJ1 to CJq based on the lower q bits of the input data DI[n-1:0]. As a result, a second voltage DAL corresponding to the lower q bits of the input data DI[n-1:0] is output. By adding up the above, a second voltage DAL corresponding to the n-bit input data DI[n-1:0] is output. As a result, an output voltage VQ corresponding to the n-bit input data DI[n-1:0] is obtained.

[0063] 9 shows a fifth configuration example of a circuit device. The circuit device 100 includes a D / A conversion circuit 111, a voltage dividing circuit 140, a first drive circuit 131, a second drive circuit 132, first to third adjustment capacitors CJ1 to CJ3, and an adjustment capacitor drive circuit 150. Components that have already been described are given the same reference numerals, and descriptions of those components will be omitted.

[0064] One end of the first adjustment capacitor CJ1 is connected to the feedback node NVFB. The logic of the first voltage VJ1 is the opposite to that of the fourth configuration example. That is, when DI[0] is at a low level, VJ1 is the second high potential side power supply voltage VDL, and when DI[0] is at a high level, VJ1 is the low potential side power supply voltage VSS. Similarly, one end of the second adjustment capacitor CJ2 and the third adjustment capacitor CJ3 is connected to the feedback node NVFB. When DI[1] and DI[2] are at a low level, VJ2 and VJ3 are the second high potential side power supply voltage VDL, and when DI[1] and DI[2] are at a high level, VJ2 and VJ3 are the low potential side power supply voltage VSS. The adjustment capacitor driving circuit 150 includes, for example, an inverter that logically inverts the first to third bits that are input, and a buffer circuit that buffers the output of the inverter and outputs it as the first to third voltages VJ1 to VJ3. The method for determining the capacitance values ​​of CJ1 to CJ3 is the same as in the fourth configuration example, except that the capacitors taken into account in calculating the capacitance values ​​are the first feedback capacitor Cfa and the second feedback capacitor Cfb.

[0065] 10 shows an example of signal waveforms in the fifth configuration example. Here, an example is shown in which the time tg at which DI[2:0] changes is delayed from the time ta at which DI[10:3] changes, but DI[2:0] and DI[10:3] may change simultaneously.

[0066] The upper 8 bits of the input data DI[10:0] are converted to a second voltage DAL by the voltage divider circuit 140 dividing the first voltage DAH. When the first to third voltages VJ1 to VJ3 change due to the lower 3 bits, charge redistribution occurs between the first to third adjustment capacitors CJ1 to CJ3 and the first feedback capacitor Cfa and second feedback capacitor Cfb, and the feedback voltage VFB changes. The second amplifier circuit 122 changes the output voltage VQ, returning the feedback voltage VFB to the second voltage DAL, and the output voltage VQ becomes a target voltage corresponding to the 11-bit input data DI[10:0].

[0067] In this embodiment, the circuit device 100 includes first to q-th adjustment capacitors CJ1 to CJq and an adjustment capacitor driving circuit 150. One ends of the first to q-th adjustment capacitors CJ1 to CJq are connected to an inverting input terminal of a second amplifier circuit 122. The adjustment capacitor driving circuit 150 outputs first to q-th voltages VJ1 to VJq corresponding to inverted bits of the lower q bits of the n-bit input data DI[n-1:0] to the other ends of the first to q-th adjustment capacitors CJ1 to CJq. n is an integer equal to or greater than 1. q is an integer equal to or greater than 1 and equal to or less than n-1. The D / A conversion circuit 111 D / A converts the upper nq bits of the n-bit input data DI[n-1:0].

[0068] According to this embodiment, the D / A conversion circuit 111 performs D / A conversion on the upper nq bits of the input data DI[n-1:0], and the voltage division circuit 140 divides the first voltage DAH. As a result, a second voltage DAL corresponding to the upper nq bits of the input data DI[n-1:0] is output. In addition, the adjustment capacitor driving circuit 150 drives the other ends of the first to q-th adjustment capacitors CJ1 to CJq based on the inverted bits of the lower q bits of the input data DI[n-1:0]. As a result, a second voltage DAL corresponding to the lower q bits of the input data DI[n-1:0] is output to the inverted input terminal of the second amplifier circuit 122. As a result, a voltage difference occurs at the differential input of the second amplifier circuit 122, and the second amplifier circuit 122 eliminates this difference, thereby changing the output voltage VQ. This change corresponds to the change in the first voltage DAH corresponding to the lower q bits of the input data DI[n-1:0]. By adding up the above, an output voltage VQ corresponding to the n-bit input data DI[n-1:0] is obtained.

[0069] 4. Second detailed configuration example of the second drive circuit Fig. 11 shows a second detailed configuration example of the second driving circuit. The configuration of Fig. 11 is applicable to any of the first to fifth configuration examples and a sixth configuration example described later of the circuit device 100. The second driving circuit 132 includes a second amplifier circuit 122, a switch SWLV, an output capacitor CQ, a first feedback capacitor Cfa, a second feedback capacitor Cfb, switches SWVD, SWVS, SWVM, resistors RM1, RM2, and an operational amplifier OPM.

[0070] Resistors RM1 and RM2 divide the second high-potential side power supply voltage VDL. A voltage follower circuit using an operational amplifier OPM buffers the divided voltage and outputs it to a node NVM as an intermediate voltage VM. The intermediate voltage VM is the center voltage of the range of the second voltage DAL. In the example of FIG. 2, VM=0.75V, or VM=0.9V when the range of the second voltage DAL is 0.4 to 1.4V.

[0071] One end of the switch SWVD is connected to a second high potential side power supply node, and the other end is connected to an output node NLVQ of the second amplifier circuit 122. The second high potential side power supply node is a node to which a second high potential side power supply voltage VDL is supplied from the second high potential side power supply. One end of the switch SWVS is connected to a low potential side power supply node, and the other end is connected to an output node NLVQ of the second amplifier circuit 122. The low potential side power supply node is a node to which a low potential side power supply voltage VSS is supplied from the low potential side power supply. One end of the switch SWVM is connected to a node NVM, and the other end is connected to an output node NLVQ of the second amplifier circuit 122.

[0072] The switch SWVD is controlled to be on or off by a control signal VDEN. The switch SWVS is controlled to be on or off by a control signal VSEN. The switch SWVM is controlled to be on or off by a control signal VMEN. The control signals VDEN, VSEN, and VMEN are output from, for example, the control circuit 40 in FIG. 18. However, although FIG. 18 shows an example in which the circuit device 100 is a driver, the circuit device 100 to which the second drive circuit 132 in FIG. 11 is applied is not limited to a driver.

[0073] Hereinafter, a signal waveform example will be described when the second driving circuit 132 in Fig. 11 is applied to the circuit device 100 in Fig. 1. Fig. 12 shows a first signal waveform example when the second driving circuit in the second detailed configuration example is used. The switches SWVD and SWVM are always off.

[0074] VQ_nonSW is the waveform of the output voltage VQ when the switch SWVS is always on, and is almost the same as VQ_nonLV in FIG. 3. When the switch SWVS is always on, the output node NLVQ of the second amplifier circuit 122 is fixed to the low potential side power supply voltage VSS, so the second drive circuit 132 does not function. For this reason, VQ_nonSW largely undershoots after overshooting. In order for VQ_nonSW to converge to the target voltage, the capacitance CP of the capacitive load 1 needs to be charged to the target voltage, which takes time about the time constant of the resistance RP and the capacitance CP. If VQ_nonSW largely undershoots during this charging, the capacitance CP will be discharged, which increases the charging time of the capacitance CP and makes the convergence time of VQ_nonSW longer.

[0075] In the waveform example of Fig. 12, the switch SWVS is turned from on to off at time tb by the control signal VSEN. The output voltage LVQ of the second amplifier circuit 122 is set to the low potential side power supply voltage VSS by the switch SWVS from time ta to time tb. When the switch SWVS is turned off at time tb, the second amplifier circuit 122 raises the output voltage LVQ from the low potential side power supply voltage VSS. This acts in the direction of raising the output voltage VQ, so the speed at which the output voltage VQ drops from the peak of the overshoot is slower than that of VQ_nonSW. As a result, the undershoot of the output voltage VQ is smaller than that of VQ_nonSW, and the convergence of the output voltage VQ is faster.

[0076] 13 shows a second signal waveform example when the second drive circuit of the second detailed configuration example is used. The switches SWVS and SWVM are always off.

[0077] VQ_nonSW is the waveform of the output voltage VQ when the switch SWVD is always on, and is almost the same as VQ_nonSW in Fig. 12. When the switch SWVD is always on, the output node NLVQ of the second amplifier circuit 122 is fixed to the second high potential side power supply voltage VDL, so the second drive circuit 132 does not function. For this reason, the initial overshoot of VQ_nonSW becomes large, and the convergence time of VQ_nonSW becomes long.

[0078] In the waveform example of FIG. 13, the switch SWVD is turned from on to off at time tb by the control signal VDEN. The output voltage LVQ of the second amplifier circuit 122 is set to the second high potential side power supply voltage VDL by the switch SWVD from time ta to time tb. When the switch SWVD is turned off at time tb, the second amplifier circuit 122 reduces the output voltage LVQ from the second high potential side power supply voltage VDL. This acts in the direction of reducing the output voltage VQ, so that the initial overshoot of the output voltage VQ becomes smaller than that of VQ_nonSW. This speeds up the convergence of the output voltage VQ. In this waveform example, the time tb is set to, for example, the time from when VQ_nonSW first exceeds the first voltage DAH to when it reaches its peak.

[0079] Fig. 14 shows a third signal waveform example when the second drive circuit of the second detailed configuration example is used. The switches SWVS and SWVD are always off. Note that Fig. 14 shows an example in which the target voltage of the second voltage DAL is the same as the intermediate voltage VM, but the target voltage of the second voltage DAL may be different from the intermediate voltage VM.

[0080] VQ_nonSW is the waveform of the output voltage VQ when the switch SWVM is always on, and is almost the same as VQ_nonSW in Fig. 12. When the switch SWVM is always on, the output node NLVQ of the second amplifier circuit 122 is fixed to the intermediate voltage VM, so the second drive circuit 132 does not function. This increases the convergence time of VQ_nonSW.

[0081] In the waveform example of FIG. 14, the switch SWVM is turned from on to off at time tb by the control signal VMEN. In this waveform example, the time tb is set, for example, to the time immediately after VQ_nonSW first exceeds the first voltage DAH. The output voltage LVQ of the second amplifier circuit 122 is set to the intermediate voltage VM by the switch SWVM from time ta to time tb. When the switch SWVM is turned off at time tb, the second amplifier circuit 122 is able to change the output voltage LVQ. Since the second amplifier circuit 122 changes the output voltage LVQ from the intermediate voltage VM, it is possible to increase or decrease the output voltage VQ. In this waveform example, the differential input voltage of the second amplifier circuit 122 is small at time tb, so the second amplifier circuit 122 does not react. When the output voltage VQ becomes somewhat high due to overshoot and the differential input voltage of the second amplifier circuit 122 becomes somewhat large, the second amplifier circuit 122 responds and causes the output voltage VQ to converge. The second amplifier circuit 122 responds faster than the first amplifier circuit 121, and therefore the output voltage VQ converges faster than VQ_nonSW.

[0082] Fig. 15 is a fourth signal waveform example when the second drive circuit of the second detailed configuration example is used. The switches SWVS and SWVD are always off. Note that, although Fig. 14 shows an example in which the target voltage of the second voltage DAL is the same as the intermediate voltage VM, the target voltage of the second voltage DAL may be different from the intermediate voltage VM.

[0083] 15, time tb is set, for example, near the peak of the first overshoot in VQ_nonSW or after the peak. Since the differential input voltage of the second amplifier circuit 122 is already large at time tb, the second amplifier circuit 122 responds to converge the output voltage VQ. Since the second amplifier circuit 122 responds faster than the first amplifier circuit 121, the convergence of the output voltage VQ is faster than VQ_nonSW.

[0084] 5. Sixth Configuration Example Fig. 16 shows a sixth configuration example of the circuit device. The circuit device 100 includes a D / A conversion circuit 111, a first drive circuit 131, a second drive circuit 132, a voltage dividing circuit 140, and a third drive circuit 160. The same reference numerals are used for components that have already been described, and descriptions of those components will be omitted. Fig. 16 shows an example in which the third drive circuit 160 is added to the first configuration example of the circuit device 100, but the third drive circuit 160 may be added to the second to fifth configuration examples.

[0085] The third drive circuit 160 drives the capacitive load 1 by capacitive driving. The third drive circuit 160 includes a capacitor circuit 10 and a capacitor drive circuit 20.

[0086] The capacitor circuit 10 includes first to n-th capacitors C1 to Cn. The capacitor driving circuit 20 includes first to n-th driving circuits DR1 to DRn. Although an example where n=11 will be described below, n may be any integer equal to or greater than 2.

[0087] One end of the capacitor Ci is connected to the output node NVQ, and the other end is connected to the capacitor driving node NDRi. i is an integer equal to or greater than 1 and equal to or less than n=11. The capacitors C1 to C11 have binary-weighted capacitance values. Specifically, the capacitance value of the capacitor Ci is 2 (i-1) ×C1.

[0088] The i-th bit DI[i-1] of the input data DI[10:0] is input to the input node of the driving circuit DRi. When the bit DI[i-1] is at a first logic level, the driving circuit DRi outputs a first voltage level to the capacitor driving node NDRi, and when the bit DI[i-1] is at a second logic level, the driving circuit DRi outputs a second voltage level to the capacitor driving node NDRi. For example, the first logic level is a low level, the second logic level is a high level, the first voltage level is a low potential side power supply voltage VSS, and the second voltage level is a first high potential side power supply voltage VDH. The driving circuit DRi is composed of transistors of a high voltage process, and operates with the first high potential side power supply voltage VDH and the low potential side power supply voltage VSS. The driving circuit DRi is composed of, for example, a level shifter that shifts the input logic level to the output voltage level of the driving circuit DRi, and a buffer circuit that buffers the output of the level shifter.

[0089] When the drive circuits DR1 to DR11 drive the capacitors C1 to C11, charge redistribution occurs between the capacitors C1 to C11 and the capacitance CP of the capacitive load 1. As a result, an output voltage VQ corresponding to the input data DI[10:0] is output to the output node NVQ.

[0090] The sum of the capacitance values ​​of the capacitors C1 to C11 is Ctot = C1 + C2 + ··· + C11. As an example, the capacitance values ​​of the capacitors C1 to C11 are set so that Ctot / CP = 2. In this case, the amplitude of the output voltage VQ due to capacitive driving is 15V × {Ctot / (Ctot + CP)} = 10V. This achieves the same amplitude of 10V for the output voltage VQ as in the example of Figure 2.

[0091] By providing the third drive circuit 160, it is possible to change the output voltage VQ at high speed by charge redistribution, and drive the capacitive load 1 at high speed. However, since charge is supplied at a speed much faster than the time constant of the capacitive load 1, there is a possibility that ringing of the output voltage VQ will become large. Even in such a case, the first drive circuit 131, which is slow but can handle large voltage changes, and the second drive circuit 132, which can handle small voltage changes but has high response speed, cooperate to suppress ringing, thereby shortening the convergence time of the output voltage VQ.

[0092] In this embodiment, the circuit device 100 includes a capacitor driving circuit 20 and a capacitor circuit 10. The capacitor driving circuit 20 outputs first to n-th capacitor driving voltages corresponding to input data DI[n-1:0] to the first to n-th capacitor driving nodes NDR1 to NDRn, where n is an integer equal to or greater than 2. The capacitor circuit 10 has first to n-th capacitors C1 to Cn arranged between the output terminal of the first amplifier circuit 121 and the first to n-th capacitor driving nodes NDR1 to NDRn.

[0093] According to this embodiment, the capacitor driving circuit 20 drives the first to n-th capacitors C1 to Cn based on the input data DI[n-1:0], causing charge redistribution between the first to n-th capacitors C1 to Cn and the capacitance CP of the capacitive load 1. As a result, an output voltage VQ corresponding to the input data DI[10:0] is output to the output node NVQ. The charge redistribution makes it possible to drive the capacitive load 1 at high speed. Although there is a possibility that ringing of the output voltage VQ will become large, the first amplifier circuit 121 and the second amplifier circuit 122 cooperate to suppress the ringing, thereby shortening the convergence time of the output voltage VQ.

[0094] 6. Electro-optical devices An example in which the circuit device 100 is used as a driver for an electro-optical device will be described below. Fig. 17 shows an example of the configuration of an electro-optical device. An electro-optical device 400 includes the circuit device 100 and an electro-optical panel 200. An electro-optical device 400 using a demultiplex drive method will be described below as an example, but is not limited to this, and for example, the electro-optical device 400 may use a phase expansion drive method. Also, an example in which the demultiplex number is 8 will be described below, but the demultiplex number may be p, where p is an integer equal to or greater than 2.

[0095] The circuit device 100 includes a control circuit 40, output circuits DD1 to DDk, output terminals TQ1 to TQk, and control signal output terminals SQ1 to SQ8, where k is an integer equal to or greater than 2. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate.

[0096] The electro-optical panel 200 includes input terminals TI1 to TIk, signal supply lines SL1 to SLk, demultiplexers DM1 to DMk, data lines DL11 to DL18, DL21 to DL28, ..., DLk1 to DLk8, and control signal input terminals SI1 to SI8. The electro-optical panel 200 is an active matrix type liquid crystal display panel, an EL display panel using self-luminous elements, or the like. EL is an abbreviation for Electro-Luminescence.

[0097] The control circuit 40 outputs grayscale data as input data to the output circuit DD1. The output circuit DD1 converts the grayscale data into a data voltage and outputs the data voltage to the output terminal TQ1. The output terminal TQ1 is connected to the input terminal TI1, and the input terminal TI1 is connected to a signal supply line SL1. The same applies to the output circuits DD2 to DDk, the output terminals TQ2 to TQk, the input terminals TI2 to TIk, and the signal supply lines SL2 to SLk.

[0098] The demultiplexer DM1 includes switches SW11 to SW18. Each switch is, for example, a TFT. TFT is an abbreviation for Thin Film Transistor. One end of the switch SW11 is connected to a signal supply line SL1, and the other end is connected to a data line DL11. The switch SW11 is controlled to be turned on or off by a control signal S1. Similarly, one end of the switches SW12 to SW18 is connected to a signal supply line SL1, and the other end is connected to data lines DL12 to DL18. The switches SW12 to SW18 are controlled to be turned on or off by control signals S2 to S8. The same is true for the demultiplexers DM2 to DMk, the switches SW21 to SW28, . . . , SWk1 to SWk8, and the data lines DL21 to DL28, . . . , DLk1 to DLk8. The number of switches and the number of data lines in each demultiplexer may be p, which is the same as the number of demultiplexes.

[0099] Although not shown in FIG. 17, the electro-optical panel 200 has a plurality of pixels arranged in a matrix. One data line and one scanning line are connected to one pixel. The scanning lines are selected by a scanning line driving circuit (not shown). The scanning line driving circuit may be included in the circuit device 100 or may be provided outside the circuit device 100.

[0100] Demultiplex driving will be explained using the output circuit DD1 as an example. In one horizontal scanning period, the switches SW11, SW12, ..., SW18 are sequentially turned on. When the switch SW11 is on, the output circuit DD1 writes a data voltage to the pixels connected to the data line DL11. Similarly, when the switches SW12, ..., SW18 are on, the output circuit DD1 writes a data voltage to the pixels connected to the data lines DL12, ..., DL1k.

[0101] Fig. 18 shows a detailed configuration example of a circuit device as a driver. Fig. 18 shows an output circuit DDj, which is any one of the output circuits DD1 to DDk, and a control circuit 40. j is an integer between 1 and k. The output circuit DDj includes a D / A conversion circuit 111, a first drive circuit 131, a voltage dividing circuit 140, a second drive circuit 132, and a third drive circuit 160. The control circuit 40 includes a processing circuit 42, an interface circuit 44, and a register circuit 48. Note that, although an example in which the sixth configuration example of the circuit device is used as the output circuit DDj is shown here, the first to fifth configuration examples may be used as the output circuit DDj.

[0102] The interface circuit 44 performs interface processing between the circuit device 100 and the display controller 300 that controls the circuit device 100. The interface circuit 44 outputs the grayscale data GD[9:0] received from the display controller 300 to the processing circuit 42. The number of bits of the received grayscale data may be arbitrary. The interface circuit 44 is, for example, an image interface circuit of the LVDS type, the parallel RGB type, or the display port type. LVDS is an abbreviation of Low Voltage Differential Signaling.

[0103] The processing circuit 42 outputs the enable signal LVEN of the second amplifier circuit 122 to the switch SWLV of the second driving circuit 132. The processing circuit 42 also outputs the input data DI[10:0] as grayscale data to the D / A conversion circuit 111 and the third driving circuit 160 based on the grayscale data GD[9:0]. The first driving circuit 131, the second driving circuit 132, and the third driving circuit 160 output a voltage corresponding to the input data DI[10:0] to the output node NVQ. As a result, the output voltage VQ of the output node NVQ becomes a data voltage corresponding to the input data DI[10:0] as grayscale data.

[0104] As an example, the common voltage is 7.5 V, the voltage range for positive drive is 7.5 V to 12.5 V, and the voltage range for negative drive is 7.5 V to 2.5 V. In this case, DI[10:0]=000h corresponds to 2.5 V, DI[10:0]=400h corresponds to 7.5 V, and DI[10:0]=4FFh corresponds to 12.5 V. When the polarity is not inverted, the grayscale data GD[9:0] may be output as is to the D / A conversion circuit 111 and the third drive circuit 160.

[0105] The register circuit 48 stores setting data that sets the time tb for which the switch SWLV is turned on. For example, the display controller 300 writes the setting data to the register circuit 48 via the interface circuit 44. Alternatively, the circuit device 100 may include a non-volatile memory (not shown) that stores the setting data in advance, and the setting data may be loaded from the non-volatile memory to the register circuit 48. The processing circuit 42 outputs an enable signal LVEN to the switch SWLV of the second drive circuit 132 based on the setting data read from the register circuit 48.

[0106] 19 shows an example of the configuration of an electronic device including a circuit device as a driver. As the electronic device of this embodiment, various electronic devices equipped with a display device can be assumed. For example, the electronic device is a projector, a television device, an information processing device, a portable information terminal, a car navigation system, a portable game terminal, or the like.

[0107] The electronic device 500 includes an electro-optical device 400, a display controller 300, a processing unit 310, a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 400 includes a circuit device 100 and an electro-optical panel 200.

[0108] The user interface unit 330 is an interface unit that accepts various operations from a user. For example, it is composed of a button, a mouse, a keyboard, or a touch panel attached to the electro-optical panel 200. The data interface unit 340 is an interface unit that inputs and outputs image data or control data. For example, it is a wired communication interface such as a USB, or a wireless communication interface such as a wireless LAN. The storage unit 320 stores image data input from the data interface unit 340. Alternatively, the storage unit 320 functions as a working memory for the processing device 310 or the display controller 300. The processing device 310 performs control processing of each part of the electronic device and various data processing. The processing device 310 is, for example, a processor such as a CPU or a microcomputer. The display controller 300 performs control processing of the circuit device 100. For example, the display controller 300 converts image data transferred from the data interface unit 340 or the storage unit 320 into a format that can be accepted by the circuit device 100, and outputs the converted image data to the circuit device 100. The circuit device 100 drives the electro-optical panel 200 based on image data transferred from the display controller 300 .

[0109] The circuit device is not limited to a driver, and the electronic device in which the circuit device is incorporated is not limited to the above. In other words, the electronic device may include a device equivalent to a capacitive load and the circuit device 100 that drives it.

[0110] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the circuit device, control circuit, output circuit, electro-optical panel, electro-optical device, electronic device, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0111] 1...capacitive load, 10...capacitor circuit, 20...capacitor driving circuit, 40...control circuit, 42...processing circuit, 44...interface circuit, 48...register circuit, 100...circuit device, 111...D / A conversion circuit, 112...second D / A conversion circuit, 121...first amplifier circuit, 122...second amplifier circuit, 131...first driving circuit, 132...second driving circuit, 140...voltage divider circuit, 150...adjustment capacitor driving circuit, 160...third driving circuit, 200...electro-optical panel, 300...display controller, 31 0...processing device, 320...storage unit, 330...user interface unit, 340...data interface unit, 400...electro-optical device, 500...electronic device, C1 to C11...capacitors, CJ1 to CJ3...adjustment capacitors, CQ...output capacitor, Cda...first voltage dividing capacitor, Cdb...second voltage dividing capacitor, Cfa...first feedback capacitor, Cfb...second feedback capacitor, DAH...first voltage, DAL...second voltage, DD1 to DDk...output circuit, DI...input data

Claims

1. a D / A conversion circuit that outputs a first voltage by D / A converting input data; a first amplifier circuit to which the first voltage is input and which is configured with a transistor having a first withstand voltage; a second amplifier circuit having a non-inverting input terminal to which a second voltage corresponding to a D / A converted voltage of the input data and lower than the first voltage is input, the second amplifier circuit being constituted by transistors having a second withstand voltage lower than the first withstand voltage; an output capacitor disposed between an output terminal of the second amplifier circuit and an output terminal of the first amplifier circuit; a first feedback capacitor disposed between the inverting input terminal of the second amplifier circuit and the output terminal of the first amplifier circuit; a second feedback capacitor disposed between the inverting input terminal of the second amplifier circuit and a predetermined potential node; A circuit device comprising:

2. 2. The circuit device according to claim 1, The second amplifier circuit is set from a disabled state to an enabled state with a delay from a timing at which the input data changes.

3. 2. The circuit device according to claim 1, a first voltage dividing capacitor disposed between an output node of the D / A conversion circuit and a non-inverting input terminal of the second amplifier circuit; a second voltage dividing capacitor disposed between the non-inverting input terminal of the second amplifier circuit and the predetermined potential node; A circuit device comprising:

4. 4. The circuit device according to claim 3, A circuit device, characterized in that a voltage division ratio between the first voltage division capacitor and the second voltage division capacitor is the same as a voltage division ratio between the first feedback capacitor and the second feedback capacitor.

5. 2. The circuit device according to claim 1, a second D / A conversion circuit that outputs the second voltage by D / A converting the input data; the D / A conversion circuit is composed of transistors of the first voltage resistance, The second D / A conversion circuit is configured with transistors of the second withstand voltage.

6. 6. The circuit device according to claim 5, the D / A conversion circuit performs D / A conversion on upper m bits (m is an integer of 1 or more and n-1 or less) of the n-bit input data (n is an integer of 1 or more); The second D / A conversion circuit performs D / A conversion on the n-bit input data.

7. 7. A circuit device according to claim 6, The circuit device according to claim 1, wherein the first amplifier circuit has a dead band wider than a variation width of the first voltage corresponding to the LSB of the most significant m bits.

8. 4. The circuit device according to claim 3, first to q-th adjustment capacitors each having one end connected to the non-inverting input terminal of the second amplifier circuit; a drive circuit that outputs first to qth voltages corresponding to lower q bits (q is an integer of 1 or more and n-1 or less) of the n-bit input data (n is an integer of 1 or more), to the other ends of the first to qth adjustment capacitors; Including, The D / A conversion circuit performs D / A conversion on the most significant nq bits of the n-bit input data.

9. 4. The circuit device according to claim 3, first to q-th adjustment capacitors each having one end connected to the inverting input terminal of the second amplifier circuit; a drive circuit that outputs first to qth voltages corresponding to inverted bits of the lowest q bits (q is an integer of 1 or more and n-1 or less) of the n-bit input data (n is an integer of 1 or more), to the other ends of the first to qth adjustment capacitors; Including, The D / A conversion circuit performs D / A conversion on the most significant nq bits of the n-bit input data.

10. 2. The circuit device according to claim 1, a capacitor driving circuit that outputs first to n-th capacitor driving voltages (n is an integer of 2 or more) corresponding to the input data to first to n-th capacitor driving nodes; a capacitor circuit having first to n-th capacitors arranged between an output terminal of the first amplifier circuit and the first to n-th capacitor driving nodes; A circuit device comprising:

11. 2. The circuit device according to claim 1, the input data is gradation data, The first amplifier circuit and the second amplifier circuit drive an electro-optical panel.

12. A circuit arrangement according to claim 11; The electro-optical panel; 1. An electro-optical device comprising:

13. An electronic device comprising the circuit device according to claim 1 .

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