Semiconductor device

Abstract

To provide a semiconductor device with large ON-state current.SOLUTION: A semiconductor device includes: a first oxide; a first conductor and a second conductor disposed apart from each other on the first oxide; and a second oxide disposed between the first conductor and the second conductor on the first oxide. Each of the first oxide and the second oxide has crystallinity. The first oxide includes a region where a c-axis is oriented so as to be substantially perpendicular to an upper surface of the first oxide. The second oxide includes a region where the c-axis is oriented so as to be substantially perpendicular to the upper surface of the first oxide, a region where the c-axis is oriented so as to be substantially perpendicular to a side surface of the first conductor, and a region where the c-axis is oriented so as to be substantially perpendicular to a side surface of the second conductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. One aspect of the invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, and There are cases where the child devices and the like can be said to have semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. An aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the issue of the [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as other materials. For example, not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals Among the oxides of multi-component metals, In-Ga-Zn oxide (hereinafter Research into IGZO (interspersed organic semiconductor) is being actively conducted.

[0005] Research on IGZO has revealed that, among oxide semiconductors, IGZO is neither single crystal nor amorphous. AAC (c-axis aligned crystalline) structure and nc (n A crystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used. Furthermore, a technology for fabricating a transistor using a CAAC structure and an nc structure has been disclosed. It has been reported in Non-Patent Documents 4 and 5 that even oxide semiconductors with lower crystallinity than and in Non-Patent Document 5.

[0006] Furthermore, transistors using IGZO as an active layer have extremely low off-state current (non- See Patent Document 6.) LSIs and displays that utilize these properties have been reported ( See non-patent literature 7 and non-patent literature 8. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device having large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another embodiment of the present invention is a semiconductor device that can be miniaturized or highly integrated. Another object of the present invention is to provide a semiconductor device having excellent electrical characteristics. Another object of the present invention is to provide a semiconductor device having a high productivity. It is an object of the present invention to provide a high-performance semiconductor device.

[0009] One embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. One object of one embodiment of the present invention is to provide a semiconductor device in which data can be written at a high speed. One object of one embodiment of the present invention is to provide a semiconductor device having high design freedom. One object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption. One object of the present invention is to provide a novel semiconductor device. is one of the challenges.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device comprising a first oxide and a semiconductor device disposed on the first oxide and spaced apart from each other. a first conductor and a second conductor, and a first oxide is formed on the first conductor and the second conductor. and a second oxide disposed between the first and second oxide bodies, Each of them has crystallinity, and the first oxide is arranged so as to be approximately perpendicular to the upper surface of the first oxide. The second oxide has a region in which the c-axis is oriented, and is approximately perpendicular to the top surface of the first oxide. and a region in which the c-axis is oriented so as to be approximately perpendicular to the side surface of the first conductor. and a region in which the c-axis is oriented approximately perpendicular to the side surface of the second conductor. The semiconductor device has a region.

[0012] In addition, one embodiment of the present invention is a first oxide and a second oxide arranged on the first oxide at a distance from each other. A first conductor and a second conductor are disposed on the first conductor and the second conductor. a first insulator disposed on the first conductor and having an opening formed therein and overlapping the first conductor and the second conductor; a third conductor disposed in the opening; and a first oxide, a first conductor, a second conductor, and and a second insulator disposed between the first insulator and the third conductor, and a first oxide. , a first conductor, a second conductor, and a first insulator and a second insulator are disposed between the first conductor and the second insulator. and a second oxide formed by the first oxide and the second oxide each having crystallinity. The first oxide has a c-axis oriented approximately perpendicular to the upper surface of the first oxide. The second oxide has a c-axis that is approximately perpendicular to the top surface of the first oxide. and a region in which the c-axis is oriented so as to be approximately perpendicular to the side surface of the first conductor. and a region in which the c-axis is oriented substantially perpendicular to the side surface of the second conductor. , a semiconductor device.

[0013] In the above, the first oxide, the first conductor, the second conductor, and the second oxide A third insulator is disposed between the object and the first insulator, and the third insulator is It may have a lower oxygen permeability.

[0014] In the above, the first oxide, the first conductor, the second conductor, and the first insulator A third insulator is disposed between the edge and the first insulator, the third insulator being more oxygen permeable than the first insulator. may be low and the second oxide may be in contact with the first insulator.

[0015] In the above, a third conductor is disposed between the first conductor and the first oxide, A fourth conductor is disposed between the second conductor and the first oxide, and a portion of the first conductor is connected to the first oxide. The first oxide may be in contact with a top surface of the first conductor, and a portion of the second conductor may be in contact with a top surface of the first oxide. In the above, the distance between the first conductor and the second conductor is the length of the opening in the channel length direction. It may be shorter.

[0016] In the above, the side surface of the first conductor is approximately perpendicular to the bottom surface of the first conductor, The side surface of the second conductor may be approximately perpendicular to the bottom surface of the second conductor.

[0017] In the above, the angle between the side surface of the first conductor and the bottom surface of the first conductor is 10° or more. 80° or less, and the angle between the side surface of the second conductor and the bottom surface of the second conductor is 10° or more and 80° or less. ° or less.

[0018] In the above, the first oxide and the second oxide are each composed of In and an element M (M is A In the above, the first The atomic ratio of In to element M in the oxide is It may be larger than the atomic ratio of n.

[0019] In the above, the first oxide is formed approximately perpendicular to the upper surface of the first oxide. The c-axis of the second oxide is aligned approximately perpendicular to the top surface of the first oxide. The oriented c-axis may be approximately continuous.

[0020] In the above, a third oxide may be disposed below the first oxide. In the above, the conduction band minimum energies of the second oxide and the third oxide are The energy of the first oxide may be higher than the energy of the bottom of the conduction band of the oxide. The second oxide and the third oxide are made of In and an element M (M is Al, Ga, Y, or S). n) and Zn. In the above, the element M in the first oxide may be The atomic ratio of In to element M in the second oxide and the third oxide is The atomic ratio may be larger than the atomic ratio of Effect of the Invention

[0021] According to one embodiment of the present invention, a semiconductor device having a large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated is provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. This can be done.

[0022] Alternatively, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with a high data writing speed can be provided. It is possible to provide a semiconductor device having a high degree of freedom. It is possible to provide a semiconductor device. Alternatively, it is possible to provide a novel semiconductor device. .

[0023] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram illustrating the oxygen transport pathway in an In—Ga—Zn oxide. [Diagram 3] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 5] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12]1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] FIG. 1 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 22] FIG. 1 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 23] FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 24] FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. [Diagram 25] 1A and 1B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 1 is a schematic diagram of a memory device according to one embodiment of the present invention. [Figure 27] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 28] 4 is a cross-sectional TEM image according to an embodiment of the present invention. [Figure 29] 4 is a cross-sectional TEM image according to an embodiment of the present invention. [Diagram 30] 4 is a cross-sectional TEM image according to an embodiment of the present invention. [Diagram 31]4 shows a cross-sectional TEM image and a crystal orientation map according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, the embodiments will be described with reference to the drawings. It is understood that the present invention can be practiced in many different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiment modes.

[0026] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in schematic form, and are not limited to the shapes or values ​​shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this is not reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. In addition, when referring to similar functions, In such cases, the hatch patterns may be the same and no particular reference numbers may be used.

[0027] In addition, the invention is easily understood, particularly in top views (also called "plan views") and perspective views. In order to simplify the description, some of the components may be omitted. The above information may be omitted.

[0028] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second "the" or "third" can be used as appropriate. The ordinal numbers described herein may not coincide with the ordinal numbers used to identify an aspect of the present invention. There are cases where this is the case.

[0029] In addition, in this specification, the terms "above" and "below" that indicate an arrangement are used to refer to the relationship between components. The positional relationship is used for convenience in describing the drawings. The relationship changes accordingly depending on the direction in which each configuration is depicted. The terms are not limited to those described above, and may be rephrased appropriately depending on the situation.

[0030] For example, in the present specification, it is explicitly stated that X and Y are connected. The cases are when X and Y are electrically connected and when X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification, etc. Therefore, the connection relationship is limited to a specific one, for example, the connection relationship shown in the figure or text. Connections other than those shown in the drawings or text may not be included in the drawings or text. It shall be so.

[0031] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0032] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0033] In this specification and the like, depending on the structure of the transistor, the channel may not actually be formed. The channel width in the region where the transistor is The channel width shown in a top view of the star (hereinafter also referred to as the "apparent channel width") For example, if the gate electrode covers the side of the semiconductor, the effective When the channel width becomes larger than the apparent channel width and its effect cannot be ignored For example, in a transistor that is very small and has a gate electrode that covers the side of the semiconductor, The proportion of the channel formation region formed on the side may become large. In that case, the apparent The effective channel width is larger than the above channel width.

[0034] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, Channel width is difficult to measure accurately.

[0035] In this specification, when the term "channel width" is used, it refers to the apparent channel width. In this specification, when the term "channel width" is used, it means an effective channel The channel length, channel width, effective channel width, apparent channel width, etc. The channel width and other parameters can be determined by analyzing cross-sectional TEM images, etc. can.

[0036] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. For example, The DOS (Density of States) of the semiconductor increases and the crystallinity decreases. When the semiconductor is an oxide semiconductor, the semiconductor characteristics may be deteriorated. The impurities to be changed include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, These include elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, for example: Hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Oxides In the case of a semiconductor, water may also function as an impurity. In some cases, oxygen vacancies may be formed due to the inclusion of impurities. In this case, impurities that change the properties of a semiconductor include, for example, oxygen and Group 1 elements excluding hydrogen. , Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0037] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. Silicon nitride oxide is a material that contains more oxygen than silicon. It has a high nitrogen content.

[0038] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." In addition, the term "conductor" can be replaced with "conductive film" or "conductive layer." In addition, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." can.

[0039] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10 degrees or more and 10 degrees or less. Therefore, it includes the case where the angle is between -5 degrees and 5 degrees. In addition, "approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state where two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it includes the case where the angle is between 85 degrees and 95 degrees. "Perpendicular" refers to two straight lines that form an angle between 60 degrees and 120 degrees.

[0040] In this specification, the term "barrier film" refers to a film that prevents impurities such as water and hydrogen from passing through, and oxygen. If the barrier film is conductive, it is called a conductive barrier. It is sometimes called the a membrane.

[0041] In this specification, the term "metal oxide" refers to metals in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used for the semiconductor layer of a transistor, Such a metal oxide may be called an oxide semiconductor. In the case of a transistor, a transistor having an oxide or an oxide semiconductor is used. This can be rephrased as ta.

[0042] In this specification and the like, normally off means that no potential is applied to the gate, or The current per 1 μm of channel width that flows through a transistor when a ground potential is applied to the gate At room temperature, -20 A or less, 1×10 at 85℃ -18 A or below, or 1×10 at 125℃ -16 This means that it is A or lower.

[0043] (Embodiment 1) The configuration and characteristics of a semiconductor device according to one embodiment of the present invention will be described below.

[0044] FIG. 1A is a cross-sectional view of a portion of a transistor 10a according to one embodiment of the present invention.

[0045] As shown in FIG. 1A, a transistor 10a includes an oxide 12 disposed on a substrate; A conductor 14a and a conductor 14b are arranged on the oxide 12 at a distance from each other, and an oxide and an oxide 13 disposed on the oxide 12 between the conductor 14a and the conductor 14b. Here, the conductor 14a and the conductor 14b are the source potentials of the transistor 10a. Although not shown, the transistor 10a functions as a gate electrode or a drain electrode. The gate insulator and gate electrode are formed on the oxide 13 between the conductors 14a and 14b. will be placed in.

[0046] The oxide 12 has a channel forming region between the conductor 14a and the conductor 14b. The channel forming region is sandwiched between the conductive body 14a (conductive body 14b) and the solenoid 14a. The semiconductor device has a source region and a drain region. Note that the source region and / or the drain region are In some cases, the conductor 14a (conductor 14b) may protrude inward. The channel formation region of the transistor 10a is not only the oxide 12 but also the oxide 12 and the oxide 13. It may also form near the interface and / or in the oxide 13.

[0047] Here, in the transistor 10a, the oxide 12 and the oxide 13 are oxide semiconductors. It is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an For example, the metal oxides that form oxide 12 and oxide 13 have an energy gap of 2 It is preferable to use an energy of 2.5 eV or more, preferably 2.5 eV or more. Transistors using metal oxides with a wide energy gap have low off-current (leakage current). By using such a transistor, a semiconductor device with low power consumption can be provided.

[0048] For example, oxide 12 and oxide 13 are In-M-Zn oxides (wherein element M is Al). Minium, Gallium, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium , Iron, Nickel, Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neo One selected from zinc, hafnium, tantalum, tungsten, or magnesium In particular, the element M may be aluminum, gallium, or a combination of metal oxides. The oxides 12 and 13 are preferably tungsten, yttrium, or tin. Alternatively, In-Ga oxide or In-Zn oxide may be used.

[0049] Here, the atomic ratio of In to element M in the metal oxide used for the oxide 12 is The ratio of the number of atoms of In to the number of atoms of element M in the metal oxide used for oxide 13 is greater than that In this manner, by disposing the oxide 13 on the oxide 12, the oxide 13 The diffusion of impurities into the oxide 12 can be suppressed from the structure formed above the In addition, oxide 12 and oxide 13 have a common element other than oxygen (main component). By this, the defect state density at the interface between the oxide 12 and the oxide 13 can be reduced. At this time, the main path of the carriers is the oxide 12 or its vicinity, for example, the oxide 12 The defect state density at the interface between the oxide 12 and the oxide 13 is Since the thickness can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-state current can be achieved. flow is obtained.

[0050] In addition, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. If impurities and oxygen vacancies exist in the region, the electrical characteristics are likely to fluctuate, resulting in poor reliability. In addition, oxygen vacancies may exist in a region in an oxide semiconductor where a channel is formed. Therefore, the transistor tends to have normally-on characteristics. It is preferable that oxygen vacancies in the region to be covered are reduced as much as possible. This transistor has stable electrical characteristics and improved reliability. The data can be provided.

[0051] It is preferable that the oxide 12 and the oxide 13 each have crystallinity. The oxide 12 and oxide 13 were prepared by CAAC-OS (c-axis aligned crystal It is preferable to use crystalline oxide semiconductor. stomach.

[0052] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The nanocrystals are connected together to form a distorted crystal structure. In a region, a lattice arrangement is formed between a region having a uniform lattice arrangement and another region having a uniform lattice arrangement. This refers to the point where the direction of the

[0053] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in the CAAC-OS, clear grain boundaries (grain bows) were observed even in the vicinity of the strain. It is difficult to confirm the presence of the lattice distortion. This is because the CAAC-OS has ab-plane orientation. In the case of the SiO2, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated due to changes in the distance, etc.

[0054] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M tend to have a layered structure. When the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn ) layer. Also, when the indium in the In layer is replaced with the element M, (In, M) layer.

[0055] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is designed to prevent impurities and defects (oxygen vacancies (V O :oxygen v It can also be said to be a metal oxide with low acancy. Metal oxides with CAAC-OS have stable physical properties. The metal oxides used are heat resistant and highly reliable.

[0056] Here, the analysis was performed using X-ray diffraction (XRD). An example of CAAC-OS will be described. For example, a CAAC having InGaZnO4 crystals When the structure of C-OS is analyzed using the out-of-plane method, the diffraction angle (2θ) A peak may appear around 31°. This peak is due to the ( 009) plane, the CAAC-OS crystal has a c-axis orientation, and the c-axis is This indicates that the direction is approximately perpendicular to the forming surface or upper surface.

[0057] We also describe examples of CAAC-OS analyzed by electron diffraction. For CAAC-OS with GaZnO4 crystals, a probe diameter of 300 was placed parallel to the sample surface. When an electron beam of 1 nm is incident on the specimen, a diffraction pattern (also called a selected area transmission electron diffraction pattern) is produced. ) may appear. This diffraction pattern includes the (009) plane of the InGaZnO4 crystal. Therefore, the electron diffraction also shows that the CAAC-OS contains The crystals contained in the substrate have a c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the surface on which the substrate is formed or the upper surface. On the other hand, the same specimen was subjected to electron microscopy with a probe diameter of 300 nm perpendicular to the specimen surface. When a beam of light is incident on a sample, a ring-shaped diffraction pattern is observed. However, it can be seen that the a-axis and b-axis of the crystals contained in CAAC-OS do not have any orientation. .

[0058] As described above, the oxide 12 is made up of a layer 12a of crystals extending in the ab-plane direction and a layer 12b of crystals extending in the ab-plane direction. The oxide 12 includes a crystalline region having a c-axis 12b perpendicular to the crystal direction. The c-axis 12b is preferably oriented in a direction approximately perpendicular to the surface on which the oxide 12 is formed or to the upper surface. Therefore, as shown in FIG. 1, the oxide 12 is formed in a substantially perpendicular manner to the upper surface of the oxide 12. The c-axis 12b is oriented in a region such that

[0059] The oxide 13 also has a crystal layer 13a extending in the ab-plane direction and a layer 13b perpendicular to the ab-plane direction. Here, the oxide 13 includes a crystalline region having a c-axis 13b. It is preferable that b faces a direction approximately perpendicular to the surface on which the oxide 13 is formed or to the upper surface. Therefore, as shown in FIG. 1, the oxide 13 is arranged to be approximately perpendicular to the upper surface of the oxide 12. The region in which the c-axis 13b is oriented as shown in FIG. 1 and the region in which the c-axis 13b is oriented as shown in FIG. The region in which the c-axis 13b is oriented and the region in which the c-axis 13b is oriented are arranged so as to be approximately perpendicular to the side surface of the conductor 14b. and a region in which b is oriented.

[0060] As will be described in detail later, CAAC-OS has the property of making it difficult for oxygen to move in the c-axis direction. Therefore, as described above, in the oxide 13, the c-axis 13b is aligned with the side surface of the conductor 14a. The c-axis 13b is oriented approximately perpendicular to the side surface of the conductor 14b. The oxide 13 is oriented vertically. Excess oxygen is absorbed from the insulator (e.g., the gate insulator) into the conductor 14a and the conductor 14b. This can prevent the conductor 14a and the conductor b from being absorbed by the conductor 14a. Therefore, oxidation of the vicinity of the side surfaces of the transistors 14b facing each other can be suppressed. The channel length of the transistor 10a becomes shorter than the designed distance between the conductors 14a and 14b. This prevents the on-state current, S value, and frequency characteristics from decreasing compared to the design values. This can be prevented.

[0061] Here, the thickness of the oxide 13 is, for example, 2 nm or more, preferably 3 nm or more, and more preferably By making the oxide 13 thick in this way, the c-axis 1 A region in which 3b is oriented so as to be approximately perpendicular to the side surface of the conductor 14a (conductor 14b). can be formed.

[0062] In addition, for example, when excess oxygen is supplied to an oxide semiconductor, stress such as voltage and high temperature can be generated. The structure of the excess oxygen in the oxide semiconductor may change due to the above. There is a risk that the electrical characteristics of transistors containing semiconductors may become unstable or their reliability may decrease. However, as described above, the c-axis 13b in the oxide 13 is located on the upper surface of the oxide 12. By having a region oriented approximately perpendicular to the oxide 13, Excess oxygen is absorbed into the oxide 12 from an insulator containing oxygen (e.g., a gate insulator). This can stabilize the electrical characteristics of the transistor and improve the signal quality. This can improve reliability.

[0063] The crystal structures of oxides 12 and 13 can be confirmed, for example, by taking cross-sectional TEM images. In addition, the crystallinity and orientation data for each pixel of the cross-sectional TEM image can be obtained. The data was then analyzed by creating a map (hereafter referred to as the crystal orientation map) in which the data was superimposed on a cross-sectional TEM image. may be carried out.

[0064] A crystal orientation map can be created as follows. First, For each pixel, a Fast Fourier Transform (FFT) is performed centered on the pixel. Set the area in which the FFT window is to be processed (hereafter referred to as the FFT window). The window should be set appropriately according to the resolution of the cross-sectional TEM image and the size of the crystal to be observed. For example, in the case of the above CAAC-OS, the FFT window is set to the cross-sectional TEM The image scale should be a circle with a diameter of about 1.5 nm.

[0065] Next, FFT processing is performed for each FFT window. Acquire an FFT image. The FFT image shows spots that reflect the crystal structure of the FFT window. That is, the intensity of the spots indicates the degree of crystallinity within the FFT window, and the arrangement of the spots indicates the degree of crystallinity within the FFT window. represents the crystal orientation within the FFT window. For example, if the above CAAC-OS is perpendicular to the c-axis, In the case of a cross-sectional TEM image taken from a perpendicular direction, two spots of high intensity are seen in the FFT image. The intensity of these two spots represents the crystallinity of the CAAC-OS. The angle of the line segment connecting the two spots represents the crystal orientation of the CAAC-OS.

[0066] Next, the pixels of the cross-sectional TEM image are colored according to the angle of the spot in the FFT image. When the pixel with the strong spot intensity is colored with low transparency, the pixel with the weak spot intensity is colored with low transparency. The crystal orientation map created in this way shows the degree of crystallinity. In areas with low crystallinity, the cross-sectional TEM image is visible as is, while in areas with high crystallinity, the The corresponding color is seen.

[0067] As described above, the c-axis 12b of the oxide 12 is approximately By having a region oriented vertically, oxygen vacancies or impurities in the oxide can be eliminated. This reduces the on-state current, the S value, and the frequency characteristics of the transistor 10a. Here, the c-axis 12b is oriented approximately perpendicular to the top surface of the oxide 12. The region needs to be formed at least in the channel forming region of the transistor 10a. That is, the source or drain region of the transistor 10a, in other words, the oxide 12 In the region near the conductor 14a (conductor 14b), the c-axis 12b is located on the upper surface of the oxide 12. In some cases, the region oriented approximately perpendicular to the surface is not formed.

[0068] In order to provide such an oxide 12, the surface on which the oxide 12 is to be formed must be made flat. For example, the average surface roughness (Ra) of the surface on which the oxide 12 is formed is preferably 1 nm or less. It is preferable that the thickness is 0.5 nm or less, and more preferably 0.3 nm or less.

[0069] In this specification, the average surface roughness (Ra) is defined as follows: The arithmetic mean roughness defined in ISO4287:1997 can be applied to curved surfaces. It is a three-dimensional extension of the 3D model, and is the average absolute value of the deviation from the reference plane to the specified plane. The average surface roughness (Ra) is expressed by the atomic force microscope (AFM). It can be measured using a microscope.

[0070] In addition, the c-axis 12b of the oxide 12 is oriented approximately perpendicular to the upper surface of the oxide 12. , and the c-axis 13b of the oxide 13 oriented approximately perpendicular to the top surface of the oxide 12 It is preferable that the c-axis of the oxide 12 and the c-axis of the oxide 13 are substantially continuous. The c-axis is approximately continuous, for example, in a cross-sectional TEM image of a laminated film of oxide 12 and oxide 13. This refers to a state in which no clear crystal grain boundaries can be confirmed. By forming the oxide 12 and the oxide 13, the defect state density at the interface between the oxide 12 and the oxide 13 is reduced. This reduces the effect of interface scattering on carrier conduction, resulting in a high on-state current. Obtained.

[0071] In order to provide the oxide 12 and the oxide 13 in this manner, the oxide 12 is flattened as described above. The oxide film is formed on a surface having good adhesion, and impurities on the oxide film 12 are removed as much as possible. It is preferable to deposit a film of the compound 13.

[0072] In the transistor 10a, the side surface of the conductor 14a is approximately The side surface of the conductor 14b is approximately perpendicular to the bottom surface of the conductor 14b. However, the present invention is not limited to this. Alternatively, the opposing side surfaces of conductor 14a and conductor 14b may have a tapered shape. Here, the angle (θ) between the side surface of the conductor 14a and the bottom surface of the conductor 14a is set to be 10° or more and 80° or less. The angle between the side surface of the conductor 14b and the conductor 14c is preferably 30° or more and 60° or less. The angle (θ) formed by the bottom surface of 14b is 10° or more and 80° or less, preferably 30° or more and 60° or less. As a result, the oxide 12 is formed in the region near the conductor 14a and the conductor 14b. This also increases the contribution of the electric field of the gate electrode, and reduces the on-current, S value, and The frequency characteristics can be improved.

[0073] In this way, even when the conductors 14a and 14b have a tapered shape, As shown in FIG. 1B, the oxide 13 has a c-axis 13b that is approximately perpendicular to the side surface of the conductor 14a. The c-axis 13b is aligned approximately perpendicular to the side surface of the conductor 14b. and a region oriented so as to

[0074] In addition, as in the case of a transistor 10c shown in FIG. The opposing side surfaces of b may have a plurality of surfaces. The angles (θ1, θ2) formed by the bottom surfaces of the oxides 13 are different from each other. The c-axis 13b has a region oriented approximately perpendicular to each of the planes. In FIG. 1C, the side surface of the conductor 14a (conductor 14b) forms an angle of θ1 with the bottom surface. The only surface that has an angle of θ2 with the bottom surface is the surface, but the semiconductor device according to the present embodiment is limited to this. The side surface of the conductor 14a (conductor 14b) may have more surfaces. .

[0075] According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. can.

[0076] <Oxygen Migration in In-Ga-Zn Oxide> Hereinafter, the relationship between the crystallinity and the oxygen permeability when the oxide 13 is an In-Ga-Zn oxide will be described. will be described.

[0077] The energy barrier related to the migration of excess oxygen (oxygen) in the crystal of In-Ga-Zn oxide is obtained by calculation. For the calculation, the plane-wave basis first-principles calculation software VASP (Vienna ab-initio simulation package) based on the density functional theory is used. kage) is used. Note that GGA-PBE is used as the functional. Also, the cut-off energy of the plane wave is set to 400 eV. In addition, the effect of the core electrons is incorporated by the PAW (Projector Augmented Wave) method. ented Wave) method. Here, in the crystal of In-Ga-Zn oxide shown in Fig. 2, the ease of migration of the excess oxygen (oxygen) in the migration paths 1, 2, 3, and 4 is calculated.

[0078] Here, in the crystal of In-Ga-Zn oxide shown in Fig. 2, the ease of migration of the excess oxygen (oxygen) in the migration paths 1, 2, 3, and 4 is calculated. movement paths 1, 2, 3, and 4 are calculated. Note that the a-axis, b-axis, and c-axis in Fig. 2 correspond to the crystal structure of the In-Ga-Zn oxide.

[0079] Note that migration path 1 is the path until the excess oxygen (oxygen) bonded to the oxygen bonded to three indium atoms and one zinc atom binds to the oxygen bonded to the adjacent three indium atoms and one zinc atom. Also, migration path 2 is the path until the excess oxygen (oxygen) bonded to the oxygen bonded to three indium atoms and one gallium atom binds to the oxygen bonded to the adjacent three indium atoms and one zinc atom across the layer containing indium and oxygen. Also, migration path 2 is the path until the excess oxygen (oxygen) bonded to the oxygen bonded to three indium atoms and one gallium atom binds to the oxygen bonded to the adjacent three indium atoms and one zinc atom across the layer containing indium and oxygen. oxygen binds to the oxygen bonded to the adjacent three indium atoms and one zinc atom across the layer containing indium and oxygen. Also, migration path 3 is the path until the excess oxygen (oxygen) bonded to the oxygen bonded to two gallium atoms and one zinc atom binds to the oxygen bonded to the adjacent three indium atoms and one zinc atom. The excess oxygen (oxygen) bound to the oxygen bound to one zinc atom is the two adjacent zinc atoms and The pathway is from one gallium atom to another and then to oxygen, which is bonded to one gallium atom. is an excess of oxygen (oxygen) bound to two gallium atoms and one zinc atom. ) crosses the layer containing gallium, zinc and oxygen and connects three adjacent indium atoms and and a pathway leading to bonding with oxygen bonded to one gallium atom.

[0080] Diffusion energy barrier E per unit time a If the frequency of exceeding is the diffusion frequency R, then R is It can be expressed by the formula below.

[0081] R = ν exp[-E a / (k B T)]

[0082] where ν is the frequency of thermal vibration of the diffusing atom, k B is the Boltzmann constant and T is the absolute temperature. ν is the Debye frequency of 10 13 [1 / sec] at 350℃ and 450 The diffusion frequency R in °C is as shown in Table 1.

[0083] [Table 1]

[0084] As shown in Table 1, in migration path 2 across the indium and oxygen containing layer, other It can be seen that the energy barrier is higher than the migration path. The oxide crystal shows that the migration of excess oxygen (oxygen) in the c-axis direction is difficult. That is, a film having a c-axis orientation, such as CAAC-OS, has a surface on which the film is formed or a top surface. In the case where the structure is oriented in a vertical direction, the structure is oriented in a direction approximately perpendicular to the surface on which the structure is formed or the upper surface. This makes it difficult for excess oxygen (oxygen) to move.

[0085] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0086] (Embodiment 2) Specific examples of the structure of the semiconductor device described in the above embodiment will be described below with reference to FIGS. This will be explained using Figure 20.

[0087] <Example of semiconductor device configuration> 3A, 3B, and 3C show transistor 2 according to one embodiment of the present invention. 00, and a top view and a cross-sectional view of the area around transistor 200.

[0088] FIG. 3A is a top view of a semiconductor device including a transistor 200. FIG. 3B) and FIG. 3C are cross-sectional views of the semiconductor device. 3(A) is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. FIG. 3(C) is a cross-sectional view taken along the dashed line A3-A4 in FIG. 3(A). 1 is a cross-sectional view of the portion indicated by the arrow A in FIG. In the top view of FIG. 3(A), some elements are omitted for clarity.

[0089] [Transistor 200] As shown in FIG. 3, transistor 200 includes an oxide semiconductor layer disposed on a substrate (not shown). The oxide 230a is a layer of a SiO 2 oxide 230b disposed on the oxide 230a. On the top of the conductor 242, a conductor 242a and a conductor 242b are arranged at a distance from each other, and a conductor 24 2a and conductor 242b, and overlapping between conductor 242a and conductor 242b. The insulator 280 has an opening formed therein, the conductor 260 disposed in the opening, and the oxide 23. 0b, conductor 242a, conductor 242b, and between insulator 280 and conductor 260 The insulator 250 disposed on the oxide 230b, the conductor 242a, the conductor 242b, and and an oxide 230c disposed between the insulator 280 and the insulator 250. As shown in FIG. 3B and FIG. 3C, the upper surface of the conductor 260 is covered with the insulator 250 and the insulator 261. 54, insulator 244, oxide 230c, and the top surface of insulator 280. In the following description, oxide 230a, oxide 230b, and oxide 230c are These may be collectively referred to as oxide 230. are sometimes collectively referred to as conductor 242.

[0090] Here, oxide 230b corresponds to oxide 12 of transistor 10a of the previous embodiment. In addition, the oxide 230c is different from the oxide 13 of the transistor 10a of the previous embodiment. The conductor 242a and the conductor 242b correspond to the transistors of the previous embodiment. These correspond to the conductors 14a and 14b in the circuit 10a.

[0091] In the transistor 200 shown in FIG. 3, the conductor 242a and the conductor 242b are The side surface on the 60 side has a substantially vertical shape similar to that of the transistor 10a shown in FIG. The transistor 200 shown in FIG. 3 is not limited to this. Similarly to the transistor 10b shown in FIG. 1B, the side surfaces of the conductor 242a and the conductor 242b are The angle of the bottom surface may be 10° or more and 80° or less, preferably 30° or more and 60° or less. In addition, similarly to the transistor 10c illustrated in FIG. Opposing sides of 242b may have multiple faces.

[0092] As shown in FIG. 3, the insulator 224, the oxide 230a, the oxide 230b, the conductor 2 42a, the conductor 242b, and the oxide 230c, and the insulator 280. 4 and an insulator 254 are preferably arranged. Here, the insulator 254 is As shown in FIG. 1C, the side surface of the oxide 230c, the top and side surfaces of the conductor 242a, and the conductor 2 The top and side surfaces of oxide 230a and oxide 230b, and the insulator 22 It is preferable that the insulator 244 is disposed in contact with the upper surface of the insulator 254. It is preferable that

[0093] In the transistor 200, a region in which a channel is formed (hereinafter, a channel forming region ) and in the vicinity thereof, oxide 230a, oxide 230b, and oxide 2 30c are laminated, the present invention is not limited to this. For example, a two-layer structure of oxide 230b and oxide 230c, or a laminated structure of four or more layers, In addition, the oxide 230a, the oxide 230b, and the oxide 230 Each of c may have a laminated structure of two or more layers.

[0094] For example, the oxide 230c may be a multilayer structure of a first oxide and a second oxide on the first oxide. In the case of a layered structure, the first oxide has a similar composition to the oxide 230b, and the second oxide The article may have a similar composition to oxide 230a.

[0095] In addition, although the conductor 260 in the transistor 200 has a two-layer structure, The present invention is not limited to this. For example, the conductor 260 may have a single-layer structure. Alternatively, it may have a laminated structure of three or more layers.

[0096] Here, the conductor 260 functions as a gate electrode of the transistor, and the conductors 242a and and the conductor 242b function as a source electrode and a drain electrode, respectively. Thus, the conductor 260 is inserted through the opening in the insulator 280 and through the conductors 242a and 242b. The conductive material 260 and the conductive material 242 are formed so as to be embedded in the region between them. The arrangement of the conductors 242a and 242b is selected to be self-aligned with respect to the openings in the insulator 280. That is, in the transistor 200, the gate electrode is connected to the source electrode and the drain electrode. Therefore, the conductor 260 can be arranged between the conductors 260 and 260 in a self-aligning manner. Since the transistor 200 can be formed without providing a gate, the area occupied by the transistor 200 can be reduced. This allows miniaturization and high integration of semiconductor devices.

[0097] As shown in FIG. 3, the conductor 260 is a conductor 2 provided inside the insulator 250. 60a, and a conductor 260b provided so as to be embedded inside the conductor 260a. It is preferable to have

[0098] The transistor 200 also includes an insulator 214 disposed on a substrate (not shown). 2, an insulator 216 is disposed on the insulator 214, and a conductive layer is disposed so as to be embedded in the insulator 216. A conductor 205 is placed on the insulator 216, and an insulator 222 is placed on the conductor 205. , and an insulator 224 disposed on the insulator 222. Preferably, oxide 230a is disposed over 4.

[0099] In addition, an insulator 274 serving as an interlayer film and an insulator Here, the insulator 274 is preferably disposed between the conductor 260 and the insulator 281. 50, the insulator 254, the insulator 244, the oxide 230c, and the insulator 280. It is preferable that the electrodes are arranged in such a manner that the electrodes are arranged in a substantially rectangular shape.

[0100] The insulators 222, 254, 244, and 274 are hydrogen (e.g., It is preferable that the material has a function of suppressing the diffusion of at least one of hydrogen atoms, hydrogen molecules, etc. For example, the insulators 222, 254, 244, and 274 are insulators. 224, insulator 250, and insulator 280 preferably have a lower hydrogen permeability. , insulator 222, insulator 254, insulator 244, and insulator 274 are resistant to oxygen (e.g., It is preferable that the material has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. For example, the insulators 222, 254, 244, and 274 are insulators. 224 , insulator 250 , and insulator 280 preferably have a lower oxygen permeability.

[0101] Here, the insulator 224, the oxide 230, and the insulator 250 are insulator 280 and insulator 250. The edge 281 is separated by the insulators 254, 244 and 274. Therefore, the insulator 224, the oxide 230, and the insulator 250 are insulated with the insulator 280 and the insulator 240. It is possible to suppress the inclusion of impurities such as hydrogen contained in the insulator 281 and excess oxygen. Cut.

[0102] A conductor 240 (conductor) electrically connected to the transistor 200 and functioning as a plug It is preferable that a conductor 240a and a conductor 240b are provided. The insulator 241 (insulator 241a and insulator 241b) is in contact with the side of the conductor 240 that functions as a That is, the insulator 254, the insulator 244, the insulator 280, the insulator 241b, 74, and an insulator 241 is provided in contact with the inner wall of the opening of the insulator 281. A first conductor of the conductor 240 is provided in contact with the side surface of the body 241, and a second conductor is provided further inward. In this case, the height of the upper surface of the conductor 240 may be set to 40. The height of the upper surface of the insulator 281 can be made approximately the same as that of the conductive layer 281. 2 shows a configuration in which a first conductor of the conductor 240 and a second conductor of the conductor 240 are stacked. However, the present invention is not limited to this. For example, the conductor 240 may be a single layer or It may be configured as a laminated structure of three or more layers. In some cases, ordinal numbers are assigned to indicate the order of occurrence to distinguish them.

[0103] The transistor 200 also includes an oxide 230 (oxide 230a) including a channel formation region. , oxide 230b, and oxide 230c) are metal oxides that function as oxide semiconductors. It is preferable to use an oxide semiconductor for the channel formation region. The transistor 200 using a semiconductor has a very low leakage current (off-state current) in a non-conducting state. ) is small, a semiconductor device with low power consumption can be provided.

[0104] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum or gallium). Sodium, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. In particular, the element M may be an oxide of a metal such as aluminum, gallium, yttrium, or the like. The oxide 230 may be In-Ga oxide, In- Zn oxide may also be used.

[0105] As described above, oxide 230b corresponds to oxide 12, and oxide 230c corresponds to oxide 13. Therefore, the oxide 230b has a c-axis that is approximately perpendicular to the upper surface of the oxide 230b. The oxide 230c has a region in which the oxide 230c is oriented approximately A region in which the c-axis is oriented perpendicular to the side surface of the conductor 242a and a region in which the c-axis is oriented perpendicular to the side surface of the conductor 242a and a region in which the c-axis is oriented so as to be approximately perpendicular to the side surface of the conductor 242b. and a region in which the crystalline silicon is oriented. As with 10a, the on-state current, S value, and frequency characteristics can be improved. The transistor 200, like the transistor 10a described above, has stable electrical characteristics and is reliable. It is possible to improve the quality of life.

[0106] As shown in FIG. 3B, the oxide 230b is formed in the region that does not overlap with the conductor 242. The thickness of the film may be thinner than the thickness of the film in the area overlapping the conductor 242. 2a and the conductor 242b, a part of the upper surface of the oxide 230b is removed. The oxide 230b is formed by depositing a conductive film that becomes the conductor 242 on the upper surface of the oxide 230b. In this way, a region with low resistance may be formed near the interface with the conductive film. A low resistance region located between conductors 242a and 242b on the top surface of oxide 230b. By removing the above, it is possible to prevent a channel from being formed in the region.

[0107] As described above, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, it is possible to provide a semiconductor device having a transistor with high frequency characteristics. Alternatively, the fluctuation of the electrical characteristics can be suppressed, and the electrical characteristics can be stabilized while improving reliability. It is possible to provide a semiconductor device having an improved off-state current. It is possible to provide a semiconductor device having the above structure.

[0108] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0109] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. It is preferable that the conductor 205 is embedded in the insulator 216. It is preferable to improve the flatness of the upper surface of the conductor 205. For example, Roughness (Ra) of 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less This can improve the flatness of the insulator 224 formed on the conductor 205. Preferably, the crystallinity of the oxide 230b and the oxide 230c can be improved.

[0110] Here, the conductor 260 functions as a first gate (also called a top gate) electrode. The conductor 205 may also serve as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be the potential applied to the conductor 260. By changing the Vth of the transistor 200 independently of the potential applied to the transistor 200, In particular, by applying a negative potential to the conductor 205, the transistor By increasing the Vth of the transistor 200 above 0V, it is possible to reduce the off-current. Therefore, applying a negative potential to the conductor 205 increases the current flow rate of the conductor 260 compared to when no negative potential is applied. This can reduce the drain current when the potential applied to is 0V.

[0111] In addition, the conductor 205 is provided to be larger than the channel formation region in the oxide 230. In particular, as shown in FIG. 3C, the conductor 205 is formed in the oxide 230 in the channel width direction. It is preferable that the film is stretched even in the region outside the end intersecting with the acid direction. The conductor 205 and the conductor 26 are disposed on the outer side of the side surface of the oxide 230 in the channel width direction. It is preferable that 0 overlaps with an insulator therebetween.

[0112] With the above-mentioned configuration, the electric field of the conductor 260 having the function of the first gate electrode The oxide 230 is then turned on by the electric field of the conductor 205, which functions as a second gate electrode. The channel forming region can be electrically surrounded by the insulating layer.

[0113] As shown in FIG. 3C, the conductor 205 is extended to function as a wiring. However, the present invention is not limited to this, and a conductive material that functions as a wiring may be provided under the conductive material 205. A body may be provided.

[0114] The conductor 205 is a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as a single layer, it may be formed as a laminated structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0115] In addition, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitric oxide are present under the conductor 205. It has the function of suppressing the diffusion of impurities such as elementary molecules (N2O, NO, NO2, etc.) and copper atoms. Alternatively, a conductive material that is impermeable to the above impurities may be used. The material has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (the oxygen is not allowed to penetrate the material) It is preferable to use a conductor that is less susceptible to impurities or acids. The function of suppressing the diffusion of elements is to suppress either one or all of the above impurities or the above oxygen. The function is to suppress diffusion.

[0116] By using a conductor having a function of suppressing the diffusion of oxygen under the conductor 205, It is possible to prevent the conductor 205 from being oxidized and the conductivity from decreasing. Examples of conductors having a function of controlling the temperature include tantalum, tantalum nitride, ruthenium, and It is preferable to use ruthenium oxide or the like for the first conductive material 205. In terms of the structure, the conductive material may be a single layer or a multilayer.

[0117] The insulator 214 prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. It is preferable that the insulator 21 functions as a barrier insulating film that suppresses the 4 is hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitric oxide molecule (NO, NO , NO2, etc.), and has the function of suppressing the diffusion of impurities such as copper atoms (the above impurities It is preferable to use an insulating material that is not easily damaged. It has a function of suppressing the diffusion of at least one of the oxygen molecules (such as oxygen). ) It is preferable to use an insulating material.

[0118] For example, aluminum oxide or silicon nitride may be used as the insulator 214. This is preferable because impurities such as water or hydrogen are transported from the substrate side to the insulator 214. It is possible to suppress diffusion to the transistor 200 side. The oxygen contained therein can be prevented from diffusing toward the substrate side relative to the insulator 214 .

[0119] In addition, the insulators 216, 280, and 281, which function as interlayer films, are insulating It is preferable that the dielectric constant of the insulating film is lower than that of the insulating film 214. By using a material with a low dielectric constant as the interlayer film, , the parasitic capacitance occurring between the wirings can be reduced. 0, and as the insulator 281, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, carbon and Silicon oxide doped with nitrogen or silicon oxide having vacancies may be used appropriately. stomach.

[0120] The insulators 222 and 224 function as gate insulators.

[0121] Here, it is preferable that the insulator 224 in contact with the oxide 230 is heated to release oxygen. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulator 224 may be made of silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. Therefore, the reliability of the transistor 200 can be improved.

[0122] Specifically, the insulator 224 is made of an oxide material from which some oxygen is released when heated. The oxide that releases oxygen by heating is called TDS (Thermal Dynamics) oxide. The oxygen in terms of oxygen atoms was analyzed by Esorption Spectroscopy. The amount of desorption is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 at oms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 That's all, is 3.0 x 10 20 atoms / cm 3 The oxide film is as above. The surface temperature of the film during deposition is 100°C to 700°C, or 100°C to 40°C. A range of 0°C or less is preferred.

[0123] In addition, the film thickness of the region not overlapping with the oxide 230b is thinner than the film thickness of the other region. In particular, as shown in FIG. 3C, the insulator 224 does not overlap with the insulator 254. Moreover, the thickness of the region not overlapping with the oxide 230b is significantly thinner than the thickness of the other regions. In the insulator 224, the oxide 230b does not overlap with the insulator 254. The thickness of the region not overlapping with the film is preferably a thickness that allows the oxygen to be diffused sufficiently.

[0124] The insulator 222, like the insulator 214, is a material that prevents impurities such as water or hydrogen from entering the substrate. It is preferable that the insulating film functions as a barrier insulating film that prevents the inclusion of the metal oxide in the transistor 200. For example, the insulator 222 preferably has a lower hydrogen permeability than the insulator 224. The insulator 222, the insulator 254, the insulator 244, and the insulator 274 form the insulator 224, By surrounding the oxide 230 and the insulator 250, water or hydrogen and the like are prevented from entering from the outside. Impurities can be prevented from entering the transistor 200.

[0125] Further, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). For example, The insulator 222 preferably has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of atoms and impurities, so that the oxygen contained in the oxide 230 is diffused to the substrate side. In addition, the conductor 205 is preferably a material having a thickness of 100 nm or less, since it can reduce diffusion to the insulator 224 or the This can prevent the oxide 230 from reacting with the oxygen contained therein.

[0126] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Insulators containing oxides include aluminum oxide, hafnium oxide, aluminum and hafnium oxide, and It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The emission of hydrogen and the incorporation of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200 are prevented. It acts as a suppressing layer.

[0127] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, etc. may be added to these insulators. tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0128] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 (BST) or (Ba,Sr)TiO3 (BST). As miniaturization and high integration of transistors progresses, If the gate insulator is made thinner, problems such as leakage current may occur. By using a high-k material as the insulator, the physical thickness can be maintained while This makes it possible to reduce the gate potential during transistor operation.

[0129] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, and may be made of different materials. For example, an insulator similar to the insulator 224 may be provided under the insulator 222. stomach.

[0130] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b on the oxide 230a. The oxide 230c is located on the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0131] The oxide 230 has a layered structure made of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the constituent elements The atomic ratio of element M in the oxide 230b is the atomic ratio of element M in the metal oxide in the constituent elements. It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the metal oxide used for the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element In. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In is larger than that of the element M in the metal oxide. The oxide 230c is a metal oxide that can be used for the oxide 230a or the oxide 230b. Things can be used.

[0132] As shown in FIG. 1, the oxide 230b and the oxide 230c have crystallinity. It is preferable to use CAAC-OS, and it is particularly preferable to use CAAC-OS. Crystalline oxides have few impurities and defects (such as oxygen vacancies), and are highly crystalline and dense. Therefore, the oxide 230b is formed by the source electrode or the drain electrode. This makes it possible to suppress the extraction of oxygen from the oxide 2 even when heat treatment is performed. Since the oxygen extraction from 30b can be reduced, the transistor 200 can be manufactured It is stable against high temperatures (so-called thermal budget) in

[0133] In addition, the energy of the conduction band minimum of the oxide 230a and the oxide 230c is It is preferable that the energy of the oxide is higher than the minimum energy of the conduction band of 0b. The electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b. In this case, the oxide 230c can be used for the oxide 230a. It is preferable to use a metal oxide. Specifically, the metal oxide used for the oxide 230c is In the metal oxide used for the oxide 230b, the atomic ratio of element M in the constituent elements is It is preferable that the atomic ratio of the element M in the constituent elements is larger than that of the oxide 230c. In the metal oxide used, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In in the metal oxide is larger than that of element In. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is In the metal oxide used in 230c, the atomic ratio of In to element M is greater than that preferable.

[0134] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, The energy level of the conduction band minimum changes gradually. The energy level of the conduction band minimum at the junction of the oxide 230c and the oxide 230b is In order to achieve this, the oxide At the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c In this case, the defect level density of the mixed layer formed in the step (b) is preferably reduced.

[0135] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c, By having a common element other than oxygen (as the main component), a mixed layer with a low defect level density is formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide The material 230a and the oxide 230c are In-Ga-Zn oxide, Ga-Zn oxide, Gallium oxide or the like may be used. The oxide 230c may have a layered structure. For example, a mixture of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide. A laminated structure, or an In-Ga-Zn oxide and a gallium oxide layer on the In-Ga-Zn oxide. In other words, a laminated structure of In-Ga-Zn oxide and In A stacked structure with an oxide that does not contain the above may be used as the oxide 230c.

[0136] Specifically, the oxide 230a is In:Ga:Zn=1:3:4 [atomic ratio], Alternatively, a metal oxide having an atomic ratio of 1:1:0.5 may be used. In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] gold The oxide 230c may be a metal oxide having a composition of In:Ga:Zn=1:3:4. [Atomic ratio], In:Ga:Zn=4:2:3 [Atomic ratio], Ga:Zn=2:1 [Atomic ratio] In addition, a metal oxide having an atomic ratio of Ga:Zn=2:5 may be used. A specific example of the compound 230c having a layered structure is In:Ga:Zn=4:2:3[ In:Ga:Zn=1:3:4 [atomic ratio] and In:Ga:Z A stacked structure of n=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], In: Layered structure of Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio] Examples include a layered structure with In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide. can be done.

[0137] At this time, the main path of the carriers is the oxide 230b and the vicinity of the interface. By configuring the oxide 230a and the oxide 230c as described above, the oxide 230a and the oxide 230 b and the interface between oxide 230b and oxide 230c. Therefore, the effect of interface scattering on carrier conduction is reduced, and The transistor 200 can obtain a high on-current and a high frequency characteristic. When the oxide 230c is formed into a laminated structure, the interface between the oxide 230b and the oxide 230c is In addition to the effect of lowering the defect level density in the oxide 230c, the constituent elements of the oxide 230c have the insulating It is expected that the oxide 230c is prevented from diffusing into the body 250. More specifically, In order to form a laminated structure and to position an oxide not containing In above the laminated structure, an insulator 25 The insulator 250 functions as a gate insulator. Therefore, if In diffuses, the transistor characteristics will be poor. By forming 230c into a laminated structure, it is possible to provide a highly reliable semiconductor device. .

[0138] The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. For example, the metal oxide that will be the channel forming region of the oxide 230 is a metal oxide having a band gap of 2 It is preferable to use a van der Waals ion beam having an energy of 2.5 eV or more, preferably 2.5 eV or more. By using metal oxide with a wide band gap, the off-current of a transistor can be reduced. By using such a transistor, a semiconductor device with low power consumption can be provided. do.

[0139] On the oxide 230b, a conductor 242 is formed, which functions as a source electrode and a drain electrode. (Conductor 242a and conductor 242b) are provided. The conductor 242 is made of aluminum. Aluminum, Chromium, Copper, Silver, Gold, Platinum, Tantalum, Nickel, Titanium, Molybdenum, Tan Gusten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, Choose from beryllium, indium, ruthenium, iridium, strontium, and lanthanum. or an alloy containing the above-mentioned metal elements or a combination of the above-mentioned metal elements. For example, tantalum nitride, titanium nitride, tungsten nitride, etc. titanium and aluminum nitrides, tantalum and aluminum nitrides, ruthenium oxides Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing titanium. Nitrides containing tantalum and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide , ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel Oxides are conductive materials that are resistant to oxidation or that maintain their conductivity even when they absorb oxygen. Therefore, it is preferable.

[0140] By providing the conductor 242 so as to be in contact with the oxide 230, the conductor of the oxide 230 In the vicinity of the conductor 242 of the oxide 230, the oxygen concentration may decrease. In the vicinity of 2, a metal compound containing a metal contained in the conductor 242 and a component of the oxide 230 is formed. In such a case, a layer of oxide 230 may be formed in the area adjacent to conductor 242. In this region, the carrier density increases and the region becomes a low resistance region.

[0141] Here, the area between the conductor 242a and the conductor 242b overlaps the opening of the insulator 280. As a result, the conductor 260 is formed between the conductor 242a and the conductor 242b. It can be arranged in a consistent manner.

[0142] The insulator 250 functions as a gate insulator. The insulator 250 is formed on the oxide 230c. The insulator 250 is preferably disposed in contact with the surface. , silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and oxide doped with carbon. Silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies were used. In particular, silicon oxide and silicon oxynitride are stable against heat. Therefore, it is preferable.

[0143] The insulator 250, like the insulator 224, is a material that is capable of preventing impurities such as water or hydrogen from being present in the insulator 250. It is preferable that the concentration is reduced. The thickness of the insulator 250 is 1 nm or more and 20 nm or less. It is preferable to set the above.

[0144] A metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the material suppresses oxygen diffusion from the insulator 250 to the conductor 260. This makes it possible to suppress oxidation of the conductor 260 due to oxygen in the insulator 250 .

[0145] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant, as the oxide. By making the base insulator have a laminated structure of the insulator 250 and the metal oxide, the base insulator is stable against heat. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. do.

[0146] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tantalum, tin, titanium, tantalum, nickel, germanium, magnesium, etc. The metal oxide may contain one or more metals selected from the following: Aluminum oxide, an insulator containing oxides of either or both of aluminum and hafnium Aluminum, hafnium oxide, oxides containing aluminum and hafnium (hafnium oxide) It is preferable to use a material such as a laminate.

[0147] Although the conductor 260 is shown as having a two-layer structure in FIG. 3, it may have a single layer structure or a structure having three or more layers. The above laminated structure may also be used.

[0148] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, an oxide, or the like. It has the function of suppressing the diffusion of impurities such as nitrogen molecules (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use a conductor that can absorb oxygen (e.g., oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material having at least one) function of suppressing the diffusion of the metal.

[0149] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can suppress the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, nitride, and the like. It is preferable to use tantalum chloride, ruthenium, ruthenium oxide, or the like.

[0150] The conductor 260b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b may be a laminated material. For example, a laminated structure of titanium, titanium nitride and the conductive material may be used. .

[0151] In addition, as shown in FIG. 3(A)(C), the area of ​​the oxide 230b that does not overlap with the conductor 242 In other words, in the channel forming region of the oxide 230, the side of the oxide 230 is conductive. This allows the gate electrode to function as a first gate electrode. The electric field of the conductive material 260, which functions as a conductive material, can be easily applied to the side surface of the oxide 230. This increases the on-current of the transistor 200 and improves the frequency characteristics.

[0152] The insulator 254, like the insulator 214, is a material that prevents impurities such as water or hydrogen from entering the insulator 2. 80 side into the transistor 200. For example, it is preferred that the insulator 254 has a lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIG. 3B and FIG. 3C, the insulator 254 is formed on the side of the oxide 230c, The top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the oxide 230a, It is preferable that the insulating layer 224 contacts the side surface of the insulating layer 230b and the top surface of the insulating layer 224. By forming the insulator 280, hydrogen contained in the insulator 280 is transferred to the conductor 242a, the conductor 242b, and the oxide. 230a, oxide 230b, and oxide 230 from the top or sides of insulator 224. It is possible to suppress the intrusion of

[0153] Further, the insulator 254 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). For example, Preferably, the rim 254 has a lower oxygen permeability than the insulator 280 or the insulator 224 .

[0154] The insulator 254 is preferably formed by sputtering. The insulating film of the insulator 224 is formed by depositing the insulating film by a sputtering method in an atmosphere containing oxygen. Oxygen can be added to the area adjacent to the body 254. This allows oxygen to be released from that area. Oxygen can be supplied to the oxide 230 through the insulator 224. 54 has the function of suppressing the upward diffusion of oxygen, so that oxygen is isolated from the oxide 230. The insulator 222 can prevent oxygen from diffusing downward to the insulator 280. By having the function of suppressing diffusion, it is possible to prevent oxygen from diffusing from the oxide 230 to the substrate side. In this way, oxygen is supplied to the channel forming region of the oxide 230. This reduces the oxygen vacancy in the oxide 230 and suppresses the normally-on state of the transistor. It can be controlled.

[0155] The insulator 254 may be, for example, an oxide of one or both of aluminum and hafnium. It is preferable to form a film of an insulator containing an oxide of aluminum or hafnium. Insulators containing both oxides include aluminum oxide, hafnium oxide, aluminum and It is preferable to use oxides containing hafnium (hafnium aluminate), etc.

[0156] The insulator 244, like the insulator 214, is a material that prevents impurities such as water or hydrogen from entering the insulator 2. 80 side into the transistor 200. For example, it is preferred that the insulator 244 has a lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIG. 3(B)(C), the insulator 244 is arranged so as to be in contact with the insulator 254. It is preferable that the insulator 280 is disposed in such a manner. The atoms penetrate into the oxide 230 from the sides of the conductor 260, the oxide 230c, and the insulator 250. It is possible to suppress the

[0157] In this manner, the insulator 254 and the insulator 244 having a barrier property against hydrogen By covering the insulator 224, the insulator 250, and the oxide 230, the insulator 280 provides an insulating The insulator 224, the oxide 230, and the insulator 244 are connected by the edge 254 or the insulator 244. 50. This prevents impurities such as hydrogen from entering the transistor 200 from the outside. , the insulator 224, the insulator 250, and the oxide 230 are inhibited from penetrating therein. The transistor 200 can be provided with good electrical characteristics and reliability.

[0158] Further, the insulator 244 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). For example, The insulator 244 preferably has a lower oxygen permeability than the insulator 224. By having a function of suppressing the diffusion of oxygen, the conductor 260 can prevent the diffusion of oxygen from the insulator 280. It is possible to suppress the reaction.

[0159] The insulator 244 may be, for example, an insulator containing aluminum nitride. The body 244 has a composition formula of AlNx (where x is a real number greater than 0 and less than or equal to 2, preferably, x is It is preferable to use a nitride insulator that satisfies the above condition (a real number greater than 0.5 and less than or equal to 1.5). This makes it possible to produce a film with excellent insulation and thermal conductivity, which is This can improve the dissipation of heat generated when the motor 200 is driven. Aluminum titanium nitride, titanium nitride, etc. can also be used as the material. By forming a film using the sputtering method, the film formation gas contains strong oxidizing agents such as oxygen or ozone. This is preferable because the film can be formed without using any gas. Silicon oxide or the like can also be used.

[0160] The insulator 244 may be, for example, aluminum or hafnium. It is preferable to form an insulator containing an oxide of either aluminum or hafnium. Or, as an insulator containing both oxides, aluminum oxide, hafnium oxide, aluminum It is preferable to use oxides containing hafnium and hafnium (hafnium aluminate). In this case, the insulator 244 is preferably deposited using an ALD method. Since this method is a film formation method with good coating properties, the unevenness of the insulator 244 does not cause any step or discontinuity. This can prevent the data from being leaked.

[0161] The insulator 280 is connected to the insulator 224, the oxide 2, through the insulator 244 and the insulator 254. 30 and the conductor 242. For example, the insulator 280 may be silicon oxide. , silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon Silicon oxide doped with carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxide and silicon oxynitride are thermally In particular, silicon oxide, silicon oxynitride, and oxide having vacancies are preferred. Materials such as silicon can easily form regions containing oxygen that desorbs when heated. This is preferable.

[0162] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. In addition, the top surface of the insulator 280 may be planarized.

[0163] The insulator 274, like the insulator 214, is designed to prevent impurities such as water or hydrogen from entering from above. It is preferable that the insulating film functions as a barrier insulating film that prevents the insulator 280 from being mixed with the insulating material. The body 274 may be, for example, an insulator that can be used for the insulators 214 and 254. can be used.

[0164] In addition, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. The insulator 281, like the insulator 224, has a low impurity concentration such as water or hydrogen in the film. is preferably reduced.

[0165] Also, the insulating material 281, the insulating material 274, the insulating material 280, and the insulating material 244 are formed The conductor 240a and the conductor 240b are disposed in the opening. The conductor 240a and the conductor 240b are disposed opposite each other with the conductor 260 in between. The height of the upper surface of 240b may be flush with the upper surface of the insulator 281.

[0166] In addition, the insulators 281, 274, 280, 254, and 244 An insulator 241a is provided in contact with the inner wall of the opening, and a conductor 240a is provided in contact with the side surface of the insulator 241a. A first conductor is formed. A conductor 242a is formed on at least a part of the bottom of the opening. The conductor 240a is in contact with the conductor 242a. The insulating body 274, the insulator 280, the insulator 254 and the insulator 244 are in contact with the inner walls of the openings. A first conductor of the conductor 240b is formed in contact with the side surface of the first conductor 241b. The conductor 242b is located at least partially on the bottom of the opening, and the conductor 240 b contacts the conductor 242b.

[0167] The conductors 240a and 240b are mainly made of tungsten, copper, or aluminum. It is preferable to use a conductive material having the following components: 0b may have a laminated structure.

[0168] In addition, when the conductor 240 has a laminated structure, the oxide 230a, the oxide 230b, the conductor 242, insulator 254, insulator 244, insulator 280, insulator 274, and insulator 281. The conductor to be used is the above-mentioned conductive material having a function of suppressing the diffusion of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, etc. It is preferable to use ruthenium or ruthenium oxide. Also, water or hydrogen etc. The conductive material having the function of suppressing the diffusion of impurities may be used in a single layer or a multilayer structure. By using the conductive material, the oxygen added to the insulator 280 is converted into the conductor 240a and It is possible to prevent the water from being absorbed by the conductor 240b. Alternatively, impurities such as hydrogen may enter the oxide 230 through the conductor 240a and the conductor 240b. It is possible to suppress the contamination of the

[0169] The insulators 241a and 241b may be used, for example, as the insulator 244. The insulator 241a and the insulator 241b are made of an insulator 254. Since the insulator 244 is provided in contact with the insulator 244, water or hydrogen or the like can be prevented from entering the insulator 280 or the like. Impurities are prevented from entering the oxide 230 through the conductors 240a and 240b. In addition, oxygen contained in the insulator 280 can be prevented from This can prevent it from being absorbed by 240b.

[0170] Although not shown, a conductive material 240a and a conductive material 240b are disposed in contact with each other on the upper surface thereof. A conductor functioning as a line may be disposed. The conductor functioning as a wiring may be tungsten. It is preferable to use a conductive material containing copper or aluminum as a main component. The conductor may be a laminated structure, for example, a layer of titanium, titanium nitride, and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator. good.

[0171] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0172] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or A conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, and silicon substrates. Fire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), resin substrate The semiconductor substrate may be, for example, a semiconductor such as silicon or germanium. Solid substrate, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of zinc oxide, gallium oxide, etc. A semiconductor substrate having an insulating region inside the substrate, such as SOI (Silicon On Insulator) Conductive substrates include graphite substrates, metal substrates, and alloy substrates. Substrates with metal nitrides, conductive resin substrates, etc. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, A substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate Alternatively, a substrate having an element provided thereon may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a recording element, Memory elements, etc.

[0173] <<Insulators>> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0174] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. The material should be selected accordingly.

[0175] Insulators with high relative dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. Oxides containing aluminum, aluminum and hafnium, and oxides containing aluminum and hafnium oxide-nitride having silicon and hafnium; oxide-nitride having silicon and hafnium; Examples of suitable materials include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0176] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, Silicon oxide doped with carbon and nitrogen, silicon oxide with voids, or resin, etc. be.

[0177] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. Insulators having a function of controlling the temperature (insulator 214, insulator 222, insulator 254, insulator 244 , and insulator 274, etc.) to stabilize the electrical characteristics of the transistor. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, is, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon Nitrogen, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, laminium Insulators containing nickel, neodymium, hafnium, or tantalum are used in single or multilayered configurations. Specifically, it has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Insulators include aluminum oxide, magnesium oxide, gallium oxide, and germanium oxide. , yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide , or metal oxides such as tantalum oxide, aluminum nitride, titanium aluminum nitride, Metal nitrides such as titanium nitride, silicon oxynitride or silicon nitride can be used. do.

[0178] In addition, the insulator that functions as the gate insulator has a region that contains oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, The oxygen deficiency of 230 can be compensated for.

[0179] <<Conductors>> Conductive materials include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from aluminum, lanthanum, etc., or alloys containing the above-mentioned metal elements It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel. Tantalum, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize or absorb oxygen. It is preferable because it is a material that maintains its conductivity even if it is oxidized. In addition, it does not contain impurity elements such as phosphorus. Highly conductive semiconductors, such as polycrystalline silicon, nickel silicide, etc. Silicide may also be used.

[0180] In addition, a plurality of conductive layers made of the above materials may be laminated. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated material that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen is In addition, the above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure in which the conductive material containing the element is combined with the conductive material containing the element may be used.

[0181] In the case where an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminate structure in which an oxygen-containing conductive material is used as the It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0182] In particular, the metal oxide in which the channel is formed is a conductor that functions as a gate electrode. It is preferable to use a conductive material containing oxygen and a metal element contained in the metal. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. In addition, a conductive material containing nitrogen such as indium tin oxide or tungsten oxide may be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may be used. By using such a material, the channel is formed In some cases, hydrogen can be captured from the metal oxide that is insulated from the outer In some cases, it may be possible to capture hydrogen that is mixed in from the surroundings, etc.

[0183] <<Metal oxides>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0184] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, and zinc are preferably included. It is preferable that the alloy contains boron, titanium, iron, or the like. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or Or multiple types may be included.

[0185] Here, the metal oxide is an In-M-Zn oxide having indium, element M and zinc. The element M can be aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, halide Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, combinations of the aforementioned elements may be used.

[0186] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0187] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As non-single crystal oxide semiconductors, for example, CAAC-OS, polycrystalline Nanocrystalline oxide semiconductor, nc-OS conductor), pseudo-amorphous oxide semiconductor (a-like OS) us-like oxide semiconductor, and amorphous oxide semiconductor There are bodies, etc.

[0188] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0189] In addition, when an alkali metal or alkaline earth metal is contained in a metal oxide, a defect level is formed. Therefore, alkali metals or alkaline earth metals may form a carrier. A transistor that uses a metal oxide containing metals in the channel formation region is a normally-on transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxide Specifically, it is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. Potassium metal or alkaline earth metal concentration (Secondary Ion Mass Spectroscopy (SIMS) The concentration obtained by 1 ×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Below do.

[0190] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the carrier In some cases, hydrogen atoms are formed by bonding with oxygen atoms that bond with metal atoms. Therefore, it is recommended to use metal oxides that contain hydrogen. Such a transistor is likely to have normally-on characteristics.

[0191] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. is the hydrogen concentration obtained by SIMS in metal oxides, expressed as 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5×1 0 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. By doing so, it is possible to impart stable electrical characteristics.

[0192] It is preferable to use a thin film with high crystallinity as the metal oxide used as the semiconductor of a transistor. By using the thin film, the stability or reliability of the transistor can be improved. The thin film may be, for example, a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, thin films of single crystal metal oxides or thin films of polycrystalline metal oxides are Formation on a substrate requires high temperature or laser heating steps. This increases the cost of the process and also reduces the throughput.

[0193] In 2009, the In-Ga-Zn oxide with CAAC structure (CAAC-IGZO) was developed. The discovery of the compound 1001, which is called "the compound 1001", has been reported in Non-Patent Document 1 and Non-Patent Document 2. CAAC-IGZO has a c-axis orientation, the grain boundaries are not clearly observed, and the low It has been reported that it is possible to form a thin film on a substrate at low temperatures. The transistors made using this method have been reported to have excellent electrical properties and reliability.

[0194] In 2013, the company also developed an In-Ga-Zn oxide (nc-IGZO) with an nc structure. (See Non-Patent Document 3.) Here, nc-IGZO is a microscopic area The atomic arrangement has periodicity in the region (for example, the region of 1 nm to 3 nm), and different It has been reported that there is no regularity in the crystal orientation between the domains.

[0195] In Non-Patent Documents 4 and 5, the above CAAC-IGZO, nc-IGZO, The average crystal size of IGZO and low-crystalline IGZO thin films was measured by electron beam irradiation. The graph shows the change in the crystallinity of the thin film of IGZO before it was irradiated with an electron beam. Even in thin films, IGZO with a crystallinity of about 1 nm has been observed. In this study, completely amorphous structure In addition, the presence of IGZO, which has low crystallinity, was not confirmed. Compared with the thin films of CAAC-IGZO and nc-IGZO, the thin films of CAAC-IGZO and nc-IGZO were irradiated with electron beams. Therefore, CAA is a promising semiconductor for transistors. It is preferable to use a C-IGZO thin film or an nc-IGZO thin film.

[0196] Transistors using metal oxide have extremely low leakage current when off. Specifically, the off-state current per 1 μm of the transistor channel width is yA / μm (10 -2 4 For example, the non-patent document 6 shows that the order of the capacitance is 100 nm. The low leakage current of the transistors used in these chips is utilized to develop low-power CPUs. (See Non-Patent Document 7).

[0197] In addition, the leakage current of a transistor using a metal oxide is low. The application of transistors to display devices has been reported (see Non-Patent Document 8). In this case, the displayed image changes several dozen times per second. The number is called the refresh rate. The refresh rate is also called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, can cause eye fatigue. This is thought to be the cause. Therefore, the refresh rate of the display device is lowered to improve image quality. It has been proposed to reduce the number of times the display is rewritten. By driving the display device, it is possible to reduce the power consumption of the display device. This is called idle stop (IDS) drive.

[0198] The discovery of the CAAC and nc structures led to the discovery of metal oxides with the CAAC or nc structures. The electrical characteristics and reliability of the transistor using the material are improved, and the manufacturing process is reduced in cost. This contributes to lowering the leakage current and improving throughput. Taking advantage of these characteristics, research is being conducted into the application of these transistors to display devices and LSIs. is.

[0199] <Method for manufacturing semiconductor device> Next, a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is shown in FIG. The manufacturing method will be described with reference to FIGS. (A) shows a top view. Also, (B) of each figure shows the area indicated by the dashed line A1-A2 shown in (A). 1 is a cross-sectional view of a portion of the transistor 200 in the channel length direction. Also, (C) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in (A). The figure also shows a cross-sectional view of the transistor 200 in the channel width direction. In the plan view, some elements are omitted for clarity of the drawing.

[0200] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The deposition of 214 was carried out by sputtering, chemical vapor deposition (CVD), and or Deposition method, Molecular Beam Epitaxy (MBE) Beam Epitaxy method, Pulsed Laser Deposition (PLD) Deposition method or ALD (Atomic Layer Deposition) method This can be done using the tion method, etc.

[0201] The CVD method is a process that uses plasma (PECVD). Enhanced CVD method, Thermal CVD (TCVD) These methods are further classified into the VD method, which uses light, and the Photo CVD method, which uses light. Depending on the source gas, metal CVD (MCVD: Metal CVD) method, metal organic CVD method (MOCVD: Metal Organic CVD) method.

[0202] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc., contained in a semiconductor device. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage occurs. Since the thermal CVD method does not require any heat treatment, the yield of the semiconductor device can be increased. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0203] In addition, the ALD method utilizes the self-regulating nature of atoms to deposit atoms one layer at a time. This allows for extremely thin film deposition, film deposition on structures with high aspect ratios, and pinhole It is possible to form films with few defects such as holes, excellent coating properties, and low temperature film formation. In addition, the ALD method includes a plasma-assisted deposition method called PEALD ( This includes the Plasma Enhanced ALD method. This may be preferable because it allows film formation at a lower temperature. Some of the films contain impurities such as carbon. For this reason, the films deposited by the ALD method are In comparison with the film formed by the film forming method of the first embodiment, the film may contain a large amount of impurities such as carbon. The quantity of impurities is determined by X-ray photoelectron spectroscopy (XPS). This can be done using NMR Spectroscopy.

[0204] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it ideal for achieving high aspect ratios. However, the ALD method is relatively slow in forming a film. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a faster deposition rate. may be preferred.

[0205] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, the film formation By changing the flow rate ratio of the source gas while heating, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transportation or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0206] In this embodiment, the insulator 214 is formed of aluminum oxide by sputtering. The insulator 214 may have a multi-layer structure. For example, a sputtering method is used. Then, an aluminum oxide film is formed by the ALD method. Alternatively, a film of aluminum may be formed by the ALD method. A film of aluminum oxide is formed on the aluminum oxide by a sputtering method. A membrane structure may also be used.

[0207] Next, a conductive film that will become the conductor 205 is formed on the insulator 214. The deposition of the conductive film is performed by sputtering, CVD, MBE, PLD, or ALD. The conductive film that becomes the conductor 205 may be a multi-layer film. In this embodiment, a tungsten film is formed as the conductive film to be the conductor 205.

[0208] Next, the conductive film that becomes the conductor 205 is processed by lithography. Form.

[0209] In the lithography method, first, the resist is exposed through a mask. The resist mask is formed by removing or leaving the resist-removed area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. For example, KrF excimer laser light, ArF excimer laser light, Laser light, EUV (Extreme Ultraviolet) light, etc. are used to A resist mask can be formed by exposing the photoresist to light. A liquid immersion technique may be used in which the substrate is filled with liquid (e.g., water) and exposed to light. Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not necessary. The resist mask can be removed by ashing or the like. Which dry etching process is performed, which wet etching process is performed, and which dry etching process is performed After the treatment, wet etching is performed, or after the treatment, dry etching is performed. It is possible to carry out the filtering process.

[0210] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating layer that is a hard mask material is formed on the conductive film that is to be the conductor 205. An insulating film and a conductive film are formed, a resist mask is formed on the insulating film and a hard mask material is etched. By this etching, a hard mask of a desired shape can be formed. The etching of the conductive film may be performed after removing the resist mask, or after removing the resist mask. In the latter case, the resist mask may be lost during etching. After etching the conductive film that becomes the conductor 205, the hard mask is removed by etching. On the other hand, if the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, If it is possible to do so, it is not necessary to remove the hard mask.

[0211] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. : Capacitively Coupled Plasma (CAP) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power source may be applied to one of the parallel plate type electrodes. A configuration in which a plurality of different high frequency power sources are applied to the electrodes may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching apparatus or the like can be used.

[0212] Next, an insulating film that becomes the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film that becomes the body 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. In this embodiment, the insulating layer 216 is formed by depositing an insulating film on the insulating layer 216. The film is made of silicon oxide by the CVD method.

[0213] Here, the thickness of the insulating film that becomes the insulator 216 is preferably equal to or greater than the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film that becomes the insulator 216 is In this embodiment, the thickness of the conductor 205 is set to 150 nm, and the insulating The thickness of the insulating film that becomes the body 216 is set to 350 nm.

[0214] Next, the insulating film that will become the insulator 216 is subjected to CMP (chemical mechanical polishing). By carrying out a polishing process, a part of the insulating film that will become the insulator 216 is removed, The surface of the conductor 205 is exposed. This exposes the insulator 216 and the conductor 205, both of which have a flat upper surface. 205 can be formed (see FIG. 4). By improving the flatness, the oxide 230b and the oxide 230c are formed by the CAAC-O The crystallinity of S can be improved.

[0215] It should be noted that the method for producing the insulator 216 and the conductor 205 is not limited to the above. For example, an insulating film that will become the insulator 216 is formed on the insulator 214, and an opening is provided in the insulating film. A conductor 205 may be formed so as to be embedded in the opening.

[0216] Next, the insulator 222 is formed on the insulator 216 and the conductor 205. As the insulating layer, an insulator containing oxide of one or both of aluminum and hafnium is formed. In addition, the insulator containing oxide of either or both of aluminum and hafnium is As examples, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium It is preferable to use aluminum and hafnium aluminate. Insulators containing one or both oxides of aluminum provide excellent barrier properties against oxygen, hydrogen, and water. The insulator 222 has a barrier property against hydrogen and water, so that the transistor Hydrogen and water contained in the structure provided around the rotor 200 pass through the insulator 222. The inward diffusion of the transistor 200 is suppressed, and the generation of oxygen vacancies in the oxide 230 is suppressed. can be suppressed.

[0217] The insulator 222 is formed by sputtering, CVD, MBE, PLD, or A. This can be done using the LD method or the like.

[0218] Next, an insulating film that will become the insulator 224 is formed on the insulator 222. The coating is formed by sputtering, CVD, MBE, PLD, or ALD. This can be done using

[0219] Subsequently, it is preferable to carry out a heat treatment. The heat treatment is preferably carried out at a temperature of 250° C. or more and 650° C. or less. The temperature is preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower. Heat treatment should be performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing oxidizing gas at less than 10 ppm. The heat treatment is carried out in an atmosphere containing 1% or more, or 10% or more. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere, followed by desorption. To compensate for the lost oxygen, an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more Heat treatment may be carried out in air.

[0220] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400° C. after the insulator 224 is formed. The heat treatment is carried out for one hour at a temperature of 100° C. The water and hydrogen contained in the insulator 224 are removed by the heat treatment. In addition, the heat treatment can be performed after the formation of the insulator 222. It can be done at any time.

[0221] Here, in order to form an excess oxygen region in the insulator 224, a plasma containing oxygen is used under reduced pressure. The oxygen-containing plasma treatment may be, for example, a high-density plasma treatment using microwaves. It is preferable to use a device having a power source that generates plasma. Alternatively, RF ( The plasma may have a power source that applies a high-density plasma. By applying RF to the substrate, high density oxygen radicals can be generated. In this way, oxygen radicals generated by the high-density plasma are efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, In order to compensate for the desorbed oxygen, a plasma treatment including oxygen may be performed. By appropriately selecting the processing conditions, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, the heat treatment is not necessary.

[0222] Next, on the insulator 224, an oxide film 230A which becomes an oxide 230a and an oxide film 230b which becomes an oxide 230b are formed. Then, an oxide film 230B that will become the conductor 242 and a conductive film 242A that will become the conductor 242 are formed in this order (see FIG. 4). It is preferable that the oxide film be formed continuously without exposing it to the air. By forming the film without exposing the oxide film 230A and the oxide film 230B to the air, the oxide film 230A and the oxide film 230B are protected from the air environment. The oxide film 230A and the oxide film 230B can be prevented from being adhered to the oxide film 230A. The vicinity of the interface with the substrate can be kept clean.

[0223] The oxide film 230A, the oxide film 230B, and the conductive film 242A are formed by sputtering. This can be performed using a VD method, an MBE method, a PLD method, an ALD method, or the like.

[0224] For example, the oxide film 230A and the oxide film 230B are formed by a sputtering method. In this case, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed is reduced. In addition, when the oxide film is formed by sputtering, In this case, the above-mentioned In-M-Zn oxide target can be used.

[0225] In particular, when the oxide film 230A is formed, a part of the oxygen contained in the sputtering gas becomes an insulator. Therefore, the oxide film 230A may be sputtered with the oxide gas 224. The percentage of oxygen contained in the gas should be 70% or more, preferably 80% or more, and more preferably 100%. Good.

[0226] In addition, when the oxide film 230B is formed by a sputtering method, the oxide film 230B is formed by sputtering. The ratio of oxygen to be added is set to 1% or more and 30% or less, preferably 5% or more and 20% or less. The oxygen-deficient oxide semiconductor is formed in the channel formation region. The transistors used in the above region have a relatively high field effect mobility. By performing the film formation while However, one embodiment of the present invention is not limited to this. The oxide film 230B is formed by a sputtering method. In this case, the ratio of oxygen contained in the sputtering gas is preferably more than 30% and less than 100%. If the film is formed with a concentration of 70% or more and 100% or less, an oxygen-excess oxide semiconductor is formed. A transistor using an oxygen-excess oxide semiconductor for a channel formation region has a relatively high Reliability is gained.

[0227] In this embodiment, the oxide film 230A is formed by sputtering In:Ga: Zn=1:1:0.5[atomic ratio] (2:2:1[atomic ratio]), or 1:3:4[ The oxide film 230B is formed by sputtering a target having a ratio of 1:1 to 1:1. The GaN-GaAs / ZnAlN alloy was grown by the GaN-GaAs / ZnAlN alloy using a target with an atomic ratio of In:Ga:Zn=4:2:4.1. By appropriately selecting the film formation conditions and atomic ratio, each oxide film can be formed in a thickness of 200 nm. It is advisable to shape it according to the characteristics desired for 30.

[0228] In addition, in forming the oxide film 230A and the oxide film 230B, the sputtering gas is high purity. For example, oxygen gas and rare gases used as sputtering gases are In this case, a gas that has been highly purified to a dew point of -60°C or less, preferably -100°C or less, is used. By using a purified sputtering gas to form the film, moisture and other substances are not absorbed into the oxide 230. It is possible to prevent intrusion as much as possible.

[0229] In addition, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, It is preferable to remove as much moisture as possible from the film-forming chamber of the deposition apparatus. A suction-type vacuum exhaust pump such as a Lyopump is used to create a high vacuum (5×10 - 7 Pa to 1×10 -4 It is preferable to evacuate the gas to a pressure of about 1 Pa. Gas molecules equivalent to H2O (m / z=18) in the deposition chamber during standby of the deposition equipment The partial pressure of the gas molecules is 1×10 -4 Pa or less, preferably 5×10 -5 Pa or less is preferred.

[0230] Next, a heat treatment may be performed. The heat treatment may be performed under the above-mentioned heat treatment conditions. By the heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B are removed. In this embodiment, the wafer is heated at 400° C. in a nitrogen atmosphere. After one hour of treatment, the sample was treated in an oxygen atmosphere at 400°C for one hour. cormorant.

[0231] Next, the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into islands. The substrate 230a, the oxide 230b and the conductive layer 242B are formed. As a result, the thickness of the insulator 224 in the region not overlapping with the oxide 230a may be reduced (see FIG. 5). reference.).

[0232] Here, the oxide 230a, the oxide 230b and the conductive layer 242B are at least partially The oxide 230a, the oxide 230b, and the conductor 205 are formed to overlap each other. The angle between the conductive layer 242B and the top surface of the insulator 222 may be small. In this case, the angle between the side surface of the oxide 230a and the top surface of the insulator 222 is The angle is preferably 60° or more and less than 70°. By making the angle like this, the following steps can be performed more easily. This improves the coverage of the insulator 254 and reduces defects such as voids. The oxide 230a, the oxide 230b and the side of the conductive layer 242B are on the insulator 222. The oxide 230a, the oxide 230b and the conductive layer 24 may be approximately perpendicular to the surface. The side surface of the insulator 222 is substantially perpendicular to the upper surface of the insulator 222, so that the plurality of transistors When providing 200, it is possible to reduce the area and increase the density.

[0233] In addition, a curved surface is provided between the side surface and the upper surface of the conductive layer 242B. In other words, it is preferable that the ends of the side surfaces and the top surface are curved (hereinafter referred to as rounded). The curved surface has a radius of curvature of, for example, 3 nm at the end of the conductive layer 242B. The thickness is from 5 nm to 6 nm, preferably from 5 nm to 6 nm. This improves the film coverage in the subsequent film formation steps.

[0234] The oxide film 230A, the oxide film 230B, and the conductive film 242A are processed by lithography. This processing can be performed by using a dry etching method or a wet etching method. Dry etching can be used for processing, and is suitable for fine processing.

[0235] In addition, by performing processes such as dry etching, the etching gas and other The impurities adhere to or spread on the surface or inside of the oxide 230a and the oxide 230b. Impurities may include, for example, fluorine or chlorine.

[0236] In order to remove the above impurities, cleaning is performed. These include wet cleaning, plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate.

[0237] Wet cleaning involves mixing oxalic acid, phosphoric acid, or hydrofluoric acid with carbonated water or pure water. The cleaning process may be carried out using an aqueous solution diluted with water. Alternatively, pure water or carbonated water may be used. In the present embodiment, ultrasonic cleaning using pure water or carbonated water is performed. Do the following.

[0238] Subsequently, a heat treatment may be performed. The heat treatment conditions are the same as those described above. It is possible.

[0239] Next, on the insulator 224, the oxide 230a, the oxide 230b and the conductive layer 242B A dummy gate film that becomes the dummy gate layer 262A is deposited.

[0240] The dummy gate film that becomes the dummy gate layer 262A is processed and used as a dummy gate. The dummy gate is a temporary gate electrode. By processing the dummy gate film, a temporary gate electrode is formed. The dummy gate is removed, and instead a gate electrode made of a conductive film or the like is formed. The dummy gate film that becomes the gate layer 262A is a film that can be easily microfabricated and can also be easily removed. It is preferable to use:

[0241] The dummy gate film that becomes the dummy gate layer 262A is formed by a sputtering method or a CVD method. , MBE, PLD, ALD, or the like. A semiconductor or a conductor can be used. Specifically, polysilicon, microcrystalline silicon, Silicon, amorphous silicon, aluminum, titanium, tungsten, etc. A metal film or the like can be used. Alternatively, a coating method can be used to form a SOG (Spin On Glass) For example, photoresist, polyester, polyolefin, etc. may be formed. olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate or The dummy gate is formed by applying SOG or resin film. In this way, the surface of the dummy gate film can be flattened. This facilitates fine processing and also facilitates removal.

[0242] In addition, the dummy gate film that becomes the dummy gate layer 262A is a multi-layer film using different film types. For example, the dummy gate film that becomes the dummy gate layer 262A can be formed as a conductive film. The dummy gate film can be formed into a two-layer structure in which a resin film is formed on a conductive film. By adopting such a structure, for example, in a subsequent CMP process, the conductive film is prevented from being damaged by the CMP process. It may function as a protective film or may enable end point detection of CMP processing. This may make it possible to reduce processing variations.

[0243] Next, a dummy gate film that will become the dummy gate layer 262A is etched by a lithography method. Then, etching is performed to form a dummy gate layer 262A (see FIG. 6). A is formed so as to overlap at least a portion of the conductor 205 and the oxide 230 .

[0244] Next, oxide 230a, oxide 230b, conductive layer 242B and dummy gate layer 26 An insulating film 254A is then formed on the insulating film 254A so as to cover the insulating film 22A. The insulating film 254A and the insulating film 244A may be formed (see FIG. 6). The film is formed by using a method such as sputtering, CVD, MBE, PLD, or ALD. It is possible.

[0245] The insulating film 254A is an insulating film having a function of suppressing the diffusion of impurities such as hydrogen and oxygen. For example, an aluminum oxide film is formed by sputtering. It is preferable to perform sputtering to deposit aluminum oxide using a gas containing oxygen. By forming an ion-doped silicon film, oxygen can be injected into the insulator 224. , the insulator 224 may have excess oxygen.

[0246] The insulating film 244A is an insulating film having a function of suppressing the diffusion of impurities such as hydrogen and oxygen. For example, it is preferable to form an aluminum oxide film by the ALD method. It is preferable to use the ALD method, which has excellent coverage, so that the dummy gate layer 262A and the like can be easily formed. Therefore, the insulating film 244A having a uniform thickness can be formed even in the stepped portion formed by the above-mentioned method. In addition, the ALD method can be used to form dense thin films. It has excellent coating properties and can form a dense thin film. For example, the insulating film 254A can be formed with voids. Even if defects such as holes or pinholes occur, they can be covered by the insulating film 244A.

[0247] The insulating film 244A may be made of aluminum nitride, silicon nitride, silicon oxynitride, or the like. For example, the insulating film 244A may be formed using an aluminum target. When forming an aluminum nitride film by reactive sputtering, the total flow rate of the film formation gas is The flow rate of the nitrogen gas is set to 30% or more and 100% or less, preferably 40% or more and 100% or less, more preferably 40% or more and 100% or less. It is more preferable that the ratio is 50% or more and 100% or less.

[0248] In addition, as the insulating film 244A, aluminum oxide is formed while the substrate is heated at a high temperature. The substrate heating temperature during the formation of the insulating film 244A is 200° C. or higher, preferably 250° C. or higher. ℃ or more, more preferably 350 ℃ or more. By forming an aluminum oxide film by the LD method, the insulating film 244 When the dummy gate layer 262A is formed, deformation of the dummy gate layer 262A can be prevented.

[0249] In addition, after forming either or both of the insulating film 244A and the insulating film 254A, Either the insulating film 244A or the insulating film 254A or The addition of fluorine to both is achieved by plasma deposition in an atmosphere containing fluorine-based gas (e.g., CF4). This can be achieved by performing a fluorine treatment or by doping with a gas containing fluorine. By adding fluorine to either or both of the insulating film 244A and the insulating film 254A, As a result, hydrogen contained in the film can be terminated or gettered by fluorine. It's promising.

[0250] In this way, the excess oxygen contained in the insulator 224 is prevented from diffusing outward. On the other hand, it is possible to prevent impurities such as water and hydrogen from entering the insulator 224. The deposition of the boundary film 244A may be omitted.

[0251] Next, an insulating film that will become the insulator 280 is formed on the insulating film 244A. The insulating film is formed by a method such as sputtering, CVD, MBE, PLD, or ALD. This can be done using, for example.

[0252] Next, the insulating film that will become the insulator 280, the dummy gate layer 262A, the insulating film 254A, and A part of the insulating film 244A is removed until a part of the dummy gate layer 262A is exposed. 280, dummy gate 262, insulator 254 and insulator 244 are formed (see FIG. 7). The insulator 280, the dummy gate 262, the insulator 254 and the insulator 244 are formed using C. It is preferable to use the MP treatment.

[0253] As described above, the dummy gate layer 262A is formed by, for example, forming a conductive film and a resin film on the conductive film. By forming a two-layer structure film, the conductive film is prevented from being damaged by the CMP process. In some cases, the conductive film functions as a stopper film. Alternatively, the conductive film may be capable of detecting the end point of the CMP process. This may enable a reduction in the variation in height of the dummy gate 262. As shown in FIG. 7B, the upper surface of the dummy gate 262, the insulator 254, the insulator 244, and and the top surface of the insulator 280 are approximately flush with each other.

[0254] Next, the dummy gate 262 is removed to form an opening 263 (see FIG. 8). The removal of the layer 262 can be achieved by wet etching, dry etching, ashing, or the like. Alternatively, a combination of the above processes may be used. For example, a wet etching process may be performed after an ashing process. By removing 262, a part of the surface of the conductive layer 242B is exposed through an opening 263. .

[0255] Next, the portion of the conductive layer 242B exposed from the opening 263 is removed to form an oxide A part of the surface of 230b is exposed, forming conductor 242a and conductor 242b. The removal can be accomplished using wet or dry etching. In this embodiment mode, dry etching is used. This is preferable because it can be thinly processed. Additionally, a portion of the top surface of oxide 230b may be removed.

[0256] At this time, the insulators 280, 244, and 254 are used as masks. The conductor 242a and the conductor 242b are formed. 4, and an opening 263 formed in the insulator 254 allows the conductors 242a and 242b to This allows the conductor 242a and the conductor 242b to overlap in the region between the conductor 242a and the conductor 242b in a later process. Conductor 260 may be positioned between bodies 242b in a self-aligned manner.

[0257] Next, it is preferable to perform a heat treatment before forming the oxide film 230C. The heat treatment may be performed at a temperature of 200° C. or higher and 400° C. or lower, for example, at 200° C. It is preferable to carry out the reaction under a high temperature, for example, in a vacuum atmosphere. The vacuum is maintained by exhausting the chamber with a sub-pump. In a vacuum atmosphere, the pressure in the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less.

[0258] After the heat treatment, the oxide film 230C is continuously formed without exposure to the atmosphere. For example, a multi-chamber type film forming apparatus is used to perform the heat treatment and the film forming. It is preferable to carry out the treatments in succession in different chambers. Therefore, the moisture and the like adsorbed on the surfaces of the oxide 230a and the oxide 230b are and removing hydrogen, and further measuring the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b. Furthermore, by performing the heat treatment and film formation consecutively without exposing the film to the outside air, This can prevent impurities such as hydrogen from re-entering the oxide 230. A similar heat treatment may also be performed before the formation of the insulating film 250A.

[0259] The oxide film 230C is formed by sputtering, CVD, MBE, PLD, or A This can be done using the LD method or the like. The oxide film 230C can be selected according to the desired characteristics. The oxide film 230C is formed by the same method as that for forming the oxide film 230A or the oxide film 230B. In the present embodiment, the oxide film 230C is formed by sputtering. So, In:Ga:Zn=1:3:4 [atomic ratio] or 4:2:4.1 [atomic ratio] The film is formed using a target of [

[0260] The oxide film 230C is preferably formed while the substrate is heated. By setting the temperature at 300° C. or higher, oxygen vacancies in the oxide film 230B and the oxide film 230C are reduced. In addition, the insulating film 250A described later can be formed at the same temperature. The oxide film 230C and the oxide 230 may be formed by heating the substrate. The crystallinity of b can be improved.

[0261] In particular, when the oxide film 230C is formed, a part of the oxygen contained in the sputtering gas is converted into the oxide. 230a and oxide 230b. Thus, the oxide film 230C The proportion of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, and more preferably It is preferable to set the ratio to 100%. In addition, the film is formed while the substrate is heated. The crystallinity of the oxide film can be improved.

[0262] Next, the insulating film 250A is formed. The insulating film 250A is formed by a method such as a sputtering method, a CVD method, or the like. The insulating film 250 can be formed by using the MBE method, the PLD method, the ALD method, or the like. It is preferable to form a silicon oxynitride film as A by the CVD method. The deposition temperature for depositing 250A is 300°C or higher and lower than 450°C, preferably 300°C or higher. It is preferable to set the temperature at or below 400° C., particularly at about 350° C. For example, the insulating film 250A is By forming the film at 350°C, an insulator with few impurities can be formed.

[0263] In addition, oxygen is excited by microwaves to generate high-density oxygen plasma, and the oxygen plasma is By exposing the insulating film 250A to oxygen, oxygen can be introduced into the insulating film 250A.

[0264] Heat treatment may also be performed. The heat treatment may be performed under the above-mentioned heat treatment conditions. The heat treatment reduces the moisture concentration and hydrogen concentration in the insulating film 250A. can be done.

[0265] Next, the conductive film 260Aa and the conductive film 260Ab are formed. The conductive film 260Ab is formed by sputtering, CVD, MBE, PLD or A This can be done by using the LD method or the like. For example, it is preferable to use the CVD method. In this embodiment, the conductive film 260Aa is formed by the ALD method, and the conductive film 260B is formed by the CVD method. A film of 260Ab is formed (see Figure 8).

[0266] Next, the oxide film 230C, the insulating film 250A, the conductive film 260Aa, and The oxide 230 is removed by polishing the conductive film 260Ab until the insulator 280 is exposed. c. Forming the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b). (See Figure 9.)

[0267] Next, a heat treatment may be performed. The heat treatment may be performed under the above-mentioned heat treatment conditions. The heat treatment can reduce the moisture concentration and hydrogen concentration of the insulator 280. Cut.

[0268] Next, an insulating film that will become the insulator 274 is formed on the insulator 280 (see FIG. 9). The insulating film that becomes the body 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. The insulating film that becomes the insulator 274 can be, for example, For example, it is preferable to form an aluminum oxide film by a sputtering method. By forming an aluminum oxide film by a deposition method, the insulator 280 has In some cases, it may be possible to suppress the diffusion of hydrogen into the oxide 230.

[0269] Next, a heat treatment may be performed. The heat treatment may be performed under the above-mentioned heat treatment conditions. The heat treatment can reduce the moisture concentration and hydrogen concentration of the insulator 280. Cut.

[0270] Next, an insulating film that will become the insulator 281 may be formed on the insulator 274. The insulating film is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using the method described above (see FIG. 9).

[0271] Next, the insulator 254, the insulator 244, the insulator 280, the insulator 274 and the insulator 281 In the above, openings are formed so as to reach the conductors 242a and 242b. The openings are formed as follows: This can be done by using a lithography method.

[0272] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator The insulating film 241 is formed. The insulating film is formed by a sputtering method, a CVD method, an MBE method, a PL method, etc. The insulating film to be the insulator 241 can be formed by the ALD method or the ALD method. In the case of ALD, it is preferable to use an insulating film having a function of suppressing oxygen permeation. It is preferable to form an aluminum oxide film or a silicon nitride film by the above-mentioned method. The anisotropic etching may be, for example, a dry etching method. By adopting such a configuration, the permeation of oxygen from the outside is suppressed, and the conductor 240 to be formed next is In addition, the conductor 240a and the conductor 240b can be prevented from being oxidized. This can prevent impurities such as water and hydrogen from diffusing to the outside from the electric body 240b.

[0273] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240b has a function of suppressing the diffusion of impurities such as water and hydrogen. It is preferable to use a laminated structure containing a conductor such as tantalum nitride or titanium nitride. The conductor 24 may be a laminate of tungsten, molybdenum, copper, etc. The conductive film that becomes 0 is formed by sputtering, CVD, MBE, PLD or AL. This can be done using Method D or the like.

[0274] Next, a CMP process is performed to remove the conductive film that will become the conductor 240a and the conductor 240b. A portion of the conductive film is removed to expose the insulator 281. As a result, the conductive film remains only in the opening. By this, it is possible to form the conductors 240a and 240b having flat upper surfaces ( (See FIG. 3.) Note that the CMP process may remove a part of the insulator 281. .

[0275] Through the above steps, a semiconductor device including the transistor 200 shown in FIG. 3 can be manufactured. As shown in FIGS. 4 to 9, the semiconductor device can be manufactured by the method for manufacturing the semiconductor device described in this embodiment. Thus, the transistor 200 can be fabricated.

[0276] According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated is provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. It is possible.

[0277] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0278] <Modifications of the semiconductor device> In the following, the above-mentioned <Configuration Example of Semiconductor Device> will be described with reference to FIGS. 10 to 20. A semiconductor device including a transistor 200 according to another embodiment of the present invention, and An example of a method for producing the body device will now be described.

[0279] 10 to 20, (A) of each figure shows a top view. FIG. 10(A) is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in FIG. 10A is a cross-sectional view of the transistor 200 in the channel length direction. 2 is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in FIG. In each figure, (A) is a top view, and some parts are omitted for clarity. The elements are omitted in the figure.

[0280] In the semiconductor device shown in FIG. 10 to FIG. 20, The structures having the same functions as those constituting the semiconductor device (see FIG. 3) are denoted by the same reference numerals. In this section, the constituent materials of the transistor 200 are described in the section "Construction of a Semiconductor Device." The materials described in detail in the Examples can be used.

[0281] The transistor 200 shown in FIG. 10 does not have the insulator 244, but has an insulator 254. The insulator 224, the oxide 230a, the oxide 230b, the conductor 242a, and the conductor 242 b and the insulator 280. That is, in the transistor 200 shown in FIG. It is configured to be in contact with 280.

[0282] In the transistor 200 illustrated in FIG. The side surface on the conductor 260 side is tapered like the transistor 10b shown in FIG. Here, the angle between the side surface and the bottom surface of the conductor 242a and the conductor 242b is The angle may be set to 10° or more and 80° or less, and preferably 30° or more and 60° or less. In addition, the oxide 230 is also formed in the region near the conductor 242a and the conductor 242b. This increases the contribution of the electric field to the transistor 200, thereby improving the on-state current and frequency characteristics of the transistor 200. It should be noted that the transistor 200 shown in FIG. 1A, the conductor 242a and the conductor 242b The side surface of the transistor 10c shown in FIG. Similarly, the opposing sides of the conductors 242a and 242b have multiple surfaces. Good too.

[0283] The semiconductor device shown in FIG. 10 can be manufactured without forming the dummy gate 262. This is preferable because it can simplify the manufacturing process of the semiconductor device.

[0284] The semiconductor device shown in FIG. 10 includes an oxide 230a, an oxide 230b, and a conductive layer 242B. The manufacturing method of the semiconductor device shown in FIG. A manufacturing method of the semiconductor device in FIG. 5 can be referred to.

[0285] Next, on the insulator 224, the oxide 230a, the oxide 230b and the conductive layer 242B Then, an insulating film 254A is formed.

[0286] Next, an insulating film that will become the insulator 280 is formed on the insulating film 254A. The insulating film is formed by a method such as sputtering, CVD, MBE, PLD, or ALD. Next, a CMP process is performed on the insulating film that will become the insulator 280. A flat surfaced insulator 280 is formed.

[0287] Next, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B are 11. The opening 264 is then removed down to the oxide 230b (see FIG. 11). It is preferable to form the oxide 230a, the oxide 230b, and the conductor 205 so as to overlap each other. By forming the opening 264, the conductor 242a, the conductor 242b, and the insulator Here, the oxide film 254 is formed. A portion of the top surface of object 230b may be removed.

[0288] The opening 264 may be formed by wet etching, but it is preferable to use a method that allows fine processing. Therefore, it is preferable to use a dry etching method. It is preferable to form a hard mask on the substrate 80. The hard mask is made of a conductive material. Alternatively, an insulator may be used.

[0289] In addition, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductor are processed. For example, a part of the insulator 280 may be dry-etched. Then, a part of the insulating film 254A is processed by a wet etching method, and the conductive layer 242B is A part of the film may be processed by dry etching.

[0290] The subsequent steps of the method for manufacturing the semiconductor device shown in FIG. 10 are the same as those of the semiconductor device shown in FIG. Therefore, the manufacturing method of the semiconductor device shown in FIG. 8 and FIG. 9 should be referred to. It is possible.

[0291] The transistor 200 shown in FIG. 12 has a conductor 242a between the conductor 242a and the oxide 230b. 43a is disposed, and a conductor 243b is disposed between the conductor 242b and the oxide 230b. 3. Here, the conductor 242a (conductor 242b) is connected to the upper surface of the conductor 243a (conductor 243b) and the side surface on the conductor 260 side. The conductor 243 is provided in contact with the upper surface of the oxide 230b. 2. Furthermore, the thickness of the conductor 243 is at least Both are preferably thicker than the conductor 242 .

[0292] In addition, in the transistor 200 shown in FIG. 12, the distance between the conductor 242a and the conductor 242b is , the channel of the opening 263 formed in the insulator 280, the insulator 244, and the insulator 254. It differs from the transistor 200 shown in FIG. 3 in that its length in the long direction is shorter.

[0293] The transistor 200 shown in FIG. 12 has the above-described structure. The electric field of the conductor 260 also contributes to the regions near the conductors 242a and 242b of FIG. This allows the effective channel length of the transistor 200 to be shortened. As a result, the on-current and frequency characteristics can be improved.

[0294] In addition, the conductor 243a (conductor 243b) overlaps with the conductor 240a (conductor 240b). It is preferable that the conductor 240a (the conductor In the etching to form an opening in which the conductor 240b is embedded, the conductor 2 is formed at the bottom of the opening. Since 43a (conductor 243b) is provided, the oxide 230b is not over-etched. This can prevent the

[0295] In the transistor 200 illustrated in FIG. The side surface on the conductor 260 side is substantially vertical, similar to the transistor 10a shown in FIG. It should be noted that the transistor 200 shown in FIG. Similarly to the transistor 10b shown in FIG. The angle between the side surface and the bottom surface of b is 10° or more and 80° or less, preferably 30° or more and 60° or less. Similarly to the transistor 10c illustrated in FIG. And the opposing side of conductor 242b may have multiple faces.

[0296] The semiconductor device shown in FIG. 12 is configured as follows: The manufacturing method of the semiconductor device shown in FIG. The law can be taken into consideration.

[0297] Next, a conductive film that will become the conductive layer 243A is formed on the oxide film 230B. The conductive film that becomes 43A is formed by sputtering, CVD, MBE, PLD, or This can be done using the ALD method or the like.

[0298] Next, a part of the conductive film that will become the conductive layer 243A is removed to form the conductive layer 243A. (See FIG. 13.) In FIG. 13, the conductive layer 243A has an opening. However, the embodiment is not limited to this. In this step, the conductive film that becomes the conductive layer 243A is Therefore, it is sufficient to remove the portion between the conductor 243a and the conductor 243b. For example, the conductive film that becomes the conductive layer 243A is divided into an island-shaped conductive material corresponding to the conductive material 243a and a conductive material The conductive island 243b may be divided into an island-shaped conductive body.

[0299] The conductive film that becomes the conductive layer 243A may be processed by using a lithography method. This processing can be performed by dry etching or wet etching. The etching method is suitable for microfabrication.

[0300] Next, a conductive film 242A is formed on the oxide 230b and the conductive layer 243A. The film 242A can be formed by referring to the method for manufacturing the semiconductor device shown in FIG.

[0301] Thereafter, a dummy gate layer 262A is formed, and an insulating film 254A and an insulating film 244A are formed. The steps up to this step (see FIG. 14) are the same as those of the manufacturing method of the semiconductor device shown in FIG. The manufacturing method of the semiconductor device according to FIGS. 5 and 6 can be referred to.

[0302] For example, the insulating film 244A is formed by forming aluminum oxide while heating the substrate at a high temperature. The substrate heating temperature during the formation of the insulating film 244A is 200° C. or higher, preferably 25 The temperature may be 0° C. or higher, more preferably 350° C. or higher. By forming an aluminum oxide film by the ALD method, the insulating film 24 When the dummy gate layer 262A is deposited, deformation of the dummy gate layer 262A can be prevented.

[0303] After the formation of either or both of the insulating film 244A and the insulating film 254A, Either the insulating film 244A or the insulating film 254A or The addition of fluorine to both is achieved by plasma deposition in an atmosphere containing fluorine-based gas (e.g., CF4). This can be achieved by performing a fluorine treatment or by doping with a gas containing fluorine. By adding fluorine to either or both of the insulating film 244A and the insulating film 254A, As a result, hydrogen contained in the film can be terminated or gettered by fluorine. It's promising.

[0304] Next, an insulating film that will become the insulator 280 is formed on the insulating film 244A. The insulating film is formed by a method such as sputtering, CVD, MBE, PLD, or ALD. This can be done using, for example.

[0305] Next, the insulating film that will become the insulator 280, the dummy gate layer 262A, the insulating film 254A, and A part of the insulating film 244A is removed until a part of the dummy gate layer 262A is exposed. 280, dummy gate 262, insulator 254 and insulator 244 are formed. 0, the dummy gate 262, the insulator 254 and the insulator 244 are formed using a CMP process. For details, the method for manufacturing the semiconductor device shown in FIG. can.

[0306] Next, the dummy gate 262 is removed to form an opening 263 (see FIG. 8). The removal of the gate 262 may be performed by wet etching, dry etching, ashing, or the like. Alternatively, a combination of the above treatments may be used as appropriate. For example, a wet etching process may be performed after an ashing process. By removing the opening 262, a part of the surface of the conductive layer 242B is exposed through the opening 263. do.

[0307] Next, on the insulator 280, the insulator 244, the insulator 254, and the conductive layer 242B, A dummy film 265 is formed (see FIG. 15). The dummy film 265 is formed on the side wall of the opening 263. The distance between the conductors 242a and 242b, That is, the substantial channel length is determined. For this reason, the dummy film 265 has high coverage and a large thickness. It is preferable to form the dummy film 265 by the ALD method, which allows relatively easy fine adjustment of the thickness. The thickness may be appropriately set according to the electrical characteristics required for the transistor 200. For example, by setting it to 5 nm, the channel length can be effectively reduced by 10 nm. Since the dummy film 265 is eventually removed, fine processing is easy and removal is also possible. It is preferable to use an easy membrane.

[0308] Next, the dummy film 265 is anisotropically etched to remove the sidewall of the opening 263 of the dummy film 265. Only the portion in contact with the dummy film 265 is left. The conductive layer 242B is etched to form the conductive material 242a and the conductive material 242b. (See FIG. 16.) In addition, the etching of the dummy film 265 and the etching of the conductive layer 242B are performed. The etching may be performed continuously. As a result, a portion of the top surface of oxide 230b may be removed.

[0309] At this time, the remaining dummy film 265 is used as a mask to form the conductor 242a and the Thus, the insulator 280, the insulator 244, and the insulator 254 form an insulator 242b. The formed opening 263 overlaps the region between the conductor 242a and the conductor 242b. As a result, in a later step, the conductor 242a and the conductor 242b are inserted between them. 60 can be arranged in a self-aligning manner.

[0310] Next, the remaining dummy film 265 is selectively removed by isotropic etching (FIG. 17). Isotropic etching can be, for example, wet etching or reactive etching. In this manner, the conductor 242a and the conductor 242b are The distance b can be made shorter than the length of the opening 263 in the channel length direction.

[0311] The steps of the manufacturing method of the semiconductor device shown in FIG. 12 are the same as those of the semiconductor device shown in FIG. Therefore, the manufacturing method of the semiconductor device shown in FIG. 8 and FIG. 9 should be referred to. It is possible.

[0312] The transistor 200 shown in FIG. 18 does not have the insulator 244, but has an insulator 254. Insulator 224, oxide 230a, oxide 230b, conductor 243a, conductor 243b, conductor At a point disposed between the conductor 242a and the conductor 242b and the insulator 280 12. That is, the transistor 200 shown in FIG. In this example, the side of oxide 230c is in contact with insulator 280.

[0313] In the transistor 200 illustrated in FIG. The side surface on the conductor 260 side is substantially vertical, similar to the transistor 10a shown in FIG. It should be noted that the transistor 200 shown in FIG. Similarly to the transistor 10b shown in FIG. The angle between the side surface and the bottom surface of b is 10° or more and 80° or less, preferably 30° or more and 60° or less. Similarly to the transistor 10c illustrated in FIG. And the opposing side of conductor 242b may have multiple faces.

[0314] The semiconductor device shown in FIG. 18 can be manufactured without forming the dummy gate 262. This is preferable because it can simplify the manufacturing process of the semiconductor device.

[0315] The semiconductor device shown in FIG. 18 includes an oxide 230a, an oxide 230b, a conductor 242a, and a conductor The steps up to the formation of the substrate 242b and the conductive layer 242B are the same as those for fabricating a semiconductor device shown in FIG. Therefore, the manufacturing method of the semiconductor device shown in FIG. 4, FIG. 5, and FIG. 13 should be referred to. It is possible.

[0316] Next, the insulator 224, the oxide 230a, the oxide 230b, the conductor 243a, and the conductor 24 An insulating film 254A is formed on the insulating layer 3b and the conductive layer 242B.

[0317] Next, an insulating film that will become the insulator 280 is formed on the insulating film 254A. The insulating film is formed by a method such as sputtering, CVD, MBE, PLD, or ALD. Next, a CMP process is performed on the insulating film that will become the insulator 280. A flat surfaced insulator 280 is formed.

[0318] Next, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B are 19. The opening 264a is then removed to reach the oxide 230b (see FIG. 19). , the oxide 230a, the oxide 230b, and the conductor 205 are formed to overlap each other. It is preferable that the opening 264a is formed to prevent the conductor 242a, the conductor 242b, and the insulating material from being damaged. The edge 254 is formed. Here, the exposed portion between the conductor 242a and the conductor 242b is A portion of the top surface of oxide 230b may be removed.

[0319] The opening 264a may be formed by wet etching, but it is preferable to use a method that allows fine processing. From this viewpoint, it is preferable to use a dry etching method. This is preferably done by forming a hard mask on the body 280. The hard mask is a conductive material. Alternatively, an insulator may be used.

[0320] In addition, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductor are processed. For example, a part of the insulator 280 may be dry-etched. Then, a part of the insulating film 254A is processed by a wet etching method, and the conductive layer 242B is A part of the film may be processed by dry etching.

[0321] Next, the opening 264a in the insulator 280 is side-etched to form an opening 264b. (See FIG. 20.) The side etching of the insulator 280 can be performed by wet etching or Isotropic etching, such as etching using a reactive gas, may be used. The sidewall of the opening 264b is recessed by 5 nm from the opening 264a, so that the conductor 242a (the conductor 2 42b) can be protruded 5 nm from the sidewall of the opening 264b. The distance between the conductive body 242a and the conductive body 242b is set shorter than the length of the opening 264b in the channel length direction. It is possible.

[0322] The subsequent steps of the method for manufacturing the semiconductor device shown in FIG. 18 are the same as those of the semiconductor device shown in FIG. Therefore, the manufacturing method of the semiconductor device shown in FIG. 8 and FIG. 9 should be referred to. It is possible.

[0323] The configurations, structures, methods, etc. described in this embodiment may be the same as those described in other embodiments. The present invention can be used in combination with other methods and structures as appropriate.

[0324] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0325] [Storage device 1] FIG. 21 shows an example of a semiconductor device (memory device) using a capacitor according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, the transistor 200 is disposed above the transistor 300. The capacitor 100 is disposed above the transistor 300 and the transistor 200. The transistor 200 may be the transistor described in the previous embodiment. Sta200 etc. can be used.

[0326] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This makes it possible to retain the memory contents for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0327] In the semiconductor device shown in FIG. 21, a wiring 1001 is electrically connected to the source of a transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200. 006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to a capacitor. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. It is electrically connected to the other.

[0328] In addition, the memory device shown in FIG. 21 has a memory cell array arranged in a matrix. It can be configured.

[0329] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 312 functioning as a gate electrode. 16, an insulator 315 acting as a gate insulator, a semiconductor region consisting of a portion of a substrate 311 313, and a low resistance region 314a which functions as a source region or a drain region, The transistor 300 may be a p-channel or n-channel type. Either a filter type or a filter panel type may be used.

[0330] Here, the transistor 300 shown in FIG. 21 has a semiconductor region 313 ( A part of the substrate 311 has a convex shape. The side and top surfaces of the semiconductor region 313 are insulated. The conductor 316 is provided so as to cover the edge 315. Materials for adjusting the work function may be used. Since it uses a protruding part, it is also called a FIN type transistor. In addition, the insulating layer may have an insulating material that functions as a mask for forming the protrusions. Here, a case where a protrusion is formed by processing a part of a semiconductor substrate is shown, but a SOI substrate is also processed. A semiconductor film having a convex shape may be formed by the above-mentioned method.

[0331] Note that the transistor 300 shown in FIG. 21 is just an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the configuration and driving method.

[0332] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. a conductor 110 serving as the first electrode, a conductor 120 serving as the second electrode, and and an insulator 130 that functions as a dielectric.

[0333] Also, for example, the conductor 112 provided on the conductor 246 and the conductor 110 are formed at the same time. Note that the conductor 112 can be used for the capacitor 100, the transistor 200, and has a function as a plug or wiring that is electrically connected to the transistor 300 .

[0334] In FIG. 21, the conductor 112 and the conductor 110 are shown to have a single-layer structure. However, the present invention is not limited to this, and may be a laminated structure of two or more layers. For example, Conductors that have barrier properties between weak conductors and those with high electrical conductivity have good adhesion to conductors with high electrical conductivity. may form a highly conductive material.

[0335] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitrogen Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium The conductive layer may be formed as a laminate or a single layer.

[0336] For example, the insulator 130 may be made of a material with high dielectric strength, such as silicon oxynitride, or a material with high dielectric strength. It is preferable to use a laminated structure with a high-k material. The element 100 has a high dielectric constant (high-k) insulator, so that it can ensure sufficient capacitance. By using an insulator having a large dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0337] In addition, oxide is an insulator for high dielectric constant (high-k) materials (materials with a high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium an oxide having silicon and hafnium, an oxide nitride having silicon and hafnium, or an oxide nitride having silicon and hafnium Nitrides containing fluorine.

[0338] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. Silicon oxide, silicon nitride, silicon nitride, silicon oxide doped with fluorine, carbon Doped silicon oxide, carbon and nitrogen doped silicon oxide, vacancy-containing silicon oxide Examples include concrete or resin.

[0339] <Wiring layer> Between each structure, a wiring layer is provided in which an interlayer film, wiring, plugs, etc. are provided. Also, a plurality of wiring layers may be provided according to the design. Conductors that function as wiring or wiring may be grouped together and given the same symbol. In addition, in the present specification and the like, the wiring and the plug that are electrically connected to the wiring may be integrated. That is, when a part of the conductor functions as a wiring, or when the conductor In some cases, some parts also function as plugs.

[0340] For example, an insulator 320, an insulator 322, and an insulator 323 are provided on the transistor 300 as an interlayer film. The edge member 324 and the insulator 326 are laminated in this order. The insulators 322, 324, and 326 are connected to the capacitive element 100 or the transistor. A conductor 328 and a conductor 330 are embedded in the conductive layer 200. The conductor 328 and the conductor 330 function as plugs or wiring.

[0341] In addition, the insulator that functions as an interlayer film acts as a flattening film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be chemically mechanically polished ( The surface may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0342] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In the insulating layer 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or a wiring.

[0343] Similarly, the insulators 210, 212, 214, and 216 are each provided with a conductive The conductive body 218 and the conductive body (conductive body 205) constituting the transistor 200 are embedded. Note that the conductor 218 is electrically connected to the capacitor 100 or the transistor 300. The conductor 120 and the insulator 130 function as a plug or wiring for connecting the conductor 120 and the insulator 130. On top of 130 is an insulator 150 .

[0344] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides having insulating properties. These include metal nitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0345] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material It is recommended to select:

[0346] For example, the insulators 150, 212, 352, and 354 have relatively low resistance. It is preferable to use an insulator with a low dielectric constant. For example, the insulator may be silicon oxide, oxide, or the like. Silicon nitride, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, carbon Silicon oxide doped with oxygen, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies The insulator preferably comprises silicon or resin, or silicon oxide. , silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine , silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. It is preferable that the insulating layer has a laminated structure of silicon oxide and a resin. Silicon oxynitride is thermally stable, so by combining it with resin, The laminated structure can have a low dielectric constant. Examples of the resin include polyester and Polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Examples include plastic or acrylic.

[0347] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the Therefore, the insulator 210, the insulator 350, etc., do not contain impurities such as hydrogen and Insulators having a function of suppressing the permeation of oxygen may be used.

[0348] Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, the following insulators have the function of suppressing the permeation of impurities such as hydrogen and oxygen: Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tungsten oxide Metal oxides such as talc, silicon oxide nitride, silicon nitride, etc. can be used. .

[0349] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Sodium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium Materials containing one or more metal elements selected from the group consisting of ruthenium and lithium can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as arsenic, A silicide such as nickel silicide may also be used.

[0350] For example, conductor 328, conductor 330, conductor 356, conductor 218, and conductor 1 12, etc., may be a metal material, an alloy material, a metal nitride material, or the like formed from the above-mentioned materials. Conductive materials such as metal oxide materials can be used in a single layer or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that is also electrically conductive. It is preferable to use tungsten. Alternatively, low resistance conductive materials such as aluminum and copper can be used. It is preferable to form the wiring from a low-resistance conductive material. can be done.

[0351] <<Wiring or plug of a layer in which an oxide semiconductor is provided>> When an oxide semiconductor is used for the transistor 200, excess An insulator having an oxygen region may be provided. In that case, the insulator having the excess oxygen region and an insulator having a barrier property is provided between the conductor and the insulator having the excess oxygen region. It is preferable to provide such a function.

[0352] For example, in FIG. 21, an insulator 276 is provided between the insulator 224 and the conductor 246. In particular, the conductor 246 is formed by sandwiching the insulator 222 having the excess oxygen region therebetween. It is preferable that the insulator 27 is provided in contact with the insulator 254 and the insulator 244. 6 is provided in contact with the insulator 222 and the insulator 281, The transistor 200 is sealed with an insulator having a barrier property. Furthermore, the insulator 276 is preferably in contact with a portion of the insulator 280. The edge 276 extends to the insulator 280, which further suppresses the diffusion of oxygen and impurities. It is possible.

[0353] In other words, by providing the insulator 276, the excess oxygen contained in the insulator 224 is absorbed by the conductor 24 In addition, the insulator 276 can prevent impurities from being absorbed by the insulator 6. The hydrogen, which is a substance, is prevented from diffusing into the transistor 200 via the conductor 246. It is possible.

[0354] The insulator 276 is made of a material that suppresses the diffusion of impurities such as water or hydrogen, and oxygen. It is advisable to use an insulating material that has the function of providing insulation. For example, aluminum oxide or hafnium oxide is In addition, for example, magnesium oxide, gallium oxide, etc. , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Metal oxides such as tantalum oxide or tantalum oxide, silicon oxide nitride or silicon nitride, etc. can be used.

[0355] The above is a description of the configuration example. By using this configuration, In a semiconductor device using a transistor, the fluctuation of electrical characteristics is suppressed and the reliability is improved. Alternatively, a transistor including an oxide semiconductor having a large on-state current can be provided. Alternatively, a transistor including an oxide semiconductor and having a low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. do.

[0356] [Storage device 2] FIG. 22 illustrates an example of a memory device using a semiconductor device according to one embodiment of the present invention. The memory device shown in FIG. 2 includes the transistor 200, the transistor 300, and the capacitor In addition to the semiconductor device having the capacitor 100 , a transistor 400 is also included.

[0357] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are connected to the source and the diode. and connect the source of the transistor 400 and the second gate of the transistor 200. In this configuration, when the second gate of the transistor 200 is held at a negative potential, The first gate-source voltage and the second gate-source voltage of the transistor 400 are In the transistor 400, the second gate voltage and the first gate voltage Since the drain current at 0V is very small, the transistors 200 and Even if power is not supplied to the transistor 400, the negative potential of the second gate of the transistor 200 can be maintained for a long time. This allows the transistor 200 and the transistor 400 to be maintained for a certain period of time. A storage device having such a function is capable of retaining stored contents for a long period of time.

[0358] Therefore, in FIG. 22, the wiring 1001 is electrically connected to the source of the transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is The back gate of the transistor 300 is electrically connected to the back gate of the transistor 200. The gate and the other of the source and drain of the transistor 200 are connected to the capacitor 100. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400. The wiring 1008 is electrically connected to the gate of the transistor 400. The wiring 1010 is electrically connected to the back gate of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and wiring 1009 are electrically connected.

[0359] 22 is arranged in a matrix, similar to the storage device shown in FIG. By doing so, a memory cell array can be configured. 0 can control the second gate voltages of the plurality of transistors 200. It is preferable to provide fewer transistors 400 than transistors 200.

[0360] <Transistor 400> Transistor 400 is formed in the same layer as transistor 200 and is fabricated in parallel. The transistor 400 has a first gate electrode and a second gate electrode. A conductor 460 (conductor 460a and conductor 460b) that functions as a gate electrode and a second gate electrode Conductors 405 (conductors 405a and 405b) functioning as electrodes and gate insulators Insulators 222, 224, and 450 function as edge layers, and a channel is formed. The oxide 430c has a region formed therein and a conductor that functions as either a source or a drain. The conductor 442a, the oxide 431a, and the oxide 431b, and the other of the source and the drain The conductor 442b, the oxide 432a, and the oxide 432b function as the conductor 44 0 (conductor 440a and conductor 440b).

[0361] In the transistor 400, the conductor 405 is the same layer as the conductor 205. The oxide 431a and oxide 432a are the same layer as the oxide 230a. b, and oxide 432b and oxide 230b are the same layer. The oxide 430c is the same layer as the oxide 230c. 450 is in the same layer as insulator 250. Conductor 460 is in the same layer as conductor 260. be.

[0362] It should be noted that structures formed in the same layer can be formed simultaneously. For example, oxide 4 30c can be formed by processing an oxide film that will become oxide 230c.

[0363] The oxide 430c that functions as the active layer of the transistor 400 is the same as the oxide 230, etc. Similarly, oxygen vacancies are reduced, and impurities such as hydrogen and water are reduced. The threshold voltage of the transistor 400 is set to be greater than 0 V to reduce the off-current and to provide a second gate. The drain current when the first gate voltage and the first gate voltage are 0 V can be made very small. do.

[0364] <<Dicing line>> In the following, a large-area substrate is divided into individual semiconductor elements to produce multiple semiconductor devices. Dicing lines (scribe lines, dividing lines) are provided when extracting chips. The following describes the method of cutting the wire. First, grooves (dicing lines) for dividing the semiconductor elements are formed on the substrate, and then the dicing In some cases, the substrate is cut at a grinding line and divided (divided) into a plurality of semiconductor devices.

[0365] Here, for example, as shown in FIG. 22, the area where the insulator 254 and the insulator 222 contact each other It is preferable to design the dicing line so that the A memory cell having a dicing layer 200 and a transistor 400 on the outer edge of the memory cell. An opening is provided in the insulator 224 near the region to be in-line. An insulator 254 and an insulator 244 are provided to cover the above.

[0366] That is, the insulator 222 and the insulator 254 are connected to each other through the opening provided in the insulator 224. For example, in this case, the insulators 222 and 254 are made of the same material and by the same method. The insulator 222 and the insulator 254 may be formed of the same material and by the same method. By using such a material, it is possible to improve the adhesion. For example, it is preferable to use aluminum oxide. It is nice.

[0367] With this structure, the insulator 222 and the insulator 254 are insulated from the insulator 224 and the transistor 200, and the transistor 400 can be encapsulated. The body 254 has a function of suppressing the diffusion of oxygen, hydrogen, and water. The substrate is divided into a plurality of chips by dividing the substrate into circuit regions each having a semiconductor element as shown in FIG. Even if the substrate is processed into a chip, impurities such as hydrogen or water may enter from the side of the cut substrate, causing a trap. Therefore, diffusion to the transistors 200 and 400 can be prevented.

[0368] In addition, this structure allows excess oxygen in the insulator 224 to migrate to the insulator 254 and the insulator 222. Therefore, the excess oxygen in the insulator 224 can be prevented from diffusing out of the insulator 224. The oxide on which the channel of the transistor 200 or the transistor 400 is formed is The oxygen is supplied to the transistor 200 or the transistor 400. This reduces the oxygen vacancies in the oxide in which the channel is formed. The oxide on which the channel of the transistor 200 or 400 is formed is made defect-free. It is possible to obtain an oxide semiconductor having a low potential density and stable characteristics. The present invention suppresses the fluctuation of the electrical characteristics of the transistor 200 or the transistor 400 and improves reliability. It can be raised.

[0369] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0370] (Embodiment 4) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. 23 and 24. A transistor used as a conductor (hereinafter, sometimes referred to as an OS transistor) and a capacitor A storage device to which the device is applied (hereinafter, sometimes referred to as an OS memory device) will be described. The OS memory device includes at least a capacitive element and an OS transistor that controls charging and discharging of the capacitive element. The off-state current of an OS transistor is extremely small, The OS memory device has excellent retention characteristics and can function as a non-volatile memory. .

[0371] <Storage device configuration example> FIG. 23A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1 411, and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 142 0, column circuit 1430, output circuit 1440, and control logic circuit 1460.

[0372] The column circuits 1430 include, for example, column decoders, precharge circuits, sense amplifiers, and write The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal. RDATA is output to the outside of the memory device 1400. For example, the memory device may have a row decoder, a word line driver circuit, etc., and may select a row to be accessed. do.

[0373] The storage device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 14 11, and the high power supply voltage (VIL) for the memory cell array 1470. The storage device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The decoder and column decoder are input to the data decoder, and WDATA is input to the write circuit.

[0374] The control logic circuit 1460 processes external input signals (CE, WE, RE). It processes the row decoder and column decoder control signals and generates the row decoder and column decoder control signals. CE is the chip enable signal. where WE is a write enable signal and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these. It is not necessary to input the control signal.

[0375] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of lines is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the recell MC, the number of memory cells MC in one row, etc.

[0376] In FIG. 23A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. Although an example of forming the insulating film on a surface has been shown, the present embodiment is not limited to this. For example, as shown in FIG. 23B, the memory cell array 1411 is provided on a part of the peripheral circuit 1411. 70 may be provided so as to overlap the memory cell array 1470. For example, In this way, a sense amplifier may be provided.

[0377] FIG. 24 illustrates an example of a memory cell configuration that can be applied to the above-mentioned memory cell MC.

[0378] [DOSRAM] 24A to 24C show examples of circuit configurations of memory cells in a DRAM. In this study, a DRAM using a memory cell of one OS transistor and one capacitor element type is called DOSRA. M(Dynamic Oxide Semiconductor Random Acc The memory cell 1471 shown in FIG. The transistor M1 has a gate It has a front gate (sometimes called a front gate) and a back gate.

[0379] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0380] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low level potential is applied to the wiring CAL. The wiring BGL is preferably used for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, The threshold voltage of M1 can be increased or decreased.

[0381] In addition, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration may be changed. For example, the memory cell MC can be a memory cell 1472 shown in FIG. In addition, the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 14 shown in FIG. As shown in FIG. 73, a transistor having a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured with a resistor M1.

[0382] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, The transistor 200 is used as M1, and the capacitance element 100 is used as the capacitance element CA. By using an OS transistor as the transistor M1, This means that the leakage current of the transistor M1 can be made very low. The frequency of memory cell refresh can be reduced by using resistor M1 for long-term retention. In addition, the refresh operation of the memory cells can be eliminated. In addition, since the leakage current is very low, the memory cells 1471, 1472, The memory cell 1473 can hold multi-level data or analog data.

[0383] In addition, in the DOSRAM, as described above, By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0384] [NOSRAM] FIG. 24(D) to (H) show a gain cell type memory cell having two transistors and one capacitor. A memory cell 1474 shown in FIG. The transistor M2 is a front-side transistor M3 and a capacitance element CB. The gate (sometimes simply referred to as the gate) and the back gate. The transistor M2 has a gain cell type memory cell. The storage device is NOSRAM (Nonvolatile Oxide Semiconductor It is sometimes called vector RAM.

[0385] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the transistor M1 is connected to the wiring CAL. The first terminal of the transistor M2 is connected to the wiring R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to a first terminal of the capacitance element CB.

[0386] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL is connected to the second It functions as a wiring for applying a specific potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, The threshold voltage can be increased or decreased.

[0387] In addition, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration may be appropriately changed. For example, the memory cell MC can be the memory cell 1475 shown in FIG. In this way, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell shown in FIG. Like the 1476, it has a single-gate transistor, i.e. no back gate. The memory cell may be configured with a transistor M2. For example, the memory cell MC As shown in FIG. 24G, a memory cell 1477 is formed by connecting a wiring WBL and a wiring RBL together. The wiring BIL may be integrated.

[0388] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor 200 is used as M2, and the transistor 300 is used as M3. The capacitance element CB can be a capacitance element 100. By using an OS transistor, the leakage current of transistor M2 is made very low. This allows the written data to be held for a long time by the transistor M2. This reduces the frequency of refreshing the memory cells. In addition, the memory cell refresh operation can be eliminated. Since the resistance is extremely low, multi-value data or analog data can be stored in the memory cell 1474. The same is true for memory cells 1475 to 1477.

[0389] The transistor M3 is a transistor having silicon in the channel formation region (hereinafter The conductivity type of the Si transistor may be The Si transistor may be an n-channel type or a p-channel type. In some cases, the field effect mobility is higher than that of the read transistor. A Si transistor may be used as the transistor M3 that functions as the By using a Si transistor for transistor M3, a transistor Since the memory cell can be provided with a transistor M2, the area occupied by the memory cell can be reduced, and the memory device can be made more efficient. Integration can be achieved.

[0390] The transistor M3 may be an OS transistor. When OS transistors are used, the memory cell array 1470 is configured with only n-type transistors. A circuit can be constructed using the same.

[0391] FIG. 24(H) shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 24(H) includes transistors M4 to M6 and a capacitor The memory cell 1478 has a capacitance element CC. The capacitance element CC is provided as appropriate. Electrically connected to L, RWL, WWL, BGL, and GNDL. Wire GNDL is a wiring for applying a low-level potential. , may be electrically connected to the wirings RBL and WBL.

[0392] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the wiring BGL. Alternatively, the transistor M4 may have a back gate. It's not necessary.

[0393] The transistors M5 and M6 are n-channel Si transistors or p-channel Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 is circuited using only n-type transistors. A path can be constructed.

[0394] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M The transistor 200 is used as the transistor M4, and the transistors M5 and M6 are the transistors 300. The capacitance element CC can be a capacitance element 100. By using an OS transistor as the gate driver, the leakage current of transistor M4 is made very low. It can be made easier.

[0395] Note that the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are The configuration is not limited to the above. The arrangement or functions of lines, circuit elements, etc. may be changed, deleted, or added as necessary. stomach.

[0396] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0397] (Embodiment 5) In this embodiment, a chip 1200 on which the semiconductor device of the present invention is mounted is shown in FIG. An example of the chip 1200 is shown. A plurality of circuits (systems) are implemented on the chip 1200. The technology of integrating multiple circuits (systems) onto a single chip is called system-on-chip (SCC). This is sometimes called System on Chip (SoC).

[0398] As shown in FIG. 25A, the chip 1200 includes a CPU (Central Processor). ssing Unit) 1211, GPU (Graphics Processing a memory controller 1212, one or more analog arithmetic units 1213, controller 1214, one or more interfaces 1215, one or more networks It has a work circuit 1216 and the like.

[0399] The chip 1200 is provided with bumps (not shown), and as shown in FIG. Printed Circuit Board (PCB) 1201 No. 1 The first surface of the PCB 1201 is connected to the second surface of the PCB 1202. 1203 is provided and connected to the motherboard 1203 .

[0400] The motherboard 1203 is provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be The NOSRAM shown in FIG.

[0401] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CP 212 may have a memory for temporarily storing data. A memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. In addition, the GPU1212 is suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or the like using the oxide semiconductor of the present invention. By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. This will be possible.

[0402] In addition, the CPU 1211 and GPU 1212 are integrated on the same chip, The wiring between the CPU1211 and the GPU1212 can be shortened, and the Data transfer from the CPU 1211 to the GPU 1212, memory of the CPU 1211 and the GPU 1212 After data transfer between GPU1212 and calculation in GPU1212, the data is transferred from GPU1212 to CPU12. The calculation results can be transferred to 11 at high speed.

[0403] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit and a digital / analog conversion circuit. The multiply-and-accumulate circuit may be provided in the

[0404] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. and a circuit that functions as an interface with the flash memory 1222.

[0405] The interface 1215 includes a display device, a speaker, a microphone, a camera, a The controller has an interface circuit for connecting to external devices such as a Such interfaces include computers, mobile phones, keyboards, and game controllers. USB (Universal Serial Bus), HDMI (registered trademark) High-Definition Multimedia Interface) There can be.

[0406] The network circuit 1216 is a LAN (Local Area Network) or the like. It may also have a circuit for network security. stomach.

[0407] The above circuits (systems) can be formed in the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a soldering process, and the chip 1200 can be produced at low cost.

[0408] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a DRAM 122 1, and the motherboard 1203 on which the flash memory 1222 is provided is a GPU module. It can be called module 1204.

[0409] The GPU module 1204 includes a chip 1200 using SoC technology. Its size can be reduced. Also, its excellent image processing makes it suitable for smart phones. Phones, tablet devices, laptop PCs, portable (portable) game consoles, etc. It is suitable for use in portable electronic devices. Deep Neural Networks (DNNs), Convolutional Neural Networks (CNN), Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It can perform operations such as deep belief networks (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a module.

[0410] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0411] (Embodiment 6) In this embodiment mode, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is used in, for example, various electronic devices (e.g., Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video recorders, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (e.g., D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 26 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a format and used in various storage devices and removable memory.

[0412] FIG. 26A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0413] FIG. 26(B) is a schematic diagram of the external appearance of an SD card, and FIG. 26(C) is a schematic diagram of the inside of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, the substrate 11 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, The capacity can be increased. In addition, a wireless chip having a wireless communication function is provided on the substrate 1113. This allows the host device and the SD card 1110 to wirelessly communicate with each other. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0414] FIG. 26(D) is a schematic diagram of the external appearance of the SSD, and FIG. 26(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing 54, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0415] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0416] (Embodiment 7) A semiconductor device according to one aspect of the present invention is a processor such as a CPU or a GPU, or a chip. FIG. 27 shows a processor such as a CPU or a GPU according to an embodiment of the present invention. Specific examples of electronic devices equipped with the chip are given below.

[0417] <Electronic equipment and systems> A GPU or chip according to an embodiment of the present invention can be installed in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, etc. Personal computers, computer monitors, digital signage tal Signage, large game machines such as pachinko machines, etc. In addition to electronic devices with large screens, digital cameras, digital video cameras, digital photos, Examples of the optical fiber include frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an integrated circuit or chip according to one embodiment of the present invention in an electronic device, It is possible to equip child devices with artificial intelligence.

[0418] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. And if a secondary battery is included, the antenna may be used for contactless power transmission.

[0419] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Numbers, distance, light, liquids, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared rays) It may have.

[0420] The electronic device according to one embodiment of the present invention can have various functions. Functions for displaying still images, videos, text images, etc. on the display, touch panel function, calendar Functions such as displaying date or time, running various software (programs) a function to read out a program or data recorded on a recording medium; It can have functions, etc. FIG. 27 shows an example of an electronic device.

[0421] [mobile phone]

[0422] FIG. 27(A) illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 551. It is provided at 0.

[0423] The information terminal 5500 uses artificial intelligence by applying the chip according to one embodiment of the present invention. It can run applications that use artificial intelligence. For example, an application that recognizes a conversation and displays the conversation content on the display unit 5511. The display unit 5511 recognizes characters, figures, etc. input by the user on the touch panel. The application to be displayed on the display unit 5511 and the application to perform biometric authentication such as fingerprint or voiceprint are displayed. Applications, etc.

[0424] [Information terminal 1] FIG. 27B shows a desktop information terminal 5300. The information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard. The present invention has a first embodiment and a second embodiment.

[0425] The desktop information terminal 5300 is similar to the information terminal 5500 described above. By applying the chip of the present invention, it is possible to execute applications using artificial intelligence. Examples of applications that use artificial intelligence include design support software. , writing correction software, automatic menu generation software, etc. By using the laptop 5300, it is possible to develop new artificial intelligence.

[0426] In the above description, a smartphone and a desktop information terminal are used as examples of electronic devices. As shown in Figures 27(A) and 27(B), the smartphone and desktop The present invention can be applied to information terminals other than personal information terminals. Examples of information terminals other than personal information terminals include PDAs (Personal Digital Assistants). Assistant), notebook type information terminal, and workstation.

[0427] [electric appliances] FIG. 27(C) shows an electric refrigerator-freezer 5800, which is an example of an electric appliance. The refrigerator 5800 includes a housing 5801, a door for a refrigerator compartment 5802, a door for a freezer compartment 5803, etc. do.

[0428] By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, artificial intelligence By utilizing artificial intelligence, The Electric Freezer Refrigerator 5800 is a refrigerator that can store food and drink. It also has a function to automatically generate menus based on the expiration date of ingredients, and a function to automatically generate menus based on the expiration date of ingredients, and the ... It can also have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0429] In this example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances may also be used. Examples include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, and induction cookers. , water servers, heating and cooling appliances including air conditioners, washing machines, dryers, Examples include audiovisual equipment.

[0430] [Game consoles]

[0431] FIG. 27(D) shows a portable game machine 5200, which is an example of a game machine. The computer includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0432] By applying a GPU or chip according to one embodiment of the present invention to the portable game console 5200, It is possible to realize a portable game machine 5200 with low power consumption. In addition, the low power consumption allows: Since heat generation from the circuit can be reduced, the circuit itself, peripheral circuits, and The impact on the module can be reduced.

[0433] Furthermore, by applying a GPU or chip according to one embodiment of the present invention to the portable game machine 5200, This makes it possible to realize a portable game machine 5200 having artificial intelligence.

[0434] Originally, the game progress, the behavior of the creatures that appear in the game, the phenomena that occur in the game, etc. The expression is determined by the program that the game has, but the portable game machine 520 By applying artificial intelligence to 0, it is possible to express things in ways that are not limited to game programs. For example, the content of the player's questions, the game progress, the time, the characters that appear in the game, This makes it possible to express things such as a person's behavior changing as they change.

[0435] In addition, when playing a game that requires multiple players on the portable game machine 5200, the artificial intelligence This allows you to create anthropomorphic game players, so you can make your opponents artificially intelligent. By making the game a game player, you can play the game by yourself.

[0436] In FIG. 27(D), a portable game machine is illustrated as an example of a game machine. The game machine to which the GPU or chip of the present invention is applied is not limited to this. Examples of game machines that apply PU or chips include home-use stationary game machines, Arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), sports facilities Examples include pitching machines for batting practice that will be installed in the stadium.

[0437] [Mobile object] The GPU or chip of one embodiment of the present invention is used in automobiles, which are moving objects, and in the vicinity of the driver's seat of the automobile. can be applied to.

[0438] FIG. 27(E1) shows an automobile 5700 as an example of a moving object, and FIG. 27(E2) shows an automobile FIG. 27(E2) is a diagram showing the area around the windshield in the interior of a vehicle. The display panels 5701, 5702, and 5703 are attached to the board. Also shown is a pillar mounted display panel 5704.

[0439] The display panels 5701 to 5703 display a speedometer, a tachometer, It can provide a variety of information, such as distance traveled, fuel amount, gear status, air conditioning settings, and more. In addition, the display items and layout displayed on the display panel can be customized to suit the user's preferences. The display panel 570 can be changed as needed to enhance the design. The display panel 5703 can also be used as a lighting device.

[0440] The display panel 5704 displays images from an imaging device (not shown) installed in the automobile 5700. By projecting images from the surroundings, it is possible to complement the view blocked by the pillars (blind spots). That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, This can compensate for blind spots and increase safety. By displaying the image on the display panel, safety checks can be performed more naturally and without discomfort. 04 can also be used as a lighting device.

[0441] The GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, e.g. For example, the chip can be used in the autonomous driving system of the 5700 automobile. The chip can be used in systems that provide road guidance, risk prediction, etc. Display panel 57 The display panels 5701 to 5704 are configured to display information such as road guidance and risk prediction. Good too.

[0442] In the above description, an automobile is used as an example of a moving object. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, etc.) These include drones, unmanned aerial vehicles (drones), airplanes, and rockets. Applying the chip of one embodiment of the present invention to a moving object and providing a system using artificial intelligence can be done.

[0443] [Broadcasting System] The GPU or chip according to one embodiment of the present invention can be applied to a broadcasting system.

[0444] FIG. 27(F) shows a schematic diagram of data transmission in a broadcasting system. Specifically, FIG. 27(F) shows how radio waves (broadcast signals) transmitted from a broadcasting station 5680 are received by televisions in each home. The diagram shows the path of the signal until it reaches the TV receiving device (TV) 5600. The broadcast signal received by the antenna 5650 is transmitted to the receiving device (not shown). The signal is then transmitted to the TV5600 via

[0445] In FIG. 27(F), the antenna 5650 is a UHF (Ultra High Frequency) The antenna shown is a BS 110°CS Antennas and CS antennas can also be applied.

[0446] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 The received radio wave 5675A is amplified and radio wave 5675B is transmitted. By receiving radio waves 5675B with the Na5650, you can watch terrestrial TV broadcasts with the TV5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 27(F), but may be any other broadcasting system. It may also be satellite broadcasting using an industrial satellite, data broadcasting via optical fiber lines, or the like.

[0447] The above-mentioned broadcasting system applies the chip according to one embodiment of the present invention to broadcast programs using artificial intelligence. The broadcasting station 5680 transmits broadcast data to the TV 5600 in each home. When the encoder is turned on, the broadcast data is compressed, and the antenna 5650 receives the broadcast data. When the data is received, the decoder of the receiving device included in the TV 5600 converts the broadcast data into By using artificial intelligence, for example, the compression method of the encoder can be improved. In motion compensation prediction, which is one of the methods, the recognition of display patterns contained in the displayed image It is also possible to perform intraframe prediction using artificial intelligence. For example, low-resolution broadcast data is received and the high-resolution TV5600 displays that broadcast data. When displaying the image, the decoder restores the broadcast data by performing up-conversion, etc. Image interpolation can be performed.

[0448] The AI-based broadcasting system described above is expected to be useful in the future, as the amount of broadcast data increases. It is suitable for revision (UHDTV: 4K, 8K) broadcasting.

[0449] In addition, as an application of artificial intelligence on the TV5600 side, for example, A recording device having the above-mentioned function may be provided. By having artificial intelligence learn the user's preferences, the system can automatically record programs that match the user's preferences. It is possible to draw

[0450] Electronic device described in the present embodiment, functions of the electronic device, application examples of artificial intelligence, and effects thereof etc. can be appropriately combined with the descriptions of other electronic devices.

[0451] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible. [Example]

[0452] In this example, a semiconductor device according to one embodiment of the present invention is a transistor shown in FIG. A transistor having a similar structure to that of Sample 200 was fabricated. The semiconductor device was examined using a scanning transmission electron microscope (STEM). The results of observations using a ion electron microscope explain.

[0453] First, the structure of sample 1 will be described. As shown in FIG. , conductor 205, insulator 216, insulator 222, insulator 224, and oxide 230. a, oxide 230b, oxide 230c, conductor 242a, conductor 242b, and insulator The edge 250, the conductor 260a, the conductor 260b, the insulator 254, and the insulator 280. , and an insulator 274.

[0454] The insulator 214 was made of aluminum oxide having a thickness of 40 nm. As the insulator 216, tungsten having a thickness of 60 nm was used. The insulator 222 was a silicon oxynitride film formed by the ALD method. The insulator 224 was made of aluminum oxide having a thickness of 35 nm. Silicon oxynitride was used.

[0455] The oxide 230a is an In film having a thickness of 5 nm formed by DC sputtering. In addition, the oxide 230a was formed using In:Ga:Zn=1 A 3:4 atomic ratio target was used, and 45 sccm of oxygen gas was used as the deposition gas. The deposition pressure was 0.7 Pa (measured using a miniature gauge MG-2 manufactured by Canon Anelva). ), the deposition power was 500 W, the substrate temperature was 200° C., and the target-substrate distance was was set to 60 mm.

[0456] The oxide 230b is a 15 nm thick I film formed by DC sputtering. The oxide 230b was formed using an n-Ga-Zn oxide. A 4:2:4.1 atomic ratio target was used, and argon gas 30 sc was used as the deposition gas. The deposition pressure was 0.7 Pa (Minichi, Canon Anelva). The temperature was measured using a gauge MG-2. The deposition power was 500 W, and the substrate temperature was 2 The temperature was set to 00° C. and the target-substrate distance was set to 60 mm.

[0457] Tantalum nitride having a film thickness of 25 nm was used as the conductor 242a and the conductor 242b. The insulator 254 is an aluminum oxide film having a thickness of 5 nm formed by sputtering. The aluminum oxide film was deposited on the aluminum substrate with a thickness of 3 nm using the ALD method. A laminated film of silicon oxide nitride was used as the insulator 280.

[0458] The oxide 230c is a laminated film. The In-Ga-Zn oxide film was 5 nm thick and was formed by the etching method. The lower layer of the object 230c was formed using a ternary compound of In:Ga:Zn=4:2:4.1 [atomic ratio]. The deposition gas used was oxygen gas at 45 sccm, and the deposition pressure was 0.7 Pa ( The measurement was performed using a miniature gauge MG-2 manufactured by Canon Anelva. The power was set to 100 W, the substrate temperature was set to 200° C., and the target-substrate distance was set to 60 mm.

[0459] In addition, a film formed by using a DC sputtering method as the upper layer of the oxide 230c is A 5 nm thick In-Ga-Zn oxide was used. The upper layer of the oxide 230c was formed using The target used was In:Ga:Zn=1:3:4 [atomic ratio], and the other film formation conditions were oxide. Same as 230a.

[0460] The insulator 250 is made of silicon oxynitride having a thickness of 10 nm. Titanium nitride with a thickness of 5 nm was used as the conductor 260a. Tungsten was used as the conductor 260b. As the insulator 274, aluminum oxide having a film thickness of 40 nm was used.

[0461] The sample 1 having the above-mentioned configuration has a channel length of 60 nm and a channel width of 60 nm. In addition to the above configuration, the sample 1 further includes a conductor 2 in the insulator 280. 40, etc., and an insulating film functioning as an interlayer film and a The conductive film is

[0462] The prepared sample 1 was accelerated using the Hitachi High-Technologies Corporation "H-9500". The voltage was set to 300 kV and cross-sectional TEM images were taken. The cross-sectional TEM images are shown in Fig. 2. 28 is a cross-sectional view TE of the oxide 230 in the channel width direction near the channel formation region. This is an M statue.

[0463] Further, Fig. 29 shows enlarged cross-sectional TEM images of the regions A to E shown in Fig. 28. Region A includes oxide 230c that is in contact with the top surface of oxide 230b. Region B includes oxide Region C includes oxide 230c in contact with the top end of oxide 230b. Region D includes an oxide 230c that is in contact with the side of the insulator 224. Region E includes the oxide 230c that is in contact with the top surface of the insulator 224. include.

[0464] In the region shown in FIG. 28 and FIG. 29, the oxide 230c is about 2 nm to 5 nm thick. The film was formed with a very thin thickness. However, as shown in Figs. 29(A) to 29(E), In addition, the oxide 230c has a layered CAAC-OS in all regions. Here, the arrows shown in FIG. 29(A) to FIG. 29(E) indicate the direction of the oxide 230c film. The arrow indicates a perpendicular direction, but the arrow indicates a normal direction of the layered crystal of the oxide 230c, i.e. The c-axis direction of the oxide 230c is roughly the same as that of the CAAC-OS. It can be seen that the OS is arranged along the irregularities of the surface on which the oxide 230c is formed.

[0465] In addition, sample 2, which has a structure similar to that of sample 1, was fabricated and a cross-sectional TEM image in the channel length direction was obtained. The cross-sectional TEM image is shown in FIG. 30. FIG. 30 shows the channel of oxide 230. This is a cross-sectional TEM image in the channel length direction near the formation region, and shows the conductor 242a and the oxide shown in FIG. 2 is an enlarged view corresponding to the vicinity of the interface of the compound 230c.

[0466] As shown in FIG. 30, in the sample 2, a layered CAAC-O Furthermore, the CAAC-OS layer in the region F is formed on the side of the conductor 242a. In other words, the c-axes of the CAAC-OS in the region F are aligned approximately parallel to the conductor 242. The oxide 230c is oriented approximately perpendicular to the side surface of the oxide 230a. At the first step, the CAAC-OS layer is approximately parallel to the CAAC-OS layer of oxide 230b. .

[0467] In addition, as in FIG. 1B, an oxide 12 is arranged on the substrate, and a metal oxide 12 is arranged on the oxide 12. Conductor 14a and conductor 14b are arranged at a distance from each other, and a conductive layer is formed on oxide 12. A sample 3 was prepared having an oxide 13 disposed between a body 14a and a conductor 14b. The substrate used was a silicon wafer with a thermal oxide film of 100 nm thickness. The oxide 12 and the oxide 13 are laminated films of In-Ga-Zn oxide. do.

[0468] The lower layer of the oxide 12 was formed by DC sputtering. The thickness of the film was 5 nm. The In-Ga-Zn oxide was used. The target was a:Zn=1:3:4 [atomic ratio], and the deposition gas was oxygen gas 45sc. The deposition pressure was 0.7 Pa (measured by a miniature gauge MG-2 manufactured by Canon Anelva). The measurement was performed under the following conditions: the deposition power was 500 W, the substrate temperature was 200° C., and the target -The distance between the boards is 60 mm.

[0469] The upper layer of the oxide 12 was formed by DC sputtering. The In:Ga:Zn oxide was used for the deposition of the upper layer of the oxide 12. A Ga:Zn=4:2:4.1 [atomic ratio] target was used, and oxygen gas 4 The deposition pressure was 0.7 Pa (Canon Anelva miniature gauge MG- The measurement was performed using a 200°C thermal expansion coefficient (TcS) 2. The deposition power was 500 W, the substrate temperature was 200°C, and the temperature was 100°C. The get-substrate distance was set to 60 mm.

[0470] The conductor 14a and the conductor 14b were made of tantalum nitride having a thickness of 25 nm. On the conductor 14a and the conductor 14b, a film having a thickness of 5 mm was formed by sputtering. nm thick aluminum oxide and a 3 nm thick aluminum oxide film formed on it using the ALD method. A laminated film of aluminum oxide was formed on the aluminum oxide laminated film. A membrane was provided.

[0471] The lower layer of the oxide 13 was formed by DC sputtering. The thickness of the film was 8 nm. The In-Ga-Zn oxide of the following structure was used. The Zn=4:2:4.1 [atomic ratio] target was used, and the other film formation conditions were the upper layer of oxide 12. The same procedure was used for the membrane.

[0472] In addition, a film having a thickness of 1.0 μm was formed on the oxide 13 by DC sputtering. An 8 nm In-Ga-Zn oxide was used. The upper layer of the oxide 13 was formed using In: The target was Ga:Zn=1:3:4 [atomic ratio], and the other film formation conditions were as follows: The same was done with the layer film.

[0473] A cross-sectional TEM image was taken of the prepared sample 3. The cross-sectional TEM image results are shown in Figure 1. FIG. 31(A) shows the channel rectangular region near the channel forming region of the oxide 12. 1. The cross-sectional TEM image corresponds to the vicinity of the interface between the conductor 14b and the oxide 13 shown in FIG. FIG.

[0474] As shown in FIG. 31(A), in the sample 3, the layered structure is formed in the region G and the region H of the oxide 13. In the region G of oxide 13 parallel to oxide 12, The AAC-OS layer was oriented approximately parallel to the CAAC-OS layer of oxide 12. In contrast, the CAAC-OS layer in region H is oriented approximately parallel to the side surface of conductor 14b. In other words, the c-axis of the CAAC-OS in the region H is aligned substantially perpendicular to the side surface of the conductor 14b. In addition, in a part of region H, the CAAC-OS layer was approximately parallel to the side surface of conductor 14b. There were also areas that were not lines.

[0475] Furthermore, a crystal orientation map created from a cross-sectional TEM image of sample 3 is shown in FIG. The crystal orientation map shown in FIG. 31(B) is a FFT map for each FFT window with a diameter of 15 nm. Analysis was performed to calculate the crystallinity and c-axis inclination of each pixel in the cross-sectional TEM image of sample 3. In FIG. 31(B), the darker the color in the crystalline region, the greater the inclination of the c-axis with respect to the substrate surface. The brighter the color, the closer the c-axis is to the substrate surface, and the brighter the color, the closer the c-axis is to the substrate surface. In other words, in the crystalline region, the darker the color, the closer the c-axis is to The brighter the color, the closer the c-axis is to being approximately parallel to the substrate surface. It becomes.

[0476] In FIG. 31(B), as in FIG. 31(A), the oxide 13 is parallel to the oxide 12. In region G, the c-axis of the CAAC-OS was aligned almost perpendicular to the substrate surface. The c-axis of the CAAC-OS in region H is tilted at an angle of about 20° to 40° with respect to the substrate surface. The CAAC-OS c There were also regions where the axis was not tilted by about 20° to 40° with respect to the substrate surface.

[0477] The configurations and methods shown in the present embodiment are at least partially described in this specification. The present invention can be implemented in appropriate combination with the embodiment modes. [Explanation of symbols]

[0478] 10a: transistor, 10b: transistor, 10c: transistor, 12: oxide, 12a: layer, 12b: c-axis, 13: oxide, 13a: layer, 13b: c-axis, 14a: conductor , 14b: conductor, 100: capacitive element, 110: conductor, 112: conductor, 120: conductor body, 130: insulator, 150: insulator, 200: transistor, 205: conductor, 210 : insulator, 212: insulator, 214: insulator, 216: insulator, 218: conductor, 222 : insulator, 224: insulator, 230: oxide, 230a: oxide, 230A: oxide film, 2 30b: Oxide, 230B: Oxide film, 230c: Oxide, 230C: Oxide film, 240: Conductive conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 24 1b: insulator, 242: conductor, 242a: conductor, 242A: conductive film, 242b: conductor body, 242B: conductor layer, 243: conductor, 243a: conductor, 243A: conductor layer, 2 43b: conductor, 244: insulator, 244A: insulating film, 246: conductor, 250: insulator , 250A: insulating film, 254: insulator, 254A: insulating film, 260: conductor, 260a: Conductor, 260Aa: Conductive film, 260Ab: Conductive film, 260b: Conductor, 262: Dummy Gate, 262A: dummy gate layer, 263: opening, 264: opening, 264a: opening, 2 64b: opening, 265: dummy film, 274: insulator, 276: insulator, 280: insulator, 281: insulator, 300: transistor, 311: substrate, 313: semiconductor region, 314a : low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator body, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor body, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 400: transistor Transistor, 405: conductor, 405a: conductor, 405b: conductor, 430c: oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: oxide, 440: Conductor, 440a: Conductor, 440b: Conductor, 442: Conductor, 442a: Conductor, 4 42b: conductor, 450: insulator, 460: conductor, 460a: conductor, 460b: conductive body, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring line, 1006: wiring, 1007: wiring, 1008: wiring, 1009: wiring, 1010: wiring Line, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB Connector, 1104: Board, 1105: Memory chip, 1106: Controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: board, 111 4: memory chip, 1115: controller chip, 1150: SSD, 1151: case 1152: connector, 1153: board, 1154: memory chip, 1155: memory chip chip, 1156: controller chip, 1200: chip, 1201: PCB, 1202 : Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog computing unit, 1214: memory controller, 121 5: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 1400: storage device, 1411: peripheral circuit, 1420: row circuit, 14 30: column circuit, 1440: output circuit, 1460: control logic circuit, 1470: memory cell array, 1471: memory cell, 1472: memory cell, 1473: memory cell 1474: memory cell, 1475: memory cell, 1476: memory cell, 1477: Memory cell, 1478: Memory cell, 5200: Portable game machine, 5201: Housing, 520 2: display unit, 5203: button, 5300: desktop information terminal, 5301: main unit, 5302: Display, 5303: Keyboard, 5500: Information terminal, 5510: Housing , 5511: display unit, 5600: TV, 5650: antenna, 5670: radio tower, 567 5A: Radio waves, 5675B: Radio waves, 5680: Broadcasting station, 5700: Car, 5701: Display panel, 5702: display panel, 5703: display panel, 5704: display panel, 580 0: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer door

Claims

1. A first oxide semiconductor; a first conductor having a region in contact with a top surface of the first oxide semiconductor and functioning as one of a source electrode and a drain electrode of a transistor; a second conductor having a region in contact with a top surface of the first oxide semiconductor and functioning as the other of the source electrode and drain electrode of the transistor; a first insulator disposed on the first conductor and the second conductor, the first insulator having an opening in a region overlapping the first oxide semiconductor; a second oxide semiconductor having a region in contact with a top surface of the first oxide semiconductor, a region in contact with a side surface of the first conductor, and a region in contact with a side surface of the second conductor, the second oxide semiconductor having a region overlapping with the opening; a second insulator having a region that overlaps with the opening and is in contact with an upper surface of the second oxide semiconductor; a third conductor disposed in the opening and having a region above the second insulator, the third conductor functioning as a gate electrode of the transistor; a third insulator having a region in contact with an upper surface of the first conductor and a region in contact with a side surface of the second oxide semiconductor; The third insulator has a lower hydrogen permeability than the first insulator.

2. In claim 1, The first oxide semiconductor and the second oxide semiconductor each contain In, an element M (M is Al, Ga, Y, or Sn), and Zn.

3. In claim 2, a ratio of the number of atoms of In to the element M in the first oxide semiconductor is greater than a ratio of the number of atoms of In to the element M in the second oxide semiconductor.

Images