Silicon carbide semiconductor device and manufacturing method of the silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of suppressing a temperature change of a diode characteristic, and provide a manufacturing method of the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device 200 includes: a silicon carbide substrate 100; a first electrode 61; a second electrode 62; a first main surface 1; a second main surface 2; a first impurity region 10; a second impurity region 20; and a third impurity region 30. The first electrode is contacted to the second and third impurity regions in the first main surface. The second electrode is contacted to the first impurity region in the second main surface. The second impurity region contains: a first region 21, and a second region 22 that is existed to between the first region and the second main surface, and is contacted to the first region. An impurity density of the first region is 6×1016 cm-3 or more.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing the same. This application claims priority to Japanese Patent Application No. 2019-196257, filed on October 29, 2019. The entire contents of the Japanese patent application are incorporated herein by reference. [Background technology]

[0002] Kazuto Takao and two others, "High-frequency-driven high-power conversion device using a hybrid pair of SiC-PiN diode and Si-IEGT," Toshiba Review, Vol. 66, No. 5, 2011 (Non-Patent Document 1), describes the IV characteristics of SiC-PiN diodes. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Kazuto Takao and 2 others, "High-frequency-driven high-power converter using hybrid pairs of SiC-PiN diodes and Si-IEGTs," Toshiba Review, Vol. 66, No. 5, 2011 Summary of the Invention

[0004] The silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface and provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having the first conductivity type. The first electrode contacts each of the second impurity region and the third impurity region on the first main surface. The second electrode contacts the first impurity region on the second main surface. The second impurity region includes a first region and a second region between the first region and the second main surface and in contact with the first region. The impurity concentration of the first region is 6×10 16 cm -3 That's all.

[0005] The silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate includes a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface and provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having the first conductivity type. The first electrode contacts each of the second impurity region and the third impurity region on the first main surface. The second electrode contacts the first impurity region on the second main surface. The second impurity region includes a first region and a second region between the first region and the second main surface and in contact with the first region. The point defect density of the first region is 6×10 12 cm -3 That's all.

[0006] A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps. A silicon carbide substrate is prepared having a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface, provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having the first conductivity type. A first electrode is formed in the first main surface in contact with each of the second impurity region and the third impurity region. A second electrode is formed in the second main surface in contact with the first impurity region. The second impurity region includes a first region and a second region between the first region and the second main surface and in contact with the first region. The impurity concentration of the first region is 6×10 16 cm -3 The first region is formed by ion implantation. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a configuration of a silicon carbide semiconductor device in accordance with the first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 3 is an enlarged schematic view of region III in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a configuration of a silicon carbide semiconductor device according to the second embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing a configuration of a silicon carbide semiconductor device according to the third embodiment. [Figure 6] FIG. 6 is a flowchart showing an outline of the method for manufacturing a silicon carbide semiconductor device according to this embodiment. [Figure 7] FIG. 7 is a flow chart outlining the steps of preparing a silicon carbide substrate in the method for manufacturing a silicon carbide semiconductor device according to this embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a first step of the method for manufacturing a silicon carbide semiconductor device in accordance with this embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a second step of the method for manufacturing a silicon carbide semiconductor device in accordance with this embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a third step of the method for manufacturing a silicon carbide semiconductor device in accordance with this embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a fourth step of the method for manufacturing a silicon carbide semiconductor device in accordance with this embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a fifth step of the method for manufacturing a silicon carbide semiconductor device in accordance with this embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a sixth step of the method for manufacturing a silicon carbide semiconductor device in accordance with this embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a seventh step of the method for manufacturing a silicon carbide semiconductor device in accordance with this embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view showing an eighth step of the method for manufacturing a silicon carbide semiconductor device in accordance with this embodiment. [Figure 16] 1 shows the relationship between drain current density and drain voltage in a silicon carbide semiconductor device according to Sample 1. FIG. [Figure 17] 13 is a graph showing the relationship between drain current density and drain voltage in a silicon carbide semiconductor device according to Sample 2. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] [Problem that this disclosure aims to solve] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of suppressing temperature change in diode characteristics and a method for manufacturing a silicon carbide semiconductor device. [Effects of this disclosure] Advantageous Effects of Invention According to the present disclosure, it is possible to provide a silicon carbide semiconductor device capable of suppressing temperature change in diode characteristics and a method for manufacturing a silicon carbide semiconductor device. [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. In the crystallographic description in this specification, an individual orientation is represented by [], a collective orientation by <>, an individual plane by (), and a collective plane by {}. A negative index in crystallography is usually represented by placing a "-" (bar) above the number, but in this specification, a negative index in crystallography is represented by placing a negative sign before the number.

[0009] (1) A silicon carbide semiconductor device 200 according to the present disclosure includes a silicon carbide substrate 100, a first electrode 61, and a second electrode 62. The silicon carbide substrate 100 includes a first main surface 1, a second main surface 2 opposite to the first main surface 1, a first impurity region 10 constituting at least a part of the second main surface 2 and having a first conductivity type, a second impurity region 20 constituting at least a part of the first main surface 1 and provided in contact with the first impurity region 10 and having a second conductivity type different from the first conductivity type, and a third impurity region 30 provided in contact with the second impurity region 20 so as to be separated from the first impurity region 10 and having the first conductivity type. The first electrode 61 contacts each of the second impurity region 20 and the third impurity region 30 on the first main surface 1. The second electrode 62 contacts the first impurity region 10 on the second main surface 2. The second impurity region 20 includes a first region 21 and a second region 22 that is between the first region 21 and the second main surface 2 and in contact with the first region 21. The impurity concentration of the first region 21 is 6×10 16 cm -3 That's all.

[0010] (2) According to the silicon carbide semiconductor device 200 according to (1) above, the impurity concentration of the second region 22 is 6×10 16 cm -3 It may be more than that.

[0011] (3) A silicon carbide semiconductor device 200 according to the present disclosure includes a silicon carbide substrate 100, a first electrode 61, and a second electrode 62. The silicon carbide substrate 100 includes a first main surface 1, a second main surface 2 opposite to the first main surface 1, a first impurity region 10 constituting at least a part of the second main surface 2 and having a first conductivity type, a second impurity region 20 constituting at least a part of the first main surface 1 and provided in contact with the first impurity region 10 and having a second conductivity type different from the first conductivity type, and a third impurity region 30 provided in contact with the second impurity region 20 so as to be separated from the first impurity region 10 and having the first conductivity type. The first electrode 61 contacts each of the second impurity region 20 and the third impurity region 30 on the first main surface 1. The second electrode 62 contacts the first impurity region 10 on the second main surface 2. The second impurity region 20 includes a first region 21 and a second region 22 that is between the first region 21 and the second main surface 2 and in contact with the first region 21. The point defect density of the first region 21 is 6×10 12 cm -3 That's all.

[0012] (4) According to silicon carbide semiconductor device 200 according to (3) above, first region 21 has a point defect density of 1×10 14 cm -3 It may be the following.

[0013] (5) According to the silicon carbide semiconductor device 200 according to any one of (1) to (4) above, the silicon carbide semiconductor device 200 may be of a planar type.

[0014] (6) According to silicon carbide semiconductor device 200 according to any one of (1) to (4) above, silicon carbide substrate 100 may be provided with trench 5. Trench 5 may have side surface 3 in contact with each of first impurity region 10, second impurity region 20 and third impurity region 30, and bottom surface 4 continuing from side surface 3 and in contact with first impurity region 10.

[0015] (7) According to silicon carbide semiconductor device 200 relating to (6) above, trench 5 may have a U-shape in a cross section perpendicular to first main surface 1.

[0016] (8) According to silicon carbide semiconductor device 200 relating to (6) above, trench 5 may have a V-shape in a cross section perpendicular to first main surface 1.

[0017] (9) According to silicon carbide semiconductor device 200 according to any one of (1) to (8) above, first main surface 1 may be a (000-1) plane or a plane inclined at an angle of 8° or less with respect to the (000-1) plane.

[0018] (10) In silicon carbide semiconductor device 200 according to any one of (1) to (9) above, first region 21 may have a higher impurity concentration than second region 22.

[0019] (11) According to the silicon carbide semiconductor device 200 according to (10) above, the impurity concentration of the first region 21 is 1×10 19 cm -3 It may be the following.

[0020] (12) A method for manufacturing a silicon carbide semiconductor device 200 according to the present disclosure includes the following steps. A silicon carbide substrate 100 is prepared, the silicon carbide substrate 100 having a first main surface 1, a second main surface 2 opposite to the first main surface 1, a first impurity region 10 constituting at least a part of the second main surface 2 and having a first conductivity type, a second impurity region 20 constituting at least a part of the first main surface 1, provided in contact with the first impurity region 10 and having a second conductivity type different from the first conductivity type, and a third impurity region 30 provided in contact with the second impurity region 20 so as to be separated from the first impurity region 10 and having the first conductivity type. A first electrode 61 is formed on the first main surface 1 in contact with each of the second impurity region 20 and the third impurity region 30. A second electrode 62 is formed on the second main surface 2 in contact with the first impurity region 10. The second impurity region 20 includes a first region 21 and a second region 22 that is between the first region 21 and the second main surface 2 and in contact with the first region 21. The impurity concentration of the first region 21 is 6×10 16 cm -3 That is all. The first region 21 is formed by ion implantation.

[0021] (13) According to the method for manufacturing silicon carbide semiconductor device 200 relating to (12) above, second region 22 may be formed by ion implantation.

[0022] (14) According to the method for manufacturing silicon carbide semiconductor device 200 according to (12) or (13) above, first impurity region 10 may be formed by epitaxial growth under a temperature condition of 1500° C. or higher and 1750° C. or lower.

[0023] (15) In the method for manufacturing silicon carbide semiconductor device 200 according to any one of (12) to (14) above, the step of preparing silicon carbide substrate 100 may include an activation annealing step. The activation annealing step may be performed under a temperature condition of 1600° C. or higher and 1850° C. or lower. [Details of the embodiment of the present disclosure] Hereinafter, the details of the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0024] (First embodiment) First, a description will be given of the configuration of a silicon carbide semiconductor device 200 in accordance with the first embodiment. Fig. 1 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device 200 in accordance with the first embodiment.

[0025] 1, the silicon carbide semiconductor device 200 according to the first embodiment is a trench MOSFET and mainly includes a silicon carbide substrate 100, a gate electrode 63, a gate insulating film 51, an isolation insulating film 52, a first electrode 61, and a second electrode 62. The silicon carbide substrate 100 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1.

[0026] The first main surface 1 is, for example, a {0001} plane or a plane that is off by 8° or less with respect to the {0001} plane. Specifically, the first main surface 1 is, for example, a (000-1) plane or a plane that is inclined at an angle of 8° or less with respect to the (000-1) plane. The first main surface 1 may be, for example, a (0001) plane or a plane that is inclined at an angle of 8° or less with respect to the (0001) plane.

[0027] As shown in FIG. 1, silicon carbide substrate 100 includes a first impurity region 10, a second impurity region 20, and a third impurity region 30. First impurity region 10 includes an n-type impurity capable of imparting n-type, such as N (nitrogen). First impurity region 10 has, for example, an n-type (first conductivity type). First impurity region 10 constitutes at least a part of second main surface 2. In other words, first impurity region 10 may constitute the entire surface of second main surface 2, or may constitute a part of second main surface 2.

[0028] The first impurity region 10 has a silicon carbide single crystal substrate 15, a buffer layer 11, a first super junction region 12, a first joint region 13, and a current spreading region 14. The silicon carbide single crystal substrate 15 constitutes the second main surface 2. The silicon carbide single crystal substrate 15 is made of, for example, hexagonal silicon carbide of polytype 4H. The buffer layer 11 is provided on the silicon carbide single crystal substrate 15. The buffer layer 11 is in contact with the silicon carbide single crystal substrate 15.

[0029] The first superjunction region 12 is provided on the buffer layer 11. The first superjunction region 12 is in contact with the buffer layer 11. In the first direction 101, the width of the first superjunction region 12 is smaller than the width of the buffer layer 11. The height of the first superjunction region 12 in the third direction 103 may be larger than the width of the first superjunction region 12 in the first direction 101. The concentration of n-type impurities in the first superjunction region 12 may be lower than the concentration of n-type impurities in the buffer layer 11.

[0030] The first joint region 13 is provided on the first superjunction region 12. The first joint region 13 is in contact with the first superjunction region 12. The first joint region 13 may be narrowed so that the width at the center is smaller than the widths at the top and bottom. The current spreading region 14 is provided on the first joint region 13. The current spreading region 14 is in contact with the first joint region 13. The current spreading region 14 is in contact with each of the bottom surface 4 and the side surface 3 of the trench 5.

[0031] The impurity concentration of the first impurity region 10 is, for example, 6×10 16 cm -3 Specifically, the concentration of the n-type impurity in the first superjunction region 12 of the first impurity region 10 is, for example, 6×10 16 cm -3 The concentration of the n-type impurity in the first superjunction region 12 of the first impurity region 10 is, for example, 8×10 16 cm -3 It can be more than 10 x 10 16 cm -3 It may be more than that.

[0032] The concentration of the n-type impurity in the first joint region 13 of the first impurity region 10 is, for example, 6×10 16 cm -3 The concentration of n-type impurities in the current spreading region 14 of the first impurity region 10 is, for example, 6×10 16 cm -3 The concentration of n-type impurities in each of the first superjunction region 12, the first joint region 13, and the current spreading region 14 is, for example, 6×10 16 cm -3 It may be more than that.

[0033] The second impurity region 20 contains a p-type impurity capable of imparting p-type, such as Al (aluminum). The second impurity region 20 has a p-type (second conductivity type) different from n-type. The second impurity region 20 is provided in contact with the first impurity region 10. The second impurity region 20 and the first impurity region 10 form a PN diode. The second impurity region 20 forms at least a part of the first main surface 1. In other words, the second impurity region 20 may form the entire surface of the first main surface 1, or may form a part of the first main surface 1.

[0034] The second impurity region 20 has a first region 21 and a second region 22. The second region 22 is between the first region 21 and the second main surface 2. The second region 22 is in contact with the first region 21. The first region 21 constitutes at least a part of the first main surface 1. The first region 21 may have, for example, a first portion 41 and a second portion 42. The first portion 41 is on the second portion 42. The second portion 42 is in contact with the first portion 41. The concentration of the p-type impurity in the first portion 41 may be higher than the concentration of the p-type impurity in the second portion 42. The second portion 42 is, for example, a channel layer. The first region 21 may not have the first portion 41. The second region 22 may be in contact with the buffer layer 11.

[0035] The second region 22 includes a second superjunction region 25, a second joint region 24, and a third joint region 23. The second superjunction region 25 is provided on the buffer layer 11. The second superjunction region 25 is in contact with the buffer layer 11. In the first direction 101, the width of the second superjunction region 25 is smaller than the width of the buffer layer 11. In the third direction 103, the height of the second superjunction region 25 may be larger than the width of the second superjunction region 25 in the first direction 101.

[0036] The first superjunction region 12 and the second superjunction region 25 configure a superjunction. The first superjunction region 12 is in contact with the second superjunction region 25. The first superjunction region 12 and the second superjunction region 25 are alternately arranged in the first direction 101. The concentration of p-type impurities in the second superjunction region 25 may be approximately equal to the concentration of n-type impurities in the first superjunction region 12. In the first direction 101, the width of the second superjunction region 25 may be approximately equal to the width of the first superjunction region 12.

[0037] The second joint region 24 is provided on the second superjunction region 25. The second joint region 24 is in contact with the second superjunction region 25. The second joint region 24 may be expanded such that the width at the center is greater than the widths at the top and bottom. In the first direction 101, the maximum width of the second joint region 24 may be greater than the width of the second superjunction region 25. The second joint region 24 is in contact with the first joint region 13. In the first direction 101, the second joint region 24 and the first joint region 13 are alternately arranged.

[0038] The third joint region 23 is provided on the second joint region 24. The third joint region 23 contacts each of the second joint region 24 and the first region 21. In the third direction 103, the third joint region 23 is located between the second joint region 24 and the first region 21. In the first direction 101, the third joint region 23 contacts the current spreading region 14.

[0039] The impurity concentration of the second region 22 is 6×10 16 cm -3 Specifically, the concentration of p-type impurities in the second superjunction region 25 of the second region 22 is 6×10 16 cm -3The concentration of p-type impurities in the second superjunction region 25 of the second region 22 is 8×10 16 cm -3 It can be more than 10 x 10 16 cm -3 The upper limit of the concentration of the p-type impurity in the second superjunction region 25 of the second region 22 is not particularly limited, but may be, for example, 6×10 18 cm -3 It may be the following.

[0040] The concentration of p-type impurities in the second joint region 24 of the second region 22 is, for example, 6×10 16 cm -3 The concentration of the p-type impurity in the third joint region 23 of the second region 22 is, for example, 6×10 16 cm -3 The concentration of p-type impurities in each of the second superjunction region 25, the second joint region 24, and the third joint region 23 is, for example, 6×10 16 cm -3 It may be more than that.

[0041] The third impurity region 30 is provided in contact with the second impurity region 20 so as to be separated from the first impurity region 10. The third impurity region 30 contains an n-type impurity capable of imparting an n-type, such as P (phosphorus). The third impurity region 30 has, for example, an n-type. The third impurity region 30 is, for example, a source region. The third impurity region 30 may constitute a part of the first main surface 1. The concentration of the n-type impurity contained in the third impurity region 30 may be higher than the concentration of the p-type impurity contained in the second portion 42.

[0042] The impurity concentration of the first region 21 is 6×10 16 cm -3 Specifically, the concentration of p-type impurities in the first region 21 is 6×10 16 cm -3That is all. The impurity concentration of the first region 21 may be higher than the impurity concentration of the second region 22. Specifically, the p-type impurity concentration of the second portion 42 of the first region 21 may be higher than the p-type impurity concentration of the second region 22. The impurity concentration of the first region 21 may be 1×10 19 cm -3 Specifically, the concentration of the p-type impurity in the second portion 42 of the first region 21 may be 1×10 19 cm -3 The concentration of the p-type impurity in the second portion 42 of the first region 21 may be 8×10 18 cm -3 It may be less than or equal to 6 x 10 18 cm -3 The lower limit of the concentration of the p-type impurity in the second portion 42 of the first region 21 is not particularly limited, but may be, for example, 6×10 17 cm -3 It may be more than that.

[0043] The silicon carbide substrate 100 is provided with a trench 5. The trench 5 opens to the first main surface 1. The trench 5 has a side surface 3 and a bottom surface 4. The bottom surface 4 is continuous with the side surface 3. The side surface 3 is in contact with each of the first impurity region 10, the second impurity region 20, and the third impurity region 30. Specifically, the side surface 3 is in contact with each of the current spreading region 14, the second portion 42, and the third impurity region 30. The bottom surface 4 is in contact with the first impurity region 10. Specifically, the bottom surface 4 is in contact with the current spreading region 14.

[0044] In a cross section perpendicular to the first main surface 1, the trench 5 may have a V-shape. The V-shape of the trench 5 means that the angle θ between the side surface 3 of the trench 5 and the first main surface 1 is greater than 90° and less than 180°. The angle θ may be, for example, greater than or equal to 115° and less than or equal to 135°.

[0045] The gate insulating film 51 is made of, for example, silicon dioxide. The gate insulating film 51 is disposed inside the trench 5. The gate insulating film 51 contacts each of the first impurity region 10, the second impurity region 20, and the third impurity region 30 at the side surface 3 of the trench 5. The gate insulating film 51 contacts the current spreading region 14 at the bottom surface 4 of the trench 5. A channel can be formed in the second portion 42 of the second impurity region 20 that contacts the gate insulating film 51. The gate insulating film 51 contacts the third impurity region 30 at the first main surface 1. The thickness of the gate insulating film 51 is, for example, not less than 40 nm and not more than 150 nm.

[0046] The gate electrode 63 is provided on the gate insulating film 51. The gate electrode 63 is arranged in contact with the gate insulating film 51. At least a portion of the gate electrode 63 is arranged inside the trench 5. The gate electrode 63 is made of a conductor such as polysilicon doped with impurities.

[0047] The isolation insulating film 52 is provided to cover the gate electrode 63. The isolation insulating film 52 is in contact with each of the gate electrode 63 and the gate insulating film 51. The isolation insulating film 52 is made of, for example, an NSG (None-doped Silicate Glass) film or a PSG (Phosphorus Silicate Glass) film. The isolation insulating film 52 electrically insulates the gate electrode 63 from the first electrode 61.

[0048] The first electrode 61 is provided on the first main surface 1. The first electrode 61 is, for example, a source electrode. The first electrode 61 has an electrode layer 60 and a wiring layer 64. The electrode layer 60 is made of a material including, for example, Ti (titanium), Al (aluminum), and Si (silicon). The electrode layer 60 may include Ni (nickel). The wiring layer 64 is made of a material including, for example, Al.

[0049] The first electrode 61 is in contact with each of the second impurity region 20 and the third impurity region 30 on the first main surface 1. Specifically, the electrode layer 60 is in contact with each of the first portion 41 and the third impurity region 30 on the first main surface 1. The first electrode 61 may be disposed so as to straddle the trench 5. The first electrode 61 may cover the isolation insulating film 52. The first electrode 61 is electrically connected to the second impurity region 20. The first electrode 61 is electrically connected to the third impurity region 30. When the first impurity region 10 is of n-type and the second impurity region 20 is of p-type, the first electrode 61 functions as an anode electrode.

[0050] The second electrode 62 is provided on the second main surface 2. The second electrode 62 is, for example, a drain electrode. The second electrode 62 is in contact with the first impurity region 10 at the second main surface 2. Specifically, the second electrode 62 is in contact with the silicon carbide single crystal substrate 15 at the second main surface 2. The second electrode 62 is electrically connected to the first impurity region 10. When the first impurity region 10 is n-type and the second impurity region 20 is p-type, the second electrode 62 functions as a cathode electrode. The second electrode 62 is made of a material capable of forming an ohmic junction with the n-type silicon carbide single crystal substrate 15, such as NiSi (nickel silicide).

[0051] In silicon carbide semiconductor device 200 according to the first embodiment, the breakdown voltage in the reverse characteristic is, for example, 600V or more, and preferably 1100V or more.

[0052] Next, a method for measuring the p-type impurity concentration and the n-type impurity concentration in each impurity region will be described.

[0053] The concentration of p-type impurities and the concentration of n-type impurities in each impurity region can be measured using SIMS (Secondary Ion Mass Spectrometry). The measurement device is, for example, a secondary ion mass spectrometer manufactured by Cameca. The measurement pitch is, for example, 0.01 μm. When the n-type impurity to be detected is nitrogen, the primary ion beam is cesium (Cs). The primary ion energy is 14.5 keV. The secondary ion polarity is negative. When the p-type impurity to be detected is aluminum or boron, the primary ion beam is oxygen (O2). The primary ion energy is 8 keV. The secondary ion polarity is positive.

[0054] Next, a method for distinguishing between p-type and n-type regions will be described. A scanning capacitance microscope (SCM) is used to distinguish between p-type and n-type regions. The measuring device is, for example, a NanoScope IV manufactured by Bruker AXS. SCM is a method for visualizing the carrier concentration distribution in a semiconductor. Specifically, a metal-coated silicon probe is used to scan the surface of the sample. During this process, a high-frequency voltage is applied to the sample. The majority carriers are excited, modulating the capacitance of the system. The frequency of the high-frequency voltage applied to the sample is 100 kHz, and the voltage is 4.0 V.

[0055] 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. As shown in FIG. 2, the second superjunction region 25 extends, for example, along the second direction 102 when viewed in a direction perpendicular to the second main surface 2. From another perspective, the longitudinal direction of the second superjunction region 25 is, for example, the second direction 102. The lateral direction of the second superjunction region 25 is, for example, the first direction 101. When viewed in a direction perpendicular to the second main surface 2, the second superjunction region 25 may be substantially rectangular. When viewed in a direction perpendicular to the second main surface 2, the first superjunction region 12 may surround the second superjunction region 25.

[0056] Each of the first direction 101 and the second direction 102 is parallel to the second main surface 2. The third direction 103 is perpendicular to the second main surface 2. The first direction 101 is, for example, the <11-20> direction. The second direction 102 is, for example, the <1-100> direction. The third direction 103 is, for example, <0001> The first direction 101 may be, for example, a direction obtained by projecting the <11-20> direction onto the first main surface 1. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1. The third direction 103 may be, for example, <0001> The direction may be inclined with respect to the direction.

[0057] 3 is an enlarged schematic diagram of region III in FIG. 2. As shown in FIG. 3, the second region 22 has a point defect 9. The energy level of the point defect 9 is 0.5 eV or more deeper than Ec (the energy at the bottom of the conduction band) and 0.4 eV or more higher than Ev (the energy at the top of the valence band). The point defect 9 is Z 1 / 2 The first defect, called the center, is 7, and the EH 6 / 7 The second defect 8 may be called the center. 1 / 2 The energy level of the center is Ec (the bottom energy of the conduction band) -0.65 eV. EH 6 / 7The energy level of the center is Ec (the bottom energy of the conduction band) -1.55 eV. The second region 22 may have both the first defects 7 and the second defects 8, may have only the first defects 7, or may have only the second defects 8.

[0058] The point defect density of the second region 22 is 6×10 12 cm -3 The point defect density of the second region 22 is, for example, 8×10 12 cm -3 It can be more than 10 x 10 12 cm -3 The point defect density of the second region 22 may be, for example, 1×10 14 cm -3 The point defect density of the second region 22 may be, for example, 0.8×10 14 cm -3 It may be less than or equal to 0.6 x 10 14 cm -3 In addition, when the second region 22 has the first defects 7 and the second defects 8, the point defect density of the second region 22 is the total point defect density of the first defects 7 and the second defects 8.

[0059] Next, a method for measuring the point defect density will be described. The point defect density can be measured by the DLTS (Deep Level Transient Spectroscopy) method and / or the ICTS (Isothermal Capacitance Transient Spectroscopy) method. In the DLTS method, the pulse width is kept constant and the temperature is changed to obtain the time change of the junction capacitance. In the ICTS method, the temperature is kept constant and the pulse width is changed to obtain the time change of the junction capacitance. Although point defect information can be obtained by either the DLTS method or the ICTS method, by performing both, the information of the point defects can be obtained more accurately. For example, the FT1230 manufactured by Phystech can be used as a measuring device. The temperature of the sample is in the range of 77K to 773K, and a pulse voltage is applied to obtain the time change of the junction capacitance. The pulse voltage is +20V to -20V, and the pulse width is 1μs to 60s. The point defect density and its energy level can be obtained by Fourier transform or Laplace transform of the transient change of the junction capacitance.

[0060] Second embodiment Next, the configuration of the silicon carbide semiconductor device 200 according to the second embodiment will be described. The silicon carbide semiconductor device 200 according to the second embodiment differs from the silicon carbide semiconductor device 200 according to the first embodiment in that the trench 5 has a U-shape, and other configurations are similar to those of the silicon carbide semiconductor device 200 according to the first embodiment. The following description will focus on the configurations that differ from the silicon carbide semiconductor device 200 according to the first embodiment.

[0061] FIG. 4 is a cross-sectional schematic diagram showing a configuration of a silicon carbide semiconductor device 200 according to a second embodiment. As shown in FIG. 4, in a cross section perpendicular to the first main surface 1, the trench 5 has a U-shape. Specifically, the trench 5 has a side surface 3 and a bottom surface 4. The angle θ between the first main surface 1 and the side surface 3 is 90°. The side surface 3 extends substantially perpendicular to the first main surface 1. The bottom surface 4 extends substantially parallel to the first main surface 1. The boundary between the side surface 3 and the bottom surface 4 may be rounded.

[0062] Third embodiment Next, a configuration of the silicon carbide semiconductor device 200 according to the third embodiment will be described. The silicon carbide semiconductor device 200 according to the third embodiment differs from the silicon carbide semiconductor device 200 according to the first embodiment in that it is a planar type, and other configurations are similar to those of the silicon carbide semiconductor device 200 according to the first embodiment. The following description will focus on the configurations that differ from the silicon carbide semiconductor device 200 according to the first embodiment.

[0063] FIG. 5 is a cross-sectional schematic diagram showing a configuration of a silicon carbide semiconductor device 200 according to the third embodiment. As shown in FIG. 5, the silicon carbide semiconductor device 200 according to the third embodiment is a planar type. The gate insulating film 51 is provided on the first main surface 1. The gate insulating film 51 may be in contact with each of the third impurity region 30, the second portion 42, and the current spreading region 14 on the first main surface 1. The second portion 42 may constitute a part of the first main surface 1. The current spreading region 14 may constitute a part of the first main surface 1. The gate electrode 63 may face each of the third impurity region 30, the second portion 42, and the current spreading region 14.

[0064] (Method for manufacturing silicon carbide semiconductor device) Next, a method for manufacturing the silicon carbide semiconductor device according to this embodiment will be described.

[0065] As shown in Fig. 6, the method for manufacturing silicon carbide semiconductor device 200 according to this embodiment mainly includes a step of preparing a silicon carbide substrate (S10: Fig. 6), a step of forming a first electrode (S20: Fig. 6), and a step of forming a second electrode (S30: Fig. 6). As shown in Fig. 7, the step of preparing a silicon carbide substrate (S10: Fig. 6) mainly includes a step of preparing a silicon carbide single crystal substrate (S11: Fig. 7), a step of forming a second region (S12: Fig. 7), and an activation annealing step (S13: Fig. 7).

[0066] First, a step (S11: FIG. 7) of preparing a silicon carbide single crystal substrate is performed. For example, a silicon carbide ingot (not shown) manufactured by sublimation is sliced ​​to prepare silicon carbide single crystal substrate 15. As shown in FIG. 8, silicon carbide single crystal substrate 15 has a third main surface 6 and a second main surface 2. Second main surface 2 is on the opposite side to third main surface 6. The polytype of silicon carbide constituting silicon carbide single crystal substrate 15 is, for example, 4H. The polytype may be 6H, 15R, or 3C. 6H is a hexagonal crystal. 15H is a rhombohedral crystal. 3C is a cubic crystal.

[0067] Next, the buffer layer 11 is formed. For example, a mixed gas of silane (SiH4) and propane (C3H8) is used as a source gas, and the buffer layer 11 is formed on the silicon carbide single crystal substrate 15 by a chemical vapor deposition (CVD) method using, for example, hydrogen (H2) as a carrier gas (see FIG. 9). During epitaxial growth, an n-type impurity such as nitrogen is introduced into the buffer layer 11.

[0068] Next, a step of forming second region 22 (S12: FIG. 7) is performed. A first epitaxial layer 70 is formed on buffer layer 11 by a CVD method using, for example, a mixed gas of silane and propane as a source gas and, for example, hydrogen as a carrier gas (see FIG. 10). During epitaxial growth, an n-type impurity such as nitrogen is introduced into first epitaxial layer 70. First epitaxial layer 70 has n-type conductivity. The concentration of n-type impurity in first epitaxial layer 70 may be lower than the concentration of n-type impurity in buffer layer 11.

[0069] Next, a mask layer (not shown) having an opening is formed on the first epitaxial layer 70. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the first epitaxial layer 70. This forms a first p-type region 251 (see FIG. 11 ). In the first epitaxial layer 70, a region in which the first p-type region 251 is not formed becomes the first n-type region 121. The first p-type region 251 is in contact with the first n-type region 121. The first p-type region 251 becomes a part of the second region 22.

[0070] Next, the second epitaxial layer 71 is formed. For example, the second epitaxial layer 71 is formed on the first epitaxial layer 70 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas (see FIG. 12). During the epitaxial growth, an n-type impurity such as nitrogen is introduced into the second epitaxial layer 71. The second epitaxial layer 71 has an n-type conductivity.

[0071] Next, a step of injecting p-type impurity ions is performed. For example, a mask layer (not shown) having an opening is formed on the second epitaxial layer 71. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the second epitaxial layer 71. This forms the second p-type region 252. The second p-type region 252 is formed so as to be connected to the first p-type region 251 (see FIG. 13). The second p-type region 252 becomes a part of the second region 22. In the second epitaxial layer 71, a region in which the second p-type region 252 is not formed becomes the second n-type region 122.

[0072] As described above, the process of forming an epitaxial layer having n-type conductivity and the process of ion implantation of p-type impurities are alternately performed. This forms a superjunction structure having a first superjunction region 12 and a second superjunction region 25. In a similar manner, a first joint region 13, a second joint region 24, a third joint region 23, and a current spreading region 14 are formed.

[0073] The second superjunction region 25, the second joint region 24, and the third joint region 23 constitute the second region 22. The second region 22 is formed by ion implantation. The impurity concentration of the second region 22 is 6×10 16 cm -3 That is all. Specifically, the second superjunction region 25 is formed by ion implantation. The second joint region 24 may be formed by ion implantation. The third joint region 23 may be formed by ion implantation. By forming the p-type impurity by ion implantation, the point defect density of the second region 22 becomes high.

[0074] Next, an n-type epitaxial layer is formed on the current spreading region 14 and the third joint region 23. P-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the entire surface of the n-type epitaxial layer, thereby forming the second portion 42 of the first region 21.

[0075] The current spreading region 14, the first joint region 13, and the first superjunction region 12 constitute a first impurity region 10. The first impurity region 10 is formed by epitaxial growth, for example, at a temperature condition of 1500° C. or more and 1750° C. or less. The temperature of the epitaxial growth of the first impurity region 10 may be, for example, 1550° C. or more, or 1600° C. or more. The temperature of the epitaxial growth of the first impurity region 10 may be, for example, 1725° C. or less, or 1700° C. or less. By performing the epitaxial growth at a high temperature, the point defect density of the second region 22 becomes high.

[0076] Next, an n-type impurity such as phosphorus (P) is ion-implanted into the entire surface of the epitaxial layer. This forms the third impurity region 30. Next, a mask layer (not shown) having an opening is formed on a region where the first portion 41 of the first region 21 is to be formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the third impurity region 30. This forms the first portion 41 in contact with the third impurity region 30. As a result, the first region 21 having the first portion 41 and the second portion 42 is formed. The first region 21 may be formed by ion implantation. Specifically, the first portion 41 may be formed by ion implantation. Similarly, the second portion 42 may be formed by ion implantation.

[0077] Next, an activation annealing step (S13: FIG. 7) is performed. The activation annealing step may be performed under a temperature condition of 1600° C. or more and 1850° C. or less. The temperature of the activation annealing step may be 1650° C. or more, or 1700° C. or more. The temperature of the activation annealing step may be 1800° C. or less, or 1750° C. or less. By performing activation annealing at a high temperature, the point defect density of the second region 22 increases. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

[0078] As described above, the silicon carbide substrate 100 is prepared. The silicon carbide substrate 100 has a first main surface 1, a second main surface 2, a first impurity region 10, a second impurity region 20, and a third impurity region 30. The second main surface 2 is on the opposite side to the first main surface 1. The first impurity region 10 constitutes at least a part of the second main surface 2 and has a first conductivity type. The second impurity region 20 constitutes at least a part of the first main surface 1, is provided in contact with the first impurity region 10, and has a second conductivity type different from the first conductivity type. The third impurity region 30 is provided in contact with the second impurity region 20 so as to be separated from the first impurity region 10, and has the first conductivity type. The second impurity region 20 includes a first region 21 and a second region 22. The second region 22 is between the first region 21 and the second main surface 2 and is in contact with the first region 21 (see FIG. 14 ).

[0079] Next, a step of forming trench 5 is performed. For example, a mask (not shown) is formed on first main surface 1 including third impurity region 30 and first portion 41. Using the mask, a part of third impurity region 30, a part of second portion 42, and a part of current spreading region 14 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF6) or a mixed gas of SF6 and oxygen (O2) as a reactive gas can be used. By etching, a recess having a side portion substantially perpendicular to first main surface 1 and a bottom portion that is continuous with the side portion and substantially parallel to first main surface 1 is formed in the region where trench 5 is to be formed.

[0080] Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms, with the mask formed on the first main surface 1. The at least one or more types of halogen atoms include at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of, for example, 800°C or more and 900°C or less. The reactive gas may include a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. For example, nitrogen gas, argon gas, or helium gas can be used as the carrier gas.

[0081] By the above thermal etching, a trench 5 is formed in first main surface 1 of silicon carbide substrate 100 (see FIG. 15 ). Trench 5 has side surface 3 and bottom surface 4. Side surface 3 is defined by third impurity region 30, second portion 42, and current spreading region 14. Bottom surface 4 is defined by current spreading region 14. An angle θ between first main surface 1 and side surface 3 is, for example, not less than 115° and not more than 135°. Next, the mask is removed from first main surface 1.

[0082] Next, a step of forming gate insulating film 51 is performed. For example, silicon carbide substrate 100 is thermally oxidized to form gate insulating film 51 in contact with third impurity region 30, second portion 42, current spreading region 14, and first portion 41. Specifically, silicon carbide substrate 100 is heated in an atmosphere containing oxygen at a temperature of, for example, 1300° C. or more and 1400° C. or less. As a result, gate insulating film 51 in contact with first main surface 1, side surface 3, and bottom surface 4 is formed.

[0083] Next, the silicon carbide substrate 100 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 100 is held, for example, for about one hour under conditions of 1100° C. or higher and 1400° C. or lower. This introduces nitrogen atoms into the interface region between the gate insulating film 51 and the second portion 42. As a result, the formation of an interface state in the interface region is suppressed, and channel mobility can be improved.

[0084] After the NO annealing, Ar annealing may be performed using argon (Ar) as the atmospheric gas. The heating temperature of the Ar annealing is, for example, equal to or higher than the heating temperature of the NO annealing. The time of the Ar annealing is, for example, about one hour. This further suppresses the formation of an interface state in the interface region between the gate insulating film 51 and the second portion 42. Note that, instead of Ar gas, other inert gases such as nitrogen gas may be used as the atmospheric gas.

[0085] Next, a step of forming the gate electrode 63 is performed. The gate electrode 63 is formed on the gate insulating film 51. The gate electrode 63 is formed, for example, by a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 63 is formed so as to face each of the third impurity region 30, the second portion 42, and the current spreading region 14.

[0086] Next, a step of forming the isolation insulating film 52 is performed. Specifically, the isolation insulating film 52 is formed so as to cover the gate electrode 63 and to be in contact with the gate insulating film 51. The isolation insulating film 52 is formed, for example, by a CVD method. The isolation insulating film 52 is made of a material containing, for example, silicon dioxide. A part of the isolation insulating film 52 may be formed inside the trench 5.

[0087] Next, a step of forming a first electrode (S20: FIG. 6) is performed. For example, etching is performed to form openings in isolation insulating film 52 and gate insulating film 51, thereby exposing third impurity region 30 and first portion 41 from isolation insulating film 52 and gate insulating film 51 at the openings. Next, electrode layer 60 is formed in contact with third impurity region 30 and first portion 41 on first main surface 1. Electrode layer 60 is formed by, for example, a sputtering method. Electrode layer 60 is made of a material including, for example, Ti, Al, and Si.

[0088] Next, alloying annealing is performed. The electrode layer 60 in contact with the third impurity region 30 and the first portion 41 is held at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least a part of the electrode layer 60 reacts with the silicon contained in the silicon carbide substrate 100 and is silicided. As a result, the electrode layer 60 in ohmic contact with the third impurity region 30 is formed. The electrode layer 60 may be in ohmic contact with the first portion 41. As a result of the above, a first electrode 61 in contact with each of the second impurity region 20 and the third impurity region 30 is formed on the first main surface 1.

[0089] Next, a step of forming a second electrode (S30: FIG. 6) is performed. A second electrode 62 is formed on the second main surface 2 by, for example, a sputtering method. The second electrode 62 is, for example, a drain electrode. The second electrode 62 contacts the first impurity region 10 on the second main surface 2. The second electrode 62 is made of a material containing, for example, NiSi or TiAlSi. In this manner, the MOSFET 200 (FIG. 1) according to the first embodiment is completed.

[0090] In the above description, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, p-type impurities are replaced with n-type impurities and n-type impurities are replaced with p-type impurities. In the above description, the silicon carbide semiconductor device 200 according to the present disclosure is described using a MOSFET as an example, but the silicon carbide semiconductor device 200 according to the present disclosure is not limited to a MOSFET. The silicon carbide semiconductor device 200 according to the present disclosure may be, for example, a PN diode, an IGBT (Insulated Gate Bipolar Transistor), or the like. EXAMPLES

[0091] (Sample preparation) Next, examples will be described. First, a silicon carbide semiconductor device 200 according to Sample 1 and a silicon carbide semiconductor device 200 according to Sample 2 were prepared. The silicon carbide semiconductor device 200 according to Sample 1 was a V-type trench MOSFET having a superjunction structure. Specifically, the silicon carbide semiconductor device 200 according to Sample 1 was the V-type trench MOSFET according to the first embodiment. In the silicon carbide semiconductor device 200 according to Sample 1, the concentration of p-type impurities in the second superjunction region 25 was 1×10 17 cm -3 The concentration of p-type impurities in the channel region (second portion 42) is 2×10 18 cm -3 In the silicon carbide semiconductor device 200 according to Sample 1, the specific on-resistance was 0.63 mΩcm 2 and the breakdown voltage was 1170 V. The silicon carbide semiconductor device 200 according to Sample 2 was a V-type trench MOSFET not having a superjunction structure. In the silicon carbide semiconductor device 200 according to Sample 2, the concentration of p-type impurities in the channel region (second portion 42) was 1×10 16 cm -3 It was decided.

[0092] (Evaluation method) Next, the diode characteristics between the drain electrode (second electrode 62) and the source electrode (first electrode 61) were measured. Specifically, the drain current density was measured while changing the drain voltage under a plurality of temperature conditions. In the silicon carbide semiconductor device 200 according to Sample 1, the temperature conditions were 25°C, 50°C, 75°C, 100°C, 125°C, 150°C, and 175°C. In the silicon carbide semiconductor device 200 according to Sample 2, the temperature conditions were 25°C, 93°C, 122°C, and 162°C.

[0093] (Evaluation Results) FIG. 16 is a diagram showing the relationship between the drain current density and the drain voltage in the silicon carbide semiconductor device 200 according to Sample 1. FIG. 17 is a diagram showing the relationship between the drain current density and the drain voltage in the silicon carbide semiconductor device 200 according to Sample 2. As shown in FIG. 17, in the silicon carbide semiconductor device 200 according to Sample 2, the gradient of the drain current density with respect to the drain voltage increases as the temperature increases. On the other hand, as shown in FIG. 16, in the silicon carbide semiconductor device 200 according to Sample 1, even when the temperature increases, the gradient of the drain current density with respect to the drain voltage does not change much. That is, it was confirmed that the temperature change of the diode characteristics can be suppressed in the silicon carbide semiconductor device 200 according to Sample 1, as compared with the silicon carbide semiconductor device 200 according to Sample 2.

[0094] In addition, the basal plane dislocations present in the silicon carbide substrate 100 may become stacking faults due to the energy of recombination of minority carriers. If there are stacking faults in the silicon carbide semiconductor device 200, the breakdown voltage of the silicon carbide semiconductor device 200 will be significantly reduced. In order to prevent the minority carriers from recombining, it is desirable to reduce the number of minority carriers. The fact that the temperature change of the diode characteristics is small (i.e., the temperature change of the resistance is small) as in the silicon carbide semiconductor device 200 according to sample 1 means that almost no conductivity modulation occurs. Therefore, it is considered that there are very few minority carriers in the silicon carbide semiconductor device 200 according to sample 1. Therefore, in the silicon carbide semiconductor device 200 according to sample 1, the occurrence of stacking faults can be suppressed, and a secondary effect of suppressing a decrease in breakdown voltage can be expected.

[0095] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered as limiting. The scope of the present invention is defined by the claims, not the above description, and is intended to include the meaning equivalent to the claims and all modifications within the scope. [Explanation of symbols]

[0096] 1 first main surface, 2 second main surface, 3 side surface, 4 bottom surface, 5 trench, 6 third main surface, 7 first defect, 8 second defect, 9 point defect, 10 first impurity region, 11 buffer layer, 12 first superjunction region, 13 first joint region, 14 current spreading region, 15 single crystal substrate, 20 second impurity region, 21 first region, 22 second region, 23 third joint region, 24 second joint region, 25 second superjunction region, 30 third impurity region, 41 first portion, 42 second portion, 51 gate insulating film, 52 isolation insulating film, 60 electrode layer, 61 first electrode, 62 second electrode, 63 gate electrode, 64 wiring layer, 70 first epitaxial layer, 71 second epitaxial layer, 100 silicon carbide substrate, 101 first direction, 102 second direction, 103 3rd direction, 121 first n-type region, 122 second n-type region, 200 silicon carbide semiconductor device (MOSFET), 251 first p-type region, 252 second p-type region.

Claims

1. a silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface, provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be spaced from the first impurity region and having the first conductivity type; a first electrode in contact with each of the second impurity region and the third impurity region on the first major surface; a second electrode in contact with the first impurity region at the second major surface; the second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region; The impurity concentration of the first region is 6×10 16 cm -3 That's all. a silicon carbide semiconductor device, wherein when forward characteristics of a body diode between the second electrode and the first electrode are measured under temperature conditions of 25° C. to 175° C., a slope of drain current density with respect to drain voltage becomes smaller as the temperature increases.

2. The impurity concentration of the second region is 6×10 16 cm -3 The silicon carbide semiconductor device according to claim 1 .

3. a silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface, provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be spaced from the first impurity region and having the first conductivity type; a first electrode in contact with each of the second impurity region and the third impurity region on the first major surface; a second electrode in contact with the first impurity region at the second major surface; the second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region; The point defect density of the first region is 6×10 12 cm -3 That's all. a silicon carbide semiconductor device, wherein when forward characteristics of a body diode between the second electrode and the first electrode are measured under temperature conditions of 25° C. to 175° C., a slope of drain current density with respect to drain voltage becomes smaller as the temperature increases.

4. The point defect density of the first region is 1×10 14 cm -3 The silicon carbide semiconductor device according to claim 3 , wherein:

5. The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide semiconductor device is of a planar type.

6. The silicon carbide substrate has a trench provided therein, 5. The silicon carbide semiconductor device according to claim 1, wherein the trench has side surfaces in contact with each of the first impurity region, the second impurity region, and the third impurity region, and a bottom surface continuing to the side surfaces and in contact with the first impurity region.

7. The silicon carbide semiconductor device according to claim 6 , wherein said trench has a U-shape in a cross section perpendicular to said first main surface.

8. The silicon carbide semiconductor device according to claim 6 , wherein said trench has a V-shape in a cross section perpendicular to said first main surface.

9. 9. The silicon carbide semiconductor device according to claim 1, wherein the first main surface is a (000-1) plane or a plane inclined at an angle of 8° or less with respect to the (000-1) plane.

10. The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of said first region is higher than an impurity concentration of said second region.

11. The impurity concentration of the first region is 1×10 19 cm -3 The silicon carbide semiconductor device according to claim 10 , wherein:

12. When the temperature rises from 25° C. to 175° C., the change in the slope of the drain current density with respect to the drain voltage is 20 A / (cm 2 12. The silicon carbide semiconductor device according to claim 1, wherein the resistance is equal to or less than 1000 V.

13. preparing a silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface, provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having the first conductivity type; forming a first electrode in contact with each of the second impurity region and the third impurity region on the first major surface; forming a second electrode in contact with the first impurity region on the second major surface; the second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region; The impurity concentration of the first region is 6×10 16 cm -3 That's all. The first region is formed by ion implantation; a first electrode connected to the first electrode and a second electrode connected to the first electrode, the first electrode connected to the second electrode and a second electrode connected to the first electrode, the first electrode connected to the second electrode and a second electrode connected to the first electrode,

14. The method for manufacturing a silicon carbide semiconductor device according to claim 13 , wherein said second region is formed by ion implantation.

15. 15. The method for manufacturing a silicon carbide semiconductor device according to claim 13, wherein said first impurity region is formed by epitaxial growth under a temperature condition of not less than 1500°C and not more than 1750°C.

16. The step of preparing the silicon carbide substrate includes an activation annealing step, The method for manufacturing a silicon carbide semiconductor device according to claim 13 , wherein the activation annealing step is performed under a temperature condition of 1600° C. or higher and 1850° C. or lower.

17. When the temperature rises from 25° C. to 175° C., the change in the slope of the drain current density with respect to the drain voltage is 20 A / (cm 2 17. The method for manufacturing a silicon carbide semiconductor device according to claim 13, wherein the resistance of the silicon carbide semiconductor device is equal to or less than 1 / 2 V.

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