Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device having a trench gate structure in which unit cells with a FinFET structure are arranged, the silicon carbide semiconductor device being capable of reducing on-resistance.SOLUTION: In a gate trench 6, first and second trenches 31, 32 linearly extending in a first direction X are arranged alternately and repeatedly in the first direction X. All crystal planes of side walls of the gate trench 6 are m-planes. A plurality of gate trenches 6 are arranged adjacent to each other in a second direction Y perpendicular to the first direction X. The width w1 of the first trench 31 in the second direction Y is wider than the width w2 of the second trench 32 in the second direction Y. Between the gate trenches 6 adjacent to each other, a first portion 41 which is sandwiched between the first trenches 31 adjacent to each other in the second direction Y and in which a Fin width w11 is made relatively narrow and second portion 42 which is sandwiched between the second trenches 32 adjacent to each other in the second direction Y and in which a Fin width w12 is made relatively narrow are arranged alternately and repeatedly in the first direction X.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This disclosure relates to silicon carbide semiconductor devices. [Background technology]

[0002] The following Non-Patent Document 1 and the following Patent Documents 2 and 3 describe that in a vertical SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor with an insulated gate having a three-layer structure of metal-oxide film-semiconductor) having a trench gate structure using silicon carbide (SiC) as a semiconductor material, miniaturization and low on-resistance are achieved by arranging unit cells (functional units of an element) having a FinFET structure. The following Patent Documents 1 and 4 describe a trench gate structure in which various characteristics are improved by utilizing the characteristics of the crystal plane inherent to the semiconductor material. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5879732 [Patent Document 2] Patent No. 6631632 [Patent Document 3] JP 2009-212369 A [Patent Document 4] International Publication No. 2020 / 031971 [Non-patent literature]

[0004] [Non-Patent Document 1] F.Udrea et al., "Experimental demonstration, challenges, and prospects of the vertical SiC FinFET", 2022 IEEE 34th ISPSD, May 2022 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above-mentioned Non-Patent Document 1 and the above-mentioned Patent Documents 2 and 3, the narrower the fin width (the width between adjacent gate trenches), the smaller the source contact area becomes, and the higher the source contact resistance becomes. For example, the above-mentioned Non-Patent Document 1 discloses that when the fin width is 200 nm or less, the rate of increase in source contact resistance is higher than when the fin width exceeds 200 nm.

[0006] An object of the present disclosure is to provide a silicon carbide semiconductor device having a trench gate structure in which unit cells of a FinFET structure are arranged, the silicon carbide semiconductor device being capable of reducing the on-resistance. [Means for solving the problem]

[0007] A silicon carbide semiconductor device according to one aspect of the disclosure is as follows. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A fourth semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A gate trench penetrates the third semiconductor region and the second semiconductor region to reach the first semiconductor region.

[0008] A gate electrode is provided inside the gate trench via a gate insulating film. A first electrode is electrically connected to the fourth semiconductor region, the third semiconductor region, and the second semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate. The gate trench is formed by alternately arranging first trenches linearly extending in a first direction parallel to the first main surface of the semiconductor substrate and second trenches linearly extending in the first direction in the first direction. The gate trenches are arranged in a stripe pattern adjacent to each other in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction.

[0009] This is a double gate structure in which one channel is formed between the gate trenches from both side surfaces in the second direction in the entire area of ​​the second semiconductor region between the gate trenches adjacent to each other. The width of the first trench in the second direction is wider than the width of the second trench in the second direction. Between the gate trenches adjacent to each other, first portions are sandwiched between the first trenches adjacent to each other in the second direction and have a relatively narrower width between the adjacent gate trenches, and second portions are sandwiched between the second trenches adjacent to each other in the second direction and have a relatively wider width between the adjacent gate trenches, and are alternately and repeatedly arranged in the first direction. Effect of the Invention

[0010] ADVANTAGEOUS EFFECTS OF THE DISCLOSURE The silicon carbide semiconductor device according to the present disclosure is a silicon carbide semiconductor device having a trench gate structure in which unit cells of a FinFET structure are arranged, and has an effect of reducing the on-resistance. [Brief description of the drawings]

[0011] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 10 is a plan view showing another example of a layout of the silicon carbide semiconductor device according to the embodiment, as viewed from the front surface side of the semiconductor substrate. FIG. [Diagram 3] FIG. 2 is an explanatory diagram showing an example of a crystal plane of silicon carbide (hexagonal crystal). [Figure 4] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 5] 2 is a cross-sectional view showing a cross-sectional structure taken along line BB' in FIG. [Figure 6] 1 is a plan view showing a layout of a silicon carbide semiconductor device of a reference example as viewed from the front surface side of a semiconductor substrate. FIG. [Figure 7] 7 is a cross-sectional view showing a cross-sectional structure taken along line AA-AA' in FIG. 6. [Figure 8] 7 is a cross-sectional view showing a cross-sectional structure taken along line BB-BB' in FIG. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] <Overview of the embodiment of the present disclosure> (1) A silicon carbide semiconductor device according to one aspect of the disclosure is as follows. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A fourth semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. A gate trench penetrates the third semiconductor region and the second semiconductor region to reach the first semiconductor region.

[0013] A gate electrode is provided inside the gate trench via a gate insulating film. A first electrode is electrically connected to the fourth semiconductor region, the third semiconductor region, and the second semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate. The gate trench is formed by alternately arranging first trenches linearly extending in a first direction parallel to the first main surface of the semiconductor substrate and second trenches linearly extending in the first direction in the first direction. The gate trenches are arranged in a stripe pattern adjacent to each other in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction.

[0014] This is a double gate structure in which one channel is formed between the gate trenches from both side surfaces in the second direction in the entire area of ​​the second semiconductor region between the gate trenches adjacent to each other. The width of the first trench in the second direction is wider than the width of the second trench in the second direction. Between the gate trenches adjacent to each other, first portions are sandwiched between the first trenches adjacent to each other in the second direction and have a relatively narrower width between the adjacent gate trenches, and second portions are sandwiched between the second trenches adjacent to each other in the second direction and have a relatively wider width between the adjacent gate trenches, and are alternately and repeatedly arranged in the first direction.

[0015] According to the above disclosure, the second portion between the adjacent gate trenches increases the contact area between the third semiconductor region and the first electrode, reducing the contact resistance between the third semiconductor region and the first electrode, thereby lowering the channel resistance. Also, the first portion between the adjacent gate trenches can enhance the effect of the FinFET structure.

[0016] (2) In the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (1), a crystal plane of a sidewall of the first trench is an m-plane. A crystal plane of a sidewall of the second trench is an m-plane. A crystal plane of a sidewall of the gate trench connecting a sidewall formed of the first trench and a sidewall formed of the second trench may be an m-plane or an a-plane.

[0017] According to the above disclosure, the carrier mobility is improved and the channel resistance is reduced.

[0018] (3) In the silicon carbide semiconductor device according to the present disclosure, in the above-mentioned (1) or (2), the first portion may have a width in the second direction narrower than a width of the first trench. The second portion may have a width in the second direction wider than a width of the second trench.

[0019] According to the above disclosure, the effect of the FinFET structure is obtained, and the effect of the second portion between the adjacent gate trenches is also obtained.

[0020] (4) In the silicon carbide semiconductor device according to any one of (1) to (3) described above, the first portion may have a width in the second direction of 200 nm or less. The second portion may have a width in the second direction of more than 200 nm.

[0021] According to the above disclosure, the effect of the FinFET structure is obtained, and the effect of the second portion between the adjacent gate trenches is also obtained.

[0022] (5) In the silicon carbide semiconductor device according to this disclosure, in any one of (1) to (4) above, the second semiconductor region is provided across the entire area in the first direction between adjacent gate trenches. The third semiconductor region is provided across the entire area in the first direction between adjacent gate trenches. The fourth semiconductor region may be provided only in the second portion and scattered in the first direction between adjacent gate trenches.

[0023] According to the above disclosure, the fin width (width in the second direction) can be made relatively narrow in the first portion where only the third semiconductor region is arranged.

[0024] (6) In the silicon carbide semiconductor device according to the present disclosure, in any one of (1) to (5) above, an interlayer insulating film is provided on a first main surface of the semiconductor substrate and covers the gate electrode. A contact hole penetrates the interlayer insulating film in a depth direction to expose the fourth semiconductor region and the third semiconductor region. The contact hole has a tapered cross-sectional shape narrowing toward the first main surface side of the semiconductor substrate. The first electrode may be in contact with the fourth semiconductor region and the third semiconductor region via the contact hole.

[0025] According to the above disclosure, the third semiconductor region and the fourth semiconductor region are easily brought into contact with the first electrode within the contact hole.

[0026] (7) Furthermore, the silicon carbide semiconductor device according to this disclosure, in any one of (1) to (6) above, may further include a fifth semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region, the fifth semiconductor region being located between the second semiconductor region and the first semiconductor region and deeper on the second electrode side than a bottom surface of the gate trench.

[0027] According to the above disclosure, the on-resistance can be reduced.

[0028] <Foundational knowledge of this disclosure> First, the structure of a silicon carbide semiconductor device of a reference example will be described. Fig. 6 is a plan view showing a layout of the silicon carbide semiconductor device of the reference example as viewed from the front surface side of the semiconductor substrate. + The source region 104 (dotted hatched area) and ++6 shows a layout of the contact region 105 (hatched portion with diagonal lines). Figures 7 and 8 are cross-sectional views showing cross-sectional structures taken along the cutting lines AA-AA' and BB-BB' in Figure 6, respectively. A silicon carbide semiconductor device 110 of a reference example shown in Figures 6 to 8 is a vertical SiC-MOSFET with a trench gate structure having a MOS gate 109 constituting a unit cell (functional unit of an element) 110a of a FinFET structure on the front surface (main surface on the p-type epitaxial layer 123 side) of a semiconductor substrate (semiconductor chip) 120 made of SiC.

[0029] The semiconductor substrate 120 is made of SiC. + On the front surface of the starting substrate 121, - The epitaxial layers 122, 123 which become the n-type drift region 102 and the p-type base region 103 are epitaxially grown in this order. + The starting substrate 121 is n + The trench gate structure includes a p-type base region 103, an n-type drain region 101, and a + type source region 104, p ++ The semiconductor substrate 120 includes a first contact region 105 and a MOS gate 109. The MOS gate 109 includes a gate trench 106, a gate insulating film 107, and a gate electrode 108. The gate trenches 106 are arranged in stripes extending linearly in a first direction X parallel to the front surface of the semiconductor substrate 120.

[0030] The width (width in the short direction) w101 of the gate trench 106 is uniform over the entire area in the first direction X (longitudinal direction). A portion between the centers of adjacent gate trenches 106 constitutes one unit cell 110a. The width (fin width) w111 between adjacent gate trenches 106 is uniform over the entire area in the first direction X. The fin width w111 is set narrow so that one channel (n-type inversion layer) is formed over almost the entire p-type base region 103 between adjacent gate trenches 106. This one channel formed between adjacent gate trenches 106 contacts different MOS gates 109 on both side surfaces in a second direction Y that is parallel to the front surface of the semiconductor substrate 120 and perpendicular to the first direction X.

[0031] The gate trench 106 penetrates the p-type epitaxial layer 123 from the front surface of the semiconductor substrate 120 in the depth direction Z. - Type epitaxial layer 122(n - The p-type drift region 102 is terminated in the inside of the gate trench 106. A gate electrode 108 is provided inside the gate trench 106 via a gate insulating film 107. The p-type epitaxial layer 123 includes an n-type epitaxial layer 123 formed by ion implantation. + type source region 104 and p ++ The portion excluding the p-type contact region 105 is the p-type base region 103. + type source region 104 and p ++ The contact regions 105 are selectively provided between the front surface of the semiconductor substrate 120 and the p-type base region 103 in contact with the p-type base region 103 .

[0032] n + type source region 104 and p ++ The contact region 105 is in ohmic contact with the contact electrode 112 on the front surface of the semiconductor substrate 120. + type source region 104 and p ++ The n-type contact regions 105 are alternately and repeatedly provided adjacent to each other in the first direction X between the adjacent gate trenches 106. + type source region 104 and p ++ The width of the contact region 105 in the second direction Y is equal to the fin width w111. - The p-type drift region 102, the p-type base region 103 and the n + type source region 104, p ++ The contact region 105 contacts the gate insulating film 107 on the side walls of the gate trenches 106 located on both sides in the second direction Y.

[0033] The interlayer insulating film 111 is provided on the entire front surface of the semiconductor substrate 120, and covers the gate electrode 108. A contact hole 111a is provided penetrating the interlayer insulating film 111 in the depth direction Z. The cross-sectional shape of the contact hole 111a is substantially rectangular with a sidewall (the side surface of the interlayer insulating film 111) that is substantially perpendicular to the front surface of the semiconductor substrate 120. The contact hole 111a has n + type source region 104 and p ++ The n-type contact region 105 is exposed. A contact electrode 112 is provided on the front surface of the semiconductor substrate 120 inside the contact hole 111a. The contact electrode 112 is + type source region 104 and p ++ The semiconductor device is in ohmic contact with the contact region 105 .

[0034] The front surface electrode 113 is provided on the interlayer insulating film 111 and the contact electrode 112 so as to be embedded in the contact hole 111a. + type source region 104 and p ++ The front surface electrode 113 and the contact electrode 112 function as a source electrode. + A back electrode 114 is provided on the back surface of the starting substrate 121. + Type drain region 101(n + The back electrode 114 is in contact with and electrically connected to the starting mold substrate 121. The back electrode 114 functions as a drain electrode.

[0035] In the silicon carbide semiconductor device 110 of the reference example described above, the non-patent document 1, and the patent documents 2 and 3, the narrower the fin width w111, the smaller the n + The contact area (source contact area) between the n-type source region 104 and the contact electrode 112 becomes smaller, +In this case, the source contact resistance between the type source region 104 and the source electrode (contact electrode 112 and front surface electrode 113) increases, and the on-resistance becomes high. Therefore, a problem to be solved in this embodiment is how to reduce the on-resistance in a silicon carbide semiconductor device having a trench gate structure in which unit cells of a FinFET structure are arranged.

[0036] Preferred embodiments of the silicon carbide semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - appended to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to similar configurations, and duplicated explanations are omitted. In this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index.

[0037] (Details of the embodiment) A silicon carbide semiconductor device according to an embodiment that solves the above-mentioned problems will be described below. Fig. 1 is a plan view showing a layout of the silicon carbide semiconductor device according to the embodiment, as viewed from the front surface side of a semiconductor substrate. Fig. 2 is a plan view showing another example of a layout of the silicon carbide semiconductor device according to the embodiment, as viewed from the front surface side of a semiconductor substrate. Figs. 1 and 2 show n + Type source region 4 (dotted hatched area) and p ++ FIG. 2 shows a layout of the contact region 5 (hatched portion). FIG. 3 is an explanatory diagram showing an example of a crystal plane of silicon carbide (hexagonal). FIGS. 4 and 5 are cross-sectional views showing the cross-sectional structures taken along the lines A-A' and B-B' in FIG. 1, respectively. The cross-sectional structures taken along the lines A-A' and B-B' in FIG. 2 are similar to those in FIGS. 4 and 5.

[0038] The silicon carbide semiconductor device 10 according to the embodiment shown in Figures 1, 2, 4 and 5 is a vertical SiC-MOSFET with a trench gate structure having a MOS gate 9 constituting a unit cell (functional unit of an element) 10a of a FinFET structure on the front surface side of a semiconductor substrate (semiconductor chip) 20 made of silicon carbide (SiC). + On the front surface of the starting substrate 21, - The epitaxial layers 22, 23 that become the p-type drift region (first semiconductor region) 2 and the p-type base region (second semiconductor region) 3 are epitaxially grown in this order. The semiconductor substrate 20 has a first main surface on the p-type epitaxial layer 23 side as the front surface, and + The second main surface (n + The back side of the starting substrate 21 is referred to as the back side. + The starting substrate 21 is n + The gate electrode is a gate-type drain region 1.

[0039] The trench gate structure includes a p-type base region 3, a n + Type source region (third semiconductor region) 4, p ++ The p-type base region 3 is made up of a p-type contact region (fourth semiconductor region) 5 and a MOS gate 9 (see FIGS. 4 and 5). The MOS gate 9 is made up of a gate trench 6, a gate insulating film 7 and a gate electrode 8. The FinFET structure is a so-called double gate structure in which the widths (Fin widths) w11 and w12 between adjacent gate trenches 6 are narrowed by a predetermined width and one channel (n-type inversion layer) formed in almost the entire area of ​​the p-type base region 3 between the gate trenches 6 is sandwiched by the MOS gates 9 from both sides. One unit cell 10a is formed between the centers of adjacent gate trenches 6. The gate trenches 6 are arranged in a stripe shape extending in a first direction X parallel to the front surface of the semiconductor substrate 20. A plurality of unit cells 10a having the same structure are arranged adjacent to each other in a second direction Y parallel to the front surface of the semiconductor substrate 20 and perpendicular to the first direction X.

[0040] The semiconductor substrate 20 has a four-layer periodic hexagonal structure (4H-SiC). The front surface of the semiconductor substrate 20 is a (0001) plane, a so-called Si plane, having an off angle of a predetermined angle (for example, about 4 degrees) in the <11-20> direction. The back surface of the semiconductor substrate 20 is a (000-1) plane, a so-called C plane. The longitudinal direction (first direction X) of the gate trench 6 is the <11-20> direction, and the lateral direction (second direction Y) of the gate trench 6 is the <1-100> direction. The sidewall of the gate trench 6 is approximately perpendicular to the front surface of the semiconductor substrate 20. All of the crystal planes of the sidewall of the gate trench 6 are m-planes (see FIGS. 1 and 3). Some of the crystal planes of the sidewall of the gate trench 6 may be a-planes instead of m-planes (see FIGS. 2 and 3). By making all of the crystal faces of the sidewall of the gate trench 6 m-planes (or even if some of them are a-planes), carrier mobility is improved and channel resistance is reduced compared to when the crystal faces of the sidewall of the gate trench 6 are other crystal faces.

[0041] The m-plane is a general term for the {1-100} planes perpendicular to the basal plane (Si plane) of silicon carbide, and includes six planes: (10-10), (-1010), (1-100), (-1100), (01-10), and (0-110). The a-plane is a general term for the {11-20} planes perpendicular to the basal plane of silicon carbide, and includes six planes: (11-20), (-2110), (1-210), (-1-120), (2-1-10), and (-12-10). Figure 3(a) shows the basal plane of a hexagonal crystal (the bottom surface of a regular hexagonal prism) viewed in the [000-1] direction. In Fig. 3(a), the intersection line between the basal plane of silicon carbide and the m-plane and the intersection line between the basal plane of silicon carbide and the a-plane are shown by a thick solid line and a thick dashed line, respectively. Fig. 3(b) is a perspective view showing an example of an m-plane corresponding to the side of a hexagonal crystal (side of a regular hexagonal prism). Fig. 3(c) is a perspective view showing an example of an a-plane corresponding to each side of a regular triangular prism inscribed in a hexagonal crystal (regular hexagonal prism) by connecting three vertices of the basal plane of the hexagonal crystal.

[0042] Specifically, the gate trench 6 has first and second trenches 31, 32 that extend linearly in the first direction X (longitudinal direction of the gate trench 6) with different widths (widths in the second direction Y (short-side direction of the gate trench 6)) w1, w2. The widths w1, w2 in the second direction Y of the first and second trenches 31, 32 are uniform over the entire area in the first direction X. The width w1 in the second direction Y of the first trench 31 is wider than the width w2 in the second direction Y of the second trench 32 (w1>w2). The side walls 31a, 32a of the first and second trenches 31, 32 are parallel to the first direction X when viewed from the front surface side of the semiconductor substrate 20, and their crystal planes are m-planes. The gate trench 6 is formed by repeatedly arranging the first and second trenches 31, 32 alternately in the first direction X so that their ends face each other.

[0043] More specifically, when all the crystal planes of the sidewalls of the gate trench 6 are m-planes (see FIG. 1), the gate trench 6 further includes a third trench 33 that connects the ends of the first and second trenches 31 and 32. The first trench 31, the third trench 33, and the second trench 32 are repeatedly arranged in this order and connected to each other at their ends to form the gate trench 6. The sidewall 33a of the third trench 33 forms an angle of approximately 60 degrees (see FIG. 1) with respect to the first direction X when viewed from the front surface side of the semiconductor substrate 20, and the crystal plane is an m-plane. The third trench 33 has a planar shape that is approximately an isosceles trapezoid, and the width in the second direction Y becomes narrower from the first trench 31 side toward the second trench 32 side.

[0044] When a crystal plane of a part of the sidewall of the gate trench 6 is the a-plane (see FIG. 2), the gate trench 6 is formed by alternately and repeatedly arranging the first and second trenches 31 and 32 adjacent to each other in the first direction X, and has a sidewall 33b connecting the sidewalls 31a and 32a of the first and second trenches 31 and 32 to each other. The sidewall 33b of the gate trench 6 forms an angle of approximately 90 degrees with respect to the first direction X when viewed from the front surface side of the semiconductor substrate 20 (approximately perpendicular to the first direction X), and its crystal plane is the a-plane. That is, the m-plane and the a-plane are alternately and repeatedly exposed in the first direction X on the sidewall of the gate trench 6. The sidewall (31a, 32a, 33a, 33b) of the gate trench 6 may have a crystal plane that is approximately equivalent to the m-plane or the a-plane within a range including an allowable error due to process variations.

[0045] The crystal plane substantially equivalent to the m-plane means, for example, that the angle between the sidewall of the gate trench 6 and the m-plane is about ±3° or less, and that the angle between the sidewall of the gate trench 6 and the bottom surface is substantially perpendicular (about 90° or more and 3° or less). The crystal plane substantially equivalent to the a-plane means, for example, that the angle between the sidewall 33b of the gate trench 6 and the a-plane is about ±3° or less, and that the angle between the sidewall of the gate trench 6 and the bottom surface is substantially perpendicular. When the angle between the sidewall of the gate trench 6 and the bottom surface exceeds 90°, the gate trench 6 has a tapered (substantially trapezoidal) cross-sectional shape in which the width in the second direction Y (widths w1 and w2 in the second direction Y of the first and second trenches 31 and 32) narrows toward the bottom surface.

[0046] The adjacent gate trenches 6 are arranged in line symmetry with a straight line parallel to the first direction X passing through the centers of the adjacent gate trenches 6 as the axis of symmetry. As a result, each unit cell 10a is in a state where a first portion 41 with a relatively narrow width (Fin width) w11 between adjacent gate trenches 6 and a second portion 42 with a relatively wide width (Fin width) w12 between adjacent gate trenches 6 are alternately repeated in the first direction X (w11 < w12). Among the adjacent gate trenches 6, the first portion 41 is a portion sandwiched between the first trenches 31 adjacent to each other in the second direction Y, and the second portion 42 is a portion sandwiched between the second trenches 32 adjacent to each other in the second direction Y.

[0047] The Fin width (width in the second direction Y) w11 of the first portion 41 between adjacent gate trenches 6 is narrower than the width w1 in the second direction Y of the first trench 31 (w11 < w1), for example, about 200 nm or less. The Fin width w12 of the second portion 42 between adjacent gate trenches 6 is wider than the width w2 in the second direction Y of the second trench 32 (w12 > w2), for example, more than 200 nm and for example, about 5000 nm or less. By setting the Fin widths w11 and w12 in this way, as will be described later, the effect of the FinFET structure (reduction of on-resistance) can be obtained, and the source contact area becomes large in the second portion 42 between adjacent gate trenches 6, and the source contact resistance is reduced.

[0048] The gate trench 6 penetrates the p-type epitaxial layer 23 from the front surface of the semiconductor substrate 20 in the depth direction Z to the n - type epitaxial layer 22 (the n-type current diffusion region 15 described later, or when the n-type current diffusion region 15 is not provided, n -The gate trench 6 terminates inside the gate insulating film 7). The depth of the gate trench 6 is approximately uniform over the entire area in the first direction X. By making all the gate trenches 6 approximately the same depth, local electric field concentration on the gate insulating film 7 can be suppressed. "Approximately uniform" and "approximately the same" depth means that the depth is the same within a range including tolerance due to process variations. The tolerance of the depth of the gate trench 6 is, for example, about ±0.2 μm with respect to the design value of the depth of the gate trench 6.

[0049] The etching rate of the gate trench 6 varies depending on the width of the gate trench 6 in the second direction Y. As described later, since the width of the gate trench 6 (first to third trenches 31, 32, 33) in the second direction Y varies partially, the gate trench 6 may be partially formed in a plurality of times depending on the width in the second direction Y. Inside the gate trench 6, a gate insulating film 7 is provided along the inner wall (side wall and bottom surface) of the gate trench 6, and a gate electrode 8 is provided on the gate insulating film 7 so as to fill the gate trench 6. Of the p-type epitaxial layer 23, an n-type impurity ion (I) formed in the p-type epitaxial layer 23 by ion implantation is formed on the p-type epitaxial layer 23. + Type source region 4 and p ++ The portion excluding the contact region 5 is the p-type base region 3 .

[0050] The p-type base region 3 and the n-type current diffusion region 15 contact the gate insulating film 7 at sidewalls 31a, 32a, 33a of the first to third trenches 31, 32, 33 of both gate trenches 6 located on both sides in the second direction Y (when a crystal plane of a portion of the sidewall of the gate trench 6 is an a-plane, the sidewall 33b of the gate trench 6 instead of the sidewall 33a of the third trench 33). Hereinafter, a case where the crystal planes of the sidewall of the gate trench 6 are all m-planes will be described as an example. When a crystal plane of a portion of the sidewall of the gate trench 6 is an a-plane, the sidewalls 31a, 32a, 33a of the first to third trenches 31, 32, 33 of the gate trench 6 may be read as the sidewalls 31a, 32a of the first and second trenches 31, 32 of the gate trench 6 and the sidewall 33b of the gate trench 6.

[0051] n +Type source region 4 and p ++ The n-type contact regions 5 are selectively provided between the front surface of the semiconductor substrate 20 and the p-type base region 3, in contact with the p-type base region 3. + Type source region 4 and p ++ The contact region 5 is in ohmic contact with the contact electrode 12 on the front surface of the semiconductor substrate 20. + The n-type source region 4 is provided between adjacent gate trenches 6 over substantially the entire area in the first direction X. + The source region 4 is p ++ In contact with the p-type contact region 5 ++ The contact area 5 is surrounded by the n + The source region 4 contacts the gate insulating film 7 at side walls 31a, 32a, 33a of the first to third trenches 31, 32, 33 of both gate trenches 6 located on both sides in the second direction Y, respectively.

[0052] p ++ The n-type contact regions 5 are provided only in the second portions 42 between the adjacent gate trenches 6, and are scattered at predetermined intervals in the first direction X. That is, in the portion (second portion 42) between the front surface of the semiconductor substrate 20 and the p-type base region 3 and between the adjacent second trenches 32 in the second direction Y, + Type source region 4 and p ++ A contact region 5 is provided, and a portion (first portion 41) sandwiched between the first trenches 31 adjacent to each other in the second direction Y and a portion sandwiched between the third trenches 33 adjacent to each other in the second direction Y are provided with n + Only the p-type source region 4 is provided. ++ The type contact regions 5 face each other in the second direction Y with the MOS gate 9 therebetween.

[0053] p ++ The width of the mold contact region 5 in the second direction Y can be set appropriately. ++ Directly below the contact region 5 (n + It is sufficient to form a channel in the p-type drain region 1 side. For example, ++The contact region 5 may be in contact with the gate insulating film 7 at the sidewall 32a of the second trench 32, or may be separated from the sidewall 32a of the second trench 32. ++ The contact region 5 may extend to a portion between the third trenches 33 adjacent to each other in the second direction Y. ++ The contact region 5 is formed in a depth direction Z from the front surface of the semiconductor substrate 20 to an n-type + It may terminate at the same depth as the n-type source region 4 (not shown) or + n type source region 4 + The dipping reaches a deep position on the drain region 1 side (the back surface side of the semiconductor substrate 20).

[0054] In this way, between the adjacent gate trenches 6, p ++ By making the fin width w12 relatively wider in the second portion 42 in which the contact region 5 is arranged, the n + The contact area (source contact area) between the n-type source region 4 and the contact electrode 12 can be increased, and the contact resistance (source contact resistance) with the source electrode (contact electrode 12 and front surface electrode 13: first electrode) can be reduced. + By relatively narrowing the Fin width w11 in the first portion 41 in which only the type source region 4 is arranged, the effect of the FinFET structure can be enhanced.

[0055] p-type base region 3 and n - Between the n-type drift region 2 and the bottom surface of the gate trench 6, + A p-type current diffusion region (fifth semiconductor region) 15 is disposed deep on the side of the n-type drain region 1, and a p-type current diffusion region (fifth semiconductor region) 16 is disposed deep on the side of the n-type drain region 1. + p-type region (hereafter, p-type region for electric field relaxation) + The n-type current diffusion region 15 and the p-type region for electric field relaxation may be selectively provided. + The type region is n -The n-type epitaxial layer 22 is a diffusion region formed by ion implantation. + When a mold region is provided, n - The portion of the epitaxial layer 22 other than these diffusion regions is n - This becomes type drift region 2.

[0056] The n-type current diffusion region 15 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. By providing the n-type current diffusion region 15, n-type current is diffused from a channel formed in the p-type base region 3 between the adjacent gate trenches 6 when the SiC-MOSFET is turned on. - Since the electron current is easily diffused to the n-type drift region 2, the on-resistance can be reduced. + The bottom surface (n + n - The n-type current diffusion region 15 contacts the gate insulating film 7 and reaches the side wall of the gate trench 6 in the second direction Y.

[0057] The n-type current diffusion region 15 faces the bottom surface of the gate trench 6 and surrounds the bottom surface of the gate trench 6. The n-type current diffusion region 15 may be in contact with the gate insulating film 7 at the bottom surface of the gate trench 6. + When the n-type region is provided, the n-type current diffusion region 15 has a p + The p-type region is in contact with the + When no type region is provided, the n-type current diffusion region 15 is connected to the p-type base region 3 and - The n-type current diffusion region 15 is provided in substantially the entire region between the n-type drift region 2. When the n-type current diffusion region 15 is not provided, the n-type current diffusion region 15 is replaced by - The p-type drift region 2 reaches the p-type base region 3 and also reaches the sidewall of the gate trench 6 in the second direction Y and contacts the gate insulating film 7.

[0058] p for electric field relaxation +The p-type region has a function of depleting when the SiC-MOSFET is turned off (or depleting the n-type current diffusion region 15, or both) to relieve the electric field applied to the gate insulating film 7. + The p-type region is provided at a position facing the bottom surface of the gate trench 6, separated from the p-type base region 3, and extends in the first direction X with a length substantially equal to the length of the gate trench 6 in the longitudinal direction (first direction X). + The p-type region is in contact with the gate insulating film 7 at the bottom of the gate trench 6. + The p-type region extends over the entire first portion 41 in which the fin width w11 between the adjacent gate trenches 6 is relatively narrow, is connected to the p-type base region 3, and is fixed to the potential of the source electrode. + The mold region is not provided in the second portion 42 in which the fin width w12 between the adjacent gate trenches 6 is relatively wide.

[0059] p for electric field relaxation + The width in the second direction Y of the portion of the mold region directly below the bottom surface of the gate trench 6 may be made partially different by making it approximately the same as the width in the second direction Y of the portion (first to third trenches 31, 32, 33) facing the gate trench 6 in the depth direction Z. In this case, before the gate electrode 8 is formed inside the gate trench 6, p ions for electric field relaxation are implanted into the bottom surface of the gate trench 6 in a self-aligned manner. + It is possible to form a p-type region for electric field relaxation. + The width in the second direction Y of the portion of the mold region directly below the bottom surface of the gate trench 6 may be approximately uniform over the entire area in the first direction X. + The type region is n + The n-type drain region 1 reaches a depth position equal to or greater than the depth of the n-type current diffusion region 15. - The p-type drift region 2 may be in contact with the p-type drift region 2. + The n-type region is n-type current spreading region 15. + Alternatively, the n-type source region 4 may terminate at a shallow position on the n-type source region 4 side and be surrounded by the n-type current diffusion region 15 .

[0060] The interlayer insulating film 11 is provided on the entire front surface of the semiconductor substrate 20 and covers the gate electrode 8. A contact hole 11a is provided penetrating the interlayer insulating film 11 in the depth direction Z. The contact hole 11a has n + Type source region 4 and p ++ The n-type contact region 5 is exposed. A contact electrode 12 is embedded inside the contact hole 11a on the front surface of the semiconductor substrate 20. The contact hole 11a has a tapered (approximately trapezoidal) cross-sectional shape that narrows toward the front surface of the semiconductor substrate 20. This allows the n-type contact region 5 to be exposed inside the contact hole 11a even if the fin widths w11 and w12 are narrow. + Type source region 4 and p ++ This makes it easier for the mold contact region 5 and the contact electrode 12 to come into contact with each other.

[0061] The contact electrode 12 is + Type source region 4 and p ++ The front electrode 13 is in ohmic contact with the n-type contact region 5. The front electrode 13 is provided on the interlayer insulating film 11 and the contact electrode 12 so as to be embedded in the contact hole 11a. The front electrode 13 is + Type source region 4 and p ++ The front surface electrode 13 and the contact electrode 12 function as a source electrode. A rear surface electrode 14 is provided on the entire rear surface of the semiconductor substrate 20. The rear surface electrode 14 is an n-type contact region 5. + Type drain region 1(n + The back electrode 14 is in contact with and electrically connected to the starting mold substrate 21. The back electrode 14 functions as a drain electrode (second electrode).

[0062] The operation of the silicon carbide semiconductor device 10 (SiC-MOSFET) according to the embodiment will be described. When a positive voltage is applied to the drain electrode (rear electrode 14) with respect to the source electrode (front electrode 13 and contact electrode 12) (drain-source is forward biased), p ++ the p-type contact region 5, the p-type base region 3 and the p +and an n-type current spreading region 15, - Type drift region 2 and n + A reverse bias is applied to the pn junction between the gate electrode 8 and the drain region 1. In this state, if the voltage applied to the gate electrode 8 is less than the gate threshold voltage, the SiC-MOSFET maintains the off state.

[0063] On the other hand, when a gate voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 8 with the drain-source being forward biased, one channel (n-type inversion layer) is formed in contact with different MOS gates 9 (gate insulating films 7 on the sidewalls of the gate trenches 6) on both sides in the second direction Y over almost the entire area in the first direction X of the p-type base region 3 between adjacent gate trenches 6. + Type drain region 1 to n - The n-type drift region 2, the n-type current diffusion region 15 and the channel are + A drift current (main current) flows toward the type source region 4, turning on the SiC MOSFET.

[0064] When the SiC-MOSFET is on, the adverse effect of the electric field generated by the flow of the main current in the second direction Y is reduced by the FinFET structure, so that there is less scattering of carriers and the mobility of carriers is improved. This reduces the channel resistance and therefore the on-resistance. In addition, even if the width (Fin widths w11, w12) between the adjacent gate trenches 6 is narrow, the p ++ By making the Fin width w12 relatively wider in the second portion 42 in which the type contact region 5 is arranged, the source contact area is increased, and therefore the source contact resistance is reduced, and the on-resistance is reduced.

[0065] As described above, according to the embodiment, in a silicon carbide semiconductor device with a double gate structure in which one channel is formed over almost the entire p-type base region between adjacent gate trenches in the first direction, a first trench extending linearly in the first direction and a second trench extending linearly in the first direction with a width in the second direction narrower than that of the first trench are alternately and adjacently arranged in the first direction such that their ends face each other to form a gate trench with a locally wider width in the second direction. By locally widening the width of the gate trench in the second direction, a first portion with a relatively narrower fin width and a second portion with a relatively wider fin width are alternately and repeatedly arranged in the first direction between adjacent gate trenches.

[0066] The second part, in which the fin width between adjacent gate trenches is relatively wide, reduces the source contact area (n + The contact area between the n-type source region and the source electrode increases, and the source contact resistance ( + Since the contact resistance between the p-type source region and the source electrode is reduced, the channel resistance is lowered and the on-resistance is reduced. The effect of the FinFET structure can be enhanced by the first portion in which the fin width between the adjacent gate trenches is relatively narrow. Also, according to the embodiment, the p-type source region is provided only in the second portion between the adjacent gate trenches. ++ A contact region is disposed on the first portion. + In this case, only the p-type source region is disposed in the p-type base region between the adjacent gate trenches, and thus the drift current can be diffused over the entire area in the first direction to the p-type base region between the adjacent gate trenches.

[0067] The present disclosure is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present disclosure. For example, + Instead of forming the n-type source region by ion implantation, + The type source region is n + In this case, the n-type epitaxial layer may be formed. + n type source region +The surface of the epitaxial layer is the front surface of the semiconductor substrate. In addition, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0068] INDUSTRIAL APPLICABILITY As described above, silicon carbide semiconductor devices according to the present disclosure are useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of symbols]

[0069] 1n + Type drain region 2n - Type Drift Region 3 p-type base region 4n + Type Source Area 5 p ++ Mold Contact Area 6 Gate trench 7 Gate insulating film 8. Gate electrode 9. MOS Gate 10 Silicon carbide semiconductor device 10a Unit cell 11 Interlayer insulating film 11a Contact hole in interlayer insulating film 12 Contact electrode 13 Front electrode 14 Back electrode 15 n-type current diffusion region 20 Semiconductor substrate 21 n + Starting substrate 22n - Type epitaxial layer 23 p-type epitaxial layer 31, 32, 33 Trench 31a, 32a, 33a, 33b Trench sidewalls 41, 42 Area between adjacent gate trenches w1, w2 Width of trench in second direction w11,w12 Fin width X: a first direction parallel to the front surface of the semiconductor body Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction

Claims

1. a first semiconductor region of a first conductivity type provided within a semiconductor substrate made of silicon carbide; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a fourth semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region and having a higher impurity concentration than the second semiconductor region; a gate trench passing through the third semiconductor region and the second semiconductor region to reach the first semiconductor region; a gate electrode provided inside the gate trench via a gate insulating film; a first electrode electrically connected to the fourth semiconductor region, the third semiconductor region, and the second semiconductor region; A second electrode provided on a second main surface of the semiconductor substrate; Equipped with the gate trench is formed by alternately arranging first trenches linearly extending in a first direction parallel to a first main surface of the semiconductor substrate and second trenches linearly extending in the first direction, the first trenches being arranged in the first direction; the gate trenches are arranged in a stripe pattern adjacent to each other in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction; a double-gate structure in which one channel is formed in the entire area of ​​the second semiconductor region between the gate trenches adjacent to each other, the channel being sandwiched between the gate trenches from both side surfaces in the second direction, The width of the first trench in the second direction is wider than the width of the second trench in the second direction, Between the adjacent gate trenches, a first portion sandwiched between the first trenches adjacent to each other in the second direction and in which a width between the gate trenches adjacent to each other is relatively narrow; a second portion sandwiched between the second trenches adjacent to each other in the second direction and having a relatively wide width between the adjacent gate trenches, the second portion being alternately arranged in the first direction.

2. a crystal plane of a sidewall of the first trench is an m-plane; the crystal plane of the sidewall of the second trench is an m-plane; 2. The silicon carbide semiconductor device according to claim 1, wherein a crystal plane of a sidewall of the gate trench connecting the sidewall formed of the first trench and the sidewall formed of the second trench is an m-plane or an a-plane.

3. a width of the first portion in the second direction is narrower than a width of the first trench in the second direction; The silicon carbide semiconductor device according to claim 1 , wherein the width of the second portion in the second direction is wider than the width of the second trench in the second direction.

4. The width of the first portion in the second direction is 200 nm or less, The silicon carbide semiconductor device according to claim 1 , wherein the second portion has a width in the second direction exceeding 200 nm.

5. the second semiconductor region is provided between the gate trenches adjacent to each other across the entire area in the first direction, the third semiconductor region is provided between the gate trenches adjacent to each other across the entire area in the first direction, 2 . The silicon carbide semiconductor device according to claim 1 , wherein the fourth semiconductor regions are provided only in the second portion and are interspersed in the first direction between the gate trenches adjacent to each other.

6. an interlayer insulating film provided on a first main surface of the semiconductor substrate and covering the gate electrode; a contact hole penetrating the interlayer insulating film in a depth direction to expose the fourth semiconductor region and the third semiconductor region; Equipped with the contact hole has a tapered cross-sectional shape narrowing toward the first main surface side of the semiconductor substrate, The silicon carbide semiconductor device according to claim 1 , wherein the first electrode is in contact with the fourth semiconductor region and the third semiconductor region through the contact hole.

7. 2. The silicon carbide semiconductor device according to claim 1, further comprising: a fifth semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region, the fifth semiconductor region being provided between the second semiconductor region and the first semiconductor region and at a position deeper on the second electrode side than a bottom surface of the gate trench.

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