Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing local electric field concentration.SOLUTION: The impurity concentrations of an n-type column region 4 and a p-type column region 5 of a parallel pn layer 3 are relatively high in the center of an active region 21, lower than that of the active region 21 in a transition region 22, and relatively low in an edge termination region 23. The transition region 22 includes a first portion 21a that overlaps the outer periphery of the active region 21 by a predetermined width d. The first portion 21a of the transition region 22 includes at least a pair of n-type column region 4 and p-type column region 5 adjacent to each other in the active region 21. In both the n-type impurity concentration distribution 51 and the p-type impurity concentration distribution 52 of the parallel pn layer 3, the impurity concentration is relatively high in the center of the active region 21, and the impurity concentration decreases in the transition region 22 from the active region 21 side toward the edge termination region 23 side, and the impurity concentration is relatively low in the termination region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In conventional vertical semiconductor devices, the on-resistance is reduced by forming the drift layer into a super junction (SJ) structure consisting of an n-type column region and a p-type column region. In order to ensure a certain breakdown voltage in the edge termination region, an SJ structure is also formed in the edge termination region under conditions different from those in the active region. Devices have been disclosed in which the impurity concentration of the column region that constitutes the SJ structure is relatively low in the edge termination region in order to make the breakdown voltage of the edge termination region higher than that of the active region (see, for example, Patent Documents 1 to 4 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5342752 [Patent Document 2] JP 2007-266505 A [Patent Document 3] JP 2015-220367 A [Patent Document 4] JP 2023-505942 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a conventional vertical semiconductor device with an SJ structure, the difference in impurity concentration between the same conductivity type column regions that constitute the SJ structure between the active region and the edge termination region becomes large, so that the n-type column region and the p-type column region adjacent to each other at the boundary between the active region and the edge termination region are likely to become charge unbalanced. Therefore, if the charge amount of the column region is biased due to process variations or the like, local electric field concentration occurs at the boundary between the active region and the edge termination region, leading to deterioration of characteristics such as a decrease in breakdown voltage.

[0005] Note that charge imbalance means that there is a large difference between the amount of charge expressed by the product of the carrier concentration (concentration of activated impurities) in the n-type column region and the width of the n-type column region, and the amount of charge expressed by the product of the carrier concentration in the p-type column region and the width of the p-type column region, and that the amounts of charge in the adjacent n-type column region and p-type column region are not balanced.

[0006] SUMMARY OF THE PRESENT DISCLOSURE In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a semiconductor device that suppresses localized electric field concentration. [Means for solving the problem]

[0007] In order to solve the above problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. An active region, a termination region, and a transition region are provided in a semiconductor substrate. The termination region is disposed outside the active region and surrounds the periphery of the active region. The transition region is a region between the active region and the termination region. A parallel pn layer is provided inside the semiconductor substrate in the active region, the transition region, and the termination region. The parallel pn layer is formed by alternately and repeatedly arranging first conductivity type regions and second conductivity type regions adjacent to each other in a first direction parallel to the front surface of the semiconductor substrate. An element structure is provided between the front surface of the semiconductor substrate and the parallel pn layer in the active region. A first electrode is provided on the front surface of the semiconductor substrate and is electrically connected to the element structure. A second electrode is provided on the back surface of the semiconductor substrate.

[0008] The transition region is disposed overlapping an outer periphery of the active region, and includes at least a pair of the first conductivity type region and the second conductivity type region adjacent to each other of the active region. The parallel pn layer has a first conductivity type impurity concentration distribution in which the impurity concentration is relatively high in a central portion of the active region on the inner side than the transition region, the impurity concentration decreases from the active region side to the termination region side in the transition region, and the impurity concentration is relatively low in the termination region, and a second conductivity type impurity concentration distribution in which the impurity concentration is relatively high in the central portion of the active region, the impurity concentration decreases from the active region side to the termination region side in the transition region, and the impurity concentration is relatively low in the termination region.

[0009] According to the above-mentioned invention, even if there is a large difference in impurity concentration between the same conductivity type regions of the parallel pn layer between the active region and the edge termination region, the impurity concentration gradient is gentle in the transition region, and charge imbalance is unlikely to occur between the adjacent first conductivity type region and second conductivity type region in this portion. Effect of the Invention

[0010] The semiconductor device according to the present invention has an effect of suppressing local electric field concentration. [Brief description of the drawings]

[0011] [Figure 1] 1 is a plan view showing a layout of a semiconductor device according to an embodiment when viewed from the front surface side of a semiconductor substrate; [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Figure 3A] 1 is a plan view showing an example of a state during the manufacture of a semiconductor device according to an embodiment; [Figure 3B] 1 is a plan view showing an example of a state during the manufacture of a semiconductor device according to an embodiment; [Figure 4] 3A is a cross-sectional view showing a cross-sectional structure taken along line BB' in FIGS. 3A and 3B. FIG. [Diagram 5] FIG. 11 is a characteristic diagram showing the results of simulating the electric field strength during reverse recovery of the body diodes of the embodiment and the reference example. [Figure 6] 1 is an explanatory diagram illustrating a schematic state during reverse recovery of a body diode of a semiconductor device according to an embodiment; [Figure 7] 1A and 1B are explanatory diagrams showing a cross-sectional structure of a semiconductor device according to a reference example and a state during reverse recovery of a body diode thereof; [Figure 8] 11 is a plan view showing a state during the manufacture of a semiconductor device according to a reference example; FIG. [Figure 9] 9 is a cross-sectional view showing a cross-sectional structure taken along line AA-AA' in FIG. 8. [Figure 10A] 1 is a plan view (part 1) showing another example of a layout of a semiconductor device according to an embodiment when viewed from the front surface side of a semiconductor substrate. FIG. [Figure 10B] 13 is a plan view (part 2) showing another example of the layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Preferred embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in layers and regions prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - appended to n or p respectively mean that the impurity concentration is higher and lower than that of layers and regions not prefixed with them. In the following description of the embodiments and the accompanying drawings, the same reference numerals are assigned to similar configurations, and duplicated explanations will be omitted.

[0013] (Reference example) First, the problems of the semiconductor device of the reference example will be described. FIG. 7 is an explanatory diagram showing the cross-sectional structure of the semiconductor device of the reference example and the state during reverse recovery of the body diode. FIG. 7 shows, under the cross-sectional view of the semiconductor device 110, a schematic diagram of impurity concentration distributions 151, 152 in the first direction X of one stage of the parallel pn layer 103 after thermal diffusion treatment, which is estimated from the formation method (multi-stage epitaxial method). FIG. 8 is a plan view showing the state during the manufacture of the semiconductor device of the reference example. FIG. 9 is a cross-sectional view showing the cross-sectional structure along the cutting line AA-AA' in FIG. 8. FIGS. 8 and 9 show the state of the parallel pn layer 103 before thermal diffusion treatment.

[0014] The semiconductor device 110 of the reference example shown in FIG. 7 is a planar gate type SJ-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor with an insulated gate having a three-layer structure of metal-oxide film-semiconductor) in which a drift layer is formed as a parallel pn layer 103 to form an SJ structure from an active region 121 of a semiconductor substrate (semiconductor chip) 140 using silicon (Si) as a semiconductor material through a part of a transition region 122 to an edge termination region 123.

[0015] The active region 121 has a substantially rectangular planar shape and is disposed approximately in the center of the semiconductor substrate 140. The edge termination region 123 is a region between the active region 121 and the chip end (the end of the semiconductor substrate 140) and surrounds the periphery of the active region 121 in a substantially rectangular shape. The edge termination region 123 faces the active region 121 via the transition region 122 in a first direction X described below, and contacts the active region 121 in a second direction Y described below. The transition region 122 is sandwiched between the active region 121 and the edge termination region 123 in the first direction X.

[0016] The semiconductor substrate 140 is ++ The n-type drain region 101 ++ The active region 121 is formed by stacking epitaxial layers 142, 143, which are to become the n-type buffer region 102 and the parallel pn layer 103, in this order on a starting substrate 141. In the active region 121, a p-type base region 106, an n-type base region 108, and an n-type base region 109 are formed between the front surface of the semiconductor substrate 140 and the parallel pn layer 103. +type source region 107 and p + A type contact region 108 is provided, and a gate insulating film 111, a gate electrode 112, an interlayer insulating film 113, and a source electrode 114 are provided on the front surface of a semiconductor substrate 140.

[0017] In transition region 122, peripheral p-type regions 131, 132 extend from edge termination region 123 between the front surface of semiconductor substrate 140 and parallel p-n layer 103, and a source contact is formed between peripheral p-type region 132 and source electrode 114 in a contact hole. The front surface of semiconductor substrate 140 in edge termination region 123 is covered with insulating layer 133, and gate runner 135 is provided on insulating layer 133 in depth direction Z, facing peripheral p-type regions 131, 132. Drain electrode 115 is provided on the entire back surface of semiconductor substrate 140.

[0018] The parallel pn layer 103 is formed by alternately and repeatedly arranging n-type column regions 104 and p-type column regions 105 adjacent to each other from the active region 121 to the transition region 122 and edge termination region 123 in a first direction X parallel to the front surface of the semiconductor substrate 140. Each n-type column region 104 and each p-type column region 105 extends linearly from the active region 121 to the edge termination region 123 in a second direction Y that is parallel to the front surface of the semiconductor substrate 140 and perpendicular to the first direction X, and forms a quadrangular prism that extends linearly in the depth direction Z.

[0019] All of the n-type column regions 104 and p-type column regions 105 are arranged with approximately the same widths W101, W102 and approximately the same repetition pitches P101, P102 in the short direction (first direction X), extend linearly with approximately the same widths W101, W102 from the active region 121 to the edge termination region 123 in the long direction (second direction Y), and extend linearly with approximately the same widths W101, W102 in the depth direction Z. That is, both the n-type column regions 104 and the p-type column regions 105 have the same stripe pattern in both plan and cross-sectional views.

[0020] Both the n-type column region 104 and the p-type column region 105 are formed by ion implantation of impurities into the non-doped epitaxial layer 143 using a multistage epitaxial method. The multistage epitaxial method is a method in which an epitaxial layer is divided into a plurality of stages and epitaxially grown in multiple stages until it reaches a predetermined thickness, and each time an impurity-implanted region of a predetermined conductivity type is selectively formed in the epitaxial layer by photolithography and ion implantation so as to face an impurity-implanted region of the same conductivity type in the lower layer in the depth direction Z.

[0021] The parallel pn layer 103 has an n-type impurity concentration distribution 151 and a p-type impurity concentration distribution 152 in which both column regions 104, 105 have a relatively high impurity concentration in the active region 121 (hereinafter referred to as the first parallel pn layer 103a), and the column regions 104, 105 have a lower impurity concentration in the transition region 122 in the first direction X toward the chip end side, and an edge termination region 123 (hereinafter referred to as the third parallel pn layer 103c) in which both column regions 104, 105 have a relatively lower impurity concentration.

[0022] The n-type impurity concentration distribution 151 and the p-type impurity concentration distribution 152 are formed in each stage of the epitaxial layer 143 that is epitaxially grown in multiple stages. The impurity concentration distribution of each column region 104, 105 in each stage of the epitaxial layer 143 is a Gaussian distribution with the apex at the depth position of the ion implantation range. The intersection of the n-type impurity concentration distribution 151 and the p-type impurity concentration distribution 152 is the interface between the n-type column region 104 and the p-type column region 105. There is a large difference in impurity concentration between the column regions of the same conductivity type between the first and third parallel pn layers 103a, 103c.

[0023] Each of the ion implantation masks for forming the n-type column region 104 and the p-type column region 105 has an opening pattern in which the opening width is relatively narrow in the portion where the impurity concentration is to be relatively low. Using this ion implantation mask, impurities of a predetermined conductivity type are ion-implanted at the same dose into the entire surface of the non-doped epitaxial layer 143 to selectively form column regions of the predetermined conductivity type. The n-type column region 104 and the p-type column region 105 have a relatively low effective impurity concentration in the portion where the opening width of the ion implantation mask is relatively narrow.

[0024] Specifically, the n-type column region 104a (104) and the p-type column region 105a (105) of the first parallel pn layer 103a (part of the active region 121) of the parallel pn layer 103 have approximately the same widths W101, W102 and approximately the same impurity concentration. The n-type column region 104a and the p-type column region 105a adjacent to each other are generally charge balanced. The n-type column region 104 and the p-type column region 105 have relatively high impurity concentrations in the n-type column region 104a and the p-type column region 105a, respectively.

[0025] In the parallel pn layer 103, the n in the transition region 122 (hereinafter referred to as the second parallel pn layer 103b) - The mold column region 104b (104) and p - The column region 105b (105) has substantially the same widths W101 and W102 and substantially the same impurity concentration. - Mold column regions 104b and p - The charge balance is roughly the same as that of the column region 105b. - Mold column regions 104b and p - The n-type column regions 105b have lower impurity concentrations than the n-type column regions 104a and the p-type column regions 105a of the active region 121, respectively.

[0026] The n of the third parallel pn layer 103c (part of the edge termination region 123) of the parallel pn layer 103 -- The type column region 104c (104) and p --The column region 105c (105) has substantially the same widths W101 and W102 and substantially the same impurity concentration. -- Mold column regions 104c and p -- The charge balance is approximately the same as that of the column region 105c. -- Mold column regions 104c and p -- The type column region 105c is a transition region 122 - Mold column regions 104b and p - The impurity concentration is lower than that of the mold column region 105b.

[0027] Charge balance means that the charge amount expressed by the product of the carrier concentration (concentration of activated impurities) of the n-type column region 104 and the width W101 is substantially the same as the charge amount expressed by the product of the carrier concentration of the p-type column region 105 and the width W102, and that the charge amounts of the adjacent n-type column region 104 and p-type column region 105 are balanced. "Substantially the same impurity concentration (carrier concentration)" and "substantially the same width" respectively mean that the impurity concentration and width are the same within the range including the allowable error due to process variations.

[0028] To form this parallel pn layer 103 by the multi-stage epitaxial method, an n-type impurity implanted region 144 is formed by photolithography and ion implantation at the center in the first direction X of the formation region of each n-type column region 104 in each stage of the epitaxial layer 143. A p-type impurity implanted region 145 is formed by photolithography and ion implantation at the center in the first direction X of the formation region of each p-type column region 105 in each stage of the epitaxial layer 143. Then, a thermal diffusion process is performed to diffuse the impurities in the epitaxial layer 143.

[0029] The n-type impurity implanted region 144 has a widest width Wn101 at a portion 144a of the active region 121, a narrower width Wn102 at a portion 144b of the transition region 122 than at a portion 144a of the active region 121, and a narrowest width Wn103 at a portion 144c of the edge termination region 123. The p-type impurity implanted region 145 has a widest width Wp101 at a portion 145a of the active region 121, a narrower width Wp102 at a portion 145b of the transition region 122 than at a portion 145a of the active region 121, and a narrowest width Wp103 at a portion 145c of the edge termination region 123.

[0030] Each stage of the parallel pn layer 103 (epitaxial layer 143) before the thermal diffusion process is in a state where n-type impurity implanted regions 144 and p-type impurity implanted regions 145 are alternately arranged in the first direction X via non-doped regions (regions where impurities are not ion-implanted and the epitaxial layer 143 remains as it is) 146 (FIGS. 8 and 9). The widths Wn101, Wn102, and Wn103 of the n-type impurity implanted regions 144 and the widths Wp101, Wp102, and Wp103 of the p-type impurity implanted regions 145 and the doses of the p-type impurities are approximately the same in adjacent portions. In FIG. 8 and 9, the portions of the epitaxial layer 143 marked with n and p are the n-type impurity implanted regions 144 and the p-type impurity implanted regions 145, respectively, and the portions marked with neither n nor p are the non-doped regions 146.

[0031] By a subsequent thermal diffusion process, the n-type impurity implanted regions 144 and the p-type impurity implanted regions 145 in each stage of the epitaxial layer 143 are diffused into the adjacent non-doped regions 146 and reach an equilibrium state. The n-type impurity implanted regions 144 in each stage of the epitaxial layer 143 are connected to each other in the depth direction Z. The p-type impurity implanted regions 145 in each stage of the epitaxial layer 143 are connected to each other in the depth direction Z. As a result, the n-type impurity implanted regions 144 and the p-type impurity implanted regions 145 in each stage of the epitaxial layer 143 become n-type column regions 104 and p-type column regions 105 having approximately the same widths W101 and W102, respectively.

[0032] In the vertical MOSFET having the SJ structure in which the drift layer is the parallel pn layer 103 as in the semiconductor device 110 of the above-mentioned reference example, the drift layer is - Compared to normal vertical MOSFETs consisting of only a gate region, the on-resistance is smaller, which allows for smaller devices and faster speeds, and they are used in a variety of applications. MOSFETs and IGBTs are also widely used for power conversion, and the mainstream MOSFETs for power conversion are vertical, with source and drain electrodes on the front and back surfaces of the semiconductor substrate, respectively.

[0033] In a vertical MOSFET, when the device is off, a depletion layer spreads vertically (toward the source electrode and the drain electrode) from the pn junction between the base region and the drift region, and the depletion layer also spreads laterally within the drift region from the active region toward the chip edge. This requires a design that controls the lateral spread of the depletion layer in the edge termination region. Since the element characteristics are primarily determined by the characteristics of the active region, in order to maximize the performance of the semiconductor device, the edge termination region is generally designed to have a higher breakdown voltage than the active region.

[0034] The breakdown voltage is determined by the width of the depletion layer, and the wider the depletion layer, the higher the breakdown voltage. The depletion layer width can be widened by lowering the impurity concentration in the drift region, but if the depletion layer reaches the chip edge, punch-through occurs and the breakdown voltage is no longer maintained. For this reason, it is necessary to stop the depletion layer within the edge termination region, but the electric field concentrates at the point where the spread of the depletion layer is suddenly suppressed, causing avalanche breakdown, leading to the destruction of the semiconductor device. On the other hand, if the spread of the depletion layer is stopped gently, the width of the edge termination region will become wider, leading to an increase in the size of the semiconductor device.

[0035] Also, the lower the impurity concentration in the drift region, the higher the on-resistance. Therefore, it is necessary to suppress the spread of the depletion layer in the edge termination region in a balanced manner, taking into consideration the trade-off relationship between the miniaturization of the semiconductor device and the improvement of the avalanche resistance, and the trade-off relationship between the high breakdown voltage and the low on-resistance. In the semiconductor device 110 of the reference example, the parallel pn layer 103 is also arranged in the edge termination region 123, so it is important to control the depletion layer that spreads from the pn junction between the p-type column region 105 and the n-type column region 104 in the edge termination region 123.

[0036] In the semiconductor device 110 of the reference example, a method for making the breakdown voltage of the edge termination region 123 higher than the breakdown voltage of the active region 121 can be achieved by using an opening pattern in which the opening width of each ion implantation mask for forming the n-type column region 104 and the p-type column region 105 is relatively narrow in the edge termination region 123 (for example, an opening pattern in which the opening width in the edge termination region 123 is half that in the active region 121), thereby making the impurity concentrations of the n-type column region 104 and the p-type column region 105 relatively low in the edge termination region 123.

[0037] In the edge termination region 123, the electric field is distributed in a fan shape centered on the outer periphery of the source electrode 114 of the active region 121, resulting in an electric field distribution in which equipotential lines are lined up at predetermined intervals in an oblique direction from the outer periphery of the source electrode 114 of the active region 121 toward the end of the drain electrode 115 (the chip end on the back surface side of the semiconductor substrate 140). For this reason, the edge termination region 123 is less susceptible to depletion than the active region 121, and the breakdown voltage can be easily increased by lowering the impurity concentrations of the n-type column region 104 and the p-type column region 105.

[0038] However, if the impurity concentrations of n-type column region 104 and p-type column region 105 are relatively low in edge termination region 123, a steep impurity concentration gradient occurs at the boundary between active region 121 and edge termination region 123 and at transition region 122, and charge imbalance is likely to occur between adjacent n-type column region 104 and p-type column region 105 in these areas. For this reason, if there is a bias in the charge amounts of column regions 104, 105 due to process variations or the like, electric field concentration occurs locally at the boundary between active region 121 and edge termination region 123 and at transition region 122, reducing the breakdown voltage.

[0039] Note that charge imbalance means that there is a large difference between the amount of charge expressed by the product of the carrier concentration (concentration of activated impurities) in the n-type column region and the width of the n-type column region, and the amount of charge expressed by the product of the carrier concentration in the p-type column region and the width of the p-type column region, and that the amounts of charge in the adjacent n-type column region and p-type column region are not balanced.

[0040] In addition, a transition region 122 having a relatively narrow width (width in the first direction X) is disposed between the active region 121 and the edge termination region 123, or the active region 121 and the edge termination region 123 are in contact with each other. Since the active region 121 has a lower resistance than the transition region 122 and the edge termination region 123, the n-type pn junction diode (body diode) of the edge termination region 123 is electrically connected to the active region 121. -- The holes accumulated in the type column region 104c tend to flow into the active region 121 as a recovery (reverse recovery) current Ir during reverse recovery of the body diode.

[0041] When an avalanche breakdown occurs in the edge termination region 123 and the recovery current Ir increases, a large current (recovery current Ir) is concentrated not only in the high resistance path I101 that passes through the source contact of the transition region 122 toward the source electrode 114, but also in the low resistance path I102 that passes through the p-type base region 106 at the outer periphery of the active region 121 toward the source electrode 114, which may result in destruction of the semiconductor device 110. Therefore, the problem to be solved in this embodiment is how to suppress local electric field concentration and local current concentration.

[0042] (Embodiment) The structure of the semiconductor device according to the embodiment will be described. FIG. 1 is a plan view showing the layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. In FIG. 1, the outer periphery of the active region 21 and the inner periphery of the edge termination region 23 are indicated by coarse dashed lines, and the inner periphery of the transition region 22 is indicated by fine dashed lines. FIG. 2 is a cross-sectional view showing the cross-sectional structure taken along the line A-A' in FIG. 1. In FIG. 2, under the cross-sectional view of the semiconductor device 10, impurity concentration distributions 51 and 52 in the first direction X for one stage of the parallel pn layer 3 after thermal diffusion processing, which are estimated from the formation method (multi-stage epitaxial method), are shown in schematic form. FIGS. 3A and 3B are plan views showing an example of a state during the manufacture of the semiconductor device according to the embodiment.

[0043] 3A and 3B show an example of the layout of the parallel pn layer 3 (n-type impurity implanted region 44 and p-type impurity implanted region 45) before thermal diffusion treatment. Fig. 4 is a cross-sectional view showing the cross-sectional structure along the cutting line B-B' in Figs. 3A and 3B. The semiconductor device 10 according to the embodiment shown in Figs. 1 and 2 is a planar gate MOSFET with an SJ structure in which the drift layer is the parallel pn layer 3 from the active region 21 to the transition region 22 and edge termination region 23 of a semiconductor substrate (semiconductor chip) 40 made of silicon (Si) as a semiconductor material.

[0044] The active region 21 is a region through which a main current (drift current) flows when the MOSFET is on. In the active region 21, a plurality of unit cells (functional units of an element) of the MOSFET having the same structure are arranged adjacent to each other. The active region 21 has a substantially rectangular planar shape, and is arranged substantially in the center (chip center) of the semiconductor substrate 40. The active region 21 is located closer to the chip center than the center of the gate electrode 12 closest to the chip end (end of the semiconductor substrate 40) in a first direction X described later, and is also located n-th of the gate electrode 12 in a second direction Y described later. + This is a portion closer to the chip center than the longitudinal ends of the source region 7 .

[0045] The semiconductor substrate 40 is ++ n-type drain region 1 ++ The semiconductor substrate 40 is formed by stacking epitaxial layers 42 and 43, which are to become the n-type buffer region 2 and the parallel pn layer 3, in this order on the front surface of a starting substrate 41. ++ The main surface on the mold starting substrate 41 side is the front surface, and n ++ The main surface on the side of the starting substrate 41 is referred to as the back surface. In the active region 21, p-type base regions 6 and n-type base regions 7 and 8 are formed between the front surface of the semiconductor substrate 40 and the parallel pn layer 3. + Type source region 7, p + A type contact region 8 and a JFET region 9 are provided.

[0046] p-type base region 6, n + Type source region 7, p + The n-type contact region 8 and the JFET region 9 are diffusion regions formed by ion implantation in the surface region of the epitaxial layer 43, and extend linearly in the longitudinal direction (first direction X) of the n-type column region 4 and the p-type column region 5, which will be described later. The p-type base region 6 is provided between the front surface of the semiconductor substrate 40 and the p-type column region 5, and has a lower surface (n ++ The p-type base region 6 is in contact with the p-type column region 5 at its surface on the side of the p-type drain region 1. The p-type base region 6 has a width in the first direction X greater than that of the p-type column region 5.

[0047] p-type base region 6, n + Type source region 7 and p +The mold contact region 8 has an arc-shaped corner portion (the boundary between the bottom surface and the side surface) that is rounded with a predetermined curvature. + Type source region 7 and p + The n-type contact regions 8 are selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 6. + Type source region 7 and p + The n-type contact region 8 is provided away from the side of the p-type base region 6 and is surrounded by the p-type base region 6. + Type source region 7 and p + The mold contact regions 8 are adjacent to each other.

[0048] n + Type source region 7 and p + The contact region 8 is exposed to a contact hole 13a (described later) on the front surface of the semiconductor substrate 40. A source contact is formed in the contact hole 13a through ohmic contact between the source electrode 14 and the semiconductor substrate 40. + The source region 7 is p + The p-type contact region 8 is located closer to the gate electrode 12 (closer to the side surface of the p-type base region 6). + The p-type contact region 8 may not be provided. + Instead of the p-type contact region 8, the p-type base region 6 reaches the front surface of the semiconductor substrate 40 and is exposed through the contact hole 13a.

[0049] The JFET region 9 is an n-type region sandwiched between adjacent p-type base regions 6, and is in contact with the p-type base region 6 on the side and with the n-type column region 4 on the bottom. The JFET region 9 is adjacent to the channel (n-type inversion layer) and serves as a current path for the drift current. The impurity concentration of the JFET region 9 is equal to or higher than the impurity concentration of the n-type column region 4, and the n + The impurity concentration of the n-type source region 7 is lower than that of the n-type source region 7. The JFET region 9 may be formed of n-type column regions 4 extending between adjacent p-type base regions 6 so as to reach the front surface of the semiconductor substrate 40.

[0050] The gate electrode 12 is provided on the front surface of the semiconductor substrate 40 via a gate insulating film 11, and the n-type + The gate electrode 12 covers the region between the n-type source region 7 and the JFET region 9. The gate electrode 12 covers the entire surface of the JFET region 9 via the gate insulating film 11, and faces the n-type column region 4 in the depth direction Z. The center in the first direction X of the gate electrode 12 approximately coincides with the center in the first direction X of the n-type column region 4 facing the gate electrode 12 in the depth direction Z. One unit cell is formed between the centers of the gate electrodes 12 adjacent to each other in the first direction X.

[0051] The interlayer insulating film 13 is provided on the entire front surface of the semiconductor substrate 40 and covers the gate electrode 12. A contact hole 13a is provided in the interlayer insulating film 13 for each unit cell. The contact hole 13a is + Type source region 7 and p + The n-type contact region 8 is exposed. The source electrode (first electrode) 14 is provided on the interlayer insulating film 13 so as to fill the contact hole 13a. + Type source region 7 and p + The source electrode 14 is in ohmic contact with the type contact region 8. The source electrode 14 has substantially the same planar shape as the active region 21 and covers substantially the entire area of ​​the active region 21.

[0052] The transition region 22 has a first portion 22a overlapping the active region 21 and a second portion 22b between the active region 21 and the edge termination region 23. The transition region 22 has a function of decreasing the impurity concentrations of the n-type column region 4 and the p-type column region 5 described below from the active region 21 side (i.e., the chip center side (inside)) toward the edge termination region 23 side (i.e., the chip end side (outside)), thereby suppressing electric field concentration near the boundary between the active region 21 and the edge termination region 23.

[0053] The first portion 22a of the transition region 22 is a portion of the transition region 22 extending from the end of the active region 21 toward the chip center, and overlaps the entire circumference of the outer periphery of the active region 21 with approximately the same predetermined width d. Specifically, the first portion 22a of the transition region 22 includes at least a pair of n-type column regions 4 and p-type column regions 5 adjacent to each other in the active region 21 in the first direction X. The inner peripheral end (the end on the chip center side) of the first portion 22a of the transition region 22 approximately coincides with the center of a predetermined n-type column region 4 (the center of the gate electrode 12) in the first direction X. The n-type column region 4 facing the inner peripheral end (the inner peripheral end of the transition region 22) of the first portion 22a of the transition region 22 in the depth direction Z is an n-type column region 4a of a first parallel pn layer 3a described later.

[0054] That is, the first portion 22a of the transition region 22 includes at least one unit cell (between the centers of two adjacent gate electrodes 12 closest to the chip end in the first direction X) from the chip end side in the first direction X, and overlaps both longitudinal ends of the unit cell by a predetermined width d in the second direction Y. Preferably, the first portion 22a of the transition region 22 has a width d that is approximately twice or more the repetition pitch P1 of the n-type column regions 4, and includes two or more unit cells from the chip end side in the first direction X. The width d of the first portion 22a of the transition region 22 is, for example, approximately 5 μm or more.

[0055] The wider the width d of the first portion 22a of the transition region 22, the more the electric field concentration in and near the transition region 22 is suppressed, but as described later, the impurity concentrations of the n-type column region 4 and the p-type column region 5 in the first portion 22a of the transition region 22 become relatively low, and the on-resistance increases. For this reason, the width d of the first portion 22a of the transition region 22 is set appropriately according to the widths W1, W2 and impurity concentrations of the n-type column region 4 and the p-type column region 5 in the first portion 22a of the transition region 22, for example, within a range of about 50 μm or less.

[0056] The second portion 22b of the transition region 22 is a portion of the transition region 22 that extends from the end of the active region 21 toward the chip end, and is adjacent to the chip end side of the first portion 22a of the transition region 22. The second portion 22b of the transition region 22 is sandwiched between the first portion 22a and the edge termination region 23 in the first direction X. The second portion 22b of the transition region 22 is not provided between the active region 21 and the edge termination region 23 in the second direction Y. The outer peripheral end (the end on the chip end side) of the second portion 22b of the transition region 22 approximately coincides with the end of the source electrode 14. When the outer peripheral end (the outer peripheral end of the transition region 22) of the second portion 22b of the transition region 22 does not approximately coincide with the pn junction between the n-type column region 4 and the p-type column region 5, the column region to which the outer peripheral end of the second portion 22b of the transition region 22 faces is the n-type column region 4c or the p-type column region 5c of the third parallel pn layer 3c described later.

[0057] In the second portion 22b of the transition region 22, an edge termination region 23 extends from the outer periphery p-type region 31 and the outer periphery p-type region 32 between the front surface of the semiconductor substrate 40 and the parallel pn layer 3. + A contact region 32 extends through the second portion 22b of the transition region 22. A contact hole 13b is provided in the interlayer insulating film 13 on the chip edge side of the gate electrode 12 in the second portion 22b of the transition region 22. The contact hole 13b extends linearly in the first direction X along the boundary between the first portion 22a and the second portion 22b of the transition region 22, and has an outer periphery p + The mold contact area 32 is exposed.

[0058] In the contact hole 13b, a source electrode 14 is buried, which extends from the active region 21 toward the chip end side. The source electrode 14 and the semiconductor substrate 40 (the outer peripheral p + A source contact is formed through ohmic contact with the n-type contact region 32). The source electrode 14 terminates on an insulating layer 33, which will be described later. The second portion 22b of the transition region 22 functions to extract holes (minority carriers) accumulated in the n-type column region 4 of the edge termination region 23 when a parasitic pn junction diode (body diode) of the MOSFET is conducting, to the source electrode 14 during reverse recovery of the body diode.

[0059] Edge termination region 23 contacts second portion 22b of transition region 22 in first direction X and contacts active region 21 in second direction Y. Edge termination region 23 surrounds active region 21 in a substantially rectangular shape, in part via second portion 22b of transition region 22. Periphery p-type region 31 is selectively provided in edge termination region 23 between the front surface of semiconductor substrate 40 and parallel p-n layer 3. Periphery p-type region 31 is formed in epitaxial layer 43 simultaneously with p-type base region 6, for example, and has substantially the same impurity concentration and substantially the same depth as p-type base region 6.

[0060] The peripheral p-type region 31 surrounds the active region 21 in a substantially rectangular shape. The p-type base regions 6 of all the unit cells are connected to the peripheral p-type region 31 at their longitudinal ends. + The peripheral p-type region 31 is fixed to the potential of the source electrode 14 via the n-type contact region 32. The underside of the peripheral p-type region 31 contacts the second portion 22b of the transition region 22 and the n-type column region 4 and the p-type column region 5 in the edge termination region 23. The peripheral end of the peripheral p-type region 31 terminates inside a predetermined n-type column region 4.

[0061] The outer periphery p-type region 31 extends further toward the chip center than the contact hole 13b in the first direction X, terminates within the second portion 22b of the transition region 22, and terminates toward the chip center in the second direction Y at the boundary between the active region 21 and the edge termination region 23. The inner periphery end of the outer periphery p-type region 31 extending toward the chip center in the first direction X faces the gate electrode 12 closest to the chip end in the depth direction Z. The inner periphery end of the outer periphery p-type region 31 extending toward the chip center in the second direction Y faces the longitudinal ends of all of the gate electrodes 12 in the depth direction Z.

[0062] In the portion of the peripheral p-type region 31 facing the gate electrode 12 in the depth direction Z, + The n-type source region 7 is not provided. The n-type source region 7 is provided in a portion of the peripheral p-type region 31 facing the gate electrode 12 in the depth direction Z. +By not providing the n-type source region 7, the gate electrode 12 comes into contact with the peripheral p-type region 31, and the pn junction between the peripheral p-type region 31 and the n-type column region 4 operates as a body diode, so that hole current can be efficiently discharged to the gate electrode 12.

[0063] Between the front surface of the semiconductor substrate 40 and the peripheral p-type region 31, a peripheral p + A contact region 32 is provided. + The contact region 32 is a diffusion region formed by ion implantation in the surface region of the epitaxial layer 43, and contacts the insulating layer 33 on the front surface of the semiconductor substrate 40. + The contact region 32 may not be provided. In this case, the outer periphery p + Instead of the p-type contact region 32, the peripheral p-type region 31 contacts the insulating layer 33 on the front surface of the semiconductor substrate 40 and is exposed to the contact hole 13b.

[0064] The front surface of the semiconductor substrate 40 in the edge termination region 23 is covered with an insulating layer 33. The insulating layer 33 is formed, for example, by laminating a field oxide film and an interlayer insulating film 13 in this order. A gate polysilicon (poly-Si) wiring layer 34 is provided inside the insulating layer 33. A gate metal wiring layer 35 is provided on the insulating layer 33, facing the gate polysilicon wiring layer 34 in the depth direction Z. The gate polysilicon wiring layer 34 and the gate metal wiring layer 35 are disposed in the depth direction Z between the peripheral p-type region 31 and the peripheral p + It faces the mold contact region 32 .

[0065] The gate polysilicon wiring layer 34 and the gate metal wiring layer 35 function as a gate runner. The gate polysilicon wiring layer 34 is disposed only at a position facing the active region 21 in the second direction Y, and the longitudinal ends of all the gate electrodes 12 are connected to each other. The gate metal wiring layer 35 surrounds the periphery of the active region 21 in a substantially rectangular shape. The gate metal wiring layer 35 contacts the gate polysilicon wiring layer 34 directly below via a contact hole (not shown) in the insulating layer 33.

[0066] The gate pad 16 is provided on the insulating layer 33 in, for example, the active region 21 (or across from the active region 21 to the transition region 22) so as to be in contact with the gate metal wiring layer 35 (FIG. 1). The gate metal wiring layer 35 and the gate pad 16 are formed, for example, at the same time as the source electrode 14. The gate metal wiring layer 35 and the gate pad 16 are provided so as to be electrically insulated from the source electrode 14. The gate pad 16 has, for example, a substantially rectangular planar shape, with one side directly contacting one side of the inner periphery of the gate metal wiring layer 35 and the remaining three sides facing the source electrode 14 at a predetermined interval.

[0067] Between the parallel pn layer 3 and the chip edge is an n-type region 36. The n-type region 36 is a diffusion region formed in the epitaxial layer 43 by a multi-stage epitaxial method when the parallel pn layer 3 is formed, and is in contact with the insulating layer 33 on the front surface of the semiconductor substrate 40 and in contact with the n-type buffer region 2 on the bottom surface. The n-type region 36 is in contact with the parallel pn layer 3 and surrounds the periphery of the parallel pn layer 3 in a substantially rectangular shape. The n-type region 36 is exposed at the chip edge. The n-type region 36 is formed in the n-type column region 4 (described later) of the edge termination region 23. -- The impurity concentration may be higher than that of the mold column region 4c).

[0068] Between the front surface of the semiconductor substrate 40 and the n-type region 36, a p + A channel stopper region 37 is selectively provided. + The channel stopper region 37 extends along the outer periphery of the chip and surrounds the parallel pn layer 3 in a substantially rectangular shape with the corners (vertices) rounded at a predetermined curvature. + The p-type channel stopper region 37 is formed in the epitaxial layer 43 at the same time as the p-type base region 6, for example, and has approximately the same impurity concentration and approximately the same depth as the p-type base region 6.

[0069] The channel stopper electrode 38 is provided on the front surface of the semiconductor substrate 40, separated from the gate metal wiring layer 35. The channel stopper electrode 38 is a metal electrode on the outermost periphery of the front surface of the semiconductor substrate 40, and is formed, for example, at the same time as the source electrode 14. The channel stopper electrode 38 extends along the chip edge and surrounds the periphery of the parallel pn layer 3 in a substantially rectangular shape. + The channel stopper electrode 38 is in contact with the drain electrode 15 and is fixed to the same potential as the drain electrode 15.

[0070] Outer p-type region 31 and p + Between the front surface of the semiconductor substrate 40 and the parallel pn layer 3, a predetermined breakdown voltage structure (not shown) such as a field limiting ring (FLR) or a RESURF structure may be disposed between the front surface of the semiconductor substrate 40 and the parallel pn layer 3, and between the front surface of the semiconductor substrate 40 and the parallel pn layer 3. ++ A drain electrode (second electrode) 15 is provided on the entire back surface of the starting mold substrate 41.

[0071] In this embodiment, a semiconductor substrate (semiconductor chip) 40 using silicon (Si) as the semiconductor material is used, but a semiconductor substrate (semiconductor chip) 40 using silicon carbide (SiC) as the semiconductor material may also be used, and a junction termination extension (JTE) structure may be provided in the edge termination region 23 as a voltage-resistant structure.

[0072] The parallel pn layer 3 is formed by alternately and repeatedly arranging n-type column regions (first conductivity type regions) 4 and p-type column regions (second conductivity type regions) 5 adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 40, from the active region 21 to the first and second portions 22a, 22b of the transition region 22 and the edge termination region 23. Each n-type column region 4 and each p-type column region 5 extends linearly from the active region 21 to the first portion 22a of the transition region 22 and the edge termination region 23 in a second direction Y that is parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X, and forms a quadrangular prism that extends linearly in the depth direction Z.

[0073] All of the n-type column regions 4 and p-type column regions 5 are arranged with approximately the same widths W1, W2 and approximately the same repetition pitches P1, P2 in the short direction (first direction X), extend linearly with approximately the same widths W1, W2 from the active region 21 to the first portion 22a of the transition region 22 and the edge termination region 23 in the long direction (second direction Y), and extend linearly with approximately the same widths W1, W2 in the depth direction Z. That is, both the n-type column regions 4 and the p-type column regions 5 have the same stripe pattern in both plan and cross-sectional views.

[0074] Both the n-type column region 4 and the p-type column region 5 are formed by ion implantation of impurities into the non-doped epitaxial layer 43 using a multistage epitaxial method. The multistage epitaxial method is a method in which an epitaxial layer is divided into a plurality of stages and epitaxially grown in multiple stages until it reaches a predetermined thickness, and each time an impurity-implanted region of a predetermined conductivity type is selectively formed in the epitaxial layer by photolithography and ion implantation so as to face an impurity-implanted region of the same conductivity type below in the depth direction Z.

[0075] The parallel pn layer 3 has an n-type impurity concentration distribution (first conductivity type impurity concentration distribution) 51 and a p-type impurity concentration distribution (second conductivity type impurity concentration distribution) 52, in which the impurity concentration is relatively high in a portion (hereinafter referred to as a first parallel pn layer) 3a of the active region 21 excluding a first portion 22a of the transition region 22, the impurity concentration is lower than that of the first parallel pn layer 3a in the transition region 22, and the impurity concentration is relatively low in a portion (hereinafter referred to as a third parallel pn layer) 3c of the edge termination region 23. Within the second portion 22b of the transition region 22, column regions 4, 5 are arranged whose impurity concentration decreases in the first direction X toward the chip end side.

[0076] The n-type impurity concentration distribution 51 and the p-type impurity concentration distribution 52 are formed in each stage of the epitaxial layer 43 that is epitaxially grown in multiple stages. The impurity concentration distribution of each column region 4, 5 in each stage of the epitaxial layer 43 is a Gaussian distribution with the depth of the ion implantation range as its apex. The n-type impurity concentration distribution 51 is formed by connecting the Gaussian distributions of the n-type column regions 4 adjacent to each other in the first direction X. The p-type impurity concentration distribution 52 is formed by connecting the Gaussian distributions of the p-type column regions 5 adjacent to each other in the first direction X.

[0077] The intersection of the n-type impurity concentration distribution 51 and the p-type impurity concentration distribution 52 corresponds to the interface between the adjacent n-type column region 4 and p-type column region 5. The vicinity of the intersection of the n-type impurity concentration distribution 51 and the p-type impurity concentration distribution 52 is almost depleted as electrons in the n-type column region 4 and holes in the p-type column region 5 recombine with each other and disappear. The second parallel pn layer 3b described later forms impurity concentration distributions 51 and 52 in which the difference in impurity concentration between the column regions of the same conductivity type between the first and third parallel pn layers 3a and 3c gradually decreases toward the chip end side.

[0078] Each of the ion implantation masks for forming the n-type column region 4 and the p-type column region 5 has an opening pattern in which the opening width is relatively narrow in the portion where the impurity concentration is to be relatively low. Using this ion implantation mask, impurities of a predetermined conductivity type are ion-implanted at the same dose into the entire surface of the non-doped epitaxial layer 43 to selectively form column regions of the predetermined conductivity type. The n-type column region 4 and the p-type column region 5 have a relatively low effective impurity concentration in the portion where the opening width of the ion implantation mask is relatively narrow.

[0079] The ratio of the relative high and low impurity concentrations in the column region approximately coincides with the relative wide and narrow ratio of the opening width of the ion implantation mask. Therefore, when the impurity concentration in the column region of the first parallel pn layer 3a of the parallel pn layer 3 is set to a reference value (=1x), the impurity concentration in the column region of the second parallel pn layer 3b described below is lowered to 0.75x the reference value, and the impurity concentration in the column region of the third parallel pn layer 3c is lowered to 0.5x the reference value, the ion implantation mask may also have an opening pattern in which the opening widths are set at a ratio of 1:0.75:0.5 at corresponding locations.

[0080] Specifically, in the parallel pn layer 3, the n-type column region 4a (n-type column region 4: first first conductivity type region) and the p-type column region 5a (p-type column region 5: first second conductivity type region) of the first parallel pn layer 3a (a portion of the active region 21 excluding the first portion 22a of the transition region 22) have approximately the same widths W1, W2 and approximately the same impurity concentration. The n-type column region 4a and the p-type column region 5a adjacent to each other are generally charge balanced. The n-type column region 4 and the p-type column region 5 have relatively high impurity concentrations in the n-type column region 4a and the p-type column region 5a, respectively.

[0081] In the parallel pn layer 3, the n of the first and second portions 22a and 22b of the transition region 22 (hereinafter referred to as the second parallel pn layer 3b) - n-type column region 4b (n-type column region 4: second first conductivity type region) and p - The p-type column region 5b (p-type column region 5: second second conductivity type region) has substantially the same width W1, W2 and substantially the same impurity concentration. - Type column regions 4b and p - The charge balance is approximately the same as that of the column region 5b. - Type column regions 4b and p - The n-type column region 5b has a lower impurity concentration than the n-type column region 4a and the p-type column region 5a located on the chip center side of the active region 21, respectively.

[0082] The first portion 22a of the transition region 22 overlaps the entire periphery of the active region 21. Therefore, a first parallel pn layer 3a consisting of an n-type column region 4a and a p-type column region 5a is arranged in the center of the active region 21 (the portion of the active region 21 toward the chip center excluding the first portion 22a of the transition region 22). - Type column regions 4b and p - A second parallel pn layer 3b made of a type column region 5b is disposed. The second parallel pn layer 3b surrounds the periphery of the first parallel pn layer 3a.

[0083] The second portion 22b of the transition region 22 has a n-type impurity layer in which the impurity concentration decreases toward the chip end side in the first direction X. - Type column regions 4b and p - The first portion 22a of the transition region 22 is also provided with an n-type column region 5b. The n-type column region 5b is arranged in the first direction X. - Type column regions 4b and p - The n-type column region 5b may be disposed in the transition region 22. - Type column regions 4b and p - The impurity concentration of each of the mold column regions 5b may be gradually decreased in the first direction X toward the chip end side.

[0084] Among the parallel pn layers 3, the n of the third parallel pn layer 3c (part of the edge termination region 23) -- n-type column region 4c (n-type column region 4: third first conductivity type region) and p -- The p-type column region 5c (p-type column region 5: third second conductivity type region) has substantially the same width W1, W2 and substantially the same impurity concentration. -- Type column regions 4c and p -- The charge balance is approximately the same as that of the column region 5c. -- Type column regions 4c and p -- The type column region 5c is a region including n of the transition region 22. - Type column regions 4b and p - The impurity concentration is lower than that of the mold column region 5b.

[0085] Charge balance means that the charge amount expressed by the product of the carrier concentration (concentration of activated impurities) of the n-type column region 4 and the width W1 is approximately the same as the charge amount expressed by the product of the carrier concentration of the p-type column region 5 and the width W2, and that the charge amounts of the adjacent n-type column region 4 and p-type column region 5 are balanced. Approximately the same impurity concentration (carrier concentration) and approximately the same width mean that the impurity concentration and width are the same within the range including the allowable error due to process variations.

[0086] To form this parallel pn layer 3 by the multistage epitaxial method, an ion implantation mask having openings in portions corresponding to the formation regions of the n-type column regions 4 is used to form an n-type impurity implanted region 44 by ion implantation at the center in the first direction X of the formation region of each n-type column region 4 in each stage of the epitaxial layer 43. An ion implantation mask having openings in portions corresponding to the formation regions of the p-type column regions 5 is used to form a p-type impurity implanted region 45 by ion implantation at the center in the first direction X of the formation region of each p-type column region 5 in each stage of the epitaxial layer 43. Then, a thermal diffusion process is performed to diffuse and activate the impurities in the epitaxial layer 43.

[0087] The n-type impurity implanted region 44 has a widest width Wn1 at a portion 44a in the center of the active region 21, a narrower width Wn2 at a portion 44b in the transition region 22 than at the portion 44a in the center of the active region 21, and a narrowest width Wn3 at a portion 44c in the edge termination region 23. The portions 44a, 44b, and 44c of the n-type impurity implanted region 44 having different widths Wn1, Wn2, and Wn3 are simultaneously formed under the same ion implantation conditions (dose amount, acceleration energy). The centers in the first direction X of the portions 44a, 44b, and 44c of the n-type impurity implanted region 44 that pass through the active region 21 and the transition region 22 and are continuous in the second direction Y are at approximately the same position.

[0088] The p-type impurity implanted region 45 has a width Wp1 that is the widest at a portion 45a in the center of the active region 21 (excluding the first portion 22a of the transition region 22), a width Wp2 that is narrower at a portion 45b of the transition region 22 than the portion 45a in the center of the active region 21, and a width Wp3 that is narrowest at a portion 45c of the edge termination region 23. The portions 45a, 45b, and 45c of the p-type impurity implanted region 45 having different widths Wp1, Wp2, and Wp3 are simultaneously formed under the same ion implantation conditions (dose amount, acceleration energy). The centers in the first direction X of the portions 45a, 45b, and 45c of the p-type impurity implanted region 45 that are continuous in the second direction Y and pass through the active region 21 and the transition region 22 are at approximately the same position.

[0089] Each stage of the parallel pn layer 3 (epitaxial layer 43) before the thermal diffusion process has n-type impurity implanted regions 44 and p-type impurity implanted regions 45 alternately arranged in the first direction X with non-doped regions (regions in which impurities are not ion-implanted and remain as non-doped epitaxial layer 43) interposed therebetween (FIGS. 3A and 3B). The non-doped regions 46 remain in stripes extending in the second direction Y with their widths partially varying. The widths Wn1, Wn2, and Wn3 of the n-type impurity implanted regions 44 and the doses of the n-type impurities and the widths Wp1, Wp2, and Wp3 of the p-type impurity implanted regions 45 and the doses of the p-type impurities are approximately the same in adjacent portions.

[0090] 3A and 3B show the vicinity of a corner (vertex of a rectangle: chip corner) of the semiconductor substrate 40. In FIGS. 3A, 3B, and 4, the portions of the epitaxial layer 43 marked with n and p are the n-type impurity-implanted region 44 and the p-type impurity-implanted region 45, respectively, and the portions marked with neither n nor p are the non-doped region 46. The portions 44a, 44b, and 44c of the n-type impurity-implanted region 44 have substantially rectangular planar shapes extending in the second direction Y with different widths Wn1, Wn2, and Wn3, respectively. The portions 45a, 45b, and 45c of the p-type impurity-implanted region 45 have substantially rectangular planar shapes extending in the second direction Y with different widths Wp1, Wp2, and Wp3, respectively (FIG. 3A).

[0091] The portions 44b, 45b of the transition region 22 of the n-type impurity implanted region 44 and the p-type impurity implanted region 45 may have a substantially rectangular shape at their longitudinal ends on the active region 21 side, and may have a tapered shape (trapezoidal shape) with the widths Wn2, Wp2 narrowing toward the edge termination region 23 side only at their longitudinal ends on the edge termination region 23 side (FIG. 3B). By tapering the longitudinal ends on the edge termination region 23 side of the portions 44b, 45b of the transition region 22 of the n-type impurity implanted region 44 and the p-type impurity implanted region 45, the impurity concentrations (charge amounts) of the adjacent n-type column region 4 and p-type column region 5 change gradually in the longitudinal direction, so that the adjacent n-type column region 4 and p-type column region 5 are less likely to become charge unbalanced, and the occurrence of electric field concentration can be suppressed.

[0092] The length in the longitudinal direction (second direction Y) of the n-type impurity implanted region 44 and the p-type impurity implanted region 45 that terminate near the corner of the semiconductor substrate 40 is defined as p + Alternatively, the length of the n-type column region 4 and the p-type column region 5 that terminate near the corner of the semiconductor substrate 40 may be relatively short depending on the curvature of the corner of the n-type channel stopper region 37. In this case, the length of the n-type column region 4 and the p-type column region 5 that terminate near the corner of the semiconductor substrate 40 may be set to p + The length of the n-type channel stopper region 37 becomes relatively shorter in accordance with the curvature of the corner of the n-type channel stopper region 37. This makes it possible to adjust the amount of charge in the n-type column region 4 and the amount of charge in the p-type column region 5 near the corner of the semiconductor substrate 40, thereby suppressing electric field concentration near the corner of the semiconductor substrate 40.

[0093] By a subsequent thermal diffusion process, the n-type impurity implanted regions 44 and the p-type impurity implanted regions 45 in each stage of the epitaxial layer 43 are diffused into the adjacent non-doped regions 46 and reach an equilibrium state. The n-type impurity implanted regions 44 in each stage of the epitaxial layer 43 are connected to each other in the depth direction Z. The p-type impurity implanted regions 45 in each stage of the epitaxial layer 43 are connected to each other in the depth direction Z. As a result, the n-type impurity implanted regions 44 and the p-type impurity implanted regions 45 in each stage of the epitaxial layer 43 become n-type column regions 4 and p-type column regions 5 having approximately the same widths W1 and W2, respectively.

[0094] The mutually adjacent n-type column regions 4 and p-type column regions 5 are generally charge balanced throughout the parallel pn layer 3. By providing the non-doped region 46 between the n-type impurity implanted region 44 and the p-type impurity implanted region 45, it is possible to prevent the width of the nearly depleted region formed at the interface between the n-type column region 4 and the p-type column region 5 in the first direction X from becoming too wide. As a result, in the parallel pn layer 3 formed of the n-type column region 4 and the p-type column region 5, an n-type impurity concentration distribution 51 and a p-type impurity concentration distribution 52 are formed which are relatively high in the active region 21, decrease in the transition region 22 from the chip center toward the chip end, and are relatively low in the edge termination region 23.

[0095] Although not particularly limited, for example, when the semiconductor device 10 (SJ-MOSFET) according to the embodiment has a breakdown voltage of 650V class, the dimensions and impurity concentrations of each part are as follows: + The impurity concentration of the channel stopper region 37 is 8.0×10 19 / cm 3 The thickness of the parallel pn layer 3 is 40.0 μm. The widths W1, W2 of the n-type column regions 4 and p-type column regions 5 of the parallel pn layer 3 are the same in all of the active region 21, the transition region 22 and the edge termination region 23, and are 6.0 μm (repeat pitches P1, P2 are 12.0 μm), preferably 4.0 μm (repeat pitches P1, P2 are 8.0 μm).

[0096] When the n-type column region 4 and the p-type column region 5 of the parallel pn layer 3 are formed by ion implantation of phosphorus (P) and boron (B), respectively, the phosphorus concentration of the n-type column region 4a of the first parallel pn layer 3a is set to 1.0×10 16 / cm 3 is used as a reference value, and the boron concentration in the p-type column region 5a is set to 1.0×10 16 / cm 3 The n of the second parallel pn layer 3b is set as the reference value. - Phosphorus concentration and p - The boron concentration in the type column region 5b is set to 3 / 4 of the reference value, and the n-- Phosphorus concentration and p -- The boron concentration in the mold column region 5c is set to 1 / 2 of a reference value.The width d of the first portion 22a of the transition region 22 is 5 μm or more and 50 μm or less.

[0097] The operation of the semiconductor device 10 according to the embodiment will be described. FIG. 5 is a characteristic diagram showing the results of simulating the electric field strength during reverse recovery of the body diodes of the example and the reference example. FIG. 6 is an explanatory diagram showing a schematic diagram of the state during reverse recovery of the body diode of the semiconductor device according to the embodiment. In FIG. 5, the example corresponds to the semiconductor device 10 according to the embodiment (see FIG. 1), and the reference example corresponds to the semiconductor device 110 of the reference example (see FIG. 7). The state during reverse recovery of the body diode of the semiconductor device 110 of the reference example is shown in FIG. 7.

[0098] The upper diagram of FIG. 5 shows the upper surface (n + 5 is a schematic diagram showing a cross-sectional structure in the vicinity of the surface of the n-type impurity region 7 on the side of the n-type source region 7. In the schematic diagram of Fig. 5, a portion with a relatively high impurity concentration in the vicinity of the apex (depth position of the range of ion implantation of the n-type impurity) of the Gaussian distribution of the n-type impurity concentration distribution 51 due to the n-type column region 4 of the parallel pn layer 3 and a portion with a relatively high impurity concentration in the vicinity of the apex (depth position of the range of ion implantation of the p-type impurity) of the Gaussian distribution of the p-type impurity concentration distribution 52 due to the p-type column region 5 of the parallel pn layer 3 are shown by different hatchings.

[0099] The lower diagram of FIG. 5 is a characteristic diagram showing the results of simulating the electric field intensity distribution at the cutting line C-C' of the schematic diagram of FIG. 5. For comparison, the characteristic diagram of FIG. 5 also shows the results of simulating the electric field intensity distribution of a reference example under the same conditions as the embodiment. The embodiment has a simplified first portion 22a of the transition region 22 and includes a smaller number of unit cells than in FIG. 2. The horizontal axis of the characteristic diagram of FIG. 5 corresponds to the horizontal position in the schematic diagram of FIG. 5. The vertical axis of the characteristic diagram of FIG. 5 is the relative ratio between the electric field intensity of the embodiment and the electric field intensity of the reference example.

[0100] In the semiconductor device 10 according to the embodiment, when a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 12 in a state where a positive voltage with respect to the source electrode 14 is applied to the drain electrode 15, the n + A channel (n-type inversion layer) is formed in the region between the n-type source region 7 and the JFET region 9. + The n-type drain region 1 passes through the n-type buffer region 2, the n-type column region 4, and the channel. + A drift current (main current) flows toward the type source region 7, turning the MOSFET on.

[0101] On the other hand, when a positive voltage with respect to the source electrode 14 is applied to the drain electrode 15, and the voltage applied to the gate electrode 12 is less than the gate threshold voltage, the p-type base region 6 and the p-type column region 5 and the p-type column region 4 are reverse biased, so that the MOSFET remains in the off state. A depletion layer spreads from the p-n junction in the vertical direction (toward the source electrode 14 and the drain electrode 15), ensuring a predetermined breakdown voltage in the active region 21. A depletion layer also spreads laterally toward the chip end, ensuring a predetermined breakdown voltage in the edge termination region 23.

[0102] The impurity concentrations of n-type column region 4 and p-type column region 5 in edge termination region 23 are set relatively low, and the breakdown voltage of edge termination region 23 is set higher than the breakdown voltage of active region 21. Even if the impurity concentrations of n-type column region 4 and p-type column region 5 in edge termination region 23 are set relatively low, first portion 22a of transition region 22 is disposed so as to overlap the entire outer periphery of active region 21, thereby suppressing electric field concentration at the boundary between active region 21 and edge termination region 23 and at second portion 22b of transition region 22.

[0103] This is because the impurity concentrations of n-type column region 4 and p-type column region 5 in first portion 22a of transition region 22 decrease from the chip center toward the chip end. Therefore, even if there is a large difference in impurity concentration between the column regions of the same conductivity type between active region 21 and edge termination region 23, the impurity concentration gradient at the boundary between active region 21 and edge termination region 23 and in second portion 22b of transition region 22 becomes gentle, and charge imbalance is unlikely to occur between adjacent n-type column region 4 and p-type column region 5 in this portion.

[0104] This makes it possible to suppress electric field concentration at the boundary between the active region 21 and the edge termination region 23 and at the second portion 22b of the transition region 22, even if the charge amount in the column regions 4 and 5 is biased due to process variations or the like. The present inventors have confirmed that by arranging the first portion 22a of the transition region 22, the electric field strength at the pn junction between the n-type column region 4 and the p-type column region 5 near the boundary between the active region 21 and the edge termination region 23 (multiple vertices D1 of the electric field strength distribution in the embodiment of FIG. 5) becomes smaller than the electric field strength at the pn junction between the n-type column region 4 and the p-type column region 5 on the chip center side of the active region 21.

[0105] In addition, during reverse recovery of the body diode of the MOSFET, the n -- The holes accumulated in the type column region 4c become a recovery (reverse recovery) current Ir and flow into the active region 21. At this time, even if an avalanche breakdown occurs in the edge termination region 23 and the recovery current Ir increases, the first portion 22a of the transition region 22 is arranged so as to overlap the entire outer periphery of the active region 21, thereby making it possible to suppress the concentration of a large current (recovery current Ir) in the active region 21 (FIG. 6).

[0106] The transition region 22 has a relatively low impurity concentration in the column regions 4 and 5 and has a high resistance compared to the active region 21. Furthermore, the transition region 22 has a relatively wide width because the first portion 22a overlaps the entire outer periphery of the active region 21. Since the recovery current Ir can be dispersed by the high resistance path I1 passing through the source contact of the transition region 22 toward the source electrode 14, the recovery current Ir flowing through the low resistance path I2 passing through the p-type base region 6 in the center of the active region 21 toward the source electrode 14 can be reduced.

[0107] In contrast, in semiconductor device 110 of the reference example (see FIG. 7), transition region 122 having a relatively narrow width is only partially disposed between active region 121 and edge termination region 123. For this reason, if the impurity concentrations of n-type column region 104 and p-type column region 105 in edge termination region 123 are made relatively low, a steep impurity concentration gradient occurs near the boundary between active region 121 and edge termination region 123, and charge imbalance is likely to occur between n-type column region 104 and p-type column region 105 adjacent to each other in this portion.

[0108] Therefore, when the charge amount of the column regions 104, 105 is biased due to process variations or the like, an electric field is locally concentrated near the boundary between the active region 121 and the edge termination region 123. The inventors have confirmed that the electric field strength at the pn junction between the n-type column region 104 and the p-type column region 105 near the boundary between the active region 121 and the edge termination region 123 (multiple vertices D2 of the electric field strength distribution in the reference example of FIG. 5) shows approximately the same maximum electric field strength as the pn junction between the n-type column region 104 and the p-type column region 105 on the chip center side of the active region 121.

[0109] Furthermore, in semiconductor device 110 of the reference example, recovery current Ir of the body diode is likely to flow into active region 121, which has a lower resistance than transition region 122 and edge termination region 123. When avalanche breakdown occurs in edge termination region 123 and recovery current Ir increases, a large current (recovery current Ir) is concentrated in high-resistance path I101 that passes through the source contact of transition region 122 toward source electrode 114, and in low-resistance path I102 that passes through p-type base region 106 at the outer periphery of active region 121 toward source electrode 114.

[0110] FIG. 10A is a plan view showing another example of the layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate (part 1). In FIG. 10A, the outer periphery of the active region 21 and the inner periphery of the edge termination region 23 are indicated by rough dashed lines, as in FIG. 1, and the inner periphery of the transition region 22 is indicated by fine dashed lines. FIG. 10A differs from FIG. 1 in that the gate pad 16 is provided so as to contact the corner (vertex) of the gate metal wiring layer 35. In this case, for example, the gate pad 16 directly contacts the corresponding corner and two sides of the gate metal wiring layer 35 at one corner and two sides sharing the corner, and faces the source electrode 14 at the remaining two sides with a predetermined gap therebetween. The gate metal wiring layer 35 and the gate pad 16 are formed, for example, at the same time as the source electrode 14. In addition, the gate metal wiring layer 35 and the gate pad 16 are provided so as to be electrically insulated from the source electrode 14. Even if the gate pad 16 is provided in contact with the corner of the gate metal wiring layer 35, the same effect as that shown in FIG. 1 can be obtained.

[0111] FIG. 10B is a plan view showing another example of the layout of the semiconductor device according to the embodiment viewed from the front surface side of the semiconductor substrate (part 2). In FIG. 10B, the outer periphery of the active region 21 and the inner periphery of the edge termination region 23 are indicated by rough dashed lines, as in FIG. 1, and the inner periphery of the transition region 22 is indicated by fine dashed lines. FIG. 10B differs from FIG. 1 in that the gate pad 16 is not in contact with the gate metal wiring layer 35, and the gate pad 16 and the gate metal wiring layer 35 are electrically connected via the gate metal wiring layer extension 39 extending on the insulating layer 33. In this case, for example, the gate pad 16 faces the source electrode 14 at a predetermined interval on almost the entire periphery except for the connection portion with the gate metal wiring layer extension 39. The gate metal wiring layer 35, the gate metal wiring layer extension 39, and the gate pad 16 are formed, for example, simultaneously with the source electrode 14. Furthermore, the gate metal wiring layer 35, the gate metal wiring layer extension 39, and the gate pad 16 are provided so as to be electrically insulated from the source electrode 14. Even if the gate pad 16 is provided so as to be connected to the gate metal wiring layer 35 via the gate metal wiring extension 39, the same effect as that of FIG.

[0112] As described above, according to the embodiment, the impurity concentration of the column region constituting the parallel pn layer is relatively high in the center of the active region, is lower in the first portion of the transition region than in the center of the active region, and is relatively low in the edge termination region. The first portion of the transition region is disposed so as to overlap the outer periphery of the active region, and includes at least a pair of adjacent n-type and p-type column regions of the active region.

[0113] Even if there is a large difference in impurity concentration between the column regions of the same conductivity type of the parallel pn layer between the active region and the edge termination region, the impurity concentration gradient becomes gentle in the transition region, and charge imbalance is unlikely to occur between the adjacent n-type column region and p-type column region in this portion. Therefore, even if there is a bias in the charge amount in the column region due to process variation or the like, electric field concentration near the boundary between the active region and the edge termination region is suppressed, and a decrease in breakdown voltage can be suppressed.

[0114] In addition, the impurity concentrations of the n-type column region and the p-type column region of the edge termination region can be appropriately reduced, which makes it easier to design the edge termination region and prevents punch-through of the depletion layer that spreads laterally in the edge termination region when the MOSFET is off, thereby ensuring a predetermined breakdown voltage. This makes it possible to suppress localized electric field concentration in the edge termination region and prevent the destruction of the semiconductor device due to avalanche breakdown. In addition, it is possible to suppress an increase in the size of the semiconductor device.

[0115] The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, in the above-mentioned embodiments, the dimensions and impurity concentrations of each part are variously set according to the required specifications. Also, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0116] The present invention is directed to a planar gate MOSFET with an SJ structure in which the drift layer is a parallel pn layer 3 from the active region 21 to the transition region 22 and edge termination region 23 of a semiconductor substrate (semiconductor chip) 40 made of silicon (Si) as a semiconductor material, but a trench gate MOSFET may also be used. Silicon carbide (SiC), gallium nitride (GaN), or the like may also be used as the semiconductor material of the semiconductor substrate. [Industrial Applicability]

[0117] As described above, the semiconductor device according to the present invention is useful as a semiconductor device for which emphasis is placed on voltage resistance characteristics, and is particularly suited to semiconductor devices for automotive applications (on-board applications). [Explanation of symbols]

[0118] 1,101 n ++ Type drain region 2,102 n-type buffer region 3,3a,3b,3c,103,103a,103b,103c, parallel pn layer 4,4a,4b,4c,104,104a,104b,104c n-type column area 5,5a,5b,5c,105,105a,105b,105c p-type column area 6,106 p-type base region 7,107 n + Type Source Area 8,108 p + Mold Contact Area 9 JFET area 10,110 Semiconductor equipment 11,111 Gate insulating film 12,112 Gate electrode 13,113 Interlayer insulating film 13a, 13b Contact holes 14,114 Source electrode 15,115 Drain electrode 16 Gate Pad 21,121 active area 22,122 transition region 22a First part of the transition region 22b Second part of transition region 23,123 Edge Termination Area 31,131,132 outer p-type region 32 Perimeter p + Mold Contact Area 33,133 Insulating layer 33a Contact hole in insulating layer 34 Gate polysilicon wiring layer 35,135 Gate metal wiring layer 36 n-type region 37-type channel stopper area 38 Channel stopper electrode 39 Gate metal wiring layer extension 40,140 Semiconductor substrate 41,141 n ++ Starting substrate 42,142 n-type epitaxial layer 43,143 Epitaxial layer 44, 44a, 44b, 44c, 144, 144a, 144b, 144c n-type impurity implanted region 45, 45a, 45b, 45c, 145, 145a, 145b, 145c p-type impurity implanted region 46,146 Non-doped region 51,151 n-type impurity concentration distribution 52,152 p-type impurity concentration distribution d Width of the first part of the transition region I1, I2, I101, I102 Recovery current paths Ir Recovery current P1, P2, P101, P102 Column area repeat pitch W1,W2,W101,W102 Column area width Wn1, Wn2, Wn3, Wn101, Wn102, Wn103 Width of n-type impurity implanted region Wp1, Wp2, Wp3, Wp101, Wp102, Wp103 Width of p-type impurity implanted region X: A first direction parallel to the front surface of the semiconductor substrate Y: A second direction that is parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z depth direction

Claims

1. an active region provided in a semiconductor substrate; a termination region disposed outside the active region and surrounding the active region; a transition region between the active region and the termination region; a parallel pn layer in which first conductivity type regions and second conductivity type regions are alternately and repeatedly arranged adjacent to each other in a first direction parallel to a front surface of the semiconductor substrate, the parallel pn layer being provided inside the semiconductor substrate in the active region, the transition region and the termination region; an element structure provided in the active region between a front surface of the semiconductor substrate and the parallel pn layer; a first electrode provided on a front surface of the semiconductor substrate and electrically connected to the element structure; A second electrode provided on a rear surface of the semiconductor substrate; Equipped with the transition region is disposed to overlap an outer periphery of the active region and includes at least a pair of the first conductivity type region and the second conductivity type region adjacent to each other of the active region; The parallel pn layer is a first conductivity type impurity concentration distribution in which an impurity concentration is relatively high in a central portion of the active region that is located on the inner side than the transition region, and the impurity concentration decreases from the active region side toward the termination region side in the transition region, and the impurity concentration is relatively low in the termination region; a second conductivity type impurity concentration distribution in which an impurity concentration is relatively high in the central portion of the active region, and the impurity concentration decreases from the active region side to the termination region side in the transition region, and the impurity concentration is relatively low in the termination region.

2. 2. The semiconductor device according to claim 1, wherein the transition region overlaps the active region with a width of 5 μm to 50 μm inward from the outer periphery of the active region.

3. The first conductivity type region is a first first conductivity type region disposed in the active region; a second first conductivity type region disposed in the transition region and having a lower impurity concentration than the first first conductivity type region; a third first conductivity type region disposed in the termination region and having an impurity concentration lower than that of the second first conductivity type region; The second conductivity type region is a first second conductivity type region disposed in the active region; a second second conductivity type region disposed in the transition region and having a lower impurity concentration than the first second conductivity type region; 2. The semiconductor device according to claim 1, further comprising: a third second-conductivity type region disposed in the termination region and having an impurity concentration lower than that of the second second-conductivity type region.

4. the width of the first conductivity type region is equal in the active region, the transition region and the termination region; the width of the second conductivity type region is equal in the active region, the transition region and the termination region; 2. The semiconductor device according to claim 1, wherein the first conductivity type region and the second conductivity type region adjacent to each other are charge balanced.

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