Display device and mother board for display device

Abstract

To suppress decrease in reliability.SOLUTION: In an embodiment, a display device includes an organic insulating layer disposed in a display region to display images and a peripheral region outside the display region, a lower electrode disposed on the organic insulating layer in the display region, an inorganic insulating layer disposed on the organic insulating layer and covering the peripheral part of the lower electrode, an organic layer disposed on the lower electrode and including a light-emitting layer, an upper electrode disposed on the organic layer, and a plurality of peripheral partition walls disposed in the peripheral region. Each of the peripheral partition walls includes a first lower part existing on the inorganic insulating layer, and a first upper part existing on the first lower part and projecting from the side surface of the first lower part. The organic insulating layer includes a fall part along the outer edge of the substrate in the peripheral region. The inorganic insulating layer includes a loop-shaped groove surrounding the display region in the peripheral region. The peripheral partition walls include a pair of first partition walls facing each other with the groove therebetween.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] An embodiment of the present invention relates to a display device and a mother substrate for the display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer that covers the lower electrode, and an upper electrode that covers the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to a light-emitting layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a motherboard for the display device, which are capable of suppressing a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, the display device comprises: a substrate; an organic insulating layer disposed above the substrate over a display region for displaying an image and a peripheral region outside the display region; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral region, each of the plurality of peripheral partitions having a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a missing portion along an outer edge of the substrate in the peripheral region, the inorganic insulating layer having a loop-shaped groove surrounding the display region in the peripheral region, and the plurality of peripheral partitions including a pair of first partitions facing each other across the groove.

[0006] According to one embodiment, the display device comprises: a substrate; an organic insulating layer disposed above the substrate over a display region for displaying an image and a peripheral region outside the display region; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral region, each of the plurality of peripheral partitions having a first lower portion and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a missing portion along an outer edge of the substrate in the peripheral region, and the plurality of peripheral partitions including a second partition disposed in the missing portion, the second partition being disposed along a corner portion of the outer edge of the organic insulating layer and being formed in an L-shape in a planar view.

[0007] According to one embodiment, the display device comprises: a substrate; an organic insulating layer disposed above the substrate over a display region for displaying an image and a peripheral region outside the display region; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral region, each of the plurality of peripheral partitions having a first lower portion and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a missing portion along an outer edge of the substrate in the peripheral region, the outer edge of the organic insulating layer including a rounded corner portion, and a radius of curvature of the rounded corner portion being equal to or greater than the width of the missing portion.

[0008] According to one embodiment, a mother substrate for a display device includes: a display region for displaying an image and a peripheral region outside the display region; a margin portion outside the panel region; and an organic insulating layer disposed across the panel region and the margin portion; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral region, each of the plurality of peripheral partitions having a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the inorganic insulating layer having a loop-shaped first groove surrounding the display region in the peripheral region, and the plurality of peripheral partitions including a pair of first partitions facing each other across the first groove.

[0009] According to one embodiment, a mother substrate for a display device includes: a panel unit having a display area for displaying an image and a peripheral area outside the display area, a margin area outside the panel unit, and an organic insulating layer arranged across the panel unit and the margin area, a lower electrode arranged on the organic insulating layer in the display area, an inorganic insulating layer arranged on the organic insulating layer and covering a peripheral area of ​​the lower electrode, an organic layer arranged on the lower electrode and including a light-emitting layer, an upper electrode arranged on the organic layer, and a plurality of peripheral partitions arranged in the peripheral area, each of the plurality of peripheral partitions having a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a missing portion that follows an outline of the panel unit, and the plurality of peripheral partitions including a second partition arranged in the missing portion, the second partition arranged along a corner portion of an outer edge of the organic insulating layer and formed in an L-shape in a planar view.

[0010] According to one embodiment, a mother substrate for a display device includes: a panel unit having a display area for displaying an image and a peripheral area outside the display area, a margin area outside the panel unit, and an organic insulating layer arranged across the panel unit and the margin area, and in the display area, a lower electrode arranged on the organic insulating layer, an inorganic insulating layer arranged on the organic insulating layer and covering a peripheral area of ​​the lower electrode, an organic layer arranged on the lower electrode and including a light-emitting layer, an upper electrode arranged on the organic layer, and a plurality of peripheral partitions arranged in the peripheral area, each of the plurality of peripheral partitions having a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a missing portion that follows the outline of the panel unit, and an outer edge of the organic insulating layer includes a rounded corner portion, and a radius of curvature of the rounded corner portion is equal to or greater than half the width of the missing portion. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Diagram 2]FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4] FIG. 4 is a diagram for explaining a manufacturing method of the display device DSP. [Diagram 5] FIG. 5 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6] FIG. 6 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 7] FIG. 7 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 8] FIG. 8 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 10] FIG. 10 is a plan view showing an example of a mother substrate 100 for a display device. [Figure 11] FIG. 11 is a plan view showing an example of the configuration of the region 100A of the display device mother substrate 100 shown in FIG. [Figure 12] FIG. 12 is a plan view showing an example of the configuration of the region 100B shown in FIG. [Figure 13] FIG. 13 is a plan view showing the display panel PNL cut along the cut line CL shown in FIG. [Figure 14] FIG. 14 is a cross-sectional view showing an example of the configuration of a mother substrate 100 for a display device. [Figure 15] FIG. 15 is a cross-sectional view showing another example of the configuration of the mother substrate 100 for a display device. [Figure 16] FIG. 16 is a cross-sectional view showing another example of the configuration of the mother substrate 100 for a display device. [Figure 17] FIG. 17 is an enlarged cross-sectional view of a region including the groove 5G. [Figure 18] FIG. 18 is a cross-sectional view for explaining a state in which the laminated film FL1 is formed in a region including the missing portion G shown in FIG. [Figure 19] FIG. 19 is a cross-sectional view for explaining a state in which the laminated film FL1 is formed in a region including the groove 5G shown in FIG. [Figure 20] FIG. 20 is a plan view showing another configuration example of the region 100B shown in FIG. [Figure 21] FIG. 21 is a plan view showing the display panel PNL cut along the cut line CL shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view showing an example of the configuration of a mother substrate 100 for a display device. [Diagram 23] FIG. 23 is a cross-sectional view showing another example of the configuration of the mother substrate 100 for a display device. [Figure 24] FIG. 24 is a cross-sectional view showing another example of the configuration of the mother substrate 100 for a display device. [Diagram 25] FIG. 25 is a diagram for explaining a problem that may occur if the peripheral partition 9A is not provided. [Figure 26] FIG. 26 is a plan view showing another configuration example of the region 100A of the display device mother substrate 100 shown in FIG. [Figure 27] FIG. 27 is a plan view showing an example of the configuration of the region 100B shown in FIG. [Figure 28] FIG. 28 is a plan view showing the display panel PNL cut along the cut line CL shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0013] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0014] The display device according to this embodiment is an organic electroluminescence display device having an organic light emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0015] FIG. 1 is a diagram showing an example of the configuration of a display device DSP.

[0016] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0017] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0018] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, the second color, and the third color are different from each other. The pixel PX may include a subpixel SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0019] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0020] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0021] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0022] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0023] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each of the terminals TE extends in a second direction Y, but this is not limited thereto. For example, some of the plurality of terminals TE may extend in an oblique direction. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0024] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0025] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0026] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0027] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0028] In the display region DA, an inorganic insulating layer 5 and a partition wall 6 are disposed. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0029] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the inorganic insulating layer 5. The partition wall 6 is conductive and is electrically connected to the terminal TE of the common potential among the multiple terminals TE shown in FIG. 1.

[0030] The sub-pixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0031] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a planar view. The periphery of each of the organic layer OR1 and the upper electrode UE1 overlaps the inorganic insulating layer 5 in a planar view. The organic layer OR1 includes a light-emitting layer that emits light in, for example, a blue wavelength region.

[0032] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a planar view. The periphery of each of the organic layer OR2 and the upper electrode UE2 overlaps the inorganic insulating layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0033] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the opening AP3. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a planar view. The periphery of each of the organic layer OR3 and the upper electrode UE3 overlaps the inorganic insulating layer 5 in a planar view. The organic layer OR3 includes a light-emitting layer that emits light in, for example, a red wavelength region.

[0034] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes illustrated in the drawings do not necessarily reflect the exact shapes.

[0035] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or a common electrode, and are in contact with the partition walls 6.

[0036] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the subpixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the subpixel SP3.

[0037] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from one another. The area of ​​the openings AP1 is larger than the area of ​​the openings AP2, and the area of ​​the openings AP2 is larger than the area of ​​the openings AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0038] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0039] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Fig. 1, and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens unevenness caused by the circuit layer 11.

[0040] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the inorganic insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. The contact holes in the insulating layer 12 are omitted in FIG. 3.

[0041] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0042] In the illustrated example, the lower portion 61 has a first conductive layer 63 disposed on the inorganic insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed to be thinner than the second conductive layer 64. In addition, in the illustrated example, both ends of the first conductive layer 63 protrude from the side surfaces of the second conductive layer 64. The upper portion 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both end portions of the first thin film 65 and the second thin film 66 protrude from the side surfaces of the second conductive layer 64.

[0043] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower portion 61.

[0044] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower portion 61.

[0045] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower portion 61.

[0046] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. The cap layers CP1, CP2, and CP3 may be omitted.

[0047] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0048] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3.

[0049] In the illustrated example, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located on the partition wall 6 around the subpixel SP1. These parts are separated from parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located in the aperture AP1 (parts constituting the display element DE1).

[0050] Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located on the partition 6 surrounding the subpixel SP2, and these portions are spaced apart from portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 that are located in the opening AP2 (portions that constitute the display element DE2).

[0051] Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located on the partition 6 surrounding the subpixel SP3, and these portions are spaced apart from portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 that are located in the opening AP3 (portions that constitute the display element DE3).

[0052] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 is referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 is referred to as a laminate film FL3.

[0053] Ends of the sealing layers SE1, SE2, and SE3 and ends of the stacked films FL1, FL2, and FL3 are located on the partition wall 6. In the illustrated example, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0054] The partition 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0055] The inorganic insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0056] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0057] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The first thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0058] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers. The lower transparent layer functions as an adhesive layer that adheres to the insulating layer 12.

[0059] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in a blue wavelength range, the emitting layer EM2 is formed of a material that emits light in a green wavelength range, and the emitting layer EM3 is formed of a material that emits light in a red wavelength range. In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers, such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0060] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0061] The cap layers CP1, CP2, and CP3 are multilayer structures made up of a plurality of thin films, all of which are transparent and have different refractive indices.

[0062] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are disposed across the display area DA and the peripheral area SA.

[0063] Next, a method for manufacturing the display device DSP will be described. Note that in each drawing for explaining the manufacturing method, illustration of the part below the insulating layer 12 is omitted.

[0064] First, a circuit layer 11 and an insulating layer 12 are formed on a substrate 10 across the display area DA and the peripheral area SA, and then, as shown in FIG. 4, a lower electrode LE1 of subpixel SP1, a lower electrode LE2 of subpixel SP2, and a lower electrode LE3 of subpixel SP3 are formed on the insulating layer 12. Thereafter, an inorganic insulating layer 5 is formed to cover the peripheries of the lower electrodes LE1, LE2, and LE3. The inorganic insulating layer 5 is made of silicon oxide, silicon nitride, silicon oxynitride, or the like. Thereafter, a partition wall 6 is formed having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61. The first conductive layer 63 of the lower portion 61 and the upper portion 62 protrude from a side surface of the second conductive layer 64 of the lower portion 61. The first conductive layer 63 is formed of a conductive material such as a titanium-based material, and the second conductive layer 64 is formed of a conductive material such as an aluminum-based material. The step of forming the openings AP1, AP2, and AP3 in the inorganic insulating layer 5 may be performed before or after the partition wall 6 is formed.

[0065] Next, the display element DE1 is formed.

[0066] First, as shown in FIG. 5, a laminated film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The process of forming the laminated film FL1 includes a process of forming an organic layer OR1 that contacts the lower electrode LE1 at the opening AP1, a process of forming an upper electrode UE1 that covers the organic layer OR1 and contacts the lower portion 61 of the partition wall 6, and a process of forming a cap layer CP1 located on the upper electrode UE1. The process of forming the organic layer OR1 also includes a process of forming a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by deposition using the partition wall 6 as a mask. The laminated film FL1 is divided into a plurality of parts by the overhanging partition wall 6. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0067] Then, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminated film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each of the divided portions of the laminated film FL1 and the partition walls 6.

[0068] 6, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps the sub-pixel SP1 and a part of the partition wall 6 around it.

[0069] 7, etching is performed using the resist RS as a mask to sequentially remove the sealing layer SE1 and stacked film FL1 exposed from the resist RS. In this etching, after removing the sealing layer SE1 exposed from the resist RS, the cap layer CP1 exposed from the sealing layer SE1 is removed, and further, after removing the upper electrode UE1 exposed from the cap layer CP1, the organic layer OR1 exposed from the upper electrode UE1 is removed. As a result, the lower electrode LE2 of the subpixel SP2 and the lower electrode LE3 of the subpixel SP3 are exposed. Thereafter, the resist RS is removed, thereby forming a display element DE1 in the subpixel SP1.

[0070] Next, as shown in FIG. 8, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as that for forming the display element DE1. That is, an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are formed in this order on the lower electrode LE2 to form a laminated film FL2. Then, a sealing layer SE2 is formed on the laminated film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. As a result, a display element DE2 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed.

[0071] Next, as shown in FIG. 9, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are formed in this order on the lower electrode LE3 to form a laminated film FL3. Then, a sealing layer SE3 is formed on the laminated film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. As a result, a display element DE3 is formed in the subpixel SP3.

[0072] Thereafter, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in Fig. 3 are formed in this order, thereby completing the display device DSP.

[0073] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order of formation of display elements DE1, DE2, and DE3 is not limited to this example.

[0074] Next, a display device mother substrate 100 for manufacturing a plurality of display devices DSPs at once will be described.

[0075] FIG. 10 is a plan view showing an example of a mother substrate 100 for a display device.

[0076] The display device mother substrate 100 includes a plurality of panel portions PP and blank portions MP on the outer side of the panel portions PP on a large substrate 10. The large substrate 10 is formed, for example, in a rectangular shape. The plurality of panel portions PP are arranged in a matrix in a first direction X and a second direction Y. Each of the panel portions PP is taken out by cutting the display device mother substrate 100 along a cut line. Each of the taken out panel portions PP corresponds to the display panel PNL shown in FIG. 1.

[0077] FIG. 11 is a plan view showing an example of the configuration of the region 100A of the display device mother substrate 100 shown in FIG.

[0078] The region 100A includes one panel portion PP. Cut lines CL shown by dashed lines in the figure extend, for example, along the first direction X and the second direction Y. These cut lines CL may form the outline of the display panel PNL shown in Fig. 1. Each panel portion PP includes a display area DA and a peripheral area SA.

[0079] The organic insulating layer IL includes at least the insulating layer 12 shown in FIG. 3. The organic insulating layer IL is disposed on each of the panel portions PP and also on the marginal portion MP. The organic insulating layer IL has a missing portion G that follows the outer shape of the panel portion PP. The cut line CL overlaps the missing portion G. The missing portion G is a region that penetrates the organic insulating layer IL so that the base is exposed, and is formed as a lattice-shaped groove that surrounds each of the panel portions PP. In the illustrated example, the missing portion G extends in the first direction X and the second direction Y. The missing portion G also has an end portion GE located in the marginal portion MP.

[0080] Focusing on one panel portion PP, the missing portion G is formed in a loop shape surrounding the panel portion PP. In the panel portion PP, the display area DA overlaps the island-shaped organic insulating layer IL. In addition, a part of the peripheral area SA also overlaps the organic insulating layer IL.

[0081] The inorganic insulating layer 5 has a loop-shaped groove (first groove) 5G surrounding the display area DA in the peripheral area SA of the panel portion PP. The groove 5G is formed between the display area DA and the missing portion G. The inorganic insulating layer 5 also has a groove (second groove) 5GA surrounding the end portion GE of the missing portion G in the margin portion MP. The groove 5G and the groove 5GA are areas that penetrate the inorganic insulating layer 5 so as to expose the base (the organic insulating layer IL). The missing portion G of the organic insulating layer IL is located between the groove 5G and the groove 5GA.

[0082] The portion of the inorganic insulating layer 5 that overlaps the display area DA is separated from the portion between the groove 5G and the missing portion G, or the portion between the groove 5G and the groove 5GA. Moreover, the portion of the inorganic insulating layer 5 between the groove 5G and the groove 5GA is separated from the portion outside the groove 5GA.

[0083] FIG. 12 is a plan view showing an example of the configuration of the region 100B shown in FIG.

[0084] The region 100B includes an intersection of a cut line CL extending in a first direction X and a cut line CL extending in a second direction Y.

[0085] The metal layers MT are disposed in the missing portion G. At the intersections, the four metal layers MT are spaced apart from one another and are formed in an L-shape along the cut lines CL. The cut lines CL extending in the first direction X are positioned between two metal layers MT adjacent to one another in the second direction Y. The cut lines CL extending in the second direction Y are positioned between two metal layers MT adjacent to one another in the first direction X. A cross-shaped space is formed between the four metal layers MT. These four metal layers MT function as, for example, alignment marks for aligning the display device mother substrate 100.

[0086] The peripheral partitions 7, 8, and 9 are disposed in the peripheral region SA and margin portion MP of the panel portion PP and are spaced apart from each other. In a plan view, the peripheral partitions 7 and 8 overlap the organic insulating layer IL, and the peripheral partition 9 overlaps the missing portion G. Although not described in detail here, each of the peripheral partitions 7, 8, and 9 has a cross-sectional shape similar to that of the partition 6 in the display area DA, and has a lower portion and an upper portion located above the lower portion and protruding from a side surface of the lower portion.

[0087] The peripheral partition wall 7 is formed in a lattice shape. In one example, the peripheral partition wall 7 is formed in the same pattern as the lattice-shaped partition wall 6 shown in FIG.

[0088] The multiple peripheral partitions (first partitions) 8 are located between the peripheral partitions 7 and the missing portion G, and are arranged along the groove 5G. For example, the multiple peripheral partitions 8 include a pair of peripheral partitions 8 each extending in the first direction X and aligned in the second direction Y. The pair of peripheral partitions 8 aligned in the second direction Y in this way face each other across the groove 5G extending in the first direction X. The multiple peripheral partitions 8 also include a pair of peripheral partitions 8 each extending in the second direction Y and aligned in the first direction X. The pair of peripheral partitions 8 aligned in the first direction X in this way face each other across the groove 5G extending in the second direction Y. The multiple peripheral partitions 8 also include an L-shaped peripheral partition 8 arranged along a corner portion of the groove 5G.

[0089] A plurality of peripheral partitions (second partitions) 9 are arranged in the missing portion G. In the missing portion G, the peripheral partitions 9 are arranged along the cut line CL. For example, the plurality of peripheral partitions 9 include a peripheral partition 9 extending in the first direction X. Such a peripheral partition 9 is arranged along the cut line CL extending in the first direction X. Moreover, the plurality of peripheral partitions 9 include a peripheral partition 9 extending in the second direction Y. Such a peripheral partition 9 is arranged along the cut line CL extending in the second direction Y. Moreover, the plurality of peripheral partitions 9 include an L-shaped peripheral partition 9 arranged along an intersection of the cut lines CL. In a plan view, some of the peripheral partitions 9 located at the intersection overlap the metal layer MT. However, from the viewpoint of preventing erroneous recognition of the alignment mark, it is preferable that the peripheral partitions 9 overlapping the metal layer MT are not arranged across an area where the metal layer MT does not exist. In the missing portion G, the metal layer MT and the peripheral partition wall 9 are arranged so as not to overlap the cut line CL in order to prevent cutting defects.

[0090] In order to prevent the peripheral partition 9 from disappearing due to excessive removal of the peripheral partition 9 arranged in the missing portion G during wet etching for forming the peripheral partitions 7, 8, and 9, it is desirable that the width W9 of the peripheral partition 9 arranged in the missing portion G be larger than the width W7 of the peripheral partition 7 arranged above the organic insulating layer IL. In the illustrated example, the width W8 of the peripheral partition 8 is larger than the width W7, but may be equal to the width W7.

[0091] FIG. 13 is a plan view showing the display panel PNL cut along the cut line CL shown in FIG.

[0092] 12 corresponds to the outer edge 10E of the substrate 10. However, when the mother substrate 100 for a display device is cut along the cut line CL and then the extracted panel portion is further cut and formed into a desired shape, the position of at least a part of the outer edge 10E differs from the position of the cut line CL shown in FIG.

[0093] The organic insulating layer IL is disposed across the display area DA and the peripheral area SA. The organic insulating layer IL has a missing portion LP along the outer edge 10E in the peripheral area SA. In the example shown, the missing portion LP is formed in a loop shape and is formed along the entire circumference of the outer edge 10E. The missing portion LP corresponds to a part of the missing portion G shown in FIG. 12.

[0094] The outer edge ILE of the organic insulating layer IL does not overlap the outer edge 10E of the substrate 10 in a plan view, and is located between the outer edge 10E and the display area DA.

[0095] When one corner of the substrate 10 is enlarged, a part of the metal layer MT and the peripheral partition wall 9 constituting the alignment mark shown in FIG. 12 are disposed in the missing portion LP. In other words, the metal layer MT and the peripheral partition wall 9 are located between the outer edge ILE and the outer edge 10E in a plan view. The metal layer MT is formed in an L-shape along the corner of the substrate 10. A part of the peripheral partition wall 9 overlapping the metal layer MT is formed in a straight line along the outer edge 10E. The other peripheral partition wall 9 overlapping the metal layer MT is formed in an L-shape along the corner of the substrate 10.

[0096] In the peripheral region SA, the peripheral partitions 7 overlapping the organic insulating layer IL are formed in a lattice pattern in a plan view. Among the peripheral partitions 8 overlapping the organic insulating layer IL, a pair of the peripheral partitions 8 arranged at a distance from each other face each other with a groove 5G therebetween.

[0097] Next, several configuration examples will be described regarding the cross-sectional structure of the mother substrate 100 for a display device taken along line CD in FIG.

[0098] FIG. 14 is a cross-sectional view showing an example of the configuration of a mother substrate 100 for a display device.

[0099] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The insulating layer 112 is an organic insulating layer and is disposed on the insulating layer 111. These insulating layers 111 and 112 are included in the circuit layer 11 shown in FIG. 3. Note that the insulating layer 111 may be omitted. Also, other insulating layers or conductive layers may be disposed between the substrate 10 and the insulating layer 111. The metal layer MT shown in FIG. 12 is disposed between the substrate 10 and the insulating layer 111.

[0100] The insulating layer 12 is an organic insulating layer that covers the insulating layer 112 and has a missing portion G in a region in contact with the insulating layer 111. In the configuration example shown in Fig. 14, the organic insulating layer IL includes the insulating layer 112 and the insulating layer 12. When attention is paid to the cross-sectional shape of such an organic insulating layer IL, the organic insulating layer IL has a stepped cross section in which the thickness decreases toward the missing portion G.

[0101] The thickness T1 of the organic insulating layer IL is the sum of the thickness of the insulating layer 112 and the thickness of the insulating layer 12, and corresponds to the length along the third direction Z from the upper surface of the insulating layer 111 to the approximately flat upper surface 121A of the insulating layer 12.

[0102] The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 12, and corresponds to the length along the third direction Z from the upper surface of the insulating layer 111 to the substantially flat upper surface 122A of the insulating layer 12. The thickness T2 is smaller than the thickness T1. The upper surface 122A is located between the upper surface 121A and the notched portion G, and is located lower than the upper surface 121A.

[0103] The inorganic insulating layer 5 covers the insulating layer 12 and covers the insulating layer 111 at the missing portion G. The groove 5G penetrates to the upper surface 121A of the insulating layer 12. The groove 5G can be formed in the same process as the opening AP1 shown in FIG. 2, for example.

[0104] The peripheral partitions 7 and 8 are disposed above the organic insulating layer IL, and the peripheral partition 9 is disposed in the missing portion G. In the illustrated example, the peripheral partitions 7 and 8 are disposed above the upper surface 121A, but are not disposed above the upper surface 122A. However, the peripheral partitions 7 and 8 may be disposed above the upper surface 122A.

[0105] The peripheral partition wall 7 has a lower portion 71 disposed on the inorganic insulating layer 5 and an upper portion 72 disposed on the lower portion 71. The upper portion 72 has a width greater than that of the lower portion 71. Both ends of the upper portion 72 protrude beyond the side surfaces of the lower portion 71.

[0106] The peripheral partition wall 8 has a lower portion 81 disposed on the inorganic insulating layer 5 and an upper portion 82 disposed on the lower portion 81. The upper portion 82 has a width greater than that of the lower portion 81. Both end portions of the upper portion 82 protrude beyond the side surfaces of the lower portion 81.

[0107] The peripheral partition 9 has a lower portion 91 disposed on the inorganic insulating layer 5, and an upper portion 92 disposed on the lower portion 91. The upper portion 92 has a width greater than that of the lower portion 91. Both ends of the upper portion 92 protrude beyond the side surfaces of the lower portion 91.

[0108] In this manner, each of the peripheral partition walls 7, 8, and 9 has an overhanging shape similar to the partition wall 6 shown in Fig. 3. The peripheral partition walls 7, 8, and 9 can be formed in the same process as the partition wall 6. In this case, the lower parts 71, 81, and 91 are formed of the same material as the lower part 61, and the upper parts 72, 82, and 92 are formed of the same material as the upper part 62.

[0109] The organic insulating layer IL having a stepped cross section can be formed, for example, by the following method. First, insulating layer 112 is formed on insulating layer 111. Then, insulating layer 12 is formed having missing portion G, upper surface 121A, and upper surface 122A. Such insulating layer 12 can be formed, for example, by the following method. That is, an insulating layer is formed on the entire surface of the display device mother substrate 100 on which the insulating layer 112 has been formed, using, for example, a positive organic material. The insulating layer is then exposed to light. In this exposure process, the amount of exposure is set to a maximum at the missing portion G, and is set to decrease stepwise from the missing portion G toward the outside. The exposed insulating layer is then developed. The insulating layer is then baked. As a result, the organic insulating layer IL having the above-mentioned cross-sectional shape is formed. The missing portion G formed at this time is formed in a loop shape surrounding the display area DA or the panel portion PP, as shown in FIG.

[0110] In such a configuration example, when the mother substrate 100 for a display device is cut along the cut line CL, the cross section of the display panel PNL along the line C'-D' in Figure 13 corresponds to the cross section of the region to the left of the cut line CL in the mother substrate 100 for a display device shown in Figure 14.

[0111] FIG. 15 is a cross-sectional view showing another example of the configuration of the mother substrate 100 for a display device.

[0112] 15 differs from the configuration example shown in FIG 14 in that the insulating layer 112 extends further toward the cut line CL than the insulating layer 12. The insulating layer 112 has a missing portion G. The insulating layer 12 is disposed on the insulating layer 112. Focusing on the cross-sectional shape of the organic insulating layer IL having the insulating layer 112 and the insulating layer 12, the organic insulating layer IL has a stepped cross section whose thickness decreases toward the missing portion G.

[0113] The thickness T1 of the organic insulating layer IL is the sum of the thickness of the insulating layer 112 and the thickness of the insulating layer 12, and corresponds to the length along the third direction Z from the upper surface of the insulating layer 111 to the approximately flat upper surface 12A of the insulating layer 12.

[0114] The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 112 exposed from the insulating layer 12, and corresponds to the length along the third direction Z from the upper surface of the insulating layer 111 to the substantially flat upper surface 112A of the insulating layer 112. The thickness T2 is smaller than the thickness T1. The upper surface 112A is located between the upper surface 12A and the notched portion G, and is located lower than the upper surface 12A.

[0115] The inorganic insulating layer 5 covers the insulating layer 12, covers the insulating layer 112 exposed from the insulating layer 12, and covers the insulating layer 111 at the missing portion G. The groove 5G penetrates the insulating layer 12 up to the upper surface 12A.

[0116] The peripheral partitions 7 and 8 are disposed above the organic insulating layer IL, and the peripheral partition 9 is disposed in the missing portion G. In the illustrated example, the peripheral partitions 7 and 8 are disposed above the upper surface 12A, but are not disposed above the upper surface 112A. However, the peripheral partitions 7 and 8 may be disposed above the upper surface 112A. Lower portions 71, 81, and 91 of the peripheral partitions 7, 8, and 9, respectively, are all disposed on the inorganic insulating layer 5.

[0117] The organic insulating layer IL having a stepped cross section can be formed, for example, by the following method. First, an insulating layer 112 having a missing portion G and an upper surface 112A is formed on an insulating layer 111. Then, an insulating layer 12 having an upper surface 12A is formed on the insulating layer 112. At this time, the insulating layer 12 is formed so as to expose a part of the insulating layer 112 in the vicinity of the missing portion G. As a result, the organic insulating layer IL having the above-mentioned cross-sectional shape is formed.

[0118] In such a configuration example, when the mother substrate 100 for a display device is cut along the cut line CL, the cross section of the display panel PNL along the line C'-D' in Figure 13 corresponds to the cross section of the region to the left of the cut line CL in the mother substrate 100 for a display device shown in Figure 15.

[0119] FIG. 16 is a cross-sectional view showing another example of the configuration of the mother substrate 100 for a display device.

[0120] The configuration example shown in Fig. 16 differs from the configuration example shown in Fig. 14 in that the organic insulating layer IL having a stepped cross section is a single layer of insulating layer 12. Insulating layer 112 does not exist. Insulating layer 12 is disposed on insulating layer 111 and has a missing portion G. Focusing on the cross-sectional shape of the organic insulating layer IL, the organic insulating layer IL has a stepped cross section in which the thickness decreases toward the missing portion G.

[0121] The thickness T1 of the organic insulating layer IL corresponds to the length along the third direction Z from the upper surface of the insulating layer 111 to the substantially flat upper surface 121A of the insulating layer 12. The thickness T2 of the organic insulating layer IL corresponds to the length along the third direction Z from the upper surface of the insulating layer 111 to the substantially flat upper surface 122A of the insulating layer 12. The thickness T2 is smaller than the thickness T1. The upper surface 122A is located between the upper surface 121A and the missing portion G, and is located lower than the upper surface 121A.

[0122] The inorganic insulating layer 5 covers the insulating layer 12, and covers the insulating layer 111 at the missing portion G. The groove 5G penetrates the insulating layer 12 up to the upper surface 121A.

[0123] The peripheral partitions 7 and 8 are disposed above the organic insulating layer IL, and the peripheral partition 9 is disposed in the missing portion G. In the illustrated example, the peripheral partitions 7 and 8 are disposed above the upper surface 121A, but are not disposed above the upper surface 122A. However, the peripheral partitions 7 and 8 may be disposed above the upper surface 122A. Lower portions 71, 81, and 91 of the peripheral partitions 7, 8, and 9, respectively, are all disposed on the inorganic insulating layer 5.

[0124] The insulating layer 12 having a stepped cross section can be formed, for example, by the following method. That is, an insulating layer is formed on the entire surface of the display device mother substrate 100 on which the insulating layer 111 is formed, using, for example, a positive organic material. The insulating layer is then exposed to light. In this exposure process, the amount of exposure is set to a maximum in the missing portion G, and is set to decrease stepwise from the missing portion G toward the outside. The exposed insulating layer is then developed. The insulating layer is then baked. As a result, the insulating layer 12 having the above-mentioned cross-sectional shape is formed.

[0125] In such a configuration example, when the mother substrate 100 for a display device is cut along the cut line CL, the cross section of the display panel PNL along the line C'-D' in Figure 13 corresponds to the cross section of the region to the left of the cut line CL in the mother substrate 100 for a display device shown in Figure 16.

[0126] FIG. 17 is an enlarged cross-sectional view of a region including the groove 5G.

[0127] The insulating layer 12 has a recess 12C overlapping the groove 5G. The recess 12C is wider than the groove 5G in a direction perpendicular to the extension direction of the groove 5G (first direction X in the illustrated example). The inorganic insulating layer 5 has an edge 5E along the groove 5G. The edge 5E overlaps the recess 12C and is spaced apart from the insulating layer 12. In other words, the inorganic insulating layer 5 is formed in an overhanging shape. The peripheral partition 8 does not overlap the recess 12C or the edge 5E.

[0128] As described above, the peripheral partition wall 8 is formed in an overhanging shape, similar to the partition wall 6. In the peripheral partition wall 8, the lower part 81 has a first conductive layer 83 disposed on the inorganic insulating layer 5 and a second conductive layer 84 disposed on the first conductive layer 83. For example, the first conductive layer 83 is formed to be thinner than the second conductive layer 84. In the illustrated example, both end parts of the first conductive layer 83 protrude from the side surfaces of the second conductive layer 84. The upper portion 82 has a first thin film 85 disposed on the second conductive layer 84 and a second thin film 86 disposed on the first thin film 85. Both end portions of the first thin film 85 and the second thin film 86 protrude from the side surfaces of the second conductive layer 84.

[0129] Since the pair of peripheral partition walls 8 are disposed on both sides of the groove 5G, the inorganic insulating layer 5 is pressed against the insulating layer 12 by the peripheral partition walls 8. This makes it possible to suppress lifting of the inorganic insulating layer 5 starting from the edge portion 5E of the inorganic insulating layer 5 and separation of the inorganic insulating layer 5 from the insulating layer 12.

[0130] FIG. 18 is a cross-sectional view for explaining a state in which the laminated film FL1 is formed in a region including the missing portion G shown in FIG.

[0131] For example, in the process of forming the display element DE1, the laminated film FL1 is formed not only in the display region but also in the marginal portion MP and the peripheral region SA. The laminated film FL1 here includes, for example, an organic layer OR1, an upper electrode UE1, and a cap layer CP1 for forming the display element DE1. The laminated film FL1 is formed on the inorganic insulating layer 5 and the peripheral partitions 7, 8, and 9.

[0132] The laminated film FL1 is divided by the overhanging peripheral partitions 7, 8, and 9. That is, when the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by deposition, the material emitted from the deposition source is blocked by the upper parts 72, 82, and 92 of the peripheral partitions 7, 8, and 9. Therefore, a part of each of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is laminated on the upper parts 72, 82, and 92. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 located on the upper parts 72, 82, and 92 are separated from the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located on the inorganic insulating layer 5. As a result, the laminated film FL1 is partially divided.

[0133] Compared to a case where the laminated film FL1 is not divided by the peripheral partitions 7, 8, and 9, the area of ​​the continuous laminated film FL1 is reduced, and stress that may occur in the laminated film FL1 is dispersed. Furthermore, the inorganic insulating layer 5 and the laminated film FL1 are held down by the peripheral partitions 7, 8, and 9. This makes it possible to suppress the inorganic insulating layer 5 from lifting up from the insulating layer 12 and the laminated film FL1 from the inorganic insulating layer 5. Furthermore, when a sealing layer SE1 is formed on the laminated film FL1, the sealing layer SE1, together with the peripheral partitions 7, 8, and 9, holds down the laminated film FL1. This makes it possible to suppress the detachment of the laminated film FL1 and the sealing layer SE1 from the inorganic insulating layer 5.

[0134] In addition, the organic insulating layer IL has a stepped cross section in which the thickness decreases toward the missing portion G. Therefore, the formation of a steep step is suppressed. The thinner the organic insulating layer IL is, the less it stretches. Therefore, when the laminated film FL1 is formed on the organic insulating layer IL, the distortion of the laminated film FL1 is small, and localized stress concentration in the laminated film FL1 can be suppressed. This makes it possible to suppress detachment of the laminated film FL1 from the inorganic insulating layer 5.

[0135] Here, a description will be given of problems that may occur when the laminated film FL1 floats up from the inorganic insulating layer 5 and breaks. The inorganic insulating layer 5 that has detached from the insulating layer 12 and the laminated film FL1 that has detached from the inorganic insulating layer 5 become foreign matter and float within the manufacturing equipment, and may become a source of contamination. Furthermore, if the floating foreign matter adheres to the processing substrate, it may cause various defects.

[0136] In contrast, according to the present embodiment, it is possible to suppress the separation of the inorganic insulating layer 5 and the laminated film FL1, thereby suppressing contamination of the manufacturing equipment and the generation of undesired foreign matter, and therefore suppressing a decrease in reliability.

[0137] The same effect can be obtained even when the laminated film FL1 is replaced with a laminated film FL2 including an organic layer OR2 for forming the display element DE2, an upper electrode UE2, and a cap layer CP2. Moreover, even if the laminated film FL1 is replaced with a laminated film FL3 including an organic layer OR3 for forming a display element DE3, an upper electrode UE3, and a cap layer CP3, the same effect can be obtained.

[0138] Here, the effect of suppressing separation of the inorganic insulating layer 5 and the laminated film FL1 has been described for the configuration example shown in FIG. 14, but the same effect can be obtained for each of the other configuration examples.

[0139] FIG. 19 is a cross-sectional view for explaining a state in which the laminated film FL1 is formed in a region including the groove 5G shown in FIG.

[0140] The laminated film FL1 is formed on the inorganic insulating layer 5 and the peripheral partition wall 8, and is also formed in the recess 12C of the insulating layer 12. The laminated film FL1 is divided by the overhanging inorganic insulating layer 5 and the peripheral partition wall 8. That is, the laminated film FL1 formed on the peripheral partition wall 8 is separated from the laminated film FL1 formed on the inorganic insulating layer 5. Furthermore, the laminated film FL1 formed on the inorganic insulating layer 5 is separated from the laminated film FL1 formed in the recess 12C. In this way, the laminated film FL1 is divided into an inner region surrounded by the loop-shaped groove 5G and an outer region.

[0141] This reduces the stress generated in the laminated film FL1, and provides the same effect as that described with reference to FIG.

[0142] In addition, since the laminated film FL1 is divided, the capacitance of the laminated film FL1 is reduced compared to when the groove 5G does not exist. This suppresses electrostatic discharge from the laminated film FL1. This makes it possible to suppress damage to the laminated film FL1 and its surroundings caused by electrostatic discharge. Therefore, deterioration of reliability is suppressed.

[0143] FIG. 20 is a plan view showing another configuration example of the region 100B shown in FIG.

[0144] The configuration example shown in Fig. 20 differs from the configuration example shown in Fig. 12 in that the multiple peripheral partitions 9 arranged in the missing portion G include peripheral partitions (second partitions) 9A arranged along corner portions of the outer edge ILE of the organic insulating layer IL. The corner portions of the outer edge ILE form a substantially right angle in plan view. The peripheral partitions 9A are formed in an L-shape in plan view.

[0145] In FIG. 20, the groove 5G of the inorganic insulating layer 5 and the peripheral partition wall 8 are omitted.

[0146] In the illustrated example, a conductive layer 9B is disposed along the straight line portion of the outer edge ILE. This conductive layer 9B is, for example, a residue generated in the process of forming the conductive peripheral partition walls 7, 8, and 9. For this reason, the conductive layer 9B is not necessarily present.

[0147] In the illustrated example, the conductive layer 9B is connected to the peripheral partition 9A. In a plan view, the width W9B of the conductive layer 9B is smaller than the width W9A of the peripheral partition 9A. In one example, the width W9A is about 20 μm, and the width W9B is several μm. The width W9B of the conductive layer 9B is smaller than the width W9 of the other peripheral partition 9. The width W9 is equal to the width W9A. As described above, from the viewpoint of suppressing disappearance of the peripheral partition 9 or defective formation of the peripheral partition 9, the widths W9 and W9A are larger than the width W7 of the peripheral partition 7.

[0148] FIG. 21 is a plan view showing the display panel PNL cut along the cut line CL shown in FIG.

[0149] When one corner of the substrate 10 is enlarged, a part of the metal layer MT and the peripheral partitions 9, 9A constituting the alignment mark shown in FIG. 20 are disposed in the missing portion LP. In other words, the metal layer MT and the peripheral partitions 9, 9A are located between the outer edge ILE and the outer edge 10E in a plan view. The metal layer MT is formed in an L-shape along the corner of the substrate 10. A part of the peripheral partition 9 overlapping the metal layer MT is formed in a straight line along the outer edge 10E. In addition, the peripheral partition 9A along the corner of the outer edge ILE is formed in an L-shape.

[0150] Next, several configuration examples will be described regarding the cross-sectional structure of the mother substrate 100 for a display device taken along the line EF in Fig. 20. Note that in each of the cross-sectional views shown in Fig. 22 to Fig. 24, the groove 5G and the peripheral partition wall 8 are omitted.

[0151] FIG. 22 is a cross-sectional view showing an example of the configuration of a mother substrate 100 for a display device.

[0152] The configuration example shown in FIG. 22 is substantially the same as the configuration example shown in FIG. 14, except that the peripheral partition 9A is disposed along the outer edge ILE.

[0153] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The insulating layer 112 is an organic insulating layer and is disposed on the insulating layer 111. The insulating layer 12 is an organic insulating layer that covers the insulating layer 112 and has a missing portion G in a region in contact with the insulating layer 111. The organic insulating layer IL including the insulating layer 112 and the insulating layer 12 has a stepped cross section whose thickness decreases toward the missing portion G.

[0154] The peripheral partition wall 9A has a lower portion 91 disposed on the inorganic insulating layer 5, and an upper portion 92 disposed on the lower portion 91. The upper portion 92 has a width greater than that of the lower portion 91. Both ends of the upper portion 92 protrude beyond the side surfaces of the lower portion 91. In this manner, the cross-sectional shape of the peripheral partition wall 9A is the same as the cross-sectional shape of the peripheral partition wall 9 shown in FIG. 14. Such a peripheral partition wall 9A can also be formed in the same process as the partition wall 6.

[0155] In such a configuration example, when the mother substrate 100 for a display device is cut along the cut line CL, the cross section of the display panel PNL along line E'-F' in Figure 21 corresponds to the cross section of the region to the left of the cut line CL in the mother substrate 100 for a display device shown in Figure 22.

[0156] FIG. 23 is a cross-sectional view showing another example of the configuration of the mother substrate 100 for a display device.

[0157] The configuration example shown in FIG. 23 is substantially the same as the configuration example shown in FIG. 15, except that the peripheral partition 9A is disposed along the outer edge ILE.

[0158] The insulating layer 112 extends further toward the cut line CL than the insulating layer 12, and has a missing portion G. The insulating layer 12 is disposed on the insulating layer 112. The organic insulating layer IL including the insulating layer 112 and the insulating layer 12 has a stepped cross section whose thickness decreases toward the missing portion G. A lower portion 91 of the peripheral partition 9A is disposed on the inorganic insulating layer 5.

[0159] In such a configuration example, when the mother substrate 100 for a display device is cut along the cut line CL, the cross section of the display panel PNL along the line E'-F' in Figure 21 corresponds to the cross section of the region to the left of the cut line CL in the mother substrate 100 for a display device shown in Figure 23.

[0160] FIG. 24 is a cross-sectional view showing another example of the configuration of the mother substrate 100 for a display device.

[0161] The configuration example shown in FIG. 24 is substantially the same as the configuration example shown in FIG. 16, except that the peripheral partition 9A is disposed along the outer edge ILE.

[0162] The insulating layer 12 is disposed on the insulating layer 111 and has a missing portion G. The organic insulating layer IL is a single layer of the insulating layer 12, and the insulating layer 112 is not present. Focusing on the cross-sectional shape of the organic insulating layer IL, the organic insulating layer IL has a stepped cross section whose thickness decreases toward the missing portion G. The lower portion 91 of the peripheral partition 9A is disposed on the inorganic insulating layer 5.

[0163] In such a configuration example, when the mother substrate 100 for a display device is cut along the cut line CL, the cross section of the display panel PNL along line E'-F' in Figure 21 corresponds to the cross section of the region to the left of the cut line CL in the mother substrate 100 for a display device shown in Figure 24.

[0164] FIG. 25 is a diagram for explaining a problem that may occur if the peripheral partition 9A is not provided.

[0165] When the conductive layer 9B is formed along the outer edge ILE as a residue generated in the process of forming the peripheral partition wall, the conductive layer 9B tends to taper toward the corner of the outer edge ILE. At this time, electric charges tend to concentrate on the sharp tip of the conductive layer 9B. This may induce electrostatic discharge between adjacent conductive layers 9B or between the conductive layer 9B and its periphery. In addition, when the laminated film FL1 is formed in a later process, electrostatic discharge may be induced between the laminated film FL1 and the conductive layer 9B.

[0166] In contrast, in the configuration example shown in FIG. 20, the peripheral partition 9A is intentionally disposed at the corner portion of the outer edge ILE, so that even if a conductive layer 9B is formed, the conductive layer 9B is connected to the peripheral partition 9A, and a sharp tip is unlikely to be formed. This suppresses electrostatic discharge originating from the conductive layer 9B. This makes it possible to suppress damage to the peripheral portion of the conductive layer 9B and the laminated film FL1 caused by electrostatic discharge. This suppresses deterioration of reliability.

[0167] FIG. 26 is a plan view showing another configuration example of the region 100A of the display device mother substrate 100 shown in FIG.

[0168] The configuration example shown in Fig. 26 differs from the configuration example shown in Fig. 11 in that the outer edge ILE of the organic insulating layer IL includes a rounded corner portion. The rounded corner portion here corresponds to a portion of the outer edge ILE of the organic insulating layer IL that is formed in an arc shape in a plan view. In the illustrated example, in the peripheral area SA of the panel portion PP, a rounded corner portion is formed near the intersection of the cut lines CL. In addition, in the margin portion MP, a rounded corner portion is formed near the intersection of the cut lines CL and at the end portion GE of the missing portion G.

[0169] Fig. 27 is a plan view showing one configuration example of the region 100B shown in Fig. 26. Note that in Fig. 27, the groove 5G of the inorganic insulating layer 5 and the peripheral partition wall 8 are omitted.

[0170] The round corner portion of the outer edge ILE of the organic insulating layer IL is formed in an arc shape with a radius of curvature RIL. The radius of curvature RIL is, for example, equal to or greater than 1 / 2 of the width WG of the notch G extending in the second direction Y along the first direction X (WG / 2≦RIL). In one example, the radius of curvature RIL is 150 μm or more.

[0171] In the illustrated example, the conductive layer 9B is disposed along the outer edge ILE including the round corner portion. The conductive layer 9B has a substantially constant width. As described above, the conductive layer 9B is a residue generated in the process of forming the conductive peripheral partition walls 7, 8, and 9, and is not necessarily present.

[0172] FIG. 28 is a plan view showing the display panel PNL cut along the cut line CL shown in FIG.

[0173] When one corner of the substrate 10 is enlarged, a portion of the metal layer MT and the peripheral partition 9 constituting the alignment mark shown in FIG. 27 are disposed in the missing portion LP. The metal layer MT is formed in an L-shape along the corner of the substrate 10. A portion of the peripheral partition 9 overlapping the metal layer MT is formed in a straight line along the outer edge 10E. The corner of the outer edge ILE is rounded. The conductive layer 9B is disposed along the outer edge ILE.

[0174] The round corner portion of the outer edge ILE is formed in an arc shape with a radius of curvature RIL. The radius of curvature RIL is equal to or greater than the width WLP of the notch portion LP extending in the second direction Y along the first direction X (WLP≦RIL), for example.

[0175] In this way, by rounding the corners of the outer edge ILE, even if the conductive layer 9B is formed, the conductive layer 9B has a substantially constant width along the outer edge ILE, and is less likely to have a sharp tip. This suppresses electrostatic discharge originating from the conductive layer 9B. This makes it possible to suppress damage to the periphery of the conductive layer 9B and the laminated film FL1 caused by electrostatic discharge.

[0176] In addition, the radius of curvature RIL of the round corner is equal to or greater than 1 / 2 the width WG of the notch G in the display device mother substrate 100, or equal to or greater than the width WLP of the notch LP in the display panel PNL. This makes it possible to prevent lifting or separation starting from the vicinity of the corner of the laminated film FL1 or the inorganic insulating layer 5. This prevents a decrease in reliability.

[0177] In the above embodiment, for example, in each of the peripheral partitions 7, 8, and 9, the lower parts 71, 82, and 91 correspond to the first lower part, the upper parts 72, 82, and 92 correspond to the first upper part, the peripheral partition 8 corresponds to the first partition, and the peripheral partitions 9 and 9A correspond to the second partition. In addition, in the partition 6, the lower part 61 corresponds to the second lower part, and the upper part 62 corresponds to the second upper part. In the organic insulating layer IL, the insulating layer 112 corresponds to the first layer, and the insulating layer 12 corresponds to the second layer. In the inorganic insulating layer 5, the groove 5G corresponds to the first groove, and the groove 5GA corresponds to the second groove.

[0178] As described above, according to the present embodiment, it is possible to provide a display device and a mother substrate for the display device that are capable of suppressing a decrease in reliability.

[0179] All display devices and mother substrates for display devices that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices and mother substrates for display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0180] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0181] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0182] DSP…display device 10…board 5...Inorganic insulating layer AP1, AP2, AP3...Openings 5G, 5GA...Groove 6...Bulkhead 61...Lower 62...Upper 7...Peripheral bulkhead 71...Lower part 72...Upper part 8...Peripheral bulkhead 81...Lower part 82...Upper part 9, 9A…Peripheral bulkhead 91…Lower part 92…Upper part SP1, SP2, SP3...Subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3...lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer DA: Display area SA: Surrounding area 100: Mother board for display device PP: Panel section MP: Blank section CL…Cut line IL: organic insulating layer 12: insulating layer 112: insulating layer G, LP: missing portion

Claims

1. A substrate; an organic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region; each of the peripheral partition walls has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; the organic insulating layer has a missing portion along an outer edge of the substrate in the peripheral region, the inorganic insulating layer has a loop-shaped groove surrounding the display area in the peripheral area, the plurality of peripheral partition walls include a pair of first partition walls opposed to each other across the groove, Display device.

2. the organic insulating layer has a recess overlapping the groove, an edge portion of the inorganic insulating layer along the groove overlaps the recess and is spaced apart from the organic insulating layer; The display device according to claim 1 .

3. the inorganic insulating layer is disposed in the missing portion, the plurality of peripheral partition walls include a second partition wall disposed on the inorganic insulating layer in the missing portion; The display device according to claim 1 .

4. the second partition wall is disposed along a corner portion of an outer edge of the organic insulating layer and is formed in an L-shape in a plan view; The display device according to claim 3 .

5. The insulating layer further includes a conductive layer disposed along a straight portion of an outer edge of the organic insulating layer, the conductive layer is connected to the second partition wall, a width of the conductive layer is smaller than a width of the second partition wall; The display device according to claim 4.

6. the outer edge of the organic insulating layer includes a round corner portion; The radius of curvature of the round corner portion is equal to or greater than the width of the missing portion. The display device according to claim 1 .

7. Further, a conductive layer is disposed along an outer edge of the organic insulating layer. The display device according to claim 6.

8. A substrate; an organic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region; Each of the plurality of peripheral partition walls has a first lower portion and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer has a missing portion along an outer edge of the substrate in the peripheral region, the plurality of peripheral partition walls include a second partition wall disposed in the missing portion, the second partition wall is disposed along a corner portion of an outer edge of the organic insulating layer and is formed in an L-shape in a plan view; Display device.

9. The insulating layer further includes a conductive layer disposed along a straight portion of an outer edge of the organic insulating layer, the conductive layer is connected to the second partition wall, a width of the conductive layer is smaller than a width of the second partition wall; The display device according to claim 8.

10. A substrate; an organic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region; Each of the plurality of peripheral partition walls has a first lower portion and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer has a missing portion along an outer edge of the substrate in the peripheral region, the outer edge of the organic insulating layer includes a round corner portion; The radius of curvature of the round corner portion is equal to or greater than the width of the missing portion. Display device.

11. Further, a conductive layer is disposed along an outer edge of the organic insulating layer. The display device according to claim 10.

12. a partition wall including a second lower portion disposed on the inorganic insulating layer in the display region and made of a conductive material, and a second upper portion disposed on the second lower portion and protruding from a side surface of the second lower portion, the lower electrode, the organic layer, and the upper electrode are surrounded by the partition wall, the upper electrode is in contact with the second lower portion of the partition wall; The display device according to claim 1 , 8 , or 10 .

13. The organic insulating layer has a first layer and a second layer covering the first layer, and has a stepped cross section whose thickness decreases toward the missing portion. The display device according to claim 1 , 8 , or 10 .

14. the organic insulating layer has a first layer and a second layer disposed on the first layer and exposing the first layer adjacent to the missing portion, and has a stepped cross section whose thickness decreases toward the missing portion. The display device according to claim 1 , 8 , or 10 .

15. The organic insulating layer is a single layer and has a stepped cross section whose thickness decreases toward the missing portion. The display device according to claim 1 , 8 , or 10 .

16. a panel section having a display area for displaying an image and a peripheral area outside the display area; a margin portion outside the panel portion; an organic insulating layer disposed across the panel portion and the marginal portion; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region; each of the peripheral partition walls has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; the inorganic insulating layer has a loop-shaped first groove surrounding the display region in the peripheral region; the plurality of peripheral partition walls include a pair of first partition walls opposed to each other across the first groove, Mother board for display devices.

17. the organic insulating layer has a recess overlapping the first groove, an edge portion of the inorganic insulating layer along the first groove overlaps the recess and is spaced apart from the organic insulating layer; The mother substrate for a display device according to claim 16.

18. the organic insulating layer has a missing portion that follows the outer shape of the panel portion, The missing portion has an end portion located in the margin portion, the inorganic insulating layer has a second groove in the marginal portion surrounding the end portion; The mother substrate for a display device according to claim 16.

19. a panel section having a display area for displaying an image and a peripheral area outside the display area; a margin portion outside the panel portion; an organic insulating layer disposed across the panel portion and the marginal portion; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region; each of the peripheral partition walls has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; the organic insulating layer has a missing portion that follows the outer shape of the panel portion, the plurality of peripheral partition walls include a second partition wall disposed in the missing portion, the second partition wall is disposed along a corner portion of an outer edge of the organic insulating layer and is formed in an L-shape in a plan view; Mother board for display devices.

20. a panel section having a display area for displaying an image and a peripheral area outside the display area; a margin portion outside the panel portion; an organic insulating layer disposed across the panel portion and the marginal portion; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region; each of the peripheral partition walls has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; the organic insulating layer has a missing portion that follows the outer shape of the panel portion, the outer edge of the organic insulating layer includes a round corner portion; The radius of curvature of the round corner portion is equal to or greater than half the width of the missing portion. Mother board for display devices.

Images