Semiconductor light emitting element and method for manufacturing semiconductor light emitting element

Abstract

To provide a semiconductor light emitting element with large reverse voltage (Vr) for a support substrate junction type semiconductor light emitting element while using dry etching technique as a mesa formation method.SOLUTION: In a semiconductor light emitting element having a reflective layer, an intermediate electrode layer, a first conductive layer, an active layer, and a second conductive layer, in that order, on a support substrate, the intermediate electrode layer consists of a dielectric section and a conductor section. The outer periphery is the dielectric section, the dielectric section is present on the outer side of the second conductive layer from the first conductive layer, the angle between the side surface of the first conductive layer and the dielectric section is between 70° and 85°, and no notches are on the side surface of the semiconductor laminate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor light-emitting device and a method for manufacturing the same. [Background technology]

[0002] Due to the diversification of LED applications, there is a growing need for high-output long-wavelength (emission wavelength: 1000-2000 nm) LEDs to be used as the light-emitting parts of blood glucose sensors or moisture sensors. A technology has been established to improve the luminous efficiency of InP-based LED elements with an emission wavelength of 1000-2000 nm by using Al in the active layer.

[0003] For example, Patent Document 1 discloses a surface-emitting semiconductor element including a semiconductor laminate including an n-type InP substrate, an n-type InP layer laminated on the n-type InP substrate, an InGaAlAs active layer laminated on the n-type InP layer, and a p-type InP layer laminated on the InGaAlAs active layer, and a reflecting member covering the semiconductor laminate. Similarly, Patent Document 2 discloses a semiconductor light-emitting element including InGaAlAs in the active layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-182154 A [Patent Document 2] Patent Publication No. 2021-77885 [Patent Document 3] JP 2022-101468 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in a support substrate-bonded semiconductor light-emitting device, there is a problem that deposition of a dielectric material occurs on the side surface of the active layer during mesa formation, resulting in poor reverse bias characteristics of the semiconductor light-emitting device. Patent Document 3 discloses an infrared device with an inclined mesa, but the emission wavelength is in the infrared region, and the mesa angle is considered, and there has been no disclosure up to now of exposing the dielectric layer by etching in a support substrate-bonded device.

[0006] An object of the present invention is to provide a semiconductor light emitting device having a large reverse voltage (Vr) while using a dry etching method as a mesa formation method for a supporting substrate-bonded semiconductor light emitting device. [Means for solving the problem]

[0007] In the case of a semiconductor light-emitting device bonded to a support substrate, when a mesa is formed by dry etching, the SiO 2 As a result of intensive research conducted by the present inventors to achieve the above object, it was found that elements with a small Vr tend to have a large amount of overetching, which will be described later, and that the SiO 2 It was found that even if a protective film is formed by a method such as a SiO2 mask, this effect remains and deteriorates the reverse bias characteristics. Therefore, it was found that the leakage current can be suppressed and a semiconductor light emitting element with a large Vr can be obtained by suppressing the overetching rate and keeping the mesa angle within a specific range under the dry etching conditions.

[0008] That is, the gist and configuration of the present invention are as follows. (1) A semiconductor device comprising: a reflective layer formed on a support substrate; an intermediate electrode layer formed on the reflective layer; a first conductive type layer formed on the intermediate electrode layer; an active layer formed on the first conductive type layer; and a second conductive type layer formed on the active layer, wherein the intermediate electrode layer is composed of a dielectric portion and a conductor portion, an outer periphery of the intermediate electrode layer is the dielectric portion, the dielectric portion is present outside a side surface of a semiconductor laminate having the first conductive type layer, the active layer, and the second conductive type layer, and in a cross section of the semiconductor device, a side surface of the first conductive type layer in the vicinity of the active layer and the 1. A semiconductor light-emitting element, characterized in that when a first line circumscribing a side surface of a second conductivity type layer and a second line tangent to a side surface of the active layer and parallel to the first line are drawn, the second line is outside the first line, the distance between the first line and the second line is zero, or the second line is inside the first line and the distance between the two lines is 10 nm or less, and a third line connecting a junction between the intermediate electrode layer and the side surface of the first conductivity type layer and a junction between the first line on the first conductivity type layer side forms an angle of 70° or more and 85° or less with respect to the side of the intermediate electrode layer on which the first conductivity type layer is placed.

[0009] (2) The semiconductor light-emitting element according to (1) above, wherein the active layer contains one or more of Al, Ga, and In as a group III element, and one or more of As, Sb, and P as a group V element, and the first conductivity type layer contains one or more of Al, Ga, and In as a group III element, and one or more of As, Sb, and P as a group V element.

[0010] (3) The semiconductor light-emitting element according to (1) or (2) above, which has a reverse voltage of 20 V or more when a reverse current of 0.1 μA is applied.

[0011] (4) The semiconductor light emitting element according to any one of (1) to (3) above, wherein a curvature of a line connecting an upper end and a lower end of a side surface of the first conductive type layer along the side surface is 0 or more and 0.11 or less.

[0012] (5) The dielectric portion is made of SiO2 Or, the semiconductor light-emitting element according to any one of (1) to (4) above is made of SiN.

[0013] (6) The semiconductor light-emitting element according to any one of (1) to (5) above, wherein the weight ratio of Si atoms on a side surface between the interface between the dielectric portion and the first conductive type layer and the center of the thickness of the second conductive type layer is 2.5 weight % or less.

[0014] (7) The dielectric portion is SiO 2 The semiconductor light-emitting element according to any one of (1) to (6) above, wherein a weight ratio of O atoms on a side surface between an interface between the dielectric portion and the first conductive type layer and a center of a thickness of the second conductive type layer is 7.5 weight % or less.

[0015] (8) A method for manufacturing a semiconductor light-emitting element, comprising the steps of: forming an etching stop layer on a growth substrate; forming a second conductive type layer on the etching stop layer; forming an active layer on the second conductive type layer; forming a first conductive type layer on the active layer; forming an intermediate electrode layer on the first conductive type layer, the intermediate electrode layer being composed of a dielectric portion and a conductive portion and having an outer periphery which is the dielectric portion; forming a reflective layer on the intermediate electrode layer; forming a metal bonding layer on a support substrate; bonding the reflective layer and the metal bonding layer; and removing the growth substrate, wherein the semiconductor laminate from the second conductive type layer to the first conductive type layer is removed by a dry etching method along a planned chip division line, thereby forming a semiconductor laminate. a mesa formation step of forming a side surface on a surface of the intermediate electrode layer, the mesa formation step further comprising: a first line circumscribing a side surface of the first conductivity type layer and a side surface of the second conductivity type layer in the vicinity of the active layer, and a second line tangent to the side surface of the active layer and parallel to the first line, the second line being outside the first line, a distance between the first line and the second line being zero, or the second line being inside the first line and a distance between the two lines being 10 nm or less, and a third line connecting a junction between the intermediate electrode layer and the side surface of the first conductivity type layer and a junction of the first line on the first conductivity type layer side forms an angle of 70° or more and 85° or less with respect to the side of the intermediate electrode layer on which the first conductivity type layer is placed.

[0016] (9) The method for producing a semiconductor light-emitting element according to (8) above, wherein an overetching rate in the dry etching method is 1% or more and 9% or less.

[0017] (10) The method for manufacturing a semiconductor light-emitting element according to (8) or (9) above, wherein the weight percentage of Si atoms on a side surface between an interface between the dielectric portion and the first conductive type layer and a center of a thickness of the second conductive type layer immediately after the mesa formation step is 2.5 weight % or less. Effect of the Invention

[0018] According to the present invention, a semiconductor light emitting device having a large reverse voltage (Vr) can be provided while using a dry etching method as a mesa formation method for a supporting substrate-bonded semiconductor light emitting device. [Brief description of the drawings]

[0019] [Figure 1] 1 is a schematic cross-sectional view showing a structure of a semiconductor light-emitting element according to the present invention. [Figure 2A] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light-emitting element according to the present invention. [Figure 2B] 2B is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor light-emitting element subsequent to FIG. 2A. [Figure 2C] 2C is a schematic cross-sectional view illustrating a state before dry etching in the method for manufacturing the semiconductor light-emitting element subsequent to FIG. 2B. FIG. [Figure 2D] 2D is a schematic cross-sectional view illustrating a state after dry etching in the method for manufacturing the semiconductor light-emitting element subsequent to FIG. 2C. FIG. [Figure 3A] FIG. 1 is a first diagram showing a cross-sectional SEM image of the semiconductor light-emitting device according to Example 1. [Figure 3B] 2 is a second diagram showing an SEM image of a side surface of a semiconductor laminate of the semiconductor light emitting device according to Example 1. FIG. [Figure 4] 13 is a diagram showing a cross-sectional SEM image of the semiconductor light emitting device according to Example 2. FIG. [Diagram 5] 13 is a diagram showing a cross-sectional SEM image of the semiconductor light emitting device according to Example 3. FIG. [Figure 6] 1 is an explanatory diagram of a notch and an angle θ using a cross-sectional SEM image of a semiconductor light emitting device according to Comparative Example 1. FIG. [Figure 7A] FIG. 1 is a first diagram showing a cross-sectional SEM image of a semiconductor light-emitting device according to Comparative Example 2. [Figure 7B] 2 is a second diagram showing an SEM image of a side surface of a semiconductor laminate of a semiconductor light emitting device according to Comparative Example 2. FIG. [Figure 8] 13 is a diagram showing a cross-sectional SEM image of a semiconductor light-emitting device according to Comparative Example 3. FIG. [Figure 9A]FIG. 1 is a first diagram showing a cross-sectional SEM image of a semiconductor light-emitting device according to Comparative Example 4. [Figure 9B] 2 is a second diagram showing an SEM image of a side surface of a semiconductor laminate of a semiconductor light emitting device according to Comparative Example 4. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Prior to describing the embodiment of the present invention, the following points will be described in advance with reference to FIG. 6 relating to a comparative example.

[0021] <Notch> In this embodiment, the notch means a recess on the side of the semiconductor laminate caused by the active layer being etched faster than the other layers. When a first straight line (A in the figure) circumscribing the side of the first conductive type layer and the side of the second conductive type layer near the active layer and a second straight line (B in the figure) tangent to the side of the active layer parallel to the first straight line are drawn, the second straight line is inside the first straight line (the second straight line is on the semiconductor laminate side), the distance between the first straight line and the second straight line is greater than 10 nm, and the side of the active layer is greatly recessed with respect to the side of the first conductive type layer and the side of the second conductive type layer. When the second straight line is outside the first straight line, when the distance between the first straight line and the second straight line is zero, or when the second straight line is inside the first straight line and the distance between the two straight lines is 10 nm or less, it is considered that there is no notch. In FIG. 6 where there is a notch, the second straight line is inside the first straight line and the distance between the two straight lines is about 400 nm. The presence of a notch may result in a shortcut for current between the first conductive type layer and the second conductive type layer, lowering the reverse voltage. The vicinity of the active layer refers to a range from the interface between the active layer and the first conductive type layer or the interface between the active layer and the second conductive type layer to three times the thickness of the active layer in the thickness direction. As a shape that does not cause a shortcut for current between the first conductive type layer and the second conductive type layer, in the above-mentioned embodiment without a notch, it is preferable that the second straight line is located outside the first straight line, or the distance between the first straight line and the second straight line is zero. When the second straight line is located outside the first straight line, the distance between the two straight lines may be a distance that does not easily damage the active layer, for example, 400 nm or less.

[0022] <Angle θ> In this embodiment, the angle θ refers to the angle made by a third line (C in the figure) connecting the junction between the intermediate electrode layer (dielectric portion) and the side surface of the first conductivity type layer and the junction between the first line (A in the figure) and the side surface of the first conductivity type layer, relative to the side of the upper surface of the intermediate electrode layer (dielectric portion) on which the first conductivity type layer is placed.

[0023] <curvature> In this embodiment, the curvature is the curvature of a line along the side surface that connects the contact point between the intermediate electrode layer (the dielectric part of the intermediate electrode layer) and the side surface of the first conductive type layer, and the contact point of the first straight line (A in the figure) on the side surface of the first conductive type layer (if there is no notch, the contact point between the side surface of the first conductive type layer and the side surface of the active layer). The curvature is calculated by using image measurement software to find a circular arc along three points, including the two contact points and a midpoint that is equidistant from the contact points, and calculating the radius of the circle.

[0024] <Over-etching rate> In this embodiment, the over-etching rate is calculated by dividing the over-etching time by the etching time, where the end time is defined as the point at which the first conductive type layer has disappeared in a part of the street region (the point at which the In plasma emission intensity becomes equal to or lower than a specified value, which is also the timing at which a part of the dielectric portion begins to be exposed) as measured by a plasma emission spectroscopic observation device attached to the dry etching device, and the over-etching time is defined as the etching time performed after the end time.

[0025] In this embodiment, the angle θ and the curvature are evaluated by forming a cross section of the semiconductor light emitting element using a FIB (focused ion beam) or the like, acquiring a cross-sectional SEM (scanning electron microscope) image, and measuring the angle and curvature from the image. The cross-sectional SEM image was acquired with a JEOL FE-SEM_JSM7000F at an acceleration voltage of 5 kV, and the angle θ and the curvature were measured using IC Measure image measurement software manufactured by The Imaging Source.

[0026] In this embodiment, the mass % and atomic % of the elements of each layer on the side surface of the semiconductor laminate are measured by energy dispersive X-ray spectroscopy (EDS) for the side surface of the semiconductor laminate. This makes it possible to confirm the presence or absence of deposition on the side surface near the active layer. The EDS analysis was performed using the above-mentioned FE-SEM_JSM7000F manufactured by JEOL Ltd. at an accelerating voltage of 10 kV.

[0027] In this embodiment, the reverse voltage Vr was measured using an LED tester manufactured by YAC Garter (model number: LX4730A). The wafer before element separation was set in a probe device, a probe was placed on the pad electrode on the upper part of the element, and the reverse voltage (Vr) was measured by passing a reverse current of 0.1 μA. The number of measurements was approximately 5000, and the average value was used.

[0028] In this embodiment, "InGaAlAs" is In, Ga, and Al, where the composition ratios are a, b, and 1-a-b, respectively. a Ga b Al 1-a―b In the present embodiment, the values ​​of the In composition ratio a and the Ga composition ratio b of the InGaAlAs composition ratio are specified from the wavelength observed by photoluminescence measurement performed on the surface of each layer when each layer is grown. Unless otherwise specified, the In composition ratio a and the Ga composition ratio b are 0 or more and 1 or less, and 0≦1-a-b≦1. As a method for specifying the In composition ratio and the Ga composition ratio from the cross section of the semiconductor light emitting device, for example, EDS can be used.

[0029] In this specification, the term "undoped" refers to a layer in which a specific dopant such as Si, S, or Zn is not intentionally added. An undoped layer may contain unavoidable dopants during the manufacturing process.

[0030] Hereinafter, one embodiment of the present invention will be described.

[0031] (Semiconductor light emitting device) The semiconductor light emitting device obtained according to this embodiment will be described.

[0032] 1, the semiconductor light emitting element 1 according to this embodiment includes a reflective layer 91 formed on a support substrate 190, a metal bonding layer 92 formed on the reflective layer 91, an intermediate electrode layer 80 formed on the metal bonding layer 92, a first conductivity type layer 60 formed on the intermediate electrode layer 80, an active layer 50 formed on the first conductivity type layer 60, and a second conductivity type layer 40 formed on the active layer 50. The intermediate electrode layer 80 is composed of a dielectric portion 82 and a conductor portion 81, and the outer periphery of the intermediate electrode layer 80 is the dielectric portion 82.

[0033] The semiconductor light emitting device 1 shown in FIG. 1 has the following features. In the semiconductor light emitting device 1, a dielectric portion 82 exists outside the side surface of a semiconductor laminate 200 having a first conductive type layer 60, an active layer 50, and a second conductive type layer 40. As a result, in the cross section of the device, the dielectric portion of the intermediate electrode layer exists outside the contact point between the intermediate electrode layer and the side surface of the first conductive type layer (the side where the first conductive type layer is not present). When the semiconductor laminate 200 is viewed from above, the semiconductor laminate 200 has a shape in which the upper surface of the dielectric portion 82 can be seen outside the outer periphery of the semiconductor laminate 200. The angle θ formed by the side surface of the first conductive type layer 60 with respect to the dielectric portion 82 is 70° or more and 85° or less. In the present specification, when there is no notch as described above, and a first line circumscribing the side surface of the first conductivity type layer 60 and the side surface of the second conductivity type layer 40 in the vicinity of the active layer and a second line tangent to the side surface of the active layer parallel to the first line are drawn, the second line is located outside the first line, the distance between the first line and the second line is zero, or the second line is located inside the first line and the distance between the two lines is 10 nm or less.

[0034] By virtue of the above configuration, the semiconductor light emitting element 1 has a reverse voltage of 20 V or more when a reverse current of 0.1 μA is applied to the semiconductor light emitting element 1.

[0035] The first conductive type layer 60 may have layers such as an electron blocking layer, a cladding layer, or a contact layer. Similarly, the second conductive type layer 40 may have layers such as a cladding layer or a contact layer. Furthermore, an undoped layer called a spacer layer may be provided between the active layer 50 and the first conductive type layer 60 or between the active layer 50 and the second conductive type layer 40. The first conductive type layer 60 and the second conductive type layer 40 are preferably layers having a larger band gap than the active layer 50.

[0036] The active layer 50 preferably contains one or more of Al, Ga, and In as a group III element, and preferably contains one or more of As, Sb, and P as a group V element. The first conductivity type layer 60 preferably contains one or more of Al, Ga, and In as a group III element, and preferably contains one or more of As, Sb, and P as a group V element. It is preferable that the layer have an emission wavelength of 1000 nm or more.

[0037] The angle θ is preferably 70° or more and 85° or less, more preferably 76° or more and 85° or less, and particularly preferably 77° or more and 84° or less. When it is less than 70°, the street width is increased to create an area without the first conductive type layer 60 having a width that does not affect dicing, thereby reducing the number of chips per wafer, and when it exceeds 85°, the reverse voltage is reduced. Furthermore, the curvature of the line along the side connecting the upper end and the lower end of the side of the first conductive type layer 60 is preferably 0 to 0.11, more preferably 0 to 0.09, and particularly preferably 0.01 to 0.08.

[0038] The dielectric portion 82 is SiO 2 Or SiN is preferable, SiO 2It is more preferable that the weight percentage of Si atoms in the side surface between the interface between the dielectric portion 82 and the first conductive type layer 60 and the center of the thickness of the second conductive type layer 40 (hereinafter also referred to as the main side surface) is 2.5% by weight or less, and the percentage of the number of Si atoms is 5% or less. It is more preferable that the weight percentage of Si atoms is 0.1% by weight or more and 2.5% by weight or less, and particularly preferably 1.0% by weight or more and 2.5% by weight or less. It is also preferable that the dielectric portion 82 is SiO 2 In this case, the weight percentage of O atoms is preferably 0.3% by weight or more and 7.5% by weight or less. Although protective film 70 is shown in Fig. 1, protective film 70 may be omitted. The percentage of the number of Si atoms on the main side surface and the weight percentage of Si or O atoms are preferably measured in a state where protective film 70 is not formed on the side surface.

[0039] Hereinafter, an embodiment of a manufacturing method for obtaining this semiconductor light emitting device 1 and each of the steps therein will be described in detail.

[0040] (Method of manufacturing semiconductor light emitting device) 2A to 2D are process diagrams of the method for manufacturing the semiconductor light-emitting element 1 described above. These diagrams are schematic diagrams of a cross section of a portion of the growth substrate, and for convenience of explanation, the intermediate electrode layer and the electrodes are simplified, and the aspect ratio of the substrate and each layer is exaggerated regardless of the actual aspect ratio. As shown in FIG. 2A to FIG. 2D, in the method for manufacturing the semiconductor light-emitting element 1 according to the present invention, first, each semiconductor layer is formed on the growth substrate 10 by epitaxial growth, and then the intermediate electrode layer 80 is formed. Next, the intermediate electrode layer 80 and the support substrate 190 are bonded via the metal bonding layer 92 and the reflective layer 91 formed on the growth substrate 10 side. Next, the growth substrate is removed. Next, the upper ohmic electrode is formed, and then the mesa is formed by dry etching.

[0041] <Semiconductor layer> The growth substrate 10 may be a compound substrate such as GaAs, InP, or InAs, and may be manufactured according to a conventional method. The growth substrate 10 is preferably n-type doped and has a thickness of 200 μm or more and 900 μm or less. Here, the element doped in the growth substrate 10 may be S or the like. Each semiconductor layer will be briefly described below.

[0042] First, the buffer layer 20 may be epitaxially grown on the growth substrate 10. The buffer layer 20 has a role of reducing the lattice mismatch between the growth substrate 10 and the etching stop layer 30 described later. The buffer layer 20 can be formed by, for example, a metal organic chemical vapor deposition (MOCVD) method. The buffer layer 20 is preferably 0.01 μm or more and 0.5 μm or less in thickness, and is preferably n-type doped. Here, an element to be doped in the buffer layer 20 includes Si and the like. Next, the etching stop layer 30 is laminated on the buffer layer 20. The etching stop layer 30 is preferably not etched under the conditions for etching the growth substrate 10 and the buffer layer 20, and is preferably lattice-matched with the second conductive type layer 40. The etching stop layer 30 is preferably 0.01 μm or more and 0.1 μm or less in thickness, and more preferably 0.02 μm or more and 0.05 μm or less in thickness. The etching stop layer 30 is preferably n-type doped, and examples of the doped element include Si. Next, the second conductive type layer 40 is laminated on the etching stop layer 30. The thickness of the second conductive type layer 40 is sufficient to supply carriers, and is preferably, for example, 2 μm to 10 μm. The second conductive type layer 40 is preferably n-type doped, and examples of the doped element include Si.

[0043] Furthermore, an active layer 50 is laminated on the second conductive type layer 40. As described above, the active layer 50 preferably contains one or more of Al, Ga, and In as a group III element, and preferably contains one or more of As, Sb, and P as a group V element. The active layer 50 may have a single layer structure, a double heterostructure (DH) structure, or a multiple quantum well structure in which multiple barrier layers and well layers are alternately laminated. In the figures of this embodiment, a multiple quantum well structure is illustrated as an example.

[0044] Next, the first conductive type layer 60 is laminated on the active layer 50. The first conductive type layer 60 may have an electron block layer on the active layer 50 side. As described above, the first conductive type layer 60 preferably contains one or more of Al, Ga, and In as a group III element, and preferably contains one or more of As, Sb, and P as a group V element. The thickness of the first conductive type layer 60 is preferably 0.4 μm to 5 μm, and more preferably 1 μm to 3 μm. In addition, the first conductive type layer 60 is preferably p-type doped, and an example of the doped element here is Zn. The semiconductor layer (the second conductive type layer 40 to the first conductive type layer 60) laminated on the etching stop layer 30 on the growth substrate 10 is called the semiconductor laminate 200.

[0045] <Intermediate electrode layer> The intermediate electrode layer 80 is formed on the first conductive type layer 60. First, it is preferable to apply a resist to the entire surface of the first conductive type layer 60. The resist is patterned into a predetermined shape by photolithography, and the semiconductor layer of the first conductive type layer 60 is exposed only in the area where the conductor portion 81 described later is to be formed. Next, it is preferable to deposit a metal film on the first conductive type layer 60 including the patterned resist. Examples of metals used here include AuZn. The resist and the metal film on the resist are removed by lift-off, so that the conductor portion 81 of a desired pattern is formed on the first conductive type layer 60. It is preferable to perform a heat treatment by RTA (high temperature short time annealing) on ​​the conductor portion 81. A contact layer that is highly doped in the first conductive type layer 60 may be patterned and arranged on the first conductive type layer 60 side of the conductor portion 81.

[0046] Next, the dielectric portion 82 is formed on the outer periphery of the conductor portion 81 on the first conductive type layer 60. It is preferable to deposit an insulating film on the first conductive type layer 60 including the conductor portion 81. The insulating film used here is SiO 2 Or SiN is preferable. After the insulating film is formed, the insulating film on the conductor portion 81 is removed by etching using a resist mask pattern, and then the remaining resist is removed by lift-off to form the dielectric portion 82. As a method for forming the metal film and insulating film, known methods such as sputtering or plasma CVD can be applied. The thickness of the intermediate electrode layer 80 is not limited, but can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm, and even more preferably 430 nm to 640 nm.

[0047] <Reflection layer formation> As shown in FIG. 2B, a reflective layer 91 is formed on the intermediate electrode layer 80. The reflective layer 91 may include a plurality of metal layers, and the metal constituting the reflective layer 91 may be Al, Pt, Ti, Ag, or the like in addition to Au. For example, the reflective layer 91 may be a single layer made of Au alone, or may include two or more Au metal layers. The reflective layer 91 preferably contains 50 mass % or more of Au in its composition, and further, in order to ensure bonding with the metal bonding layer 92 in the subsequent process, it is preferable that the outermost layer of the reflective layer 91 (the surface opposite to the intermediate electrode layer 80) is an Au metal layer.

[0048] For example, the reflective layer 91 can be formed by depositing each metal in the order of Al, Au, Pt, and Au on the intermediate electrode layer 80. The thickness of the Au on the outermost surface of the reflective layer 91 can be, for example, 400 nm to 2000 nm, and the thickness of the metal layer made of a metal other than Au can be, for example, 5 nm to 200 nm. The reflective layer 91 can be formed by depositing a film using a general method such as a vapor deposition method.

[0049] A metal bonding layer 92 is formed on the support substrate 190 by laminating metals such as Ti, Pt, Au, or a metal (such as Sn) that forms a eutectic alloy with Au, or solder. For example, the metal bonding layer 92 can be formed by laminating, in order from the surface of the support substrate 190, Ti having a thickness of 400 nm to 800 nm, Pt having a thickness of 5 nm to 20 nm, and Au having a thickness of 700 nm to 1200 nm. In order to ensure bonding to the above-mentioned reflective layer 91, it is preferable that the outermost surface of the metal bonding layer 92 (the surface opposite to the support substrate) is also an Au metal layer. In this case, bonding between Au layers can be achieved by Au-Au diffusion.

[0050] <Joining with supporting substrate> The bonding to the support substrate 190 will be described with reference to Fig. 2B. The semiconductor laminate 200 and the intermediate electrode layer 80 are bonded to the support substrate 190 via the reflective layer 91 and the metal bonding layer 92. The metal bonding layer 92 and the reflective layer 91 are placed opposite each other and bonded together, and then heated and compressed at 250°C to 500°C with a surface pressure of 5 kN to 15 kN for 20 minutes to 40 minutes, thereby bonding the two together.

[0051] The support substrate 190 will be described. The support substrate 190 may be a substrate of a different type from the growth substrate 10, and may be a submount substrate based on the semiconductor substrate, metal substrate, or ceramic substrate described above. Since the above-mentioned bonding method is used, the support substrate 190 may be lattice-mismatched with each semiconductor layer formed in this embodiment. The support substrate 190 may be insulating depending on the application, but is preferably a conductive substrate. By using a Si substrate, the thickness of the support substrate 190 can be significantly reduced compared to the conventional method, and it is also suitable for mounting in combination with various semiconductor devices. In addition, the Si substrate is also advantageous in terms of heat dissipation.

[0052] <Removal of growth substrate> The removal of the growth substrate 10 will be described with reference to FIG. 2C. After the support substrate 190 is bonded, the growth substrate 10 is removed. When the growth substrate 10 is an InP substrate, for example, it can be wet-etched using diluted hydrochloric acid. Alternatively, parts of the growth substrate 10, the buffer layer 20, and the etching stop layer 30 may be removed by polishing.

[0053] After removing the growth substrate 10, it is preferable to form an ohmic electrode (not shown) on the upper surface of the semiconductor layer (the surface opposite to the support substrate 190). The ohmic electrode can be formed using a metal such as Au, Ge, Ni, Ti, or a metal (such as Sn) that forms a eutectic alloy with Au, or solder. The ohmic electrode can be formed by depositing a film using a general method such as a vapor deposition method. The thickness of the ohmic electrode is not limited, but can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm.

[0054] After forming the ohmic electrode, it is preferable to form a pad electrode on the ohmic electrode. The pad electrode can be formed using a metal such as Ti or Au, a metal that forms a eutectic alloy with Au (Sn, etc.), or solder. The pad electrode can be formed by using a general method such as a vapor deposition method.

[0055] After the pad electrode is formed, the surface of the ohmic electrode is roughened except for the surface of the pad electrode. This is because roughening improves the light extraction efficiency. The surface of the ohmic electrode can be roughened by a general method such as selective etching using a mask. The non-roughened ohmic electrode and pad electrode are combined to form the top ohmic electrode and pad electrode 170.

[0056] <Mesa formation process> As shown in FIG. 2D, a part of the semiconductor laminate 200 is removed by dry etching to form a side surface on the semiconductor laminate 200. The dry etching method is preferably reactive ion etching (RIE), and an inductively coupled plasma (ICP) can be used as a plasma source. Dry etching is performed on a street region having a certain width along the planned chip division line when viewed from above. The width of the street region (street width) is a width required for performing chip division without adversely affecting the active layer, etc., and is, for example, 40 to 100 μm. The street region can be in a lattice shape, and the pad electrode formed above or the conductor part 81 of the intermediate electrode layer 80 is disposed in the region other than the street region when viewed from above. A mask (for example, SiO 2 After forming a mask (mask), dry etching is performed on the street region. Here, the dry etching is performed until the dielectric portion 82 of the intermediate electrode layer 80 is exposed outside the side surface of the semiconductor laminate 200. Furthermore, the angle θ between the dielectric portion 82 and the first conductivity type layer 60 is 70° or more and 85° or less, and the dry etching conditions are optimized so that no notch is generated on the side surface of the active layer 50. The dry etching conditions are as follows: a stage temperature of 180° C. or more and 200° C. or less, and a gas type of SiCl 4Preferably, the gas mixture is a mixture of Ar and SiO2, the pressure is 0.2 Pa to 1.0 Pa, the bias power is 50 W to 150 W, and the ICP power is 190 W to 400 W. More preferably, the stage temperature is 190° C. to 200° C., the pressure is 0.2 Pa to 0.6 Pa, the bias power is 70 W to 150 W, and the ICP power is 190 W to 250 W. More preferably, the overetching rate is 1% to 9%, more preferably 3% to 7%, and more preferably 6% or less. If the overetching rate is less than 0 to 1%, it is not possible to create a region without the first conductive type layer 60 having a width that does not affect dicing, and there is a risk that the street width will be increased and the number of chips per wafer will be reduced.

[0057] Mask SiO 2 and SiO of the dielectric portion 82 2 Although the etching rate of the mask is low, it is not completely etched. The SiO 2 Since the Si atoms or oxygen atoms scattered from the SiO 2 hardly reach the side surface of the semiconductor laminate 200, problems caused by the Si atoms or oxygen atoms adhering to the side surface of the semiconductor laminate 200 do not occur when the conventional dielectric portion 82 is not provided or etching is not performed until the dielectric portion 82 is exposed. 2 In this configuration, the dry etching is performed until the SiO of the dielectric portion 82 is exposed. 2 In this case, a problem occurred in that Si atoms or oxygen atoms scattered from the intermediate electrode layer 80 collided with the side surface of the semiconductor laminate 200. By suppressing the overetching rate as in the present invention and setting the angle θ between the intermediate electrode layer 80 (the dielectric portion 82 of the intermediate electrode layer 80) and the first conductive type layer 60 to 70° or more and 85° or less, the SiO 2 It is believed that the amount of particles colliding with the side surface near the active layer of the semiconductor laminate 200 was reduced based on the relationship between the amount of particles scattered from the semiconductor laminate 200 and the scattering angle.

[0058] By appropriately adjusting the dry etching conditions, it is preferable that the weight percentage of Si atoms in the side (main side) between the interface between the dielectric portion 82 and the first conductivity type layer 60 and the center of the thickness of the second conductivity type layer 40 is 2.5% by weight or less and the percentage of the number of Si atoms is 5% or less, as determined by EDS analysis. The weight percentage of Si atoms is more preferably 0.1% by weight or more and 2.5% by weight or less, and particularly preferably 1.0% by weight or more and 2.5% by weight or less. In addition, when the dielectric portion 82 is SiO 2 In this case, the weight percentage of O atoms is preferably 0.3% by weight or more and 7.5% by weight or less. The percentage of the number of Si atoms and the weight percentage of Si or O atoms on the main side surface are preferably measured in a state where a protective film 70 described later is not formed on the side surface.

[0059] After the mesa formation process, it is preferable to form a protective film 70 by using plasma CVD or the like. The protective film used at this time is SiO 2 The SiO mask in the mesa formation process is 2may be a part of the protective film 70. It is also preferable that the protective film 70 does not cover the upper surface of the pad electrode. The thickness of the protective film 70 is preferably 50 nm or more and 500 nm or less. Next, in order to adjust the thickness of the entire semiconductor light emitting device, it is preferable to adjust the thickness by polishing or etching the support substrate 190. In this embodiment, there is no limit to the thickness of the entire semiconductor light emitting device, but it is preferably 2.4 μm or more and 15 μm or less. Next, it is preferable to form the back ohmic electrode 160 on the back surface of the support substrate 190. The back ohmic electrode 160 can be formed using a metal such as Ti, Pt, or Au, or a metal (Sn, etc.) that forms a eutectic alloy with Au, or solder. The back ohmic electrode 160 can be formed by depositing a film using a general means such as a vapor deposition method. The thickness of the back ohmic electrode 160 is not limited, but can be, for example, 300 nm or more and 1300 nm or less, more preferably 350 nm or more and 800 nm or less. It is preferable to heat-treat the formed back ohmic electrode 160 by RTA. Finally, it is preferable to perform dicing using a dicer or a scriber to separate the semiconductor light emitting elements.

[0060] The key to this invention is that we found that the shape, angle θ, and curvature of the main side surface can be kept within a certain range by optimizing the overetching time in the etching conditions for mesa formation. The leakage current is suppressed by setting the angle θ to 85° or less. The reason for this is that when dry etching is performed under conditions where the angle θ is 85° or less, the overetching rate is small, so deposition on the side surface of the active layer is reduced, and the leakage current caused by the deposition is suppressed, which may have improved the reverse bias characteristics.

[0061] Furthermore, it is preferable not to roughen the side surfaces of the semiconductor laminate 200 after the mesa formation step. This is because roughening may result in the formation of notches. It is preferable to roughen the top surface of the semiconductor laminate 200. It is more preferable that the range of the top surface of the semiconductor laminate 200 to be roughened excludes the street region, the top surface ohmic electrode, and the pad electrode 170 and their vicinity.

[0062] The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples in any way. EXAMPLES

[0063] Example 1 n-type InP growth substrate (thickness: 600 μm, S-doped, dopant concentration: 2.0 × 10 18 / cm 3 ) by MOCVD, an n-type InP buffer layer (thickness: 0.1 μm, Si doped, dopant concentration: 5.0 × 10 17 / cm 3 ), n-type In 0.57 Ga 0.43 As etching stop layer (thickness: 0.02 μm, Si doped, dopant concentration: 5.0 × 10 17 / cm 3 ), n-type InP cladding layer (thickness: 3.5 μm, Si doped, dopant concentration: 5.0 × 10 17 / cm 3 Next, undoped In was formed as the active layer. 0.42 Ga 0.42 Al 0.16 As barrier layer and undoped InGa 0.195 Al 0.04 A multi-quantum well structure is formed by using an 8-nm-thick InAs well layer. 0.42 Ga 0.42 Al 0.16 After forming an As barrier layer, a 10 nm thick InGa 0.195 Al 0.04 As well layer and 8-nm-thick In 0.42 Ga 0.42 Al 0.16The first barrier layer was replaced by an undoped In / As barrier layer, forming a multi-quantum well structure with 10.5 pairs of layers. 0.522 Al 0.478 As electron blocking layer (thickness: 0.02 μm), p-type InP cladding layer (thickness: 2.4 μm, Zn doped, dopant concentration: 7.0 × 10 17 / cm 3 The thickness and dopant concentration of each semiconductor layer described here are the design values ​​at the time of growth of each layer.

[0064] Next, resist was applied to the entire surface of the p-type InP cladding layer. The resist was patterned into a specified shape by photolithography, and the resist was removed from the area where the conductor section was to be formed, exposing the p-type InP cladding layer. AuZn (thickness: 550 nm) was evaporated onto the p-type InP cladding layer, including on the resist, by sputtering. After that, the resist and the AuZn on the resist were removed by lift-off. Furthermore, a heat treatment was performed by RTA (conditions: 300°C). This allowed the conductor section of the intermediate electrode layer to be formed.

[0065] Next, SiO was deposited on the p-type InP cladding layer including the conductive portion by plasma CVD. 2 An insulating film (thickness: 700 nm) was formed. 2 A resist is applied onto the insulating film, and the SiO 2 The dielectric portion can be formed by removing the insulating film by etching and then removing the remaining resist by lift-off. This results in the formation of an intermediate electrode layer composed of a dielectric portion and a conductor portion, with the outer periphery being the dielectric portion. Note that there is a constant gap between the dielectric portion and the conductor portion, and the thickness of the dielectric portion is thicker than the thickness of the conductor portion.

[0066] A reflective layer (Ti (thickness: 2 nm) / Au (thickness: 650 nm) / Pt (thickness: 100 nm) / Au (thickness: 900 nm)) was formed on the intermediate electrode layer by vapor deposition, and a metal bonding layer (Ti (thickness: 650 nm) / Pt (thickness: 20 nm) / Au (thickness: 900 nm)) was formed on a support substrate (Si substrate) by vapor deposition. The reflective layer and the metal bonding layer were placed facing each other and subjected to thermal compression bonding at a surface pressure of 10 kN and 350°C for 30 minutes. Although not shown in the figure, at this time, the gap between the dielectric part and the conductor part and the thickness of the dielectric part were thicker than the thickness of the conductor part, so that a recess in the reflective layer occurred at a position corresponding to the conductor part and its periphery, resulting in a gap at the interface between the reflective layer and the metal bonding layer.

[0067] Next, the growth substrate and the buffer layer were removed by wet etching using diluted hydrochloric acid to expose the etching stop layer. The etching stop layer was masked by photolithography to leave the positions where the upper ohmic electrode and the pad electrode were to be formed as contact layers, and the other areas were removed by wet etching using a tartaric acid-hydrogen peroxide mixture.

[0068] The mask was removed to expose the etching stop layer, and Au (thickness: 10 nm) / Ge (thickness: 30 nm) / Au (thickness: 60 nm) / Ni (thickness: 30 nm) / Au (thickness: 800 nm) / Ti (thickness: 100 nm) / Au (thickness: 1000 nm) were formed by deposition on the etching stop layer to form the upper ohmic electrode. Next, a pad electrode (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was formed on the upper ohmic electrode by deposition. The lift-off method using resist was used to form the electrode pattern.

[0069] Next, a resist mask was formed by photolithography to cover the street region along the chip division line as well as the upper ohmic electrode and the pad electrode, and the light extraction surface of the n-type InP cladding layer other than the masked region was roughened by wet etching. Since the street region was not roughened by covering it with a mask, the street region covered by the mask became a bank-shaped non-etched region surrounding the roughened recessed portion as observed in FIG. 3A. By forming this non-etched region, a mask exposed region along the chip division line described later can be formed on the upper flat surface of the region, which is preferable because it is possible to suppress meandering or abnormality of the mesa shape caused by dry etching.

[0070] Next, SiO 2 After forming the SiO 2 layer, a mask pattern is formed using a resist and then etched to expose the street areas along the planned chip division lines. 2 A mask was formed. The width of the street region exposed by the mask pattern was 55 μm. Dry etching (ICP-RIE) was performed to expose the dielectric portion of the periphery of the intermediate electrode layer in the street region, and to expose the side surfaces from the p-type InP clad layer to the n-type InP clad layer. The etching conditions were dry etching, stage temperature 200°C, pressure 0.2 Pa, bias power 150 W, ICP power 190 W, overetching rate 5%, and ratio of gas species used SiCl 4 :Ar=4:8.

[0071] After the mesa is formed, the SiO 2 After removing the mask, the entire surface (the remaining SiO 2A SiN film was formed as a protective film on the upper surface of the mask and on the exposed side and street regions of the semiconductor laminate. Then, the SiN on the upper surface of the pad electrode was removed by etching using a resist mask pattern, and then the resist was removed. The thickness of the SiN was 190 μm. Next, the rear surface of the support substrate was polished (by polishing or etching) to make the thickness of the entire semiconductor light emitting device 150 μm. Next, a rear ohmic electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the rear surface of the support substrate by deposition, and heat treatment was performed at 300° C. for 60 seconds by RTA. Finally, the semiconductor light emitting device according to Example 1 was produced by separating the semiconductor light emitting device into individual rectangular elements with a chip size of 250 μm×250 μm using laser dicing.

[0072] Example 2 The etching conditions for mesa formation were dry etching, stage temperature 200°C, pressure 0.2 Pa, bias power 150 W, ICP power 190 W, overetching rate 5%, and ratio of gas species used SiCl 4 A semiconductor light emitting device according to Example 2 was obtained in the same manner as in Example 1, except that Ar=7:14.

[0073] Example 3 The etching conditions for mesa formation were dry etching, stage temperature 200°C, pressure 0.25 Pa, bias power 100 W, ICP power 190 W, overetching rate 5%, and ratio of gas species used was SiCl 4 A semiconductor light emitting device according to Example 3 was obtained in the same manner as in Example 1, except that Ar=9:20.

[0074] Comparative Example 1 A semiconductor light-emitting element according to Comparative Example 1 was obtained in the same manner as in Example 1, except that the etching method for forming the mesa was wet etching, the etching solution was Br-MeOH, the immersion time was 20 minutes, and the above-mentioned top surface roughening was not performed, but rather the top surface and side surface of the semiconductor laminate were roughened by wet etching immediately after the mesa formation.

[0075] Comparative Example 2 The etching conditions for mesa formation were dry etching, stage temperature 200°C, pressure 0.25 Pa, bias power 100 W, ICP power 190 W, overetching rate 10%, and the ratio of gas species used was SiCl 4 A semiconductor light emitting device according to Comparative Example 2 was obtained in the same manner as in Example 1, except that:Ar=9:20.

[0076] Comparative Example 3 The etching conditions for mesa formation were dry etching, stage temperature 200°C, pressure 0.2 Pa, bias power 150 W, ICP power 190 W, overetching rate 15%, and ratio of gas species used was SiCl 4 A semiconductor light emitting device according to Comparative Example 3 was obtained in the same manner as in Example 1, except that:Ar=7:14.

[0077] Comparative Example 4 The etching conditions for mesa formation were dry etching, stage temperature 200°C, pressure 0.25 Pa, bias power 100 W, ICP power 190 W, overetching rate 15%, and the ratio of gas species used was SiCl 4 Except for changing the Ar ratio to 9:20, a semiconductor light-emitting device according to Comparative Example 4 was obtained in the same manner as in Example 1. Table 1 below shows the etching methods and conditions used for forming the mesas in Examples 1 to 3 and Comparative Examples 1 to 4.

[0078] [Table 1]

[0079] Cross-sectional SEM images of Examples 1 to 3 and Comparative Examples 1 to 4 were obtained, and the shape of the main side surface, the angle θ, the curvature, the presence or absence of a notch on the side surface of the active layer, and the distance between the first straight line and the second straight line were measured. Figures 3A to 5 correspond to Examples 1 to 3, respectively, and Figures 6 to 9B correspond to Comparative Examples 1 to 4, respectively. As described above, the cross-sectional SEM images were obtained using an FE-SEM_JSM7000F manufactured by JEOL Ltd., and photographed at an acceleration voltage of 5 kV. Figures 3A, 4, 5, 6, 7A, 8, and 9A are cross-sectional SEM images of the completed element. Also, the angle θ and the curvature were measured using IC Measure, an image measurement software manufactured by The Imaging Source, as described above. Furthermore, for the elements of Example 1, Example 3, Comparative Example 2, and Comparative Example 4 after the mesa formation and before the protective film formation, SEM images of the main side of the semiconductor laminate were obtained as shown in Figures 3B, 7B, and 9B, and the above main side was subjected to EDS analysis using an FE-SEM_JSM7000F at an acceleration voltage of 10 kV. In the EDS analysis, measurements were taken at 10 points at equal intervals in the thickness direction of the main side, and the measurement points within the half-thickness range on the side away from the active layer in the second conductive type layer were excluded, and the average value of the wt% of Si atoms and oxygen atoms was calculated for the measurement points from the first conductive type layer including the side of the active layer to the half-thickness on the active layer side of the second conductive type layer. Then, the amount of deposition on the side of the active layer was evaluated from the weight ratio of Si atoms obtained by the EDS analysis. Furthermore, using the LED tester (model number: LX4730A) manufactured by YAC Garter mentioned above, the wafer before being singulated was set in a probing device, the probe was placed on the pad electrode on the top of the element, and a current of 0.1 μA was applied to measure the reverse voltage (Vr). 5,000 points were measured, and the average value was used. The results are shown in Table 2.

[0080] [Table 2]

[0081] As shown in Table 2, when a first straight line circumscribing the side surface of the first conductive type layer and the side surface of the second conductive type layer in the vicinity of the active layer in the cross-sectional SEM images of Examples 1 to 3 and Comparative Examples 1 to 4 and a second straight line tangent to the side surface of the active layer parallel to the first straight line were drawn, the distance between the first straight line and the second straight line was checked. In Comparative Example 1 (FIG. 6), the second straight line was inside the first straight line and the distance was 430 nm, but in Examples 1 to 3 and Comparative Examples 2 to 4, the second straight line was outside the first straight line or the distance was zero. Note that the value of the distance is indicated as negative when the second straight line is inside the first straight line and concave, and indicated as positive when the second straight line is outside the first straight line and convex.

[0082] From Table 2, it was confirmed that when the mesa is formed and roughened by wet etching, the side of the active layer is largely etched, causing notches, which leads to poor reverse current characteristics of the semiconductor light emitting device. On the other hand, it was confirmed that when the mesa is formed by dry etching without roughening the main side, no notches are formed, but this alone is not sufficient to improve the poor reverse current characteristics of the semiconductor light emitting device. If the overetching time is short, the exposed SiO 2 If the overetching time is short, side etching progresses toward the support substrate side, and the angle θ is 70° or more and 85° or less. 2 As the etching time for the overetching is long, side etching of the supporting substrate side progresses and the angle θ becomes closer to perpendicular. Table 2 confirms that, under the dry etching conditions, when the overetching time is extended, the angle θ becomes closer to perpendicular and the amount of deposition increases. It was confirmed that by optimizing the overetching time (rate) and setting the angle θ to 70° or more and 85°, a semiconductor light-emitting device with a large reverse voltage (Vr) can be fabricated.

[0083] [Table 3]

[0084] Table 3 shows the number of measured chips, the average value (V), and the standard deviation (V) of the reverse voltage (Vr) when a reverse current of 0.1 μA was applied to the semiconductor light-emitting devices of Examples 1 to 3 and Comparative Examples 2 to 4. It can be seen that Examples 1 to 3 not only have an average value exceeding 20 V, but also a small standard deviation. This shows that high yield production is possible by performing etching during mesa formation under the conditions of the present invention. [Explanation of symbols]

[0085] 1. Semiconductor light emitting device 10 Growth substrate 20 Buffer Layer 30 Etching stop layer 40 Second conductive layer 50 active layer 60 First conductive layer 70 Protective film 80 Intermediate electrode layer 81 Conductor part 82 Dielectric section 91 Reflective layer 92 Metal bonding layer 160 Backside ohmic electrode 170 Top Ohmic Electrode and Pad Electrode 190 Support substrate 200 Semiconductor laminate

Claims

1. A reflective layer formed on a supporting substrate; an intermediate electrode layer formed on the reflective layer; a first conductive type layer formed on the intermediate electrode layer; an active layer formed on the first conductivity type layer; a second conductive type layer formed on the active layer; A semiconductor device comprising: the intermediate electrode layer is composed of a dielectric portion and a conductor portion, the outer periphery being the dielectric portion, the dielectric portion is present outside a side surface of a semiconductor laminate having the first conductive type layer, the active layer, and the second conductive type layer, In a cross section of the semiconductor element, when a first straight line circumscribing a side surface of the first conductive type layer and a side surface of the second conductive type layer in the vicinity of the active layer and a second straight line tangent to the side surface of the active layer and parallel to the first straight line are drawn, the second straight line is located outside the first straight line, a distance between the first straight line and the second straight line is zero, or the second straight line is located inside the first straight line and a distance between the two straight lines is 10 nm or less, a third straight line connecting a contact point between the intermediate electrode layer and a side surface of the first conductive type layer and a contact point of the first straight line on the first conductive type layer side, the third straight line forming an angle of 70° or more and 85° or less with respect to a side of the upper surface of the intermediate electrode layer on which the first conductive type layer is placed; Semiconductor light emitting element.

2. the active layer contains one or more of Al, Ga, and In as a group III element, and one or more of As, Sb, and P as a group V element, The first conductive type layer contains one or more of Al, Ga, and In as a group III element, and one or more of As, Sb, and P as a group V element. The semiconductor light emitting device according to claim 1 .

3. The reverse voltage is 20 V or more when a reverse current of 0.1 μA is applied. The semiconductor light emitting device according to claim 1 .

4. a curvature of a line connecting an upper end and a lower end of a side surface of the first conductive type layer along the side surface is equal to or greater than 0 and equal to or less than 0.11; The semiconductor light emitting device according to claim 1 .

5. The dielectric portion is made of SiO ２ Or SiN; The semiconductor light emitting device according to claim 1 .

6. a weight ratio of Si atoms on a side surface between an interface between the dielectric portion and the first conductive type layer and a center of a thickness of the second conductive type layer is 2.5% by weight or less; The semiconductor light emitting device according to claim 1 .

7. The dielectric portion is made of SiO ２ a weight ratio of O atoms on a side surface between an interface between the dielectric portion and the first conductive type layer and a center of a thickness of the second conductive type layer is 7.5% by weight or less. The semiconductor light emitting device according to claim 1 .

8. forming an etch stop layer on the growth substrate; forming a second conductivity type layer on the etching stop layer; forming an active layer on the second conductivity type layer; forming a first conductivity type layer on the active layer; forming an intermediate electrode layer on the first conductive type layer, the intermediate electrode layer including a dielectric portion and a conductive portion, the outer periphery of the intermediate electrode layer being the dielectric portion; forming a reflective layer on the intermediate electrode layer; forming a metal bonding layer on a support substrate; bonding the reflective layer and the metal bonding layer; removing the growth substrate; A method for manufacturing a semiconductor light emitting device comprising the steps of: a mesa forming step of forming a side surface of the semiconductor laminate by removing a semiconductor laminate from the second conductive type layer to the first conductive type layer by a dry etching method along a chip dividing line; In a cross section of the semiconductor element, when a first line circumscribing a side surface of the first conductivity type layer and a side surface of the second conductivity type layer in the vicinity of the active layer and a second line tangent to the side surface of the active layer and parallel to the first line are drawn, the second line is located outside the first line, a distance between the first line and the second line is zero, or the second line is located inside the first line and a distance between the two lines is 10 nm or less, a third straight line connecting a contact point between the intermediate electrode layer and a side surface of the first conductive type layer and a contact point of the first straight line on the first conductive type layer side, the third straight line forming an angle of 70° or more and 85° or less with respect to a side of the upper surface of the intermediate electrode layer on which the first conductive type layer is placed; A method for manufacturing a semiconductor light emitting device.

9. The overetching rate in the dry etching method is set to 1% or more and 9% or less. The method for manufacturing a semiconductor light emitting device according to claim 8 .

10. 9. The method for manufacturing a semiconductor light-emitting element according to claim 8, wherein a weight percentage of Si atoms on a side surface between an interface between the dielectric portion and the first conductive type layer and a center of a thickness of the second conductive type layer immediately after the mesa formation step is 2.5 weight % or less.

Images