Encoder speed monitoring device

Abstract

To provide a speed monitoring device that can accurately detect a velocity anomaly.SOLUTION: A rotation speed monitoring device comprises a second MCU 4b that outputs a second count value C2 by clearing a counter with the Z-phase signal. The second MCU 4b comprises a phase counting counter 6b that counts an A-phase signal and a B-phase signal and outputs them as a base count value Cb, a first capture circuit 7a that latches the base count value Cb with a capture cycle Ts and outputs it as a position count value Cp, a second capture circuit 7b that latches the base count value Cb with the active edge of the Z-phase signal and outputs it as a reference count value Cz, and a second counter arithmetic part 9 that calculates the second count value C2 based on the position count value Cp and the reference count value Cz.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] This specification discloses a speed monitoring device using an encoder that outputs signals with a phase difference according to a rotation angle. [Background technology]

[0002] International standards require a speed limit monitoring function for the spindles of machine tools. For example, ISO23125 requires that the spindles of lathes be equipped with speed limit monitoring in safety category 3.

[0003] Generally, the speed detector used for the spindle of a machine tool is a type that outputs cosine signals, sine signals, etc. with a phase difference of 90 degrees at N wave numbers per rotation according to the rotation angle, such as a magnetic encoder (hereafter referred to as an "encoder"). Usually, these signals are called A-phase signals and B-phase signals.

[0004] When speed monitoring is performed using this encoder, the difference between count values ​​during speed monitoring cycles is usually used using the count value of a phase difference counter that performs a 4-times pulse count based on the phase difference between the A-phase signal and the B-phase signal. That is, the safety controller that performs speed monitoring samples the count value of the phase difference counter every monitoring cycle T, and calculates the monitored speed V as V=(P(n)-P(n-1)) / (T×4×N) where the current count value is P(n) and the previous count value is P(n-1). Therefore, to correctly monitor speed using the phase difference counter, the number of waves per revolution N set in the phase difference counter must match the number of waves per revolution N of the actual encoder. Sampling of the phase difference counter by the safety controller is performed, for example, in safety communication where the reliability of communication data is guaranteed by a protocol.

[0005] Furthermore, to achieve speed monitoring in safety category 3 using this encoder, it is necessary to use two phase difference counters with different elements and compare the speeds (difference in pulse counts) calculated by each to monitor each other. Also, encoders usually have a marker signal that outputs one pulse per rotation, called a Z-phase signal, to identify the position within one rotation. Furthermore, one of the phase difference counters is configured by combining an in-rotation counter that is cleared by the Z-phase signal, and a multi-rotation counter that counts up and down the Z-phase signal.

[0006] Then, by calculating the speed based on a phase difference counter that combines the within-one-revolution counter and the multi-revolution counter using a Z-phase signal, and the speed based on a phase difference counter that does not use a Z-phase signal, and comparing the two obtained speeds, it is possible to confirm whether the number of waves per revolution of the encoder is correct.

[0007] A counter using a Z-phase signal is disclosed, for example, in Non-Patent Document 1. Non-Patent Document 1 discloses a microcontroller unit (hereinafter referred to as "MCU") equipped with a function for clearing a one-rotation counter by the rising edge of a Z-phase signal, and for counting up or down a multi-rotation counter depending on the count-up or count-down direction of the immediately preceding one-rotation counter.

[0008] Furthermore, Patent Document 1 discloses a method for clearing the within-revolution counter and counting up and down the multi-revolution counter based on the logical level of the Z-phase signal and the rising or falling edges of the A-phase signal and B-phase signal, rather than on the edge of the Z-phase signal. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2009-153335 A [Non-patent literature]

[0010] [Non-Patent Document 1] “32-Bit Microcontroller FM0+ Family Peripheral Manual Timer Part”, Cypress Semiconductor Corporation, September 9, 2020 Summary of the Invention [Problem to be solved by the invention]

[0011] In the counter implemented in the general-purpose MCU described in Non-Patent Document 1, when only the Z-phase signal changes without changes in the A-phase signal and B-phase signal, such as when the Z-phase signal vibrates at an angle where the edge changes, the multi-turn counter repeatedly counts up or down, making it impossible to monitor the speed correctly. For example, as shown in Figure 3, if vibration of less than one count continues near the edge of the Z-phase signal after forward rotation, the multi-turn counter repeatedly counts up at each rising edge of the Z-phase signal.

[0012] In addition, if the pulse width of the Z-phase signal is wide, an error occurs in the speed monitoring by the count of the pulse width when the direction of rotation is changed. For example, Figure 4 is an example of a timing chart when switching from forward rotation to reverse rotation and passing the Z-phase signal. In the example of Figure 4, there is a 6-count difference between the Z-phase rising edge during forward rotation (Figure 4(a)) and the Z-phase rising edge during reverse rotation (Figure 4(b)). Therefore, at the first Z-phase rising edge after the direction of rotation changes, a 6-count difference occurs between the phase difference counter using the Z-phase signal and the phase difference counter not using the Z-phase signal. Due to these factors, a difference occurs in the difference in count value with the phase difference counter not using the Z-phase signal, and the safety controller erroneously detects an abnormality in the speed monitoring interface.

[0013] In addition, according to the counter circuit described in Patent Document 1, it is possible to accurately configure a multi-turn counter and a within-one-turn counter using a Z-phase signal, but such a counter circuit is not installed in a general-purpose MCU. Therefore, in order to realize a counter equivalent to that in Patent Document 1 using a general-purpose MCU, it is necessary to add a complex logic circuit outside the MCU, which leads to increased costs and an increase in the probability of dangerous failure (PFHD). In addition, the frequency of the A-phase signal and the B-phase signal may exceed 100 kHz, and it is difficult to simply replace the processing equivalent to that of the counter circuit described in Patent Document 1 with software processing of the MCU. [Means for solving the problem]

[0014] The rotation speed monitoring device disclosed in this specification is a rotation speed monitoring device for monitoring the rotation speed of an object, and includes an encoder that outputs an A-phase signal of N pulses per rotation, a B-phase signal that is 90 degrees out of phase with the A-phase signal, and a Z-phase signal of one pulse per rotation, a first unit that outputs a first count value by quadruple phase counting based on the A-phase signal and the B-phase signal, a count value within one rotation obtained by counter clearing the count value obtained by quadruple phase counting based on the A-phase signal and the B-phase signal based on the Z-phase signal, and a multi-rotation count value obtained by counting up or down the Z-phase signal according to the rotation direction; and a safety controller that calculates a first monitoring speed based on the amount of change in the first count value, calculates a second monitoring speed based on the amount of change in the second count value, and determines whether or not there is a speed abnormality based on a comparison result between the first monitoring speed and the second monitoring speed. The second unit is a phase counting counter that phase-counts the A-phase signal and the B-phase signal by multiplying them by four and outputs the result as a base count value. a first capture circuit that latches the base count value at a capture period that is a value obtained by dividing a speed monitoring period by a positive integer and outputs it as a position count value; a second capture circuit that latches the base count value at an active edge of the Z-phase signal and outputs it as a reference count value; and a second counter calculation unit that calculates the second count value based on the position count value and the reference count value, wherein the second counter calculation unit calculates a reference count correction value corresponding to a difference between the base count value and the reference count value at a reference position of the Z-phase signal based on a current value of the reference count value, a previous value of the reference count value, and a previous value of the reference count correction value, calculates a reference count estimate value by adding the reference count correction value to the reference count value, counts up or counts down the multiple-revolution count value based on a magnitude relationship between the current value of the position count value, the previous value of the position count value, and the reference count estimate value, and calculates a difference value between the position count value and the reference count estimate value as the within-one-revolution count value. Effect of the Invention

[0015] According to the present invention, it is possible to construct a phase difference counter using a Z-phase signal using a general-purpose MCU, and it is possible to inexpensively configure speed monitoring including confirmation of agreement between the one-revolution wave number setting value in speed monitoring and the actual one-revolution wave number of the encoder. [Brief description of the drawings]

[0016] [Figure 1] FIG. 2 is a block diagram showing a speed monitoring device. [Diagram 2] 11 is a flowchart showing an example of a calculation method for a multi-turn counter and a single-turn counter. [Diagram 3] 11 is a timing chart illustrating a problem with a multi-turn counter in a conventional example. [Figure 4] 1 is a timing chart illustrating a problem with a phase difference counter in a conventional example. [Diagram 5] 2 is a timing chart showing the operation of a counter in the speed monitoring device of FIG. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] When a phase difference counter is duplicated using different elements, the timing of change of the count value does not match due to differences in signal delay times, etc. Therefore, it is necessary to allow a difference in the difference between the count values ​​of the duplicated counters within a range that does not adversely affect speed monitoring. When the counting method of the phase difference counter is 1x, the tolerance is 1 count or less, which is the minimum resolution, that is, 1 wave number or less. Even when the counting method of the phase difference counter is 4x, if the tolerance is set as a value with the same resolution as the counting method of 1x, a difference in the count value of 1 wave number or less (i.e., 4 counts or less) in the duplicated counter is allowed. Therefore, a phase difference counter mounted on a general-purpose MCU is calculated based on a position count value sampled at each speed monitoring cycle and a reference count value sampled at the active edge of a Z-phase signal, and a phase difference counter that combines a multi-revolution counter using a Z-phase signal and a within-one-revolution counter, in which the error with a phase difference counter that does not use a Z-phase signal is less than 4 counts (less than 1 wave number) for the difference of the speed monitoring cycle, by software processing.

[0018] The speed monitoring device will be described with reference to Figures 1 and 2. Figure 1 is a block diagram showing an example of the configuration of the speed monitoring device, and Figure 2 is a flow chart showing an example of a calculation method for the multiple-turn counter and the single-turn counter by this speed monitoring device.

[0019] The encoder 1 of FIG. 1 outputs an A-phase signal with wave number N per rotation, a B-phase signal with a phase difference of 90 degrees with respect to the A-phase signal, and a Z-phase signal with one pulse per rotation according to the rotation angle of an object (not shown). The Z-phase signal is a signal that becomes active when the rotation angle reaches a reference position that is determined at one point in one rotation. The A-phase signal is level-converted and pulsed by the pulse circuit 2a, and is input as an A-phase pulse signal to the first MCU 4a and the second MCU 4b. Similarly, the B-phase signal is level-converted and pulsed by the pulse circuit 2b, and is input as a B-phase pulse signal to the first MCU 4a and the second MCU 4b. The Z-phase signal is level-converted and pulsed by the pulse circuit 2c, and is input as a Z-phase pulse signal to the second MCU 4b. The first MCU 4a and the second MCU 4b are microcontroller units equipped with counter circuits 6a and 6b capable of phase counting as peripherals, capture circuits 7a, 7b and 7c for capturing the count value of the counter by at least two external signals, and calculation units 8 and 9, and various products are generally available on the market. The first MCU 4a generates a first count value C1 that does not perform counter clearing by the Z-phase pulse signal for the count value obtained by phase counting the A-phase pulse signal and the B-phase pulse signal, and outputs it to the safety controller 10 for each speed monitoring period. The second MCU 4b obtains a one-revolution count value Cs that is cleared by the Z-phase pulse signal and a multiple-revolution count value Cm that counts the Z-phase pulse signal from the count value obtained by phase counting the A-phase pulse signal and the B-phase pulse signal (hereinafter referred to as the "base count value Cb"). The second MCU 4b outputs the single-revolution count value Cs and the multiple-revolution count value Cm as a second count value C2 to the safety controller 10 for each speed monitoring period. The second count value C2 can be converted into a count value of the same format as the first count value C1 by using the number of teeth per revolution N, and the number of teeth per revolution N is set in the safety controller.The output of the first count value C1 and the second count value C2 from the first MCU 4a and the second MCU 4b to the safety controller 10 is performed, for example, by safety communication in which measures against transmission errors are taken.

[0020] The first speed monitoring unit 11 of the safety controller 10 calculates a first monitoring speed V1 by V1=ΔC1 / N' based on the amount of change ΔC1 in the first count value C1 for each speed monitoring period T and a one-revolution count set value N' of the encoder 1 that is preset in the safety controller 10, and performs speed monitoring. The one-revolution count set value N' is the count value of the phase count when the encoder 1 makes one revolution. When phase counting is performed at a factor of four, the one-revolution count set value N' is N'=4×N using the number of teeth per revolution N. Similarly, the second speed monitoring unit 12 of the safety controller 10 calculates a second monitoring speed V2 by V2=ΔC2 / N' based on the amount of change ΔC2 in the second count value C2 for each speed monitoring period T and a one-revolution count set value N' of the encoder 1 that is preset, and performs speed monitoring. The second count value C2 is converted to a count value of the same format as when the counter is not cleared by the Z-phase signal, and is used for calculating ΔC2. This conversion is performed by applying the multiple-rotation count value Cm and the single-rotation count value Cs to Equation 1. C2 = (Cm + F) × N' + Cs (1)

[0021] Here, F is 0 when the one-revolution count value Cs is 0 or more, and 1 when it is negative. The first speed monitoring unit 11 and the second speed monitoring unit 12 exchange the change amount ΔC1 of the first count value C1 and the change amount ΔC2 of the second count value C2 with each other, and detect an abnormality of the speed monitoring interface when |ΔC1-ΔC2| becomes equal to or greater than a predefined abnormality detection threshold. The abnormality detection threshold can be set to, for example, 4 counts, that is, a count value for one wave. This makes it possible to detect an abnormality when the one-revolution wave number N of the encoder 1 and the one-revolution wave number set value N' do not match.

[0022] The phase counter 6a of the first MCU 4a is a counter circuit that performs quadruple phase counting based on the A-phase pulse signal and the B-phase pulse signal. Before being input to the phase counter 6a, the A-phase pulse signal and the B-phase pulse signal may be subjected to noise removal by noise filters 5a and 5b. The capture circuit 7a detects the active edge of the capture timing signal output by the capture timing generation unit 3 described later, and latches the count value of the phase counter 6a. Before being input to the capture circuit 7a, the capture timing signal may be subjected to noise removal by a noise filter 5c.

[0023] The first counter arithmetic unit 8 executes a predetermined interrupt process each time the count value of the capture circuit 7a is latched. As an interrupt process, the first counter arithmetic unit 8 aligns the count value latched by the capture circuit 7a with the bit width M' of the first count value C1 required by the safety controller 10, and outputs it to the safety controller 10 as the first count value C1 for each speed monitoring period.

[0024] The alignment of the bit width is executed by software processing. When M ≥ M' with respect to the bit width M of the phase counter 6a, the first counter arithmetic unit 8 extracts the lower M' bits. When M < M', the first counter arithmetic unit 8 detects overflow and underflow based on the change in the count value latched by the capture circuit 7a, and increments the extended counter of (M' - M) bits by 1 at overflow and decrements it by 1 at underflow. Although not shown, the first counter arithmetic unit 8 is a microcomputer and includes various memories, arithmetic units (i.e., processors), etc. necessary for performing software processing.

[0025] The phase counting counter 6b of the second MCU 4b is a counter circuit that performs quadruple phase counting using the A-phase pulse signal and the B-phase pulse signal. The A-phase pulse signal and the B-phase pulse signal may be subjected to noise removal by noise filters 5d and 5e before being input to the phase counting counter 6b. The first capture circuit 7b detects an active edge of the capture timing signal output by the capture timing generating unit 3 and latches the count value of the phase counting counter 6b. The capture timing signal may be subjected to noise removal by a noise filter 5f before being input to the first capture circuit 7b. The second capture circuit 7c detects an active edge of the Z-phase pulse signal and latches the count value of the phase counting counter 6b. The Z-phase pulse signal may be subjected to noise removal by a noise filter 5g before being input to the second capture circuit 7c.

[0026] The second counter calculation unit 9 executes an interrupt process every time the first capture circuit 7b latches a count value. As the interrupt process, the second counter calculation unit 9 calculates the one-revolution count value Cs and the multiple-revolution count value Cm by software processing, which will be described later, based on the position count value Cp latched by the first capture circuit 7b and the reference count value Cz latched by the second capture circuit 7c. Then, the second counter calculation unit 9 outputs the one-revolution count value Cs and the multiple-revolution count value Cm as the second count value C2 to the safety controller 10 every speed monitoring period. Although not shown, the second counter calculation unit 9 is a microcomputer and includes various memories, a calculation device (i.e., a processor), and the like, which are necessary for performing software processing.

[0027] The capture timing generation unit 3 is a circuit that generates and outputs a capture timing signal indicating a capture period Ts. The capture period Ts is a value that satisfies Ts=T / INT (INT is a positive integer) for a speed monitoring period T. The capture period Ts is a value that is preset so as to be smaller than the period of the Z-phase signal when the encoder 1 rotates at the maximum rotation speed. Although the capture timing generation unit 3 is illustrated in FIG. 1 as a component independent of the first MCU 4a and the second MCU 4b, it does not need to be an independent component. For example, the capture timing signal may be output by the first MCU 4a or the second MCU 4b.

[0028] The processing of the second count calculation unit 9 will be described below with reference to the flowchart in Fig. 2. As described above, the processing of the flowchart in Fig. 2 is started for each count latch of the first capture circuit 7b (i.e., for each capture period Ts). In the following, the current value of the position count value Cp obtained by the latch is represented as Cp(n), and the previous value is represented as Cp(n-1). Other parameters are represented in the same manner.

[0029] In S901, the position count value Cp(n) is acquired from the first capture circuit 7b and the reference count value Cz(n) is acquired from the second capture circuit 7c with zero extension, and the previous values ​​of the position count value Cp(n) and the reference count value Cz(n) are acquired from the memory with zero extension as the previous position count value Cp(n-1) and the previous reference count value Cz(n-1), and then the process proceeds to S902.

[0030] S902 is a correction process for eliminating discontinuity of the Cp(n), Cz(n), Cp(n-1), and Cz(n-1) caused by overflow and underflow of the phase counting counter 6b in the process after S903. Specifically, the corrected position count value Cp'(n), the corrected previous position count value Cp'(n-1), the corrected reference count value Cz'(n), and the corrected previous reference count value Cz'(n-1) are calculated by the following equations, and the process proceeds to S903. Cp'(n) = Cp(n) + f × f1 × 2 M Cp'(n-1) = Cp(n-1) + f × f2 × 2 M Cz'(n) = Cz(n) + f × f3 × 2 M Cz'(n-1) = Cz(n-1) + f × f4 × 2 M

[0031] Here, M is the bit width of the phase counter 6b. f is a flag indicating whether or not correction processing is performed, and at least one of the count values ​​Cp(n), Cz(n), Cp(n-1), and Cz(n-1) is used for judgment, and the count value used for judgment is equal to or less than the lower threshold or equal to or more than the upper threshold, and is set to 1, otherwise to 0. For example, the threshold value is set by dividing the lower threshold by 2 using the bit width M. M / 4, the upper threshold is 2 M f1 is set to 1 when Cp(n) is equal to or less than the judgment value, and 0 when it is greater than the judgment value. Similarly, f2 is set to 1 when Cp(n-1), f3 is set to Cz(n), and f4 is set to 0 when it is greater than the judgment value. The judgment value can be set, for example, by using the bit width M, 2 (M-1) The method of setting the lower limit threshold, the upper limit threshold, and the judgment value is merely an example, and may be changed as appropriate.

[0032] In step S903, a Z-phase passing flag is used to determine whether the multiple rotation count value Cm has been counted up or down even once. If the Z-phase passing flag is OFF, the process proceeds to step S904. If the Z-phase passing flag is ON, the process proceeds to step S911. The Z-phase passing flag is turned OFF in an initialization process (not shown).

[0033] S904 to S910 are processes that are performed when the multiple rotation count value Cm has never been counted up or down. Here, the multiple rotation count value Cm is counted up or down when it is considered that the multiple rotation count value Cm has passed the reference position determined by the Z-phase signal. The reference position of the Z-phase signal is determined based on the logic levels of the A-phase pulse signal, the B-phase pulse signal, and the Z-phase pulse signal. For example, when the Z-phase pulse signal is an active H signal, the reference position of the Z-phase signal is a position where the A-phase pulse signal is at an L level, the B-phase pulse signal is at an L level, and the Z-phase pulse signal is at an H level.

[0034] In step S904, the second capture circuit 7c acquires a status indicating whether or not the latch operation of the phase count counter 6b has been performed even once due to the active edge of the Z-phase pulse signal. If the latch operation has been performed, the process proceeds to step S905. If not, the process proceeds to step S910.

[0035] S905 and S907 are processes for determining whether the reference position based on the Z-phase signal has been passed. In this example, if the active edge of the Z-phase signal is detected and then the count advances by more than two counts, it is deemed that the reference position has been passed. Therefore, if the relationship Cp'(n)>Cz'(n)+2≧Cp'(n-1) is satisfied, it is determined that the reference position has been passed in the forward direction. Note that the reference count value Cz is the value obtained by latching the base count value Cb at the timing when the active edge of the Z-phase signal is detected, as described above. Therefore, Cz'(n) is the base count value Cb when the active edge of the Z-phase signal was most recently detected.

[0036] If it is Yes in S905, proceed to S906, set +2 for the reference count correction value Zc(n) and +1 for the multi-rotation count value Cm. On the other hand, if it is No in S905, proceed to S907. When the relationship Cp’(n) < Cz’(n) - 2 ≤ Cp’(n - 1) is satisfied, it is determined that the reference position has been passed in the reverse direction, and the process proceeds to the process of S908. In S908, set -2 for the reference count correction value Zc(n) and -1 for the multi-rotation count value Cm. S909 is executed after the processes of S906 and S907, and is a common process when it is regarded that the reference position has been passed by the Z-phase signal. In S909, turn on the Z-phase passing flag, and set the reference count estimated value Czc to the value obtained by adding the reference count value Cz’(n) and the reference count correction value Zc(n).

[0037] Here, the reference count correction value Zc(n) is a correction value for correcting the difference between the base count value Cb (i.e., the reference count value Cz) at the active edge of the Z-phase pulse signal and the base count value Cb at the true Z-phase reference position. Also, the reference count estimated value Czc is the base count value Cb at the estimated Z-phase reference position. The true Z-phase reference position is determined based on the logic levels of the A-phase pulse signal, the B-phase pulse signal, and the Z-phase pulse signal as described above. For example, when the Z-phase pulse signal is an active H signal, the true Z-phase reference position is, as an example, the position where the A-phase pulse signal is at the L level, the B-phase pulse signal is at the L level, and the Z-phase pulse signal is at the H level.

[0038] S910 is a process when it is regarded that the reference position by the Z-phase signal has not been passed at all, and clears the reference count correction value Zc(n), the reference count estimated value Czc, and the Z-phase passing flag.

[0039] S911 to S920 are processes that are performed after it is deemed that the reference position based on the Z-phase signal has been passed at least once. S911 to S915 are processes that update the reference count correction value Zc(n). Specifically, if the relationship Cz'(n)-Cz'(n-1)>6 is satisfied, it is determined that the active edge of the Z-phase signal has been passed in the forward direction, and Zc(n)=+2 is set. If the relationship Cz'(n)-Cz'(n-1)<-6 is satisfied, it is determined that the active edge of the Z-phase signal has been passed in the reverse direction, and Zc(n)=-2 is set. Furthermore, in other cases, it is determined that the rotation direction has changed and the active edge of the Z-phase signal has been passed, or that the active edge has not been passed, and Zc(n)=Zc(n-1)-Cz'(n)+Cz'(n-1) is set.

[0040] Here, Zc(n-1) is the previous value of the reference count correction value Zc(n), and the value stored in the memory is acquired. The reference value for judgment, 6, is the maximum value of the difference between the base count value Cb at the active edge of the Z-phase pulse signal and the base count value Cb at the non-active edge of the Z-phase pulse signal. In other words, the reference value "6" is a count value corresponding to the maximum pulse width of the Z-phase pulse signal. When the maximum width of the Z-phase pulse signal exceeds 6 counts, the reference positions based on the logic levels of the A-phase pulse signal, the B-phase pulse signal, and the Z-phase pulse signal will exist at multiple locations regardless of the phase relationship of the A-phase pulse signal, the B-phase pulse signal, and the Z-phase pulse signal. Therefore, the maximum width of the Z-phase pulse signal is always 6 counts or less.

[0041] In step S916, a value obtained by adding the reference count value Cz'(n) and the reference count correction value Zc(n) is set to the reference count estimated value Czc, and the process proceeds to step S917.

[0042] From S917 to S920, it is a process of incrementing and decrementing the multi-rotation count value Cm. Specifically, when the relationship Cp'(n) ≥ Czc > Cp'(n - 1) is satisfied, it is determined that the reference position by the Z-phase signal has been passed in the forward rotation direction, and the multi-rotation count value Cm is incremented. Also, when the relationship Cp'(n) < Czc ≤ Cp'(n - 1) is satisfied, the multi-rotation count value Cm is decremented.

[0043] S921 is a process of calculating the one-rotation count value Cs, and a value obtained by subtracting Czc from Cp'(n) is set as the one-rotation count value.

[0044] S922 stores the position count value Cp(n), the reference count value Cz(n), and the reference count correction value Zc(n) in the memory as the previous values for reference at the next process startup.

[0045] Here, as described above, the safety controller 10 determines the presence or absence of speed abnormality based on the difference component between the change amount ΔC1 of the first count value C1 and the change amount ΔC2 of the second count value C2, that is, |ΔC1 - ΔC2|. When the base count value Cb at the true Z-phase reference position is defined as the "true reference count value Cz*", the difference component |ΔC1 - ΔC2| is the change amount of the error ΔCz = |Czc - Cz*| between the reference count estimated value Czc and the true reference count value Cz*, plus or minus 1 of the difference in the count values captured by the capture circuit 7a and the first capture circuit 7b. The difference in the capture values occurs, for example, due to the difference in the delay time of the internal signals of the first MCU 4a and the second MCU 4b.

[0046] The ΔCz is determined depending on the reference position correction value Zc(n) and the pulse width of the Z-phase pulse signal. That is, the difference between the base count value Cb (i.e., the reference count value Cz) when the active edge of the Z-phase pulse signal passes in the forward direction and the base count value Cb (i.e., the true reference count value Cz*) at the true Z-phase reference position is w1, and the difference between the reference count value Cz when the active edge passes in the reverse direction and the true reference count value Cz* is -w2. In this case, the ΔCz when the active edge of the Z-phase pulse signal passes in the forward direction is w1-2, and the ΔCz when the active edge passes in the reverse direction is -w2+2. Therefore, if w=w1+w2, the amount of change in the ΔCz is at most |w-4| as shown in Equation 2. |Change in ΔCz|=|(w1-2)-(-w2+2)|=|w-4| (2)

[0047] Here, w=w1+w2 is the pulse width when the Z-phase pulse signal is at an active level, converted into the count value of the phase counting counter 6b. As described above, the maximum value of w is 6, and the minimum value of w is 2, under the condition that the active level of the Z-phase pulse signal includes the logical level range of the A-phase pulse signal and the B-phase pulse signal, which is the true Z-phase reference position. Therefore, from equation (2), the amount of change in ΔCz in the speed monitoring period Ts falls within the range of ±2. Therefore, the difference between ΔC1, which is the amount of change in the first count value C1, and ΔC2, which is the amount of change in the second count value C2, falls within the range of ±3.

[0048] As a result, by configuring the second counter calculation unit 9 using the processing previously described using FIG. 2, the difference between ΔC1, which is the amount of change in the first count value C1, and ΔC2, which is the amount of change in the second count value C2, during a speed monitoring period Ts can be kept to less than 4 counts, which is less than the equivalent of one wave number, and the safety controller 10 can perform speed monitoring without erroneously detecting an abnormality in the speed monitoring interface.

[0049] For example, in Figure 5, when the number of teeth N is 25 and the Z-phase signal pulse width is equivalent to 6 counts, the Z-phase signal is [1] Two or more forward rotations (not shown) [2] Forward direction (between (a) and (b) in Figure 5) [3] Reverse direction (between (c) and (d) in Figure 5) [4] Reverse direction (Figure 5 (e) and (f)) 1 shows an example of a timing chart when the signals pass through in this order.

[0050] In FIG. 5, in order to make the timing chart easier to understand, the correction process (zero extension in S901 and S902) in the flowchart in FIG. 2 that takes overflow and underflow into consideration is omitted. The Z-phase signal passing in [2] is a Z-phase signal passing when forward rotation continues, and the reference count correction value Zc is held at +2 by the process of S912 in FIG. 2. Therefore, no error occurs in the count value difference. The Z-phase signal passing in [3] is the first Z-phase signal passing when forward rotation changes to reverse rotation, and the reference count correction value Zc is corrected by the pulse width of the Z-phase signal by the process of S915 in FIG. 2. Therefore, the reference count estimation value Czc becomes the same value as when the Z-phase signal passed in the immediately previous forward rotation direction ([2] above), and no error occurs in the count value difference. The Z-phase signal passing of [4] is the second Z-phase signal passing after the rotation changes from forward to reverse, and the reference count correction value is set to -2 by the process of S914 in Fig. 2. At this time, while the difference in the phase count counter is -4 between (e) and (f) in Fig. 5, the count value difference after converting the one-revolution count value Cs and the multiple-revolution count value Cm using the above formula (1) is -6, resulting in an error of -2. In Fig. 5, the pulse width of the Z-phase signal is equivalent to 6 counts, which coincides with the calculation result using formula (2). [Explanation of symbols]

[0051] 1 Encoder, 2a, 2b, 2c Pulse forming circuit, 3 Capture timing generation unit, 4a First MCU, 4b Second MCU, 5a, 5b, 5c, 5d, 5e, 5f, 5g Noise filter, 6a, 6b Phase measurement counter, 7a Capture circuit, 7b First capture circuit, 7c Second capture circuit, 8 First counter calculation unit, 9 Second counter calculation unit, 10 Safety controller, 11 First speed monitoring unit, 12 Second speed monitoring unit.

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