Semiconductor device

Abstract

To provide a semiconductor device having improved electrical characteristics.SOLUTION: A semiconductor device according to the present invention includes a bit line formed on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a channel surrounding at least a portion of a sidewall of the bit line, a word line formed on the substrate and at least a portion of which overlaps with the channel in a horizontal direction parallel to the upper surface of the substrate, and a capacitor electrically connected to the channel and at least a portion of which overlaps with the channel and the word line in the horizontal direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices having improved electrical characteristics. [Background technology]

[0002] A DRAM semiconductor device includes word lines, bit lines, channels, and capacitors, and research and development into techniques for efficiently arranging these to improve integration is becoming a daily necessity and challenge. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in consideration of the above problems with conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device having improved electrical characteristics. Another object of the present invention is to provide a three-dimensional DRAM (3D-DRAM) semiconductor device. [Means for solving the problem]

[0004] In order to achieve the above-mentioned object, a semiconductor device according to the present invention is characterized in that it comprises: a bit line formed on a substrate and extending in a first direction perpendicular to an upper surface of the substrate; a channel surrounding at least a portion of a sidewall of the bit line; a word line formed on the substrate and at least a portion of which overlaps with the channel in a horizontal direction parallel to the upper surface of the substrate; and a capacitor electrically connected to the channel and at least a portion of which overlaps with the channel and the word line in the horizontal direction.

[0005] In order to achieve the above object, a semiconductor device according to the present invention is characterized in that it comprises: a bit line formed on a substrate and extending in a first direction perpendicular to an upper surface of the substrate; a back gate electrode formed on the substrate and spaced apart from the bit line in a horizontal direction parallel to an upper surface of the substrate and extending in the first direction; a channel surrounding a sidewall of the back gate electrode and electrically connected to the bit line; a word line formed on the substrate, at least a portion of which overlaps with the channel in the horizontal direction; and a capacitor electrically connected to the channel and at least a portion of which overlaps with the channel and the word line in the horizontal direction.

[0006] In order to achieve the above object, a semiconductor device according to the present invention is characterized in that it comprises: a plurality of bit lines formed on a substrate, each extending in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other in a second direction parallel to the upper surface of the substrate; channels formed along sidewalls of each of the bit lines and spaced apart from each other in the first direction, each surrounding at least a portion of the sidewall of each of the bit lines; word lines extending in the second direction on the substrate, spaced apart from each other along the first direction, each at least partially overlapping with the channel corresponding to the second direction; capacitors spaced apart from each other in the first direction, each parallel to the upper surface of the substrate and at least partially overlapping with the channel corresponding to the second direction in a third direction intersecting the second direction; and contact plugs each extending in the first direction and in contact with upper surfaces of the word lines. Effect of the Invention

[0007] In the semiconductor device according to the present invention, the channel and the capacitor are both formed in the layer in which the word lines are formed, thereby reducing the vertical thickness of each memory cell including them. This reduces the vertical thickness and the height of the top surface of the semiconductor device including the memory cells, thereby improving the integration density. [Brief description of the drawings]

[0008] [Figure 1] 1 is a plan view for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a cross-sectional view for illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 3] 1 is a cross-sectional view for illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 5] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 25] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 26] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 27] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 29] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 30] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 31] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 32] 1 is a cross-sectional view for illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 33] 1 is a plan view for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 34] 1 is a cross-sectional view for illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 35] 1 is a plan view for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 36] 1 is a cross-sectional view for illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 37] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 38] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 39] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 40] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 41] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 42] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 43] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 44] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 45] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 46] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 47] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 48] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 49] 1 is a plan view for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 50] 1 is a cross-sectional view for illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 51] 1 is a cross-sectional view for illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 52] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 53] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 54] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 55] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 56] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 57] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 58] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 59] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 60] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 61] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 62] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 63]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 64] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 65] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 66] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 67] 1 is a plan view for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 68] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 69] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 70] 1 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Next, specific examples of embodiments for carrying out the semiconductor device and the manufacturing method thereof according to the present invention will be described with reference to the drawings.

[0010] In this specification, when a material, layer (film), region, pad, electrode, pattern, structure, or process is referred to as "first," "second," and / or "third," this is not intended to limit these components, but is merely intended to distinguish each material, layer (film), region, electrode, pad, pattern, structure, and process. Thus, "first," "second," and / or "third" are used selectively or interchangeably with respect to each material, layer (film), region, electrode, pad, pattern, structure, and process, respectively. Hereinafter, the vertical direction perpendicular to the top surface of the substrate is defined as a first direction (D1), and two mutually intersecting horizontal directions parallel to the top surface of the substrate are defined as a second and third directions (D2, D3), respectively. In one embodiment, the second direction (D2) and the third direction (D3) are perpendicular to each other.

[0011] 1 to 3 are plan views and cross-sectional views for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention. 1 is a plan view, FIG. 2 is a cross-sectional view taken along line AA' in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB' in FIG.

[0012] As shown in FIGS. 1 to 3, a semiconductor device according to an embodiment of the present invention includes a first gate electrode 210, a first gate insulating film 200, a bit line 250, a channel 160, first and second ohmic contact patterns (240, 300), a capacitor structure 340, and first and second contact plugs (380, 390) formed on a substrate 100. The semiconductor device further includes first, third, fourth and fifth insulating patterns (115, 170, 220, 260), a second insulating film 150, and first and second interlayer insulating films (130, 370).

[0013] Substrate 100 may comprise, for example, a semiconductor material such as silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, or the like. According to one embodiment, the substrate 100 is a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate.

[0014] The substrate 100 includes a first and a second region (I, II). Here, the first region (I) is a cell region in which memory cells are formed, and the second region (II) is an extension region or pad region in which contact plugs are formed to transmit electrical signals to the memory cells. In one embodiment, the second region (II) surrounds the first region (I). Alternatively, the second region (II) may be formed only on both sides of the first region (I) in the second direction (D2).

[0015] The first gate electrodes 210 extend in a second direction (D2) on the first and second regions (I, II) of the substrate 100 and are stacked spaced apart from each other along the first direction (D1) to form a first gate electrode structure. Here, a first insulating pattern 115 is formed between the first gate electrodes 210 adjacent to each other in the first direction (D1), and the first insulating pattern 115 is also formed between the substrate 100 and the bottom first gate electrode 210, and on the top first gate electrode 210. Each first gate electrode 210 serves as a word line in a semiconductor device, and thus the first gate electrode structure is referred to as a word line structure.

[0016] In one embodiment, the extension length of the first gate electrode 210 in the second direction (D2) decreases in a step-like manner from the lower layer to the upper layer, so that the first gate electrode structure has a step shape as a whole. Here, in each first gate electrode 210, the portion not overlapped in the first direction (D1) by the upper first gate electrode 210, ie, each end in the second direction (D2), is called a pad. In one embodiment, the pads are arranged on the second region (II) of the substrate 100 along the second direction (D2). The first gate electrode 210 includes, for example, a metal, a metal nitride, a metal silicide, or impurity-doped polysilicon.

[0017] In one embodiment, the first gate electrode structures are formed spaced apart from each other along a third direction (D3), and the fourth insulating patterns 220 and the first sacrificial patterns 125 are alternately arranged between the first gate structures along the third direction (D3). Here, the fourth insulating pattern 220 extends in a second direction (D2) on the first and second regions (I, II) of the substrate 100 and penetrates the first gate electrode structure and the first insulating pattern 115. Meanwhile, the first sacrificial pattern 125 is stacked alternately with the first insulating pattern 115 in the first direction (D1) and penetrates the first gate electrode structure formed between adjacent fourth insulating patterns 220 in the third direction (D3) to separate it into two in the third direction (D3).

[0018] Each of the first and fourth insulating patterns (115, 220) comprises an oxide, such as silicon oxide, and the first sacrificial pattern 125 comprises a material having an etching selectivity with respect to the first insulating pattern 115, such as an insulating nitride, such as silicon nitride. The first gate insulating film 200 covers the upper and lower surfaces of the first gate electrode 210, the sidewall of the first gate electrode 210 facing the first sacrificial pattern 125, and the sidewall facing the channel 160, and is also formed on the sidewall of the first insulating pattern 115 facing the fourth insulating pattern 220. The first gate insulating film 200 includes an oxide such as, for example, silicon oxide.

[0019] The bit line 250 is formed on a first region (I) of the substrate 100, has a pillar shape extending in a first direction (D1), and penetrates the first gate electrode structure and the first insulating pattern 115. In one embodiment, the bit lines 250 are formed spaced apart from each other in the second direction (D2) while penetrating the first gate electrode structure extending in the second direction (D2), thereby forming a plurality of bit lines 250 spaced apart from each other along the second and third directions (D2, D3). Bitline 250 may comprise, for example, a metal, a metal nitride, a metal silicide, or impurity-doped polysilicon.

[0020] The third insulating pattern 170 is formed on a first region (I) of the substrate 100, has a pillar shape extending in a first direction (D1), and penetrates the first gate electrode structure and the first insulating pattern 115. In one embodiment, the third insulating pattern 170 contacts the sidewall of the bit line 250 in the third direction (D3) and, together with the bit line 250, has a circular, elliptical, polygonal, or rectangular shape with rounded corners when viewed from above. Each bit line 250 and third insulating pattern 170 penetrates the top of the substrate 100 and, in one embodiment, the bottom surface of the bit line 250 is lower than the bottom surface of the third insulating pattern 170 . The third insulating pattern 170 comprises an oxide, such as, for example, silicon oxide.

[0021] The channel 160 is formed in the layer in which each of the first gate electrodes 210 is formed, and surrounds the sidewalls of the bit line 250 and the third insulating pattern 170 . Here, the channel 160 contacts the sidewall of the third insulating pattern 170 , and a first ohmic contact pattern 240 is formed between the channel 160 and the sidewall of the bit line 250 . Meanwhile, a first gate insulating film 200 is formed between the channel 160 and the first gate electrode 210 . The upper and lower surfaces of the channel 160 are covered by the second insulating film 150, and the second insulating film 150 contacts the sidewalls of the first insulating pattern 115 portion formed between adjacent channels 160 in the first direction (D1) and the sidewalls of the third insulating pattern 170 portion facing thereto.

[0022] The second insulating film 150 also covers the lower surface of the third insulating pattern 170 and is in contact with the upper surface of the substrate 100 . The second insulating layer 150 may comprise an oxide, such as silicon oxide, and may merge with the first insulating pattern 115 and / or the third insulating pattern 170 in contact therewith. In one embodiment, the channel 160 has a ring shape, such as a circular ring, an elliptical ring, a polygonal ring, etc. The channels 160 are formed in the layer in which the first gate electrodes 210 are formed, and thus are spaced apart from each other along the first direction (D1). In addition, the channels 160 are formed to surround the sidewalls of the bit lines 250 and the third insulating patterns 170, and thus are spaced apart from one another in the second and third directions (D2 and D3).

[0023] The channel 160 may include a semiconductor material, such as, for example, silicon, germanium, silicon-germanium, or an oxide semiconductor material. Examples of oxide semiconductor materials include ZTO (zinc tin oxide), IZO (indium zinc oxide), ZnOx (zinc oxide), IGZO (indium gallium zinc oxide), IGSO (indium gallium silicon oxide), indium oxide (InOx, In2O3), SnO2 (tin oxide), TiOx (titanium oxide), ZnxOyNz (zinc oxide nitride), MgxZnyOz(magnesium zinc oxide), InxZnyOa(indium zinc oxide), InxGayZnzOa(indium gallium zinc oxide), ZrxInyZnzOa(zirconium indium zinc oxide), HfxInyZnzOa(hafnium indium zinc oxide), SnxInyZnzOa(tin indium zinc oxide), AlxSnyInzZnaOd(aluminum tin indium zinc oxide), SixInyZnzOa (silicon indium zinc oxide), ZnxSnyOz (zinc tin oxide), AlxZnySnzOa (aluminum zinc tin oxide), GaxZnySnzOa (gallium zinc tin oxide), ZrxZnySnzOa (zirconium zinc tin oxide), and InGaSiO (indium gallium silicon oxide).

[0024] The first ohmic contact pattern 240 covers the bottom surface of the bit line 250 and also contacts the top surface of the substrate 100 . The first ohmic contact pattern 240 includes a metal silicide, such as, for example, cobalt silicide, nickel silicide, titanium silicide, and the like. In one embodiment, the first ohmic contact pattern 240 is not formed between the channel 160 and the sidewall of the bit line 250. In this case, an impurity region doped with, for example, n-type impurities or p-type impurities is formed on the side of the channel 160 facing the sidewall of the bit line 250 to replace the role of the first ohmic contact pattern 240.

[0025] The capacitor structure 340 includes a first capacitor electrode 315, a dielectric pattern 325, and a second capacitor electrode 335, which are stacked in sequence. The second capacitor electrode 335 includes an extension portion extending in a first direction (D1) and a second direction (D2) through the first insulating pattern 115 on the first region (I) of the substrate 100, and a first protrusion portion protruding in the third direction (D3) from each side wall of the extension portion in the third direction (D3). In one embodiment, the second capacitor electrode 335 has a plurality of first protrusions formed thereon, each of which faces a sidewall of the corresponding channel 160 in the third direction (D3). As a result, a plurality of first protrusions spaced apart from each other along the first and second directions (D1, D2) are formed on both side walls of the second capacitor electrode 335 in the third direction (D3). On the other hand, the second capacitor electrode 335 further includes a second protrusion protruding in a semicircular shape from each of both ends of the extension portion in the second direction (D2) when viewed from above, and the second protrusions, like the first protrusions, are each formed in the layer in which the channel 160 is formed, and are formed in a plurality of locations spaced apart from each other along the first direction (D1).

[0026] The dielectric pattern 325 covers the sidewalls and bottom surface of the second capacitor electrode 335 . Here, the dielectric pattern 325 covers the upper and lower surfaces of each protrusion of the second capacitor electrode 335, both side walls in the second direction (D2), and one side wall in the third direction (D3). The first capacitor electrode 315 covers the top, bottom and side walls of the portion of the dielectric pattern 325 that covers the top, bottom and side walls of the first protrusion of the second capacitor electrode 335 . The first capacitor electrodes 315 are formed in a plurality of locations spaced apart from each other along the second and third directions (D2, D3) on the first region (I) of the substrate 100 corresponding to the channel 160, and are also formed in a plurality of locations spaced apart from each other along the first direction (D1). Here, each first capacitor electrode 315 is formed in the same layer as the corresponding channel 160 .

[0027] In the capacitor structure 340, each first capacitor electrode 315, a portion of the dielectric pattern 325 formed in the same layer as and in contact with it, and a portion of the second capacitor electrode 335 formed in the same layer as and in contact with the dielectric pattern 325 portion together define a capacitor. As a result, the capacitor structure 340 includes multiple capacitors spaced apart from each other along the second and third directions (D2, D3) in the same layer corresponding to the layout of the first capacitor electrode 315, and the capacitors are formed in multiple layers spaced apart from each other along the first direction (D1), respectively.

[0028] In one embodiment, the outer wall in the third direction (D3) of the first capacitor electrode 315 included in each capacitor contacts the second ohmic contact pattern 300, thereby electrically connecting with the channel 160. Here, the outer sidewall of the first capacitor electrode 315 in the third direction (D3) faces the sidewall of the bit line 250 that is at least partially surrounded by the channel 160. In addition, the outer wall of the first capacitor electrode 315 in the second direction (D 2 ) contacts the fifth insulating pattern 260 . Meanwhile, the first capacitor electrode 315 is also formed on the upper and lower surfaces and side walls of the dielectric pattern 325 portion covering the upper and lower surfaces and side walls of the second protrusion of the second capacitor electrode 335 .

[0029] The fifth insulating pattern 260 extends in the first direction (D1) through the first insulating pattern 115 on the first region (I) of the substrate 100 and is formed between the first capacitor electrodes 315 adjacent to each other in the second direction (D2) on either side of the second capacitor electrode 335 in the third direction (D3). That is, the first capacitor electrodes 315 adjacent to each other in the second direction (D2) are spaced apart and electrically insulated from each other by the fifth insulating pattern 260. Thus, the fifth insulating patterns 260 are formed on both sides of the second capacitor electrode 335 in the third direction (D3) and spaced apart from each other along the second direction (D2). Meanwhile, the fifth insulating pattern 260 also contacts the sidewall of the first gate insulating film 200 . The fifth insulating pattern 260 comprises an oxide, such as for example silicon oxide, or an insulating nitride, such as for example silicon nitride.

[0030] Each of the first and second capacitor electrodes (315, 335) includes, for example, a metal, a metal nitride, a metal silicide, a semiconductor material doped with impurities, etc., and the dielectric pattern 325 includes, for example, a metal oxide having a high dielectric constant, such as hafnium oxide, zirconium oxide, etc.

[0031] The first and second interlayer insulating films (130, 370) are sequentially stacked on the substrate 100 in a first direction (D1), with the first interlayer insulating film 130 covering the sidewalls of the first gate electrode structure and the first insulating pattern 115, and the second interlayer insulating film 370 being formed on the first interlayer insulating film 130, the first gate electrode structure, the bit line 250, the capacitor structure 340, the third to fifth insulating patterns (170, 220, 260), and the second insulating film 150. Each of the first and second interlayer dielectric layers (130, 370) comprises an oxide, such as, for example, silicon oxide.

[0032] The first contact plug 380 penetrates the first and second interlayer insulating films 130, 370 and the first gate insulating film 200 on the second region (II) of the substrate 100 and contacts the upper surface of the pad of each first gate electrode 210, and the second contact plug 390 penetrates the second interlayer insulating film 370 on the first region (I) of the substrate 100 and contacts the upper surface of each bit line 250. Meanwhile, although not shown in the drawing, third contact plugs penetrating the second interlayer insulating film 370 and contacting the upper surfaces of the second capacitor electrodes 335 are further included. Each of the first and second contact plugs 380, 390 and the third contact plug may include, for example, a metal, a metal nitride, a metal silicide, or a semiconductor material doped with impurities.

[0033] As described above, in the semiconductor device of the present invention, the channel 160 and the first capacitor electrode 315 are formed together in the layer in which each first gate electrode 210 is formed, thereby reducing the thickness in the first direction (D1), i.e., the vertical direction, of each memory cell including them, for example, compared to when the first gate electrode 210 is formed above and / or below the channel 160 and the first capacitor electrode 315. Thus, the vertical thickness and top surface height of the semiconductor device including the memory cells are reduced.

[0034] Meanwhile, the channel 160 surrounds the sidewall of the bit line 250 and the third insulating pattern 170 in contact therewith, and the first capacitor electrode 315, the channel 160, and the bit line 250 formed on both sides in the third direction (D3) based on the extension portion of the second capacitor electrode 335 extending in the second direction (D2) have symmetrical shapes to each other. In addition, the bit line 250, the first capacitor electrode 315, and the channel 160 portion formed therebetween are arranged in a third direction (D3) perpendicular to the second direction (D2), which is the extension direction of the first gate electrode 210.

[0035] 4 to 31 are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, Figures 5, 9, 11, 14, 19, 22, 25, 26, 28, and 30 are plan views, Figures 4, 6 to 8, 10, 12, 15, 17, 20, and 23 are cross-sectional views taken along line A-A' in the corresponding plan views, and Figures 13, 16, 18, 21, 24, 27, 29, and 31 are cross-sectional views taken along line B-B' in the corresponding plan views.

[0036] As shown in FIG. 4, a first insulating film 110 and a first sacrificial film 120 are alternately stacked on a substrate 100 including a first and second region (I, II) to form a mold film, and a photoresist pattern is formed on the mold film. After that, an etching process using the photoresist pattern on the mold film as an etching mask and a trimming process on the photoresist pattern are alternately performed to form a mold having an overall step shape.

[0037] The first insulating film 110 includes an oxide such as silicon oxide, and the first sacrificial film 120 includes a material having an etching selectivity with respect to the first insulating film 110, for example, an insulating nitride such as silicon nitride. Here, the mold includes step layers each composed of a first insulating film 110 and a first sacrificial film 120 stacked in a first direction (D1), and the length of the step layers in a second direction (D2) decreases in a step manner from the lower layer to the upper layer. In the following, the portion of each step layer that is not overlapped in the first direction (D1) by an upper step layer, i.e., each end of each step layer in the second direction (D2), is defined as a step.

[0038] In one embodiment, a mold step is formed on the second region (II) of the substrate 100 . In the drawing, a step is shown in which one side in the second direction (D2) of the mold formed on the second region (II) of the substrate 100 is aligned in the second direction (D2). On the other hand, although the drawings show that each step layer is composed of a first insulating film 110 and a first sacrificial film 120 stacked in a first direction (D1), the present invention is not limited to this, and for example, each step layer may be composed of a first sacrificial film 120 and a first insulating film 110 stacked in a first direction (D1).

[0039] As shown in Figures 5 and 6, after a first interlayer insulating film 130 covering the mold is formed on a substrate 100, a planarization process is performed on the first interlayer insulating film 130 until the top surface of the mold is exposed, so that the first interlayer insulating film 130 covers the sidewalls of the mold. Planarization steps include, for example, chemical mechanical polishing (CMP) steps and / or etch back steps.

[0040] Thereafter, an etching process is performed on the mold portion formed on the first region (I) of the substrate 100 to expose the upper surface of the substrate 100 and form a first hole 140 extending in a first direction (D1). The first holes 140 penetrate the upper portion of the substrate 100 and are formed in a plurality of locations on the first region (I) of the substrate 100, spaced apart from each other along second and third directions (D2, D3). Each of the first holes 140 may have various shapes, such as a circle, an ellipse, a polygon, or a polygon with rounded corners, when viewed from above.

[0041] As shown in FIG. 7, the side of the first sacrificial film 120 exposed by the first hole 140 is removed to form a first recess 145 . In one embodiment, the first recesses 145 are formed in the first sacrificial film 120, for example, by a wet etching process, thereby forming a plurality of first recesses 145 each communicating with the first hole 140 and spaced apart from each other along the first direction (D1). Here, each of the first recesses 145 has, for example, a ring shape.

[0042] As shown in FIG. 8, a second insulating film 150 is formed on the inner walls of the first hole 140 and the first recess 145, the upper surface of the mold, and the upper surface of the first interlayer insulating film 130. A channel film is then formed on the second insulating film 150 to fill a portion of the first hole 140 and the first recess 145. The channel film is then partially etched to form a channel 160. The second insulating film 150 may comprise, for example, silicon oxide and oxide, and may merge with portions of the first insulating film 110 that it contacts.

[0043] The channel film is partially removed, for example, by a wet etching process. In one embodiment, a plurality of channels 160 are formed along a sidewall of the first hole 140 in a first direction (D1) at intervals, and each channel 160 has, for example, a ring shape. In one embodiment, the channels 160 are formed in a plurality of spaces apart from each other along the second and third directions (D2, D3) on the first region (I) of the substrate 100 to form a channel array. Here, the channel array includes a plurality of channels 160 each arranged in a second direction (D2) and a plurality of rows of channels spaced apart from one another in a third direction (D3).

[0044] As shown in Figures 9 and 10, a third insulating film filling the first hole 140 is formed on the second insulating film 150 and the channel 160, and then a planarization process is performed on the third insulating film until the upper surface of the mold and the upper surface of the first interlayer insulating film 130 are exposed, thereby forming a third insulating pattern 170 in the first hole 140.

[0045] The third insulating patterns 170 have a pillar shape extending in a first direction (D1), and are formed in a plurality of patterns spaced apart from each other along second and third directions (D2, D3) on the first region (I) of the substrate 100. On the other hand, in the planarization step, the portions of the second insulating film 150 formed on the upper surface of the mold and the upper surface of the first interlayer insulating film 130 are also removed.

[0046] As shown in FIGS. 11 to 13, a first opening 180 is formed through the mold to expose the upper surface of the substrate 100, and the first opening 180 also penetrates the upper part of the substrate 100. In one embodiment, the first openings 180 are formed on the first and second regions (I, II) of the substrate 100, extending to both ends of the mold in the second direction (D2) and spaced apart from each other along the third direction (D3). By forming the first openings 180, the first insulating film 110 is separated into first insulating patterns 115 each extending in the second direction (D2) and spaced apart from each other along the third direction (D3), and the first sacrificial film 120 is separated into first sacrificial patterns 125 each extending in the second direction (D2) and spaced apart from each other along the third direction (D3).

[0047] In one embodiment, each first opening 180 is formed between adjacent channel rows in the third direction (D3), and two channel rows are disposed between adjacent first openings 180 in the third direction (D3). Thereafter, the side of the first sacrificial pattern 125 exposed by the first opening 180 and the adjacent portion of the second insulating film 150 are removed to form a second recess 190 exposing the sidewall of the channel 160.

[0048] In one embodiment, the second recesses 190 are formed in the first sacrificial pattern 125 and the second insulating film 150, for example, by a wet etching process, and are formed in a plurality of locations spaced apart from each other along the first direction (D1), each of which communicates with the first opening 180. Here, each of the second recesses 190 extends in a second direction (D2) on the first and second regions (I, II) of the substrate 100. In one embodiment, the second recesses 190 expose a majority of the sidewalls of each channel 160 in the row of channels adjacent to the first opening 180 .

[0049] As shown in Figures 14 to 16, a first gate insulating film 200 is formed on the inner walls of the first opening 180 and the second recess 190, the upper surface of the third insulating pattern 170, the upper surface of the second insulating film 150, the upper surface of the mold, and the upper surface of the first interlayer insulating film 130. A first gate electrode film is then formed on the first gate insulating film 200 to fill a part of the first opening 180 and the second recess 190. Then, the first gate electrode film is partially etched to form a first gate electrode 210.

[0050] The first gate dielectric 200 may comprise, for example, silicon dioxide and oxide, and the portion of the second dielectric 150 in contact therewith may be merged into the first gate dielectric 200 . The first gate electrode film is partially removed by, for example, a wet etching process. In one embodiment, the first gate electrode 210 extends in the second direction (D2) on either side of the first opening 180 in the third direction (D3), thereby forming a plurality of first gate electrodes 210 spaced apart from one another along the third direction (D3). Here, each first gate electrode 210 covers most of the sidewall of each channel 160 included in the channel column, and a first gate insulating film 200 is sandwiched between each first gate electrode 210 and each channel 160 included in the channel column.

[0051] In addition, a plurality of first gate electrodes 210 are formed spaced apart from each other in the first direction (D1) to form a first gate electrode structure. Here, the first gate electrode structure has a step shape in which the length in the second direction D2 decreases in a step manner from the bottom to the top. Hereinafter, in each first gate electrode 210 included in the first gate electrode structure, the portion that is not overlapped in the first direction (D1) by the upper first gate electrode 210, i.e., each end portion in the second direction (D2), will be referred to as a pad.

[0052] As shown in Figures 17 and 18, a fourth insulating film filling the first opening 180 is formed on the first gate insulating film 200 and the first gate electrode 210, and then a planarization process is performed on the fourth insulating film until the upper surface of the mold, the upper surface of the third insulating pattern 170, the upper surface of the second insulating film 150, and the upper surface of the first interlayer insulating film 130 are exposed, thereby forming a fourth insulating pattern 220 in the first opening 180.

[0053] The fourth insulating patterns 220 extend in the second direction (D2) on the first and second regions (I, II) of the substrate 100, penetrate the mold, and are formed in a plurality of locations spaced apart from each other along the third direction (D3). In the planarization process, the portions of the first gate insulating film 200 formed on the upper surface of the mold, the upper surface of the third insulating pattern 170, and the upper surface of the first interlayer insulating film 130 are also removed.

[0054] As shown in FIGS. 19 to 21, a portion of the third insulating pattern 170 and an adjacent portion of the second insulating film 150 are removed to form a second hole 230 exposing the upper surface of the substrate 100. As the second hole 230 is formed, the channel 160 and the sidewall of the first insulating pattern 115 are partially exposed. In one embodiment, a plurality of second holes 230 are formed on the first region (I) of the substrate 100, spaced apart from each other along the second and third directions (D2, D3).

[0055] As shown in FIGS. 22 to 24, a first ohmic contact pattern 240 is formed on the sidewall of the channel 160 exposed by the second hole 230. In one embodiment, the first ohmic contact pattern 240 is formed by forming a first metal film on the inner walls of the second hole 230, the top surfaces of the third and fourth insulating patterns (170, 220), the top surface of the second insulating film 150, the top surface of the mold, and the top surface of the first interlayer insulating film 130, and then performing a heat treatment process thereon to cause the metal contained in the first metal film to react with the semiconductor material contained in the channel 160, and the portion of the first metal film that does not react with the channel 160 is removed.

[0056] The first ohmic contact patterns 240 are formed in a plurality of locations spaced apart from each other along a first direction (D1) on a first region (I) of the substrate 100, and are also formed in a plurality of locations spaced apart from each other along second and third directions (D2, D3). Here, each of the first ohmic contact patterns 240 has, for example, a partial shape of a ring. Meanwhile, the first ohmic contact pattern 240 includes a semiconductor material and is also formed on the upper surface of the substrate 100 exposed by the second hole 230 .

[0057] Thereafter, a bit line film filling the second hole 230 is formed on the substrate 100, the third and fourth insulating patterns (170, 220), the second insulating film 150, the mold, and the first interlayer insulating film 130, and a planarization process is performed on the bit line film until the upper surface of the first interlayer insulating film 130 is exposed, thereby forming a bit line 250 in the second hole 230. In one embodiment, the bit lines 250 are formed spaced apart from each other along the second and third directions (D2, D3) on the first region (I) of the substrate 100, and each bit line 250 has a pillar shape extending in the first direction (D1). Here, each bit line 250 contacts the first ohmic contact pattern 240, and is thereby electrically connected to each channel 160 arranged in the first direction (D1).

[0058] As shown in FIG. 25, a third hole is formed through the mold on the first region (I) of the substrate 100 to expose the top surface of the substrate 100, and then a fifth insulating pattern 260 is formed in the third hole. The third hole also penetrates the upper part of the substrate 100 , so that the fifth insulating pattern 260 formed in the third hole penetrates the upper part of the substrate 100 . In one embodiment, the fifth insulating pattern 260 has a pillar shape extending in a first direction (D1) and is formed at a distance from each other along the second and third directions (D2, D3) to form a fifth insulating pattern array.

[0059] The fifth insulating pattern array includes a plurality of fifth insulating patterns 260 each arranged in the second direction (D2) and spaced apart from each other in the third direction (D3). Here, each fifth insulating pattern 260 included in each fifth insulating pattern row penetrates a mold portion formed between channels 160 included in a corresponding channel row and contacts a sidewall of the first gate insulating film 200. Meanwhile, the fifth insulating patterns 260 included in the fifth insulating pattern rows adjacent to each other in the third direction (D3) and corresponding to each other are aligned with each other in the third direction (D3).

[0060] As shown in Figures 26 and 27, a second opening 270 is formed through the mold on the first region (I) of the substrate 100 to expose the upper surface of the substrate 100, and then the exposed portion of the first sacrificial pattern 125 and the adjacent portion of the second insulating film 150 are removed, for example by a wet etching process, to form a third recess 280.

[0061] In one embodiment, the second openings 270 extend in the second direction (D2) and are formed between adjacent fifth insulating pattern rows in the third direction (D3) to expose the sidewalls of the fifth insulating patterns 260 included therein. In one embodiment, the third recesses 280 are formed in a plurality of locations spaced apart from each other by the fifth insulating pattern 260 along the second direction (D2), and are also formed in a plurality of locations spaced apart from each other by the first insulating pattern 115 along the first direction (D1). Here, each of the third recesses 280 exposes a portion of the sidewall of the corresponding channel 160, specifically, the sidewall in the third direction (D3). Meanwhile, in the wet etching process, the portions of the first sacrificial pattern 125 adjacent to both ends of the second opening 270 in the second direction (D2) are also removed, thereby forming the third recess 280 in a semicircular shape adjacent to each end of the second opening 270 when viewed from above.

[0062] As shown in FIGS. 28 and 29, a second ohmic contact pattern 300 is formed on the sidewall of the channel 160 exposed by the third recess 280.

[0063] In one embodiment, the second ohmic contact pattern 300 is formed by forming a second metal film on the inner walls of the second opening 270 and the third recess 280, the upper surfaces of the third and fourth insulating patterns (170, 220), the upper surface of the second insulating film 150, the upper surface of the bit line 250, the upper surface of the mold, and the upper surface of the first interlayer insulating film 130, and then performing a heat treatment process thereon to cause the metal contained in the second metal film to react with the semiconductor material contained in the channel 160, and the portion of the second metal film that does not react with the channel 160 is removed.

[0064] The second ohmic contact patterns 300 are formed in a plurality of locations spaced apart from each other along a first direction (D1) on the first region (I) of the substrate 100, and are also formed in a plurality of locations spaced apart from each other along second and third directions (D2, D3). Here, each of the second ohmic contact patterns 300 has, for example, a partial shape of a ring. Meanwhile, the second ohmic contact pattern 300 includes a semiconductor material and is also formed on the upper surface of the substrate 100 exposed by the second opening 270 .

[0065] Thereafter, a first capacitor electrode film is formed on the inner walls of the second opening 270 and the third recess 280, the upper surfaces of the third and fourth insulating patterns (170, 220), the upper surface of the second insulating film 150, the upper surface of the bit line 250, the upper surface of the mold, and the upper surface of the first interlayer insulating film 130. A second sacrificial film filling the third recess 280 is then formed on the first capacitor electrode film. The second sacrificial film is then partially removed, for example, by a wet etching process, to form a second sacrificial pattern filling the remaining portion of the third recess 280, thereby exposing the portion of the first capacitor electrode film formed on the outer periphery of the third recess 280.

[0066] Thereafter, the exposed portion of the first capacitor electrode film is removed to form a first capacitor electrode 315 on the inner wall of the third recess 280, and the second sacrificial pattern is removed. In one embodiment, the first capacitor electrodes 315 are formed in a plurality of locations spaced apart from each other along a first direction (D1) on a first region (I) of the substrate 100, and also formed in a plurality of locations spaced apart from each other along second and third directions (D2, D3) to form a first capacitor electrode array. The first capacitor electrode array includes a plurality of first capacitor electrodes 315 each spaced apart from one another in a second direction (D2) and a plurality of first capacitor electrode rows spaced apart from one another in a third direction (D3).

[0067] Each of the first capacitor electrodes 315 contacts the second ohmic contact pattern 300 and a sidewall of the second insulating film 150 , and is electrically connected to the channel 160 through the second ohmic contact pattern 300 . Meanwhile, the first capacitor electrode 315 is also formed in a third recess 280 adjacent to each of both ends of the second opening 270 in the second direction (D2), which has a semicircular shape when viewed from above.

[0068] Then, a dielectric film 320 is formed on the first capacitor electrode 315, the inner wall of the second opening 270, the upper surfaces of the third and fourth insulating patterns (170, 220), the upper surface of the second insulating film 150, the upper surface of the bit line 250, the upper surface of the mold, and the upper surface of the first interlayer insulating film 130, and a second capacitor electrode film 330 is formed on the dielectric film 320 to fill the remaining portion of the second opening 270.

[0069] As shown in Figures 30 and 31, a planarization process is performed on the second capacitor electrode film 330 and the dielectric film 320 until the top surface of the mold is exposed, thereby converting them into a second capacitor electrode 335 and a dielectric pattern 325, respectively. Here, the first capacitor electrode 315 , the dielectric pattern 325 , and the second capacitor electrode 335 together form a capacitor structure 340 .

[0070] In one embodiment, the second capacitor electrodes 335 extend along the second direction (D2) on the first region (I) of the substrate 100 and are formed in a plurality of locations spaced apart from each other along the third direction (D3). Here, each second capacitor electrode 335 includes an extension portion extending in the second direction (D2) and a first protrusion portion protruding in the third direction (D3) from each side wall of the extension portion in the third direction (D3) and facing the side wall of the channel 160. Here, the first protrusions are formed in a plurality of positions spaced apart from each other along the second and third directions (D2, D3) corresponding to the channels 160, and also formed in a plurality of positions spaced apart from each other along the first direction (D1). On the other hand, the second capacitor electrode 335 includes second protrusions adjacent to both ends of the extension in the second direction (D2) and protruding to have a semicircular shape when viewed from above.

[0071] Referring again to Figures 1 to 3, after a second interlayer insulating film 370 is formed on the third to fifth insulating patterns (170, 220, 260), the dielectric pattern 325, the second capacitor electrode 335, the second insulating film 150, the bit line 250, the mold, and the first interlayer insulating film 130, a first contact plug 380 is formed which penetrates the first and second interlayer insulating films (130, 370) and contacts the pad of the corresponding first gate electrode 210, and a second contact plug 390 is formed which penetrates the second interlayer insulating film 370 and contacts the upper surface of the corresponding bit line 250. On the other hand, although not shown in the figure, a third contact plug that penetrates the second interlayer insulating film 370 and contacts the upper surface of the corresponding second capacitor electrode 335 is also formed. By carrying out the above steps, the manufacture of the semiconductor device of the present invention is completed.

[0072] As described above, a mold including a first insulating film 110 and a first sacrificial film 120 is formed on a substrate 100, a first hole 140 is formed through the mold, and then a portion of the first sacrificial film 120 adjacent to the first hole 140 is removed to form a first recess 145, and a channel 160 is formed within the first recess 145. Thereafter, a third insulating pattern 170 is formed in the first hole 140, a first opening 180 penetrating the mold is formed, and an adjacent portion of the first sacrificial layer 120 is removed to form a second recess 190, and a first gate electrode 210 is formed in the second recess 190.

[0073] Thereafter, a portion of the third insulating pattern 170 is removed to form a second hole 230, a bit line 250 is formed in the second hole 230, a second opening 270 is formed through the mold, and an adjacent portion of the first sacrificial layer 120 is removed to form a third recess 280 that exposes the sidewall of the channel 160, and a first capacitor electrode 315 is formed in the third recess 280. Therefore, compared to when the channel 160, the first gate electrode 210, and the first capacitor electrode 315 are formed in the same layer and at least a portion of them are formed in the vertical direction, the vertical thickness is reduced, and the process of forming them can be easily performed.

[0074] FIG. 32 is a cross-sectional view for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention, and corresponds to FIG. The semiconductor device according to this embodiment is similar to the semiconductor device explained with reference to FIGS. 1 to 3 except for some components, so a duplicated explanation will be omitted.

[0075] As shown in FIG. 32, the semiconductor device according to the present embodiment further includes a metal pattern 245 covering the sidewalls of the bit lines 250 . That is, by performing the process described in Figures 22 to 24, a first ohmic contact pattern 240 is formed on the side wall of the channel 160 exposed by the second hole 230, and then the first metal film portion that does not react with the channel 160 is not removed but is left in place, and here the remaining first metal film portion is referred to as a metal pattern 245.

[0076] 33 and 34 are a plan view and a cross-sectional view for explaining a schematic configuration of a semiconductor device according to one embodiment of the present invention, and correspond to FIGS. 1 and 3, respectively. The semiconductor device according to this embodiment is similar to the semiconductor device explained with reference to FIGS. 1 to 3 except for some components, so a duplicated explanation will be omitted.

[0077] As shown in FIGS. 33 and 34, the semiconductor device according to the present embodiment does not include a third insulating pattern 170. That is, by performing the process described in Figures 19 to 21, when the second hole 230 is formed, the third insulating pattern 170 is removed as a whole, and the first ohmic contact pattern 240 and the bit line 250 are formed in the second hole 230. As a result, the first ohmic contact pattern 240 formed between the bit line 250 and the channel 160 has, for example, a ring shape and entirely surrounds the sidewall of the bit line 250 portion formed in the same layer. The channel 160 also entirely surrounds the sidewall of the bit line 250 portion formed in the same layer.

[0078] 35 and 36 are a plan view and a cross-sectional view for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention, and correspond to FIGS. 1 and 3, respectively. The semiconductor device according to this embodiment is similar to the semiconductor device explained with reference to FIGS. 1 to 3 except for some components, so a duplicated explanation will be omitted.

[0079] As shown in FIGS. 35 and 36, the semiconductor device according to this embodiment further includes a second gate electrode 450, a second gate insulation pattern 440, and a fourth contact plug 490. The second gate electrode 450 is formed on a first region (I) of the substrate 100 and extends through the first gate electrode structure and the first insulating pattern 115 in a first direction (D1). In one embodiment, the second gate electrode 450 penetrates a portion of the first gate electrode structure adjacent to the bit line 250 in the third direction (D3). The second gate electrode 450 serves as a back gate electrode in the semiconductor device.

[0080] A plurality of second gate electrodes 450 are formed on the first region (I) of the substrate 100, spaced apart from each other along the second and third directions (D2, D3), forming a second gate electrode array. In one embodiment, the second gate electrode array includes a plurality of second gate electrodes 450 each arranged in a second direction (D2) and includes second gate electrode rows spaced apart from each other in a third direction (D3). Here, two second gate electrode rows are formed between the fourth insulating patterns 220 adjacent to each other in the third direction (D3), which are formed on both sides of the second capacitor electrode 335 in the third direction (D3) and are arranged symmetrically with respect to each other based on this.

[0081] The second gate insulating pattern 440 covers the sidewalls and the bottom surface of the second gate electrode 450 . Meanwhile, unlike in FIGS. 1 to 3, the channel 160 contacts and surrounds the sidewall of the second gate insulating pattern 440 formed on the sidewall of the second gate electrode 450, instead of surrounding the sidewall of the bit line 250. However, the channel 160 contacts the first ohmic contact pattern 240 surrounding the sidewall of the bit line 250 , and is thereby electrically connected to the bit line 250 .

[0082] Meanwhile, the first capacitor electrode 315 of the capacitor structure 340 is electrically connected to the channel 160 through a second ohmic contact pattern 300 formed on the sidewall of the channel 160 in a third direction (D3) surrounding the sidewall of the second gate insulation pattern 440. The fourth contact plug 490 penetrates the second interlayer insulating film 370 and comes into contact with the upper surface of the second gate electrode 450 . Each of the second gate electrodes 450 and the fourth contact plugs 490 may include, for example, a metal, a metal nitride, a metal silicide, a semiconductor material doped with impurities, etc., and the second gate insulating pattern 440 may include, for example, an oxide such as silicon oxide.

[0083] In the semiconductor device according to this embodiment, the channel 160 surrounds the sidewall of the second gate insulation pattern 440 formed on the sidewall of the second gate electrode 450, and the first capacitor electrode 315, the channel 160, the second gate electrode 450, and the bit line 250 formed on both sides in the third direction (D3) based on the second capacitor electrode 335 extending in the second direction (D2) have mutually symmetrical shapes. In addition, the bit line 250, the first capacitor electrode 315, and the channel 160 portion formed therebetween are arranged in a third direction (D3) perpendicular to the second direction (D2), which is the extension direction of the first gate electrode 210.

[0084] 37 to 48 are plan views and cross-sectional views for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, Figures 37, 39, 41, 43, 45, and 47 are plan views, and Figures 38, 40, 42, 44, 46, and 48 are cross-sectional views taken along line CC' of the corresponding plan views. The method for manufacturing a semiconductor device according to the present embodiment includes steps similar to those described with reference to FIGS. 4 to 31 and 1 to 3, and therefore a duplicated description thereof will be omitted.

[0085] As shown in Figures 37 and 38, processes similar to those described in Figures 4 to 6 are performed to form a first hole 140 in a first region (I) of a substrate 100, and then a third insulating pattern 170 and a sixth insulating pattern 400 covering the sidewall and bottom surface of the third insulating pattern 170 are formed in the first hole 140. In one embodiment, the first holes 140 are formed in a plurality of rows spaced apart from each other along the second and third directions (D2, D3) to form a first hole array, and the first hole array includes a plurality of first holes 140 each arranged in the second direction (D2) and a plurality of rows of first holes spaced apart from each other along the third direction (D3).

[0086] As shown in Figures 39 and 40, an etching process is performed on the mold portion formed on the first region (I) of the substrate 100 to expose the top surface of the substrate 100 and form a fourth hole extending in a first direction (D1). In one embodiment, the fourth holes are formed in a plurality of locations spaced apart from each other along the second and third directions (D2, D3) on the first region (I) of the substrate 100, and the fourth holes are each formed adjacent to the first holes 140 in the third direction (D3).

[0087] Thereafter, the same processes as those described in Figures 7 and 8 are performed to form a fourth recess communicating with the fourth hole, and a second insulating film 150 is formed on the inner walls of the fourth hole and the fourth recess, the upper surface of the mold, and the upper surface of the first interlayer insulating film 130, and then a channel 160 is formed in the fourth recess. The fourth recess is formed by removing the portion of the first sacrificial film 120 exposed by the fourth hole, and further by partially removing the sixth insulating pattern 400 adjacent to the first sacrificial film 120 to expose a portion of the sidewall of the third insulating pattern 170. As a result, the portion of the second insulating film 150 formed on the inner wall of the fourth recess comes into contact with the exposed sidewall portion of the third insulating pattern 170 .

[0088] Thereafter, a third sacrificial layer is formed on the second insulating layer 150 and the channel 160 to partially fill the fourth hole, and a fourth sacrificial layer is formed on the third sacrificial layer to fill the remaining portion of the fourth hole. After that, a planarization process is performed on the third and fourth sacrificial layers until the top surface of the mold and the top surface of the first interlayer insulating layer 130 are exposed, thereby forming third and fourth sacrificial patterns (410, 420), respectively, in the fourth hole.

[0089] The third sacrificial pattern 410 comprises an insulating material such as, for example, silicon oxycarbide, silicon oxynitride, silicon nitride, etc., and the fourth sacrificial pattern 420 comprises an oxide such as, for example, silicon oxide. On the other hand, in the planarization step, the portions of the second insulating film 150 formed on the upper surface of the mold and the upper surface of the first interlayer insulating film 130 are also removed.

[0090] As shown in FIGS. 41 and 42, the same steps as those described with reference to FIGS. 11 to 18 are performed to form a first gate insulating film 200, a first gate electrode 210, and a fourth insulating pattern 220. Here, the first gate insulating layer 200 contacts the sidewalls of the sixth insulating pattern 400 , the channel 160 and the first sacrificial pattern 125 .

[0091] As shown in FIGS. 43 and 44, the same processes as those described with reference to FIGS. 19 to 24 are performed to form a first ohmic contact pattern 240 and a bit line 250. As shown in FIG. However, as shown in Figures 33 and 34, the first ohmic contact pattern 240 and the bit line 250 can be formed after the third insulating pattern 170 is entirely removed, but the present invention is not limited to this, and as shown in Figures 22 to 24, the first ohmic contact pattern 240 and the bit line 250 can also be formed after the third insulating pattern 170 is partially removed.

[0092] As shown in Figures 45 and 46, the third and fourth sacrificial patterns (410, 420) are removed to form a fifth hole exposing the sidewall of the channel 160 and the top surface of the substrate 100, and here, the portion of the second insulating film 150 formed on the sidewall of the first insulating pattern 115 is also removed, exposing the sidewall of the first insulating pattern 115. Thereafter, a second gate insulating film is formed on the inner wall of the fifth hole, the upper surface of the bit line 250, the upper surface of the sixth insulating pattern 400, the upper surface of the mold, and the upper surface of the first interlayer insulating film 130. A second gate electrode film is formed on the second gate insulating film. Then, a planarization process is performed on the second gate electrode film and the second gate insulating film until the upper surface of the mold is exposed, and a second gate electrode 450 and a second gate insulating pattern 440 are formed in the fifth hole, respectively.

[0093] As shown in FIGS. 47 and 48, the fifth insulating pattern 260, the second ohmic contact pattern 300, and the capacitor structure 340 are formed by performing the same processes as those described with reference to FIGS. Here, the first capacitor electrode 315 of the capacitor structure 340 is electrically connected to the channel 160 through the second ohmic contact pattern 300 .

[0094] Again, as shown in FIGS. 35 and 36, steps similar to those described with reference to FIGS. 1 to 3 are carried out to complete the manufacture of the semiconductor device according to this embodiment. However, a fourth contact plug 490 penetrating the second interlayer insulating film 370 and in contact with the upper surface of the corresponding second gate electrode 450 is further formed.

[0095] 49 to 51 are plan views and cross-sectional views for explaining a schematic configuration of a semiconductor device according to one embodiment of the present invention. The semiconductor device according to this embodiment is similar to the semiconductor device explained with reference to FIGS. 1 to 3 except for some components, so a duplicated explanation will be omitted.

[0096] As shown in Figures 49 to 51, unlike the semiconductor device in Figures 1 to 3, the bit line 250, the first capacitor electrode 315, and the channel 160 portion formed therebetween are arranged in a second direction (D2), which is the extension direction of the first gate electrode 210. In one embodiment, a first gate electrode structure is formed between adjacent fourth insulating patterns 220 in the third direction (D3), and a bit line column including a plurality of bit lines 250 arranged in the second direction (D2), a channel column including a plurality of channels 160 arranged in the second direction (D2), and a capacitor structure column including a plurality of capacitor structures 340 arranged in the second direction (D2) are formed penetrating the first gate electrode structure.

[0097] Here, each bit line column includes two bit lines 250 spaced apart from each other by a first distance in the second direction (D2), and includes a plurality of bit line pairs spaced apart from each other by a second distance along the second direction (D2) that is greater than the first distance. However, only one bit line 250 is arranged at each end of the bit line array in the second direction (D2). The drawing shows a bit line 250 arranged at one end of the bit line array, and one adjacent bit line pair.

[0098] The channel 160 surrounds the sidewall of the bit line 250 and the third insulating pattern 170 in contact therewith, and a first ohmic contact pattern 240 is formed between the channel 160 and the bit line 250 . A capacitor structure 340 is formed between a pair of bit lines adjacent to each other in the second direction (D2). Here, the second capacitor electrode 315 of the capacitor structure 340 includes an extension portion extending in a first direction (D1) between the bit line pair, and a protrusion portion extending in the second direction (D2) from each side wall of the extension portion in the second direction (D2). As a result, two first capacitor electrodes 315 spaced apart from each other in the second direction (D2) are formed between the bit line pair.

[0099] In the semiconductor device according to this embodiment, the first capacitor electrode 315, the channel 160, and the bit line 250 formed on both sides of the second direction (D2) have symmetrical shapes relative to each other with respect to a virtual line that passes through the extension portion of the second capacitor electrode 335 and extends in the third direction (D3).

[0100] 52 to 66 are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, Figures 52, 54, 56, 59, 62, and 65 are plan views, Figures 53, 55, 57, 60, 63, and 66 are cross-sectional views taken along line E-E' in the corresponding plan views, and Figures 58, 61, and 64 are cross-sectional views taken along line F-F' in the corresponding plan views. The method for manufacturing a semiconductor device according to the present embodiment includes steps similar to those described with reference to FIGS. 4 to 31 and 1 to 3, and therefore a duplicated description thereof will be omitted.

[0101] As shown in FIGS. 52 and 53, a first hole 140 is formed in a first region (I) of the substrate 100 by carrying out steps similar to those described with reference to FIGS. The first holes 140 are formed in a plurality of rows spaced apart from each other along the second and third directions (D2, D3) to form a first hole array, and the first hole array includes a plurality of first holes 140 each arranged in the second direction (D2) and a plurality of first hole rows spaced apart from each other along the third direction (D3).

[0102] In one embodiment, each first hole row includes two first holes 140 spaced apart from each other by a first distance in the second direction (D2), and includes a plurality of first hole pairs spaced apart from each other by a second distance along the second direction (D2) that is greater than the first distance. However, only one first hole 140 is arranged at each end of each first hole row in the second direction (D2). The drawing shows a first hole 140 located at one end of each row of first holes, and one adjacent pair of first holes.

[0103] As shown in FIGS. 54 and 55, the same processes as those described with reference to FIGS. 7 to 10 are performed to form a second insulating film 150, a channel 160, and a third insulating pattern 170. As shown in FIGS. 56 to 58, the same steps as those described with reference to FIGS. 11 to 13 are performed to form a first opening 180 and a second recess 190. As shown in FIG.

[0104] In one embodiment, each first opening 180 is formed between adjacent channel rows in the third direction (D3), and one channel row is disposed between adjacent first openings 180 in the third direction (D3). Meanwhile, the second recesses 190 are formed by entirely removing the portions of the first sacrificial pattern 125 formed between adjacent first openings 180 in the third direction (D3) to expose the sidewalls of each channel 160 included in the channel row.

[0105] As shown in FIGS. 59 to 61, the same steps as those described with reference to FIGS. 14 to 18 are performed to form a first gate insulating film 200, a first gate electrode 210, and a fourth insulating pattern 220. Here, the first gate insulating film 200 surrounds the sidewalls of the channel 160 .

[0106] As shown in FIGS. 62 to 64, the same processes as those described with reference to FIGS. 19 to 24 are performed to form a first ohmic contact pattern 240 and a bit line 250. As shown in FIGS. However, as shown in FIGS. 33 and 34, the first ohmic contact pattern 240 and the bit line 250 may be formed after the third insulating pattern 170 is entirely removed.

[0107] As shown in FIGS. 65 and 66, the fifth insulating pattern 260, the second ohmic contact pattern 300, and the capacitor structure 340 are formed by performing the same processes as those described with reference to FIGS.

[0108] 49 to 51 again, steps similar to those described with reference to FIGS. 1 to 3 are carried out to complete the manufacture of the semiconductor device according to this embodiment.

[0109] FIG. 67 is a plan view for explaining a schematic configuration of a semiconductor device according to one embodiment of the present invention. The semiconductor device according to this embodiment is similar to the semiconductor device described with reference to FIGS. 49 to 51 except for some components, so a duplicated description will be omitted.

[0110] As shown in Figure 67, unlike the semiconductor devices in Figures 49 to 51, two first gate electrode structures are formed between fourth insulating patterns 220 adjacent to each other in the third direction (D3), and one bit line row, one channel row, and one capacitor structure row are formed penetrating each first gate electrode structure. However, each channel 160 included in the channel column is not completely surrounded by each first gate electrode 210 included in the first gate electrode structure, and one side in the third direction (D3) is covered by the first sacrificial pattern 125.

[0111] In the semiconductor device according to this embodiment, the first capacitor electrode 315, the channel 160, and the bit line 250 formed on both sides of the second direction (D2) based on an imaginary line passing through the second capacitor electrode 335 and extending in the third direction (D3) have mutually symmetrical shapes. In addition, the capacitor structure 340, the channel 160, and the bit line 250 formed on both sides in the third direction (D3) based on an imaginary line passing through the fifth insulating pattern 260 and extending in the second direction (D2) have symmetrical shapes to each other.

[0112] 68 to 70 are plan views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device according to this embodiment includes steps similar to those explained with reference to FIGS. 52 to 66 and 49 to 51, and therefore a duplicated explanation thereof will be omitted.

[0113] As shown in FIG. 68, a first hole 140 is formed in a first region (I) of the substrate 100 by performing steps similar to those described with reference to FIGS. As shown in Figure 69, processes similar to those described in Figures 54 to 61 are performed to form a second insulating film 150, a channel 160, a third insulating pattern 170, a first gate insulating film 200, a first gate electrode 210, and a fourth insulating pattern 220.

[0114] In one embodiment, each first opening 180 is formed between adjacent channel rows in the third direction (D3), and two of the channel rows are disposed between adjacent first openings 180 in the third direction (D3). On the other hand, the second recess 190 is formed by removing portions of the first sacrificial pattern 125 adjacent to the first openings 180 that are adjacent to each other in the third direction (D3), such that the portion of the first sacrificial pattern 125 formed in the center between the first openings 180 is not removed but remains. The first gate insulating film 200 contacts a portion of the sidewall of the channel 160 , and the remaining portion of the sidewall of the channel 160 contacts the sidewall of the first sacrificial pattern 125 .

[0115] As shown in Figure 70, by performing processes similar to those described in Figures 62 to 66, a first ohmic contact pattern 240, a bit line 250, a fifth insulating pattern 260, a second ohmic contact pattern 300, and a capacitor structure 340 are formed. Referring again to FIG. 67, the manufacture of the semiconductor device according to this embodiment is completed by carrying out steps similar to those described with reference to FIGS.

[0116] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0117] 100 Substrates 110 First insulating film 115 First insulating pattern 125 First Sacrifice Pattern 130 First interlayer insulating film 140 First Hall 145 First Recess 150 Second insulating film 160 Channels 170 Third Insulation Pattern 180 First opening 190 Second Recess 200 First gate insulating film 210 First gate electrode 220 Fourth Insulation Pattern 230 Second Hall 240 First ohmic contact pattern 250 bit lines 260 Fifth Insulation Pattern 270 Second Opening 280 Third Recess 300 Second ohmic contact pattern 315 First Capacitor Electrode 325 Dielectric Pattern 335 Second Capacitor Electrode 340 Capacitor Structure 370 Second interlayer insulating film 380 First Contact Plug 390 Second Contact Plug

Claims

1. a bit line formed on a substrate and extending in a first direction perpendicular to an upper surface of the substrate; a channel surrounding at least a portion of a sidewall of the bitline; a word line formed on the substrate, at least a portion of which overlaps with the channel in a horizontal direction parallel to an upper surface of the substrate; a capacitor electrically connected to the channel, at least a portion of which overlaps with the channel and the word line in the horizontal direction.

2. 2. The semiconductor device according to claim 1, wherein the channel entirely surrounds a sidewall of the bit line portion formed in the same layer as the channel.

3. an insulating pattern extending in the first direction on the substrate and contacting a sidewall of the bit line; 2. The semiconductor device of claim 1, wherein the channel entirely surrounds a sidewall of a structure including the bit line portion and the insulating pattern portion, the structure being formed in the same layer as the channel.

4. 2. The semiconductor device according to claim 1, further comprising an ohmic contact pattern formed between the channel and a sidewall of the bit line.

5. 2. The device according to claim 1, wherein the word line entirely surrounds a sidewall of the channel.

6. the word lines extend in a second direction parallel to a top surface of the substrate; 2. The semiconductor device according to claim 1, wherein the bit line and the capacitor are arranged in a third direction that is parallel to an upper surface of the substrate and intersects with the second direction.

7. the word lines extend in a second direction parallel to a top surface of the substrate; 2. The semiconductor device according to claim 1, wherein the bit line and the capacitor are arranged in the second direction.

8. The capacitor is An extension portion extending in the first direction; a second capacitor electrode including a protrusion protruding in the horizontal direction from a sidewall of the extension; a dielectric pattern formed on upper and lower surfaces of the protrusion of the second capacitor electrode and on a side wall facing the side wall of the channel; 2. The semiconductor device according to claim 1, further comprising: a first capacitor electrode formed on upper and lower surfaces of the dielectric pattern and on a sidewall opposite to a sidewall of the channel.

9. a bit line formed on a substrate and extending in a first direction perpendicular to an upper surface of the substrate; a back gate electrode formed on the substrate, spaced apart from the bit line in a horizontal direction parallel to an upper surface of the substrate, and extending in the first direction; a channel surrounding a sidewall of the back gate electrode and electrically connected to the bit line; a word line formed on the substrate, the word line at least partially overlapping the channel in the horizontal direction; a capacitor electrically connected to the channel, at least a portion of which overlaps with the channel and the word line in the horizontal direction.

10. a plurality of bit lines formed on a substrate, each extending in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other in a second direction parallel to the upper surface of the substrate; channels formed along sidewalls of each of the bitlines, spaced apart from one another in the first direction, each surrounding at least a portion of a sidewall of each of the bitlines; word lines extending in the second direction on the substrate and spaced apart from one another along the first direction, each word line at least partially overlapping a corresponding one of the channels in the second direction; capacitors spaced apart from each other in the first direction, each of which is parallel to an upper surface of the substrate and at least partially overlaps the channel corresponding to a third direction intersecting the second direction; and contact plugs each extending in the first direction and in contact with an upper surface of the word line.

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