Electronic device and driving method for transistor

Abstract

To realize operation of both an excitatory synapse and an inhibitory synapse using a pulse voltage of one of positive and negative polarities.SOLUTION: An electronic device includes a transistor including a first gate electrode, a first gate insulating film, a first semiconductor film of a first conductivity type provided on the first gate insulating film, a second semiconductor film of a second conductivity type provided on the first gate insulating film and partially in contact with the first semiconductor film, a memory film provided on each of the first semiconductor film and the second semiconductor film, a second gate insulating film provided on the memory film, and a second gate electrode provided on the second gate insulating film, a first circuit that reads out drain current of the transistor in a first period, and a second circuit that applies a gate voltage where the drain current flows to the second gate electrode in the first period and applies a pulse voltage to the second gate electrode in a second period.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to an electronic device and a method for driving a transistor. [Background technology]

[0002] In order to realize an Internet of Things (IoT) society and a decarbonized society, integrated circuits capable of processing information at high speeds and with low power consumption are being developed. One such integrated circuit is a neuron mimicking computer. In a von Neumann-type computer, in which a processor executes instructions sequentially and writes the results to memory, communication between the processor and memory becomes a bottleneck, limiting how fast it can be. In contrast, a neuron mimicking computer can easily operate at high speeds because the multiple neurons that make up the artificial neural network operate independently and in parallel. Moreover, a neuron mimicking computer can also reduce power consumption because only the neurons that receive signals at synapses among the multiple neurons operate independently.

[0003] Neuron-inspired computers have been realized in various ways, including using memristors. In addition, a technology has been proposed to realize a neuron-inspired computer using anti-ambipolar transistors that combine field-effect transistors and floating gate memories (Non-Patent Document 1).

[0004] In the anti-ambipolar transistor of Non-Patent Document 1, a gate insulating film of HfO2 is formed on a gate electrode, and a ReS2 film of an n-type semiconductor and a black phosphorus film of a p-type semiconductor are laminated in this order on a partial region of the gate insulating film. The ReS2 film is not present beside the partial region of the gate insulating film, and the black phosphorus film is formed on the gate insulating film via the natural oxide film. The natural oxide film of the black phosphorus film functions as a floating gate that accumulates electric charge, and the threshold voltage of the transistor changes depending on the amount of electric charge.

[0005] For example, when a positive pulse voltage is repeatedly applied to the gate electrode, electrons are accumulated in the natural oxide film, which allows operation corresponding to an excitatory synapse, where the drain current increases with the number of times the pulse voltage is applied. When a negative pulse voltage is then repeatedly applied to the gate electrode, the electrons accumulated in the natural oxide film are released, allowing operation corresponding to an inhibitory synapse, where the drain current decreases with the number of times the pulse is applied. By using such changes in the drain current as the weighting coefficients of an artificial neural network, a neuron-mimicking computer can be realized. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] X. Xiong et al., “Reconfigurable Logic-in-Memory and Multilingual Artificial Synapses Based on 2D Heterostructures”, Advanced Functional Materials, vol. 30, page 1909645, 2020 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the technology of Non-Patent Document 1, it is necessary to apply pulse voltages of two polarities, positive and negative, to the gate electrode in order to realize the operation of both excitatory and inhibitory synapses. Therefore, the circuit configuration of the voltage generation circuit that generates the pulse voltage becomes complicated, and the accompanying circuit delay makes it difficult to shorten the generation interval of the pulse voltage.

[0008] In one aspect, the present invention aims to enable the operation of both excitatory synapses and inhibitory synapses to be achieved by using a pulse voltage of either positive or negative polarity. [Means for solving the problem]

[0009] According to one aspect, an electronic device has a transistor including a first gate electrode, a first gate insulating film provided on the first gate electrode, a first semiconductor film of a first conductivity type provided in a first region on the first gate insulating film, a second semiconductor film of a second conductivity type provided in a second region on the first gate insulating film and having a portion in contact with the first semiconductor film, a memory film provided on each of the first semiconductor film and the second semiconductor film and in which an internal electric field remains, a second gate insulating film provided on the memory film, and a second gate electrode provided on the second gate insulating film; a first circuit that reads out a drain current flowing between the first semiconductor film and the second semiconductor film during a first period; and a second circuit that applies a gate voltage to the second gate electrode during the first period such that the drain current flows, and applies a pulse voltage to the second gate electrode during a second period different from the first period.

[0010] In the electronic device, the gate voltage may be a first gate voltage at which the drain current decreases as the cumulative time during which the pulse voltage is applied increases.

[0011] In the above electronic device, the gate voltage may be a second gate voltage at which the drain current increases as the cumulative time during which the pulse voltage is applied increases.

[0012] In the above electronic device, the gate voltage may be a third gate voltage at which the drain current changes from increasing to decreasing as the cumulative time during which the pulse voltage is applied increases.

[0013] In the above electronic device, the second circuit may narrow the pulse width of the pulse voltage before the drain current changes from increasing to decreasing compared to the pulse width of the pulse voltage after the drain current changes from increasing to decreasing.

[0014] In the above electronic device, the second circuit may apply a voltage having an opposite polarity to the pulse voltage before a period in which the drain current increases as the accumulation time increases.

[0015] In the above electronic device, the first circuit may apply a forward voltage between the first semiconductor film and the second semiconductor film during the first period.

[0016] In the above electronic device, the memory film may be a carrier accumulation film that accumulates carriers, or a ferroelectric film.

[0017] In the above electronic device, the carrier accumulation film may be star polystyrene in which polystyrene is bonded to metal phthalocyanine.

[0018] According to one aspect, a method for driving a transistor includes a first gate electrode, a first gate insulating film provided on the first gate electrode, a first semiconductor film of a first conductivity type provided in a first region on the first gate insulating film, a second semiconductor film of a second conductivity type provided in a second region on the first gate insulating film and having a portion in contact with the first semiconductor film, a memory film provided on each of the first semiconductor film and the second semiconductor film and in which an internal electric field remains, a second gate insulating film provided on the memory film, and a second gate electrode provided on the second gate insulating film, the driving method including: reading out a drain current flowing between the first semiconductor film and the second semiconductor film during a first period; applying a gate voltage to the second gate electrode during the first period such that the drain current flows; and applying a pulse voltage to the second gate electrode during a second period different from the first period.

[0019] In the above-described method for driving a transistor, the gate voltage may be a first gate voltage at which the drain current decreases as the cumulative time during which the pulse voltage is applied increases.

[0020] In the above-described method for driving a transistor, the gate voltage may be a second gate voltage at which the drain current increases as the cumulative time during which the pulse voltage is applied increases.

[0021] In the above-described method for driving a transistor, the gate voltage may be a third gate voltage at which the drain current changes from increasing to decreasing as the cumulative time during which the pulse voltage is applied increases.

[0022] In the above-described transistor driving method, a pulse width of the pulse voltage before the drain current changes from increasing to decreasing may be narrower than a pulse width of the pulse voltage after the drain current changes from increasing to decreasing.

[0023] The above-described method for driving a transistor may further include applying a voltage having an opposite polarity to the pulse voltage before a period in which the drain current increases as the accumulation time increases. Effect of the Invention

[0024] According to the present invention, it is possible to realize the operation of both excitatory synapses and inhibitory synapses by using a pulse voltage of either positive or negative polarity. [Brief description of the drawings]

[0025] [Figure 1] 1(a) and (b) are cross-sectional views (part 1) of an anti-ambipolar transistor according to this embodiment during its manufacture. [Diagram 2] 2(a) and (b) are cross-sectional views (part 2) of the anti-ambipolar transistor according to this embodiment during its manufacture. [Diagram 3] FIG. 3 is a cross-sectional view (part 3) of the anti-ambipolar transistor according to this embodiment during its manufacture. [Figure 4] 4(a) and (b) are optical microscope images taken from above of an anti-ambipolar transistor in the process of being manufactured according to this embodiment. [Diagram 5]5(a) and 5(b) are schematic cross-sectional views for explaining the operation of the anti-ambipolar transistor according to this embodiment. [Figure 6] FIG. 6 is a schematic diagram of an electronic device including an anti-ambipolar transistor according to this embodiment. [Figure 7] FIG. 7 is a graph showing the results of investigating the current-voltage characteristics of the anti-ambipolar transistor according to this embodiment. [Figure 8] Figures 8(a) to (c) are diagrams (part 1) obtained from an investigation into whether operations similar to excitatory synapses and inhibitory synapses can be realized. [Figure 9] Figures 9(a) to (c) are diagrams (part 2) showing that operations similar to excitatory synapses and inhibitory synapses can be realized. [Figure 10] Figures 10(a) to (c) are diagrams (part 3) showing that similar operations can be achieved for both excitatory and inhibitory synapses. [Figure 11] 11(a) to (c) are schematic diagrams showing that the anti-ambipolar transistor according to this embodiment can be applied to an artificial neural network. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that like elements are given like reference numerals and their description will be omitted.

[0027] In the anti-ambipolar transistor according to the present embodiment, the lower gate voltage is adjusted to realize both excitatory and inhibitory synapse operations with only a positive or negative pulse voltage. The anti-ambipolar transistor will be described while following its manufacturing process.

[0028] 1 to 3 are cross-sectional views of the anti-ambipolar transistor according to the present embodiment during its manufacture.

[0029] First, as shown in FIG. 1(a), a silicon substrate is prepared as a first gate electrode 11, and a silicon oxide film is formed as an underlying insulating film 12 to a thickness of about 90 nm by thermally oxidizing the surface of the silicon substrate.

[0030] 1(b), a hexagonal boron nitride (h-BN) film having a thickness of about 24 nm is transferred as a first gate insulating film 13 onto the base insulating film 12 in the channel region R0 of the transistor by a dry transfer method. In the dry transfer method, the hexagonal boron nitride film attached to a stamp (not shown) is pressed against the base insulating film 12 to transfer the hexagonal boron nitride film to the base insulating film 12. As the stamp, for example, a gel-like PDMS (polydimethylsiloxane) stamp having a surface coated with a PPC (polypropylene carbonate) film is used.

[0031] Furthermore, a ReS2 film having a thickness of about 11 nm is transferred as an n-type first semiconductor film 15 onto the first gate insulating film 13 in the first region R1. Then, a WSe2 film having a thickness of about 13 nm is transferred as a second semiconductor film 16 onto the first gate insulating film 13 and the first semiconductor film 15 in the second region R2. Each of the semiconductor films 15 and 16 is a two-dimensional layered compound, and is transferred by dry transfer using a PDMS stamp, similar to the base insulating film 12. Note that the n-type is an example of the first conductive type, and the p-type is an example of the second conductive type.

[0032] Moreover, the regions R1 and R2 are set to overlap each other in part of the channel region R0. Therefore, a part 16a of the second semiconductor film 16 is formed to contact the upper surface of the first semiconductor film 15, thereby forming a pn junction at the interface between the semiconductor films 15 and 16.

[0033] Each of the semiconductor films 15 and 16 is not limited to the above and may be an organic semiconductor film. In this example, a part 16a of the second semiconductor film 16 is laminated on the first semiconductor film 15, but the order of lamination is not limited to this. For example, the second semiconductor film 16 may be formed on the first gate insulating film 13 first, and then the first semiconductor film 15 may be formed on the first gate insulating film 13, so that a part of the first semiconductor film 15 is laminated on the second semiconductor film 16.

[0034] 2(a), a chromium film and a gold film are laminated in this order on the first semiconductor film 15 by electron beam heating deposition, and the laminated film is patterned by electron beam lithography to remain as a drain electrode 18d. Also, a palladium film and a gold film are laminated in this order on the second semiconductor film 16 by electron beam heating deposition, and the laminated film is patterned by electron beam lithography to remain as a source electrode 18s.

[0035] Next, as shown in Figure 2(b), a ZnPc-PS4 film is formed by spin coating on each of the semiconductor films 15, 16 and each of the electrodes 18d, 18s to a thickness of about 20 nm as memory film 19. Memory film 19 is a carrier accumulation film that accumulates carriers that have migrated from each of the semiconductor films 15, 16 when a voltage is applied, and in which an internal electric field caused by the carriers remains even after the applied voltage is removed. ZnPc-PS4, the material for the carrier accumulation film, is a material that uses zinc as the metal element M in the following general formula, and metal phthalocyanine plays the role of accumulating carriers.

[0036] [ka]

[0037] As shown in the above general formula, ZnPc-PS4 is a star polystyrene (MPc-PS4) in which polystyrene is bonded to four benzene rings of a metal phthalocyanine complex, and uses zinc as the central metal M. The material of memory film 19 is not limited to ZnPc-PS4, and may be MPc-PS4 in which any of the transition metals copper, nickel, cobalt, iron, and manganese is used as the central metal M.

[0038] 3, a hexagonal boron nitride film is transferred onto the memory film 19 as a second gate insulating film 20 by the above-mentioned transfer method. The material of the second gate insulating film 20 is not limited to hexagonal boron nitride, and may be alumina (Al2O3) or hafnium oxide (HfO2). Furthermore, a silicon oxide film is formed to a thickness of about 100 nm on the entire upper surface of the base insulating film 12 by electron beam heating deposition, and the silicon oxide film is patterned by electron beam lithography to remain as an insulating sidewall 21 around the channel region R0. The insulating sidewall 21 can prevent the memory film 19 from dissolving around the channel region R0.

[0039] Thereafter, a titanium film and a gold film are laminated in this order on the second gate insulating film 20 by electron beam heating deposition, and the laminated film is patterned by electron beam lithography to form a second gate electrode 22.

[0040] With the above steps, the basic structure of the anti-ambipolar transistor 10 according to this embodiment is completed.

[0041] The anti-ambipolar transistor 10 is a p-type MOS transistor TR p and n-type MOS transistor TR n It is equivalent to an inverter circuit in which the above are connected in parallel.

[0042] Of these, the MOS transistor TR n is a transistor having an n-type first semiconductor film 15 as a channel, and the on / off of the channel is controlled by the voltages of the first gate electrode 11 and the second gate electrode 22, respectively.

[0043] In addition, the MOS transistor TR p is a transistor having a p-type second semiconductor film 16 as a channel, and an n-type MOS transistor TR n The channel of the MOS transistor TR p The on / off of the channel is controlled by the voltages of the first gate electrode 11 and the second gate electrode 22, respectively.

[0044] 4(a) and (b) are optical microscope images taken from above of the anti-ambipolar transistor 10 according to this embodiment during its manufacture.

[0045] 4(a) is an optical microscope image before the formation of the memory film 19. As shown in FIG. 4(a), the hexagonal boron nitride film formed as the first gate insulating film 13 is flake-shaped in top view, and the semiconductor films 15 and 16, which are elongated in top view, are provided thereon. In this example, two source electrodes 18s and two drain electrodes 18d are formed.

[0046] On the other hand, Fig. 4(b) is an optical microscope image after forming the second gate electrode 22. As shown in Fig. 4(b), the hexagonal boron nitride film formed as the second gate insulating film 20 is also flake-shaped in top view, and the second gate electrode 22, which is rectangular in top view, is provided thereon.

[0047] Furthermore, it can be confirmed that the memory layer 19 does not exist outside the insulating sidewall 21, and the insulating sidewall 21 prevents the memory layer 19 from dissolving into the surrounding area.

[0048] Next, the operation of the antibipolar transistor 10 according to the present embodiment will be described.

[0049] 5(a) and (b) are schematic cross-sectional views for explaining the operation of the anti-ambipolar transistor 10 according to this embodiment. In the following, the voltage applied to the first gate electrode 11 is the lower gate voltage V bg and the voltage applied to the second gate electrode 22 is the upper gate voltage V tg It is written as follows.

[0050] Figure 5(a) shows the V tg -V bg 5(a), in this case, holes move from each of the semiconductor films 15 and 16 to MPc-PS4 of the memory film 19, and holes are accumulated in the memory film 19 in almost the entire region of the channel region R0.

[0051] Figure 5(b) shows the V tg -V bg is a schematic cross-sectional view when the potential difference is positive. As shown in Fig. 5(b), in this case, electrons move from the first semiconductor film 15 to MPc-PS4 of the memory film 19, and electrons are accumulated in the memory film 19 closer to the drain electrode 18d. On the other hand, almost no electrons move from the second semiconductor film 16 to the memory film 19, and almost no electrons are accumulated in the memory film 19 closer to the source electrode 18s.

[0052] This is believed to be because, immediately after a voltage is applied to each gate electrode 11, 22 (see Figure 3), electrons move from the second semiconductor film 16 to the memory film 19 near the source electrode 18s, but over time, due to the action of WSe2 that constitutes the second semiconductor film 16, the electrons near the second semiconductor film 16 move out of the memory film 19.

[0053] In the anti-ambipolar transistor 10, V tg -V bg When the value of is positive, the electrons stored in the memory film 19 are biased.

[0054] The material of the memory film 19 is not limited to MPc-PS4 as long as it is a material that allows carriers to accumulate and an internal electric field to remain. For example, a laminated film in which an insulating film and a metal film are laminated in this order may be used as the memory film 19, and carriers may be accumulated in the metal film. The insulating film of the laminated film serves to insulate the electrodes 18s, 18d and the semiconductor films 15, 16 from the metal film.

[0055] Furthermore, a ferroelectric film may be formed as the memory film 19. In this case, the lower gate voltage V bg and the upper gate voltage V tg A polarization corresponding to the potential difference with respect to the positive electrode 14 occurs in the memory film 19, and an internal electric field remains due to the polarization.

[0056] FIG. 6 is a schematic diagram of an electronic device including an anti-ambipolar transistor 10 according to this embodiment.

[0057] As shown in FIG. 6, the electronic device 40 includes an anti-ambipolar transistor 10, a read circuit 41, an upper gate voltage application circuit 42, and a lower gate voltage application circuit 43.

[0058] The read circuit 41 applies a drain voltage V to the drain electrode 18d with the source electrode 18s grounded. d By applying a voltage Vcc, a drain current I d The read circuit 41 is a circuit for reading out the drain voltage V d and the drain voltage V d The read circuit 41 is an example of a first circuit.

[0059] The upper gate voltage application circuit 42 is an example of a second circuit, and applies an upper gate voltage V tg Furthermore, the upper gate voltage application circuit 42 is a circuit that applies the upper gate voltage V tg and the upper gate voltage V tg and the period during which the voltage is applied.

[0060] The lower gate voltage application circuit 43 is an example of a third circuit, and applies a lower gate voltage V bg Furthermore, the lower gate voltage application circuit 43 is a circuit that applies the lower gate voltage V bg and the lower gate voltage V bg and the period during which the voltage is applied.

[0061] FIG. 7 is a graph showing the current-voltage characteristics of the anti-ambipolar transistor 10 obtained by using the circuits 41 to 43. In this study, the upper gate voltage V tg and the drain current I d The relationship between the drain current I d The lower gate voltage V bg is -10V, and the drain voltage V d was set to -0.5V.

[0062] 7 is a graph showing the current-voltage characteristics in the initial state where no holes or electrons are stored in the memory film 19. In the initial state, the upper gate voltage V tg With the increase of d Also increases, V tg = Drain current I d The peak of the upper gate voltage V tg When exceeds -0.05V, the drain current I d has started to decrease, and V tg It became zero around 1.5V.

[0063] As described above, the anti-ambipolar transistor 10 includes each MOS transistor TR n , T.R. p As shown in Figure 7, the upper gate voltage V tg The drain current is lower than the peak height in the negative region of the p-type MOS transistor TR p is in the on state, but the n-type MOS transistor TR n This is because the upper gate voltage V tgThe drain current is lower than the peak height in the positive region of the n-type MOS transistor TR n is in the on state, but the p-type MOS transistor TR p is close to the off state.

[0064] The dotted line in Figure 7 indicates the V tg 1 is a graph showing current-voltage characteristics measured after applying a pulse voltage of −16 V to the second gate electrode 22 ten times. In this case, the drain current I d The peak height of the drain current I d The peak position of V tg =-1.05V, and compared to the initial state, V tg The peak position of the MOS transistor TR shifted in the negative direction. This is because an internal electric field remains in the memory film 19 due to holes accumulated in almost the entire channel region R0 as shown in FIG. 5(a), and the internal electric field weakens the electric field around the second gate electrode 22. n , T.R. p This is thought to be because the threshold voltages of both

[0065] On the other hand, the dashed line in Figure 7 shows the V tg 1 is a graph showing current-voltage characteristics measured after applying a pulse voltage of +15 V to the second gate electrode 22 ten times. In this case, the drain current I d This is because the peak height of the n-type MOS transistor TR n The threshold voltage of the p-type MOS transistor TR increases from the initial state, whereas the threshold voltage of the p-type MOS transistor TR p This is thought to be because the threshold voltage of is almost the same as that in the initial state.

[0066] Thus, with the anti-ambipolar transistor 10, the upper gate voltage V tg When a negative pulse voltage is repeatedly applied as dThe upper gate voltage V tg shifts in the negative direction. Meanwhile, the upper gate voltage V tg When a positive pulse voltage is repeatedly applied as d The upper gate voltage V tg is shifted in the positive direction and the peak height is reduced. By using this shift in the peak position, we can realize operations similar to excitatory and inhibitory synapses as follows.

[0067] Figures 8(a) to (c) are diagrams (part 1) obtained from an investigation into whether operations similar to excitatory synapses and inhibitory synapses can be realized.

[0068] FIG. 8(a) shows the upper gate voltage V tg and the bottom gate voltage V bg 1 is a diagram showing the waveforms of

[0069] As shown in FIG. 8(a), in this example, in the first period T1, the lower gate voltage application circuit 43 (see FIG. 6) applies the lower gate voltage V bg was set to −10 V. The lower gate voltage V bg is an example of an on-voltage that turns on the channels of the first semiconductor layer 15 and the second semiconductor layer 16. This also applies to Figs. 8(b), 9(a), 9(b), 10(a), and 10(b) described later.

[0070] In the first period T1, the read circuit 41 detects a drain current I d The first period T1 is a period during which the drain voltage V d was set to −0.5 V. As a result, a forward voltage was applied between the semiconductor films 15 and 16.

[0071] The upper gate voltage V during the first period T1 tgis an example of a first gate voltage, which was set to −4 V by the upper gate voltage application circuit 42.

[0072] Furthermore, in a second period T2 different from the first period T1, the upper gate voltage application circuit 42 (see FIG. 6) applies the upper gate voltage V tg A pulse voltage of +15 V was applied as the second period T2, which is the pulse width during which the pulse voltage continues, and was set to 50 milliseconds here.

[0073] In this example, one cycle is defined as a period of two seconds including the first period T1 and the second period T2, and the drain current I d The readout and application of a pulse voltage were repeated. As an example, a period from 0.5 to 1.0 second from the beginning of one cycle was set as a first period T1, and the last 50 milliseconds of one cycle was set as a second period T2.

[0074] FIG. 8(b) shows the upper gate voltage V tg and the bottom gate voltage V bg 1 is a diagram showing the waveforms of

[0075] In this case, the start time and length of each period T1 and T2, and the lower gate voltage V bg The value of is the same as in FIG. 8(a). In addition, the upper gate voltage V applied as a pulse voltage in the second period T2 is tg The value of the upper gate voltage V in the first period T1 was set to −16 V. tg was set to −4 V, as in FIG. 8(a).

[0076] FIG. 8(c) is a graph obtained by investigating the characteristics of the anti-ambipolar transistor 10 realized at the voltages shown in FIG. 8(a) and FIG. 8(b).

[0077] In this example, the cycle of FIG. 8(a) was repeated 100 times during period A, and then the cycle of FIG. 8(b) was repeated 100 times during period B. The horizontal axis of FIG. 8(c) indicates the cumulative time of the second period T2 during which the pulse voltage was applied. The vertical axis of FIG. 8(c) indicates the drain current I read by the read circuit 41 during the first period T1. d Indicates the value of.

[0078] As shown in Figure 8(c), the upper gate voltage V tg During period A when a positive pulse voltage is applied, the drain current I d This is because the upper gate voltage V tg Since (-4.0V) is located to the left of the peak position in the initial state, when the peak position moves to the right with the application of a positive pulse voltage, V tg = Drain current I at -4.0V d This is because the number of employees has decreased.

[0079] In this case, a pulse voltage is applied to the neurotransmitter received by the synapse, and the drain current I d If we make the above correspondence, then during period A, an operation similar to that of an excitatory synapse is realized.

[0080] On the other hand, the upper gate voltage V tg During period B when a negative pulse voltage is applied, the drain current I d This is because the upper gate voltage V tg Since the initial peak position is located to the left of the initial peak position (see Figure 7), when a negative pulse voltage is applied and the peak position moves to the left, V tg = Drain current I at -4.0V d This is because the number of

[0081] In this case, a pulse voltage is applied to the neurotransmitter received by the synapse in the same manner as above, and the drain current I dIf we make the above correspondence, then during period B, an operation similar to that of an excitatory synapse is realized.

[0082] Figures 9(a) to (c) are diagrams (part 2) showing that operations similar to excitatory synapses and inhibitory synapses can be realized.

[0083] FIG. 9(a) shows the upper gate voltage V tg and the bottom gate voltage V bg 1 is a diagram showing the waveforms of

[0084] In this case, the read circuit 41 detects the drain voltage V d was set to −0.5 V. The upper gate voltage V tg is an example of the second gate voltage, which is set to +1.5 V by the upper gate voltage application circuit 42. The rest is the same as in FIG.

[0085] FIG. 9(b) shows the upper gate voltage V tg and the bottom gate voltage V bg 1 is a diagram showing the waveforms of

[0086] In this case, the upper gate voltage application circuit 42 also applies the upper gate voltage V tg was set to +1.5 V. The rest is the same as in Figure 8(b).

[0087] FIG. 9(c) is a graph obtained by investigating the characteristics of the anti-ambipolar transistor 10 realized at the voltages shown in FIG. 9(a) and FIG. 9(b).

[0088] As in Fig. 8(c), in this example, the cycle of Fig. 9(a) was repeated 100 times in period A, and then the cycle of Fig. 9(b) was repeated 100 times in period B. The meanings of the horizontal and vertical axes in Fig. 9(c) are the same as those in Fig. 8(c), so their explanation will be omitted.

[0089] As shown in Figure 9(c), the upper gate voltage V tg During period A when a positive pulse voltage is applied, the drain current I d This is because the upper gate voltage V tg Since (+1.5V) is located to the right of the peak position in the initial state, when the peak position moves to the right with the application of a positive pulse voltage, V tg = Drain current I at +1.5V d This is because increases.

[0090] This shows that in period A, the anti-ambipolar transistor 10 exhibits an operation similar to that of an excitatory synapse.

[0091] On the other hand, the upper gate voltage V tg During period B when a negative pulse voltage is applied, the drain current I d This is because the upper gate voltage V tg Since the initial peak position (+1.5V) is located to the right of the initial peak position (see Figure 7), when a negative pulse voltage is applied and the peak position moves to the left, V tg = Drain current I at +1.5V d This is because it decreases.

[0092] This shows that in period B, the anti-ambipolar transistor 10 exhibits an operation similar to that of an inhibitory synapse.

[0093] Figures 10(a) to (c) are diagrams (part 3) showing that similar operations can be achieved for both excitatory and inhibitory synapses.

[0094] FIG. 10(a) shows the upper gate voltage V V for realizing the operation of both the inhibitory synapse and the excitatory synapse by applying a positive pulse voltage to the second gate electrode 22. tg and the bottom gate voltage V bg 1 is a diagram showing the waveforms of

[0095] In this example, the read circuit 41 measures the drain voltage V d was set to −0.5 V. The upper gate voltage V tg is an example of the third gate voltage, which was set to −0.3 V by the upper gate voltage application circuit 42.

[0096] In addition, the upper gate voltage application circuit 42 (see FIG. 6) applies the upper gate voltage V tg A pulse voltage of +13 V was applied as the second period T2. The second period T2 was set to 5 milliseconds, which is shorter than both of Figs. 8(a) and 9(a).

[0097] FIG. 10(b) shows the upper gate voltage V when the length of the second period T2 is set to 20 milliseconds, which is longer than the length in FIG. 10(a). tg and the bottom gate voltage V bg 10(a) is a diagram showing the waveforms of the first and second periods T1 and T2, respectively.

[0098] FIG. 10(c) is a graph obtained by investigating the characteristics of the anti-ambipolar transistor 10 realized at the voltages shown in FIG. 10(a) and FIG. 10(b).

[0099] In this example, the cycle of Fig. 10(a) was repeated 100 times in period A, and then the cycle of Fig. 10(b) was repeated 75 times in period B. The meanings of the horizontal and vertical axes in Fig. 10(c) are the same as those in Fig. 8(c) and Fig. 9(c), so their explanation will be omitted.

[0100] In this example, before the period A, the upper gate voltage application circuit 42 applied a negative voltage having a polarity opposite to that of the positive pulse voltage to the second gate electrode 22. The voltage value of the negative voltage is −16V, and the application period is 10 seconds. The number of times that the negative voltage is applied is 10 times. Instead of applying the negative voltage multiple times in this way, the upper gate voltage application circuit 42 may apply the negative voltage to the second gate electrode 22 only once. In this way, the upper gate voltage application circuit 42 generates a negative voltage in addition to the positive pulse voltage, but the application period of the negative voltage is longer than that of the positive pulse voltage in the period A or period B. Therefore, the upper gate voltage application circuit 42 does not need to switch the negative voltage on and off at high speed, and the circuit configuration of the upper gate voltage application circuit 42 does not become significantly complicated.

[0101] As shown in FIG. 10(c), in the initial period A, the drain current I d However, as the accumulation time increases, the drain current I d At the beginning of the period, the drain current I d The reason why is that the peak position is shifted to the negative side from the initial state as shown by the dotted line in FIG. 7 by the application of the negative pulse voltage described above, and the upper gate voltage V tg This is because (-0.3V) is located on the right side. In this case, the peak position moves to the right as a positive pulse voltage is applied, and V tg = Drain current I at -0.3V d increases.

[0102] In the example of Figure 10(c), the peak height in period A is approximately -28.5 nA, which is higher than the peak height (approximately -24.5 nA) of the dotted line in Figure 7. This is thought to be because in Figure 7, the pulse width of the pulse voltage is long at 10 seconds, measuring a state in which the movement of carriers has settled, whereas in the example of Figure 10(c), the pulse width is short at 5 milliseconds, measuring a transient state.

[0103] Then, the cumulative time increases and the gate voltage V tgWhen (-0.3V) is located to the left of the peak position, the drain current I d will begin to decrease.

[0104] In particular, in this example, as shown in FIG. 5(b), electrons are accumulated in the memory film 19 near the drain electrode 18d, so that the peak voltage when a positive pulse voltage is applied, as shown by the dashed line in FIG. 7, becomes lower than the initial state (solid line). As a result, the drain current I d can be reduced.

[0105] In period B, the drain current I d has decreased.

[0106] Thus, the drain current I d The upper gate voltage V tg When the potential was set to -0.3 V, an operation similar to that of an excitatory synapse was achieved in the early stage of period A, and an operation similar to that of an inhibitory synapse was achieved at the end of period A and in the subsequent period B.

[0107] In particular, in this example, the upper gate voltage application circuit 42 generates a drain current I d The length of the second period T2 before the drain current I d The length of the second period T2 (20 milliseconds) in period B after the drain current I d Before the drain current I d This can prevent the period during which the potential increases from being shortened due to a sudden accumulation of electrons.

[0108] According to the electronic device 40 described above, the upper gate voltage application circuit 42 controls the drain current I dA gate voltage sufficient to allow a current to flow is applied to the second gate electrode 22 during the first period T1, and a pulse voltage is applied to the second gate electrode 22 during the second period T2. As a result, carriers are accumulated in the memory layer 19 in an amount corresponding to the cumulative time during which the pulse voltage is applied, modulating the threshold voltage, and a drain current I d You can control the behavior of.

[0109] As a result, even with only one positive pulse voltage, the drain current I d Therefore, the upper gate voltage application circuit 42 (see FIG. 6) can be simplified so as to generate only the positive pulse voltage out of the positive and negative pulse voltages, and the generation interval of the pulse voltages can be prevented from becoming shorter due to circuit delay.

[0110] Note that an excitatory synapse (period B in FIG. 8(c)) and an inhibitory synapse (period B in FIG. 9(c)) may be realized by using only a negative pulse voltage.

[0111] 8(a), 9(a), and 10(a), the lower gate voltage application circuit 43 (see FIG. 6) applies an on-voltage to the first gate electrode 11 during the first period T1. Furthermore, the read circuit 41 applies a drain voltage V d This causes the drain current I d The read circuit 41 detects the drain current I d can be read out.

[0112] 11(a) to (c) are schematic diagrams showing that the anti-ambipolar transistor 10 according to this embodiment can be applied to an artificial neural network.

[0113] Of these, Fig. 11(a) is a schematic diagram showing the behavior of an excitatory synapse. Fig. 11(a) illustrates an example in which a signal is transmitted from a presynapse 61 to a postsynapse 62. In an excitatory synapse, when a neurotransmitter 64 released from the presynapse 61 is received by a receptor 63 of the postsynapse 62, the synaptic potential of the postsynapse 62 increases.

[0114] Fig. 11(b) is a schematic diagram showing the behavior of an inhibitory synapse. As shown in Fig. 11(b), in an inhibitory synapse, when a receptor 63 receives a neurotransmitter 64, the synaptic potential of a postsynaptic part 62 drops.

[0115] FIG. 11(c) is a schematic diagram showing that a signal transmission can be simulated by the anti-ambipolar transistor 10. As described above, the drain current I d is the upper gate voltage during readout, V tg Depending on the value of , the drain current I d By making it correspond to the synaptic potential, it is possible to simulate both excitatory and inhibitory synapses.

[0116] Taking advantage of these characteristics, the anti-ambipolar transistor 10 according to the present embodiment can be applied to an artificial neural network. For example, if the drain current I d By updating the weighting coefficients by the back error propagation method using the above, it is possible to derive an optimal combination of weighting coefficients for each of the multiple anti-ambipolar transistors 10. In this case, since the inhibitory and excitatory functions can be switched by a pulse voltage of only one of the positive and negative polarities, the optimal combination of weighting coefficients can be reached in a short time. [Explanation of symbols]

[0117] 11...first gate electrode, 12...underlying insulating film, 13...first gate insulating film, 15...first semiconductor film, 16...second semiconductor film, 16a...part, 18s...source electrode, 18d...drain electrode, 19...memory film, 21...insulating sidewall, 22...second gate electrode, 40...electronic device, 41...readout circuit, 42...upper gate voltage application circuit, 43...lower gate voltage application circuit, 61...presynaptic portion, 62...postsynaptic portion, 63...receptor, 64...neurotransmitter, R0...channel region, R1...first region, R2...second region, V tg …Top gate voltage, V bg … bottom gate voltage, V d …Drain voltage, TR n …n-type MOS transistor, TR p ...p-type MOS transistor.

Claims

1. The first gate electrode and A first gate insulating film provided on the first gate electrode, A first semiconductor film of a first conductivity type provided in a first region on the first gate insulating film, A second semiconductor film of a second conductivity type is provided in a second region on the first gate insulating film, and a portion of it is in contact with the first semiconductor film. A memory film provided on each of the first semiconductor film and the second semiconductor film, wherein an internal electric field remains, A second gate insulating film provided on the memory film, A transistor comprising a second gate electrode provided on the second gate insulating film, A first circuit reads the drain current flowing between the first semiconductor film and the second semiconductor film during a first period of time, A second circuit that applies a gate voltage to the second gate electrode during the first period such that the drain current flows, and applies a pulse voltage to the second gate electrode during a second period different from the first period, An electronic device having

2. The electronic device according to claim 1, characterized in that the gate voltage is a first gate voltage in which the drain current decreases as the cumulative time of application of the pulse voltage increases.

3. The electronic device according to claim 1, characterized in that the gate voltage is a second gate voltage at which the drain current increases as the cumulative time of application of the pulse voltage increases.

4. The electronic device according to claim 1, characterized in that the gate voltage is a third gate voltage at which the drain current changes from increasing to decreasing as the cumulative time for which the pulse voltage is applied increases.

5. The electronic device according to claim 4, characterized in that the second circuit narrows the pulse width of the pulse voltage before the drain current changes from increasing to decreasing compared with the pulse width of the pulse voltage after the drain current changes from increasing to decreasing.

6. The electronic device according to claim 4 or 5, characterized in that the second circuit applies a voltage opposite in polarity to the pulse voltage before the period during which the drain current increases as the cumulative time increases.

7. The electronic device according to claim 1 or 2, characterized in that the first circuit applies a forward voltage between the first semiconductor film and the second semiconductor film during the first period.

8. The electronic device according to claim 1 or 2, characterized in that the memory film is a carrier storage film that stores carriers, or a ferroelectric film.

9. The electronic device according to claim 8, characterized in that the carrier storage film is star polystyrene in which polystyrene is bonded to metal phthalocyanine.

10. A method for driving a transistor, The aforementioned transistor is The first gate electrode and A first gate insulating film provided on the first gate electrode, A first semiconductor film of a first conductivity type provided in a first region on the first gate insulating film, A second semiconductor film of a second conductivity type is provided in a second region on the first gate insulating film, and a portion of it is in contact with the first semiconductor film. A memory film provided on each of the first semiconductor film and the second semiconductor film, wherein an internal electric field remains, A second gate insulating film provided on the memory film, The device comprises a second gate electrode provided on the second gate insulating film, The aforementioned drive method is The drain current flowing between the first semiconductor film and the second semiconductor film is read out during a first period, A gate voltage such that the drain current flows is applied to the second gate electrode during the first period, This includes applying a pulse voltage to the second gate electrode during a second period different from the first period, The method of driving a transistor.

11. The transistor driving method according to claim 10, characterized in that the gate voltage is a first gate voltage in which the drain current decreases as the cumulative time of the applied pulse voltage increases.

12. The transistor driving method according to claim 10, characterized in that the gate voltage is a second gate voltage at which the drain current increases as the cumulative time of the applied pulse voltage increases.

13. The transistor driving method according to claim 10, characterized in that the gate voltage is a third gate voltage at which the drain current changes from increasing to decreasing as the cumulative time for which the pulse voltage is applied increases.

14. The transistor driving method according to claim 13, characterized in that the pulse width of the pulse voltage before the drain current changes from increasing to decreasing is made narrower compared with the pulse width of the pulse voltage after the drain current changes from increasing to decreasing.

15. The method for driving a transistor according to claim 13 or 14, further comprising applying a voltage of opposite polarity to the pulse voltage before the period during which the drain current increases as the cumulative time increases.

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