Boron-doped diamond mosfet and manufacturing method thereof

Abstract

To provide a single crystal diamond p-type MOSFET improved in electric characteristics as a transistor such as a drain current ID, transconductance gm and an ON / OFF ratio characteristic under a high temperature environment like 300°C.SOLUTION: In a boron-doped diamond MOSFET, a semiconductor layer consisting of a boron (B)-doped diamond single crystal is formed in contact with a first principal surface of a single crystal diamond substrate, and a source electrode and a drain electrode are formed on the semiconductor layer. The first principal surface of the semiconductor layer, excluding the source electrode and the drain electrode, is covered with an insulator film, and a gate electrode is formed at a partial location within a region that is interposed between the source electrode and the drain electrode and that is not in electrical contact with the source electrode and the drain electrode, on the insulator film. An oxide film is formed so as to cover end portions of the gate electrode, the source electrode, and the drain electrode, as well as the surface of the exposed insulator film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a boron-doped diamond MOSFET and a method for fabricating the same. [Background technology]

[0002] Single crystal semiconductor diamond has a wide band gap energy (5.47 eV), a low dielectric constant (5.7), and a high dielectric breakdown field strength (10 MV cm -1 ), high carrier saturation velocity (1.5–2.7 × 10 for electrons and holes, respectively) 7 cm·s -1 and 0.85 to 1.2 × 10 7 cm·s -1 ), high thermal conductivity (22W cm -1 ·K -1 ) and high carrier mobility (4500 cm for electrons and holes, respectively). 2 ·V -1 ·s -1 and 3800 cm 2 ·V -1 ·s -1 ) where the above values ​​are at room temperature. For this reason, electronic devices using single crystal diamond as a semiconductor are expected to exhibit high-power operation, high-speed and high-frequency operation, high voltage resistance, and high thermal limit.

[0003] In particular, metal-oxide semiconductor field-effect transistor (MOSFET) semiconductor devices that use single crystal diamond as a semiconductor are expected to play an important role as core elements in constructing high-performance inverters and high-output radio-frequency amplifiers, as well as elements that can withstand harsh environments such as high temperatures and radiation.

[0004] In light of this background, the development of MOSFETs using single-crystal diamond semiconductors has been progressing, focusing on p-type MOSFETs that use vacancies (holes) as carriers, which are particularly likely to produce excellent electrical properties. Examples of such developments include Non-Patent Documents 1 and 2. There are two trends in p-type MOSFETs that use single-crystal diamond semiconductors: MOSFETs that use a hydrogen-terminated diamond semiconductor layer, and MOSFETs in which impurities such as boron (B) or aluminum (Al) are doped into the single-crystal diamond semiconductor layer. The MOSFET using the hydrogen-terminated diamond semiconductor layer has a drain current I D , transconductance g m Although diamond has excellent ON / OFF ratio characteristics, the heat resistance is insufficient due to the low thermal stability of the surface adsorbates, and the high thermal limit characteristics of diamond materials cannot be fully utilized.

[0005] On the other hand, MOSFETs in which impurities such as boron are doped into the single-crystal diamond semiconductor layer have a very low hole density and a low drain current I D , transconductance g m Another problem was that transistor characteristics such as the ON / OFF ratio characteristics were not fully utilized. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] K. Kudara, et al., IEEE Transactions on Electron Devices, Vol. 68, pp3942-3949(2021) [Non-Patent Document 2] TTPham et al., IEEE Electron Letters, Vol. 38, No. 11, pp1571-1574 (2017) [Non-Patent Document 3] TTPham et al.,Appl.Phys.Lett.,Vol.111,No.17,p.173503(2017) [Non-Patent Document 4] J.Liu et al.,IEEE Trans.Electron Dev.,Vol.68,No.8,pp3963-3967(2021) [Non-Patent Document 5] J.Liu et al., IEEE Trans.Electron Dev.,Vol.70,No.5,pp2199-2203(2023) Summary of the Invention [Problem to be solved by the invention]

[0007] The problem that this invention is trying to solve is that the drain current I D , transconductance g m The present invention provides a p-type single crystal diamond MOSFET (also called diamond MOSFET) having excellent electrical characteristics as a transistor, such as excellent ON / OFF ratio characteristics, and a method for manufacturing the same. [Means for solving the problem]

[0008] The configuration of the present invention that solves the above problems is shown below. (Configuration 1) a semiconductor layer made of a boron (B)-doped diamond single crystal is formed in contact with a first main surface of the single crystal diamond substrate; A source electrode and a drain electrode are formed on the semiconductor layer, the first main surface of the semiconductor layer other than the source electrode and the drain electrode is covered with an insulating film; a gate electrode is formed in a portion of a region on the insulating film that is sandwiched between the source electrode and the drain electrode and that is not in electrical contact with the source electrode and the drain electrode; A boron-doped diamond MOSFET, comprising an oxide film formed to cover each end of the gate electrode, the source electrode, and the drain electrode, as well as the exposed surface of the insulating film. (Configuration 2) The boron-doped diamond MOSFET according to configuration 1, wherein the oxide film is one or more selected from the group consisting of alumina (Al2O3), hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO2), silicon dioxide (SiO2), silicon oxynitride (SiON), zirconium dioxide (ZrO2), lanthanum aluminum trioxide (LaAlO3), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2) and magnesium oxide (MgO). (Configuration 3) 3. The boron-doped diamond MOSFET according to configuration 2, wherein the oxide film is an ALD-Al2O3 film. (Configuration 4) 4. The boron-doped diamond MOSFET according to any one of claims 1 to 3, wherein the thickness of the oxide film is 10 nm or more and 50 nm or less. (Configuration 5) The boron-doped diamond MOSFET according to any one of configurations 1 to 4, wherein the insulating film is one or more selected from the group consisting of alumina (Al2O3), hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO2), silicon dioxide (SiO2), silicon oxynitride (SiON), zirconium dioxide (ZrO2), lanthanum aluminum trioxide (LaAlO3), tantalum pentoxide (Ta2O5), boron nitride (BN), calcium difluoride (CaF2), magnesium difluoride (MgF2), titanium dioxide (TiO2) and magnesium oxide (MgO). (Configuration 6) 6. The boron-doped diamond MOSFET according to configuration 5, wherein the insulating film is made of an ALD-Al2O3 film. (Configuration 7) 7. The boron-doped diamond MOSFET according to any one of configurations 1 to 6, wherein the insulating film has a thickness of 10 nm or more and 50 nm or less. (Configuration 8) The boron-doped diamond MOSFET according to any one of the configurations 1 to 7, wherein the material of the gate electrode is selected from the group consisting of gold (Au), platinum (Pt), iridium (Ir), rhenium (Re), palladium (Pd), rhodium (Rd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), magnesium (Mg), tungsten (W), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), zinc (Zn), cadmium (Cd), mercury (Hg), gallium (Ga), indium (In), boron (B), carbon (C), silicon (Si) and germanium (Ge). (Configuration 9) The boron-doped diamond MOSFET according to configuration 8, wherein the material of the source electrode and the drain electrode in contact with the semiconductor layer is selected from the group consisting of titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), palladium (Pd), titanium (Ti) / gold (Au) bilayer and titanium (Ti) / platinum (Pt) bilayer. (Configuration 10) Providing a substrate having a single crystal diamond layer formed on at least a portion of its surface; forming a semiconductor layer doped with boron (B) on the surface of the substrate on which the single crystal diamond layer is formed; forming a source electrode and a drain electrode with ohmic contact on the semiconductor layer; forming a gate insulating film; forming a gate electrode on the gate insulating film in a state not in electrical contact with the source electrode and the drain electrode; A method for manufacturing a boron-doped diamond MOSFET, comprising forming an oxide film covering each end of the gate electrode, the source electrode, and the drain electrode, as well as an exposed surface of the gate insulating film. (Configuration 11) The method for manufacturing a boron-doped diamond MOSFET according to configuration 10, wherein the method for forming an oxide film covering each end of the gate electrode, the source electrode, and the drain electrode, as well as the exposed surface of the insulating film, comprises forming an oxide film, and etching the oxide film in a part of the region on the gate electrode, the source electrode, and the drain electrode, not including the ends of the gate electrode, the source electrode, and the drain electrode. (Configuration 12) 12. The method for producing a boron-doped diamond MOSFET according to claim 10 or 11, wherein the oxide film is one or more selected from the group consisting of alumina (Al2O3), hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO2), silicon dioxide (SiO2), silicon oxynitride (SiON), zirconium dioxide (ZrO2), lanthanum aluminum trioxide (LaAlO3), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2) and magnesium oxide (MgO). (Configuration 13) 13. The method for producing a boron-doped diamond MOSFET according to claim 12, wherein the oxide film is an alumina (Al2O3) film produced by atomic layer deposition (ALD) using Al(CH3)3 and ozone as precursors. (Configuration 14) The method for producing a boron-doped diamond MOSFET according to any one of configurations 10 to 13, wherein the gate insulating film is an alumina (Al2O3) film produced by atomic layer deposition (ALD) using Al(CH3)3 and ozone as precursors. (Configuration 15) A method for producing a boron-doped diamond MOSFET according to any one of configurations 10 to 14, wherein after forming the semiconductor layer, at least a first main surface of the semiconductor layer is washed with an acidic solution before forming the insulating film, the source electrode and the drain electrode. (Configuration 16) 16. A method for producing a boron-doped diamond MOSFET according to claim 15, wherein the acid solution is a mixed acid of sulfuric acid and nitric acid in which the volume ratio of sulfuric acid to nitric acid is 3:1. Effect of the Invention

[0009] According to the present invention, the drain current I D , transconductance g m The present invention provides a p-type single crystal diamond MOSFET having excellent electrical characteristics as a transistor, such as excellent ON / OFF ratio characteristics, and a method for manufacturing the same. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a structure of a main part of a MOSFET according to the present invention. [Diagram 2] 1A to 1C are explanatory diagrams illustrating a manufacturing process of a MOSFET according to the present invention using top views. [Diagram 3] FIG. 2 is a flow chart showing a manufacturing process of the MOSFET of the present invention. [Figure 4] 1A to 1C are cross-sectional views of a main part illustrating a manufacturing process of a MOSFET according to the present invention. [Diagram 5] 1A to 1C are cross-sectional views of a main part illustrating a manufacturing process of a MOSFET according to the present invention. [Figure 6] 1 is a SEM photograph of an element fabricated in an example, observed from above. [Figure 7] FIG. 2 is a cross-sectional view of a main part of an element fabricated in an embodiment. [Figure 8] FIG. 2 is a characteristic diagram showing the boron concentration distribution in the single crystal diamond semiconductor layer of the element fabricated in the examples. [Figure 9] FIG. 1 is a characteristic diagram showing the C-2-V characteristics of an element fabricated in an example. [Figure 10] 1 is a characteristic diagram showing the ID-VD characteristics of the element fabricated in the example, where (a) shows the case at room temperature and (b) shows the case at 300° C. [Figure 11] 1 is a characteristic diagram showing the ID-VGS characteristics of the element fabricated in the example, where (a) shows the case at room temperature and (b) shows the case at 300° C. [Figure 12] FIG. 1 is a characteristic diagram showing the gm characteristics of the element fabricated in the embodiment, where (a) shows the gm characteristics at room temperature and (b) shows the gm characteristics at 300° C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] <Element structure> As shown in FIG. 1, a p-type MOSFET (101) of the present invention comprises a substrate 11 made of single crystal diamond, a semiconductor layer 12 made of p-type single crystal diamond, a drain electrode 13, a source electrode 14, an insulating film 15 having a gate insulating film function, a gate electrode 16 and an oxide film 17. The p-type MOSFET (101) has a semiconductor layer 12 made of a diamond single crystal doped with boron (B) formed in contact with a first main surface of a single crystal diamond substrate 11, a drain electrode 13 and a source electrode 14 formed on the semiconductor layer 12, the first main surface of the semiconductor layer 12 other than the drain electrode 13 and the source electrode 14 being covered with an insulating film 15, a gate electrode 16 is formed in a part of the region sandwiched between the drain electrode 13 and the source electrode 14 on the insulating film 15 and not in electrical contact with the drain electrode 13 and the source electrode 14, and an oxide film 17 is formed to cover each end of the gate electrode 16, the drain electrode 13, and the source electrode 14, as well as the exposed surface of the insulating film 15.

[0012] Examples of the single crystal diamond substrate 11 include a single crystal diamond substrate and a substrate whose first main surface is made of single crystal diamond. Examples of the substrate whose first main surface is made of single crystal diamond include a substrate in which a single crystal diamond layer is epitaxially formed on a single crystal diamond substrate, and a substrate in which a single crystal diamond film cut by cleavage or the like is bonded to a rigid base such as a metal substrate such as a Si wafer, an aluminum substrate, or a glass substrate such as a synthetic quartz substrate. Here, the single crystal diamond substrate is preferably a p-type single crystal diamond substrate containing boron (B) or aluminum (Al), or an n-type single crystal diamond substrate containing phosphorus (P) or nitrogen (N), and the surface orientation of the substrate is preferably one selected from the group consisting of (100), (111) and (110). By using this substrate and this substrate surface orientation, the boron-doped single crystal diamond, which is the semiconductor layer 12 formed thereon, tends to be of high quality with few crystal defects.

[0013] The semiconductor layer 12 is made of a single crystal diamond semiconductor doped with boron, and can be formed by an epitaxial growth method. Specifically, one selected from the group consisting of microwave plasma chemical vapor deposition (MPCVD), direct current plasma chemical vapor deposition (DCPCVD), hot filament chemical vapor deposition (HFCVD), and combustion flame deposition can be used, and microwave plasma chemical vapor deposition, which is less likely to form crystal defects or unintended levels, is particularly preferred. The amount of boron doped is not particularly limited, but may be, for example, 10 15 cm -3 Over 10 21 cm -3 The thickness of the semiconductor layer 12 is not particularly limited, but may be, for example, 50 nm or more and 5 μm or less.

[0014] The drain electrode 13 and the source electrode 14 may be made of a metal or metal-containing material that has sufficient electrical conductivity as an electrode and can make ohmic contact with the semiconductor layer 12. Specifically, a material containing one selected from the group consisting of titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), palladium (Pd), a titanium (Ti) / gold (Au) bilayer, and a titanium (Ti) / platinum (Pt) bilayer may be preferably used. The film may be in the form of a single layer or a laminated film. The thickness of the drain electrode 13 and the source electrode 14 is not particularly limited, but may be, for example, 50 nm or more and 1000 nm or less.

[0015] The insulating film 15 is a dense insulating film with a low dielectric constant and low leakage current that functions as a gate insulating film, and specifically, one or more selected from the group consisting of alumina (Al2O3), hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO2), silicon dioxide (SiO2), silicon oxide nitride (SiON), zirconium dioxide (ZrO2), lanthanum aluminum trioxide (LaAlO3), tantalum pentoxide (Ta2O5), boron nitride (BN), calcium difluoride (CaF2), magnesium difluoride (MgF2), titanium dioxide (TiO2), and magnesium oxide (MgO) can be preferably exemplified. Among these, an ALD-Al2O3 (Atomic Layer Deposition-Al2O3) film can be exemplified as an insulating film 15 that can obtain particularly good electrical characteristics as a transistor. It is preferably used because it generates few defects and impurity levels. The thickness of the insulating film 15 is not particularly limited as long as it functions as a gate insulating film, but a thickness of 10 nm to 50 nm is preferably used as a thickness that provides good electrical characteristics.

[0016] The gate electrode 16 can be preferably made of a material including one or more selected from the group consisting of gold (Au), platinum (Pt), iridium (Ir), rhenium (Re), palladium (Pd), rhodium (Rd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), magnesium (Mg), tungsten (W), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), zinc (Zn), cadmium (Cd), gallium (Ga), boron (B), carbon (C), silicon (Si), and germanium (Ge) in terms of work function and conductivity.

[0017] As the oxide film 17, one or more materials selected from the group consisting of alumina (Al2O3), hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO2), silicon dioxide (SiO2), silicon oxynitride (SiON), zirconium dioxide (ZrO2), lanthanum aluminum trioxide (LaAlO3), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2) and magnesium oxide (MgO) can be preferably used. In particular, the ALD-Al2O3 film can be cited as an example of the oxide film 17 that provides good electrical characteristics as a transistor. The ALD-Al2O3 has conformal coverage and can cover the side surfaces of the gate electrode 16, drain electrode 13, and source electrode 14 and the edges where they contact the substrate surface with an oxide film that is free of gaps and has few defects and impurities, improving the reliability and transistor characteristics of the p-type diamond MOSFET (101) that is produced. The thickness of the oxide film 17 is preferably 10 nm to 50 nm, more preferably 10 nm to 35 nm, and even more preferably 12 nm to 30 nm. When the thickness of the oxide film 17 is within this range, good electrical characteristics as a transistor can be obtained.

[0018] As will be shown in the examples, the p-type MOSFET (101) having the above structure has a drain current I D and mutual conductance g m The electrical characteristics of the transistor are excellent from the initial stage.

[0019] <Manufacturing method> A method for manufacturing a p-type MOSFET (101) according to the present invention will now be described with reference to FIGS.

[0020] First, a substrate 11 having a single crystal diamond layer formed on at least a portion of its surface is prepared (step S11). Examples of the substrate (11) include a single crystal diamond substrate, a substrate having a single crystal diamond layer epitaxially formed on a single crystal diamond substrate, and a substrate having a single crystal diamond film cut by cleavage or the like bonded to a rigid base, such as a metal substrate such as a Si wafer or an aluminum substrate, or a glass substrate such as a synthetic quartz substrate. As the single crystal diamond layer, in addition to non-doped single crystal diamond, doped single crystal diamond with boron (B), aluminum (Al), phosphorus (P) and nitrogen (N) can be used. As the type of single crystal diamond, for example, Ib type and IIa type can be mentioned. As the surface orientation of the single crystal diamond layer, other than (100) surface, (111) surface, (110) surface, etc. can be used. After preparing the substrate 11, the substrate surface is treated with a mixed acid of sulfuric acid and nitric acid, with the volume ratio of sulfuric acid to nitric acid being 3:1 at a temperature of 50°C to 400°C for 3 hours, and then cleaned with acetone, ethanol, and pure water, in that order, using ultrasonic waves for 5 minutes each (Figure 2(a)).

[0021] Next, a semiconductor layer 12 (step S12, Figures 2(b) and 4(a)) made of boron-doped p-type single crystal diamond is formed on the surface of the substrate 11 on which the single crystal diamond layer has been formed. The method for forming the semiconductor layer 12 may be one selected from the group consisting of microwave plasma chemical vapor deposition (MPCVD), direct current plasma chemical vapor deposition (DCPCVD), hot filament chemical vapor deposition (HFCVD) and combustion flame deposition, and microwave plasma chemical vapor deposition, which is less likely to form crystal defects or unintended levels, is particularly preferred.

[0022] Thereafter, the surface of the semiconductor layer 12 is washed with an acidic solution to clean the surface of the semiconductor layer 12 made of single crystal diamond and to oxygen-terminate the surface of the single crystal diamond (FIG. 2(c)). Here, it is preferable for the acidic solution to be heated at a temperature of 50° C. to 400° C. in order to efficiently improve the cleaning effect and densely terminate oxygen. As the acidic solution, a mixed acid composed of sulfuric acid and nitric acid, in which the volume ratio of sulfuric acid to nitric acid is 3:1, is preferably used, which is widely used as a cleaning solution and enables stable treatment including cleaning.

[0023] Thereafter, the drain electrode 13 and the source electrode 14 are formed on the semiconductor layer 12 (step S13, FIG. 2(d) and FIG. 4(b)). The drain electrode 13 and the source electrode 14 may be made of a single layer film or a multilayer film, and the material used is preferably one selected from the group consisting of titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), palladium (Pd), a titanium (Ti) / gold (Au) bilayer, and a titanium (Ti) / platinum (Pt) bilayer. Examples of the method for forming the drain electrode 13 and the source electrode 14 include a film formation / etching method that combines film formation, lithography, and etching, a lift-off method, and a masking deposition method. Examples of the method for forming the drain and source electrode materials include one or more methods selected from the group consisting of a sputtering method, a thermal and electron beam deposition method, and an atomic layer deposition method (ALD).

[0024] After that, a heat treatment (annealing) is performed to form the drain electrode 13 and the source electrode 14. This forms ohmic contact with the semiconductor layer 12 (FIG. 2(e)). The heat treatment is carried out under argon or low vacuum (0.1 Pa to 100 Pa), and the temperature is preferably 400° C. or higher and 600° C. or lower.

[0025] Next, an insulating film 15a that will become a gate insulating film is deposited (step S14, FIG. 2(f), FIG. 4(c)). Examples of the deposition method include an ALD (Atomic Layer Deposition) method, a CVD (Chemical Vapour Deposition) method, a sputtering method, and a coating method. Examples of materials for the gate insulating film include one or more selected from the group consisting of alumina (Al2O3), hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO2), silicon dioxide (SiO2), silicon oxide nitride (SiON), zirconium dioxide (ZrO2), lanthanum aluminum trioxide (LaAlO3), tantalum pentoxide (Ta2O5), boron nitride (BN), calcium difluoride (CaF2), magnesium difluoride (MgF2), titanium dioxide (TiO2), and magnesium oxide (MgO). Among these, an Al2O3 film formed by the ALD method is preferred because of its high quality.

[0026] Thereafter, the gate electrode 16 is formed (step S15, FIG. 2(g), FIG. 5(a)). Examples of the method for forming the gate electrode 16 include a deposition-etching method that combines deposition, lithography, and etching, a lift-off method, and a patterned deposition method. Examples of the method for forming a film of the gate electrode material include one or more methods selected from the group consisting of a sputtering method, a thermal and electron beam deposition method, and an atomic layer deposition method (ALD). The gate electrode 16 can preferably use a material containing one or more selected from the group consisting of gold (Au), platinum (Pt), iridium (Ir), rhenium (Re), palladium (Pd), rhodium (Rd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), magnesium (Mg), tungsten (W), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), zinc (Zn), cadmium (Cd), mercury (Hg), gallium (Ga), indium (In), boron (B), carbon (C), silicon (Si) and germanium (Ge).

[0027] Thereafter, an oxide film 17a is deposited (step S16, FIG. 2(h) and FIG. 5(b)). Examples of the deposition method include an ALD (Atomic Layer Deposition) method, a CVD (Chemical Vapour Deposition) method, a sputtering method, and a coating method. The material of the oxide film 17a is preferably one or more selected from the group consisting of alumina (Al2O3), hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO2), silicon dioxide (SiO2), silicon oxynitride (SiON), zirconium dioxide (ZrO2), lanthanum aluminum trioxide (LaAlO3), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2) and magnesium oxide (MgO). Among these, an Al2O3 film produced by the ALD method using Al(CH3)3 and ozone as precursors is of high quality and is preferred.

[0028] Finally, openings for wiring (via holes) are opened in the insulating film 15a and the oxide film 17a to form the gate insulating film 15 and the oxide film 17, respectively, to obtain the p-type MOSFET (101) (step S17, FIG. 2(i), FIG. 5(c)).

[0029] As shown in the examples, the above manufacturing method can achieve a drain current I D and mutual conductance g m It is possible to provide a p-type MOSFET (101) having excellent electrical characteristics from the initial stage. EXAMPLES

[0030] In the examples, a p-type MOSFET (101) was fabricated using the boron-doped diamond semiconductor layer described in the embodiment, and its electrical characteristics were evaluated.

[0031] <Structure of prototype element> Scanning electron microscope (SEM) photographs of the fabricated p-type MOSFET (101) taken from the top are shown in Figure 6. (a) is an SEM image taken at low magnification, (b) at medium magnification, and (c) at high magnification. The p-type MOSFET (101) has a circular drain electrode 13 with a diameter of 299.6 μm and a gate length L g The gate electrode 16 has a circumferential width of 2.6 μm, and the source electrode 14 is disposed outside the gate electrode 16 with a gap of 5.8 μm from the gate electrode 16. G From the circumference calculation, it is 940.7 nm.

[0032] The structure and typical dimensions of the prototype p-type MOSFET (101) are shown in FIG. As the substrate 11, a high pressure, high temperature (HPHT) synthetic single crystal diamond substrate (manufactured by Sumitomo Electric Industries) of Ib type (100) orientation having a size of 3 mm×3 mm and a thickness of 0.5 mm was used. The epitaxially formed semiconductor layer 12 made of boron-doped single crystal diamond has a thickness of 2650 nm. The concentration of doped boron is approximately 10 15 ~10 16 cm -3 , C, which will be described later -2 The concentration of the susceptor calculated by -V measurement is 6.0×10 14 cm -3 It is.

[0033] The drain electrode 13 and the source electrode 14 are made of a double-layer film in which titanium (Ti) and gold (Au) are laminated from the bottom. Here, the Ti layer, which functions to adhere to the semiconductor layer 12, is 10 nm thick, and the Au layer, which has high conductivity and mainly functions as a conductive film, is 200 nm thick. The gate electrode 16 is made of a two-layer film in which titanium (Ti) and gold (Au) are laminated from the bottom. Here, the Ti layer is 10 nm thick, and has a function of adhering to the semiconductor layer 12, similar to the drain electrode 13 and the source electrode 14. The Au layer, which mainly functions as a conductive film, is 150 nm thick.

[0034] The insulating film 15 and the oxide film 17 are both made of alumina (Al2O3) films by atomic layer deposition (ALD), and each has a thickness of 26 nm.

[0035] <Sample preparation> First, a Ib type (100) oriented high pressure, high temperature (HPHT) synthetic single crystal diamond substrate 11 was prepared (step S11), and the surface of the substrate was cleaned using a mixed solution of nitric acid (HNO3) and sulfuric acid (H2SO4). The volume ratio of sulfuric acid to nitric acid was 1:3, and the substrate was boiled at a temperature of 300°C for 3 hours.

[0036] Thereafter, a semiconductor layer 12 made of boron-doped single crystal diamond was formed on the substrate 11 to a thickness of 2650 nm by microwave plasma chemical vapor deposition (MPCVD) (FIG. 4(a), step S12). Here, a microwave plasma chemical vapor deposition system (homemade) was used as the apparatus, and the microwave output, temperature, and chamber pressure were 1.4 kW, 1000°C, and 18.6 kPa, respectively. The boron source was the residual boron in the chamber from the immediately preceding boron doping experiment, and the gas flow rates of the source gases H2 and CH4 were 49 sccm and 1 sccm, respectively. The substrate temperature during film formation was 960±10°C.

[0037] The boron doping concentration distribution of the semiconductor layer 12 was measured by SIMS (Secondary Ion Mass Spectrometry) using a similarly prepared sample. The results are shown in FIG. 8. The doped boron concentration was 10 15 cm -3 And the board side is 10 16 cm -3The SIMS device used was a CAMECA IMS-7f (manufactured by Ametec Co., Ltd.), and the ion species was Cs + The measurement was performed at an acceleration voltage of 150 kV.

[0038] Thereafter, contamination on the surface of the semiconductor layer 12 was removed and the surface of the semiconductor layer 12 was oxidized (oxygen terminated) using a boiled cleaning solution (300°C) of a mixed acid consisting of nitric acid and sulfuric acid. Here, the ratio of nitric acid to sulfuric acid was 1:3 by volume.

[0039] Thereafter, the drain electrode 13 and the source electrode 14, each made of a two-layer metal film in which titanium (Ti) having a thickness of 10 nm and gold (Au) having a thickness of 150 nm were laminated in that order, were formed on the semiconductor layer 12 (FIG. 4(b), step S13). By using Ti as the lower layer, the adhesion of the drain electrode 13 and the source electrode 14 to the semiconductor layer 12 is improved. In forming the drain electrode 13 and the source electrode 14, an electron gun deposition system (ADS-RDEB, manufactured by R-Deck) was used, and a rapid annealing system (RTP-6, manufactured by Advance Riko) was also used to make ohmic contact with the semiconductor layer 12. Here, the pressure in the chamber during deposition was 10 -6 The deposition pressure was set to 5 Pa and the deposition rate was set to 0.05 nm / s. Annealing was performed in an argon (Ar) gas atmosphere at a pressure of 5 Pa at 550° C. for 20 minutes.

[0040] Thereafter, an insulating film 15a (gate insulating film) made of Al2O3 was formed on the surface of the sample with a thickness of 26 nm by atomic layer deposition (ALD) (FIG. 4(c), step S14). Specifically, the film was deposited in an environment of 200°C using an Al(CH3)3 precursor and ozone.

[0041] Next, the gate electrode 16 was formed on the insulating film 15a in a state of being in no electrical contact with the source electrode 14 and the drain electrode 13 (FIG. 5(a), step S15). The gate electrode 16 is a two-layer film consisting of titanium (Ti) with a thickness of 10 nm and gold (Au) with a thickness of 200 nm formed thereon. It was formed by using an electron gun deposition system (ADS-RDEB, manufactured by RDEC) in the same manner as the drain electrode 13 and the source electrode 14. The pressure in the chamber during deposition was 10 -6 The deposition pressure was set to 1 Pa and the deposition rate was set to 0.05 nm / s. The cross-sectional shape of the gate electrode 16 was rectangular with vertical side walls and a very slight depression in the contact surface with the insulating film 15a.

[0042] Thereafter, an oxide film 17a made of Al2O3 was formed on the surface of the sample to a thickness of 26 nm using a process similar to that of step S14 so as to conformally cover the entire sample (FIG. 5(b)). The Al2O3 film formed by the ALD method has excellent conformality and contributes to improving the transistor characteristics of the MOSFET to be fabricated. Thereafter, openings for electrode wiring were opened at desired locations in the laminated film consisting of the oxide film 17a and the insulating film 15a by lithography and dry etching, and a p-type MOSFET (101) was fabricated in which the oxide film 17 was formed to cover the ends of the gate electrode 16, the source electrode 14, and the drain electrode 13, and the exposed surface of the gate insulating film 15 (FIG. 5(c), step S16). The gases used for the etching were CHF3 and Ar, and the plasma power, chamber pressure, CHF3 flow rate, and Ar flow rate were 100 W, 3.0 Pa, 10 sccm, and 40 sccm, respectively.

[0043] <Semiconductor layer evaluation> As part of the evaluation of the boron-doped semiconductor layer 12, the acceptor concentration of the semiconductor layer 12 was measured using the C -2 -V characteristics evaluation. Measured C -2 The -V characteristics are shown in Figure 9. The slope of the curve (dC -2 / dV) is 41368cm 4 / μF 2 V, from which the acceptor concentration of the semiconductor layer 12 is 6.0×10 14The electrical properties were measured at room temperature (25°C) and 300°C using a Grail 10-5-LV-HTV prober system. The electrical measurements below were also performed using this prober system.

[0044] <Electrical characteristic evaluation> < D -V D Characteristics>> Drain current (I D ) drain-gate voltage (V D ) dependency I D -V D The characteristics were measured at room temperature (25°C) and at 300°C. Specifically, the sample was placed in a room temperature or 300°C environment, operated for one hour, and then the gate-source voltage (V GS ) from -20V to 78V in 2V steps, D -I D The properties were measured. The results are shown in Figure 10. (a) shows the results at room temperature, and (b) shows the results at 300°C. The bottom row shows the V GS = -20V measurement, V increases in 2V increments as it goes up GS becomes larger, and the top row is V GS V at 78V D -I D Indicates characteristics. Maximum drain current (I D,max ) was -1.2mA / mm at room temperature and -10.9mA / mm at 300°C. In particular, at an operating temperature of 300°C, the I D,max was obtained.

[0045] < D -V GS Characteristics>> Figure 11(a) shows the V GS -I D The figure (b) shows the V at 300℃ operation. GS -I D Based on these measurement results, the threshold voltage V TH ​​The ON / OFF ratio was 10 at room temperature and 300°C. 9 The subthreshold voltage (SS) was 315mV / dec when operated at room temperature and 570mV / dec when operated at 300℃.

[0046] < <g m Characteristics>> Mutual conductance g m V GS The results of operation at room temperature are shown in Fig. 12(a), and the results of operation at 300°C are shown in Fig. 12(b). m The maximum value of g m,max The resistance was high, at 29.0 μS / mm for room temperature operation and 215.7 μS / mm for 300°C operation.

[0047] The above measurement data are summarized in Table 1. The published values ​​in Non-Patent Documents 2-5 are also listed in the table for reference. In particular, Non-Patent Document 5 was written by the inventor of the present application, and the differences in structure and fabrication between Non-Patent Document 5 and the present application are limited to the following points as comparative examples. The present application differs from Non-Patent Document 5 in that a step S16 is added to form an oxide film 17 that covers the ends of the gate electrode 16, the drain electrode 13, and the source electrode 14, as well as the exposed surface of the gate insulating film 12, and the area of ​​the source electrode 14 is increased to 4.5×10 5 μm 2 From 1.9 × 10 6 μm 2 The only difference is that the acceptor concentration in the semiconductor layer 12 is about one order of magnitude lower in the present invention. m,max or I D,max This demonstrates that the manufacturing method including step S16 and the device structure having the oxide film 17 can provide a MOSFET using a boron-doped single crystal diamond semiconductor layer that has good electrical characteristics from the initial characteristics, and in particular, a p-type MOSFET using a boron-doped single crystal diamond semiconductor layer that has good electrical characteristics from the initial characteristics not only at room temperature but also at 300° C.

[0048] [Table 1] [Industrial Applicability]

[0049] According to the present invention, there is provided a p-type MOSFET that uses single crystal diamond for its semiconductor layer, which operates stably even at a high temperature of 300° C. and has excellent transistor electrical characteristics, and a method for producing the same. Single crystal diamond has outstanding physical properties such as a wide band gap energy, a low relative dielectric constant, a high dielectric breakdown field strength, a high carrier saturation velocity, a high thermal conductivity, and a high carrier mobility. Therefore, the present invention makes it possible to provide a p-type MOSFET with high performance and excellent resistance to harsh environments. Therefore, the present invention has great potential for industrial use. [Explanation of symbols]

[0050] 11: Substrate, single crystal diamond substrate 12: Semiconductor layer, boron-doped single crystal diamond 13: Drain, drain electrode, Ti / Au film 14: Source, source electrode, Ti / Au film 15: Insulating film, gate insulating film, Al2O3 film 15a: Insulating film, Al2O3 film 16: Gate, gate electrode, Ti / Au film 17: Oxide film, Al2O3 film 17a: Oxide film, Al2O3 film 101: p-type MOSFET (boron-doped single crystal diamond p-type MOSFET)

Claims

1. A semiconductor layer made of boron (B)-doped diamond single crystal is formed in contact with the first main surface of a single-crystal diamond substrate. A source electrode and a drain electrode are formed on the semiconductor layer, The first main surface of the semiconductor layer other than the source electrode and the drain electrode is covered with an insulating film. A gate electrode is formed in a portion of the region on the insulating film that is sandwiched between the source electrode and the drain electrode, and does not electrically contact the source electrode and the drain electrode. A boron-doped diamond MOSFET is provided, wherein an oxide film is formed on each end of the gate electrode, the source electrode, and the drain electrode, as well as on the surface of the exposed insulating film.

2. The oxide film is composed of one or more selected from the group consisting of alumina (Al ２ O ３ ), hafnium dioxide (HfO ２ ), hafnium silicon dioxide (HfSiO ２ ), silicon dioxide (SiO ２ ), silicon oxynitride (SiON), zirconium dioxide (ZrO ２ ), lanthanum aluminum trioxide (LaAlO ３ ), tantalum pentoxide (Ta ２ O ５ ), titanium dioxide (TiO ２ ), and magnesium oxide (MgO), the boron-doped diamond MOSFET according to claim 1.

3. The aforementioned oxide film is ALD-Al ２ O ３ A boron-doped diamond MOSFET according to claim 2, comprising a film.

4. The boron-doped diamond MOSFET according to any one of claims 1 to 3, wherein the thickness of the oxide film is 10 nm or more and 50 nm or less.

5. The insulating film is alumina (Al ２ O ３ ), hafnium dioxide (HfO ２ ), hafnium silicon dioxide (HfSiO ２ ), silicon dioxide (SiO ２ ), silicon oxide nitride (SiON), zirconium dioxide (ZrO ２ ), aluminum lanthanum trioxide (LaAlO ３ ), tantalum pentoxide (Ta ２ O ５ ), boron nitride (BN), calcium difluoride (CaF ２ ), magnesium difluoride (MgF ２ ), titanium dioxide (TiO ２ A boron-doped diamond MOSFET according to claim 1, comprising one or more selected from the group consisting of ) and magnesium oxide (MgO).

6. The aforementioned insulating film is ALD-Al ２ O ３ A boron-doped diamond MOSFET according to claim 5, comprising a film.

7. The boron-doped diamond MOSFET according to claim 1, wherein the thickness of the insulating film is 10 nm or more and 50 nm or less.

8. The boron-doped diamond MOSFET according to claim 1, wherein the material of the gate electrode includes one or more selected from the group consisting of gold (Au), platinum (Pt), iridium (Ir), rhenium (Re), palladium (Pd), rhodium (Rd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), magnesium (Mg), tungsten (W), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), zinc (Zn), cadmium (Cd), mercury (Hg), gallium (Ga), indium (In), boron (B), carbon (C), silicon (Si), and germanium (Ge).

9. The boron-doped diamond MOSFET according to claim 8, wherein the material of the source electrode and the drain electrode in contact with the semiconductor layer includes one selected from the group consisting of titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), palladium (Pd), titanium (Ti) / gold (Au) bilayer, and titanium (Ti) / platinum (Pt) bilayer.

10. Prepare a substrate in which a single-crystal diamond layer is formed on at least a portion of the surface, A boron (B) doped semiconductor layer is formed on the surface of the substrate on which the single-crystal diamond layer is formed. Forming ohmic contact source and drain electrodes on the semiconductor layer, Forming a gate insulating film, The gate electrode is formed on the gate insulating film in an electrically non-contact state with the source electrode and the drain electrode, A method for manufacturing a boron-doped diamond MOSFET, comprising forming an oxide film that covers the exposed surfaces of the gate electrode, the source electrode, the drain electrode, and the gate insulating film.

11. A method for forming an oxide film covering each end of the gate electrode, the source electrode, and the drain electrode, and the exposed surface of the gate insulating film, comprising forming an oxide film and etching the oxide film in a portion of the region on the gate electrode, the source electrode, and the drain electrode, excluding each end of the gate electrode, the source electrode, and the drain electrode.

12. The aforementioned oxide film is made of alumina (Al ２ O ３ ), hafnium dioxide (HfO ２ ), hafnium silicon dioxide (HfSiO ２ ), silicon dioxide (SiO ２ ), silicon oxide nitride (SiON), zirconium dioxide (ZrO ２ ), aluminum lanthanum trioxide (LaAlO ３ ), tantalum pentoxide (Ta ２ O ５ ), titanium dioxide (TiO ２ A method for producing a boron-doped diamond MOSFET according to claim 10 or 11, comprising one or more selected from the group consisting of ) and magnesium oxide (MgO).

13. The aforementioned oxide film is Al(CH ３ ) ３ Alumina (Al) produced by atomic layer deposition (ALD) using ozone as a precursor. ２ O ３ A method for producing a boron-doped diamond MOSFET according to claim 12, wherein the film is a membrane.

14. The gate insulating film is Al(CH ３ ) ３ Alumina (Al) produced by atomic layer deposition (ALD) using ozone as a precursor. ２ O ３ A method for producing a boron-doped diamond MOSFET according to claim 10, wherein the film is a membrane.

15. A method for manufacturing a boron-doped diamond MOSFET according to claim 10, wherein, after forming the semiconductor layer, at least the first main surface of the semiconductor layer is cleaned with an acidic solution before forming the gate insulating film, the source electrode, and the drain electrode.

16. The method for producing a boron-doped diamond MOSFET according to claim 15, wherein the acidic solution is a mixed acid consisting of sulfuric acid and nitric acid, with a volume ratio of 1 part sulfuric acid to 3 parts nitric acid.

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