Imaging device

Abstract

To provide an imaging device with low power consumption.SOLUTION: An imaging device comprises: pixels that have a function of holding first imaging data, and a function of acquiring difference data between the first imaging data and second imaging data; and an A / D conversion circuit that has a comparator circuit and a counter circuit. When outputs of the pixels correspond to the difference data, a clock signal to be supplied to the counter circuit is stopped.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] Oxide semiconductors have been attracting attention as a semiconductor material that can be used in transistors. Transistors are made using zinc oxide or In-Ga-Zn oxide semiconductors as the oxide semiconductor. Techniques for producing such a capacitor have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, an imaging device in which a transistor including an oxide semiconductor is used as part of a pixel circuit is It is disclosed in patent document 3.

[0006] In addition, the sensor is equipped with a 133 megapixel CMOS (Complem (entry metal oxide semiconductor) imaging element Such a technology is disclosed in Non-Patent Document 1. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-119711 A [Non-patent literature]

[0008] [Non-Patent Document 1] R. Funatsu et al., “133Mpixel 60fps CMOS Image Sensor with 32-Column Shared High-Speed ​​Column-Parallel SAR ADCs”, IEEE ISSCC Dig.Tech.Papers, 2015. Summary of the Invention [Problem to be solved by the invention]

[0009] When transmitting data captured by an imaging device, the data is compressed to For example, in video compression, a reference frame is inserted every few frames. Between the reference frames, the imaging data of the reference frame and the imaging data of the current frame are set. Examples of methods include a method for obtaining the difference between the

[0010] In addition, in an imaging device having pixels arranged in a matrix, the In many cases, there are many pixels whose output data does not change. In most cases, the difference data for the same pixel is "0". By using an encoding process that can efficiently express ", the net amount of data can be reduced. do.

[0011] On the other hand, compressing the data captured by the imaging device reduces the load of data transmission, The digital image processing required to compress the data consumes a huge amount of power. A / D conversion of data output from each pixel of the device, output of the A / D converted data, frame In particular, the data output from each pixel of the image sensor is The power consumption is dominated by the power required for A / D conversion and differential processing of the digital data.

[0012] Therefore, an object of one embodiment of the present invention is to provide an imaging device with low power consumption. Alternatively, the present invention aims to provide an imaging device that reduces power consumption in A / D conversion processing. Alternatively, an imaging device that acquires differential data between successive frames is Another object of the present invention is to provide an imaging device suitable for high-speed operation. Another object of the present invention is to provide an imaging device with high resolution. Another object of the present invention is to provide an imaging device with a high degree of integration. It is an object of the present invention to provide an imaging device capable of capturing images dynamically. One of the objects of the present invention is to provide an imaging device with a wide range of characteristics. Another object of the present invention is to provide an imaging device that can be used in a wide range of applications. Another object of the present invention is to provide a highly reliable imaging device. Another object of the present invention is to provide a novel imaging device. Another object of the present invention is to provide a method for driving the imaging device. One of the objectives of the present invention is to provide a body device, etc.

[0013] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0014] According to one aspect of the present invention, there is provided a method for obtaining differential data between imaging data of a reference frame and imaging data of a current frame. The present invention relates to an imaging device that outputs

[0015] One aspect of the present invention is an imaging device having pixels arranged in a matrix and an A / D conversion circuit. The A / D conversion circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. a pixel is electrically connected to the first circuit, and the first to fourth circuits are The first circuit can input and output a signal having a high potential or a low potential. The first circuit has a function of stopping the operation in accordance with a second signal output from the pixel. and a third signal which is a reference potential signal, and outputs a fourth signal. The circuit includes a fourth signal, a fifth signal for controlling the fourth circuit, and a sixth signal for controlling the second circuit. and a seventh signal determined from a combination of the first and second signals, and the third circuit has a function of: The fourth circuit has a function of stopping the output of the clock signal according to the seventh signal. The device is characterized by having a function of performing counting according to a signal and outputting the counted data. It is an imaging device.

[0016] The first circuit may be a comparator circuit, and the fourth circuit may be a counter circuit.

[0017] The pixel has a function of holding the first imaging data and a function of storing the first imaging data and the second imaging data. The differential data may be acquired from the above.

[0018] The first circuit operates when the first signal is at a high level potential, and operates when the first signal is at a low level potential. It can be stopped at the bell potential.

[0019] The fourth signal output by the first circuit is a signal that is generated when the first signal is at a high level potential and the second signal is at a third level potential. When the first signal is a high level potential and the second signal is a high level potential, When the signal is smaller than the third signal, the potential is low, and when the first signal is low, the potential is low. When the potential is low, the potential can be set to low level.

[0020] The seventh signal output from the second circuit is a signal that is generated when the sixth signal is at a high level potential and the fifth signal is at a low level potential. and the fourth signal are both at a high level potential or at a low level potential. the sixth signal is at a high level potential and one of the fifth signal and the fourth signal is at a high level potential; the sixth signal is at a high level potential, the other is at a low level potential, and the sixth signal is at a high level potential when the other is at a low level potential. When it is at a low level potential, it can be set as a low level potential.

[0021] When the first signal is at a low level potential, the sixth signal may be at a low level potential. can.

[0022] The third circuit outputs a clock signal when the seventh signal is at a high level potential. The clock signal can be stopped when the signal is at a low level potential.

[0023] The fourth circuit performs an addition operation when the fifth signal is at a high level potential, and performs an addition operation when the fifth signal is at a low level potential. When the potential is at a level, a subtraction operation can be performed.

[0024] The pixel includes first to fifth transistors, a first capacitor, a second capacitor, and a photoelectric conversion element. One electrode of the photoelectric conversion element is connected to the source electrode or drain electrode of the first transistor. The first transistor is electrically connected to one of the source and drain electrodes of the first transistor. The other electrode is electrically connected to one of the source electrode or the drain electrode of the second transistor. The other of the source electrode and the drain electrode of the first transistor is connected to the first capacitance element. The other electrode of the first capacitor is electrically connected to one electrode of the third transistor. The other electrode of the first capacitance element is electrically connected to one of the source electrode and the drain electrode. is electrically connected to the gate electrode of the fourth transistor, and the other electrode of the first capacitance element is electrically connected to one electrode of the second capacitor element, and a source electrode of the fourth transistor or one of the drain electrodes is connected to one of the source electrode or drain electrode of the fifth transistor. The other of the source electrode and the drain electrode of the fifth transistor is electrically connected to The first circuit may be electrically connected to the second circuit.

[0025] The first to sixth transistors each have an oxide semiconductor in an active layer. The oxide semiconductor may be a transistor containing In, Zn, and M (M is A). It is preferable that the metal oxide has a metal content of 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, I wish.

[0026] In addition, the photoelectric conversion element may use selenium or a compound containing selenium in the photoelectric conversion layer. For example, the selenium may be amorphous or crystalline. do. Effect of the Invention

[0027] By using one embodiment of the present invention, an imaging device with low power consumption can be provided. It is possible to provide an imaging device that reduces power consumption in A / D conversion processing. It is possible to provide an imaging apparatus that acquires difference data between successive frames. Alternatively, it is possible to provide an imaging device suitable for high speed operation. Alternatively, a highly integrated imaging device can be provided. Alternatively, it is possible to provide an imaging device capable of imaging under low illuminance. It is possible to provide an imaging device with a wide dynamic range. Alternatively, it is possible to provide an imaging device having a high aperture ratio. Alternatively, a highly reliable imaging device can be provided. It is possible to provide an imaging device or the like. Or, it is possible to provide a driving method for the imaging device. Alternatively, a novel semiconductor device or the like can be provided.

[0028] Note that the effects of one embodiment of the present invention are not limited to these. In some cases or depending on the situation, the above effects may be different. Alternatively, for example, one aspect of the present invention may be, in some cases, or depending on the situation, In some cases, these effects may not be present. [Brief description of the drawings]

[0029] [Figure 1] 1A and 1B are a block diagram and a circuit diagram illustrating an imaging apparatus. [Diagram 2] 1A and 1B are a block diagram and a circuit diagram illustrating an imaging apparatus. [Diagram 3] FIG. 2 is a circuit diagram illustrating a pixel and a readout circuit. [Figure 4] 4 is a timing chart illustrating the operation of imaging and A / D conversion processing. [Diagram 5] 4 is a timing chart illustrating the operation of imaging and A / D conversion processing. [Figure 6] FIG. 2 is a circuit diagram illustrating a pixel and a readout circuit. [Figure 7] FIG. 2 is a circuit diagram illustrating a pixel and a readout circuit. [Figure 8] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 9] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 10] 4A and 4B are diagrams for explaining the operations of the rolling shutter system and the global shutter system. [Figure 11] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 12] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 13] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 14] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 15] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 16] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 17]1A and 1B are a cross-sectional view and a circuit diagram illustrating an imaging device. [Figure 18] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 19] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 20] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 21] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 22] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Diagram 23] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 24] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Diagram 25] 1A and 1B are diagrams illustrating a curved imaging device. [Figure 26] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 28] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 29] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 30] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Diagram 31] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 32] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 33] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 34] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 35] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 36] FIG. 1 is a top view illustrating a transistor. [Figure 37] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Figure 38]Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Figure 39] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Diagram 40] Cross-sectional TEM image of a-like OS. [Diagram 41] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 42] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Diagram 43] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Diagram 44] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0031] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0032] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0033] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0034] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0035] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. and the case where they are electrically connected to each other.

[0036] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0037] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0038] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0039] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a transistor The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not include the second connection path, and the third connection path The connection path is the path through Z2. The source (or the first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, the first connection path does not have a second connection path, The second connection path includes a connection path through a transistor, and the second connection path includes a drain of the transistor. (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1, and the first electrical path is The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , the fourth electrical path is not included, and the fourth electrical path is a drain of the transistor (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguish between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0040] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0041] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0042] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0043] Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. The size is determined by the distance between the ground and the ground. Even if it is stated, it does not necessarily mean that the potential is 0 volts. For example, "ground" or "GND" may be defined based on the lowest potential in the circuit. Or, define "ground" or "GND" based on the midpoint of the circuit potential. In such cases, positive and negative potentials are defined based on that potential. This results in:

[0044] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0045] An imaging device according to one embodiment of the present invention includes a plurality of pixels and an A / D conversion circuit. A function for storing the first imaging data and a function for storing a difference between the first imaging data and the second imaging data. It has the function of acquiring data.

[0046] The A / D conversion circuit has a comparator circuit and a counter circuit. The counter circuit has a function of comparing the output potential of the comparator circuit with a reference potential. It has the function of counting according to force.

[0047] When the output of the pixel corresponds to the difference data, the reference potential is increased from the first reference potential. A first period in which the potential is increased to the first reference potential and a second period in which the potential is decreased from the second reference potential are provided. In the second period, the output of the comparator circuit is inverted. The clock signal that is input to the clock generating section is stopped.

[0048] FIG. 1 is a diagram illustrating an imaging device according to one embodiment of the present invention. The imaging device has a matrix The pixel array includes pixels 20 arranged in a matrix and a circuit 23 and a circuit 24 for driving the pixels. In addition, the image sensor 10 includes a circuit 25 (A / D conversion circuit) to which a signal output from the pixel 20 is input. .

[0049] The circuit 25 has a function of converting an analog signal output from the pixel 20 into a digital signal, FIG. 1 shows a specific circuit diagram. In FIG. 1, the pixels 20 in the first column are connected. The figure shows the connection between the wiring 90 (OUT[1]) and the circuit 25[1]. The wiring 90 (OUT[2]) of the pixel 20 in the nth column is connected to the circuit 25[2], and the pixel 20 in the nth column The wiring 90 (OUT[n]) can be connected to the circuit 25[n]. In addition, one circuit 25 is electrically connected to each of a plurality of wirings 90(OUT), and the wirings 90( OUT) may be switched to perform processing.

[0050] The circuit 25 includes a comparison circuit, a determination circuit, and a counter circuit. As an example, the configuration and operation of the circuit 25 having a 3-bit counter circuit will be described. A counter circuit having a larger number of bits may also be used.

[0051] The comparison circuit may be a comparator circuit 31. A signal output from the pixel 20 is input to the first input terminal (+) via a wiring 90 (OUT). The second input terminal (-) can be input with a reference signal from the wiring 91 (RAMP). A potential signal can be input.

[0052] Here, the output signal COMP output from the output terminal of the comparator circuit 31 is When the reference potential signal is lower than the signal output by the pixel 20, the signal becomes “H” and When the reference potential signal is high, the comparator circuit 31 is at "L". When "H" is input from the wiring 92 (CEN) connected to the terminal, it becomes active, and when "L" When this signal is input, the device is in a non-operating state (output signal COMP is "L"). In this case, "H" means a high potential signal, and is expressed as "1" or a high level potential signal. Also, "L" means a low potential signal, and is expressed as "0" or a low level potential signal. It can also be realized.

[0053] The decision circuit can be composed of a circuit 32 and a circuit 33. The circuit 32 has two inputs When both are "H" or when both are "L", a "H" signal is output. For example, the circuit configuration shown in FIG. The configuration is not limited.

[0054] One signal input to the circuit 32 is the output signal COMP of the comparator circuit 31, and the other The other signal is input from the wiring 93 (UPDN). The input signal differs depending on the operation mode of the counter circuit. When the counter is operated as an incrementer, a "H" is input from line 93 (UPDN) and the counter is When using it as a counter for subtraction, "L" is input.

[0055] A control signal EN is input to the circuit 32 via a wiring 94 (EN). When the signal is H”, the circuit 32 receives the output signal COMP and the signal input from the wiring 93 (UPDN). Depending on the combination of signals, a "H" or "L" signal can be output. When the control signal EN is at "L", the circuit 32 outputs a signal at "L" regardless of the value of the output signal COMP. The number can be output.

[0056] Circuit 33 outputs a "H" signal when both input signals are "H". One signal input to the circuit 33 is the output signal of the circuit 32, and the other One signal is a clock signal (CLK1) input from a wiring 95 (CLK). When the output signal of the circuit 32 is "H", the clock signal (CLK2) is output from the circuit 33. is output. Here, the clock signal (CLK2) is used to operate the counter circuit.

[0057] The counter circuit includes flip-flop circuits 34, 35, and 36, inverter circuits 51 and 52, 53, 54, 55 and selector circuits 56, 57, 58, 59. Note that these components are merely examples and perform the same operations as those described below. Other elements may be components of the counter circuit. Other elements with integrated functionality may be components of the counter circuit.

[0058] The flip-flop circuits 34, 35, and 36 have a clock signal input terminal, an input terminal (D), and an output The flip-flop can have a configuration having a power terminal (Q) and a reset terminal (R). The reset terminals (R) of the drop circuits 34, 35, and 36 are provided with a reset signal. The signal line 96 (RST) is electrically connected to the signal line 96 (RST).

[0059] The output terminal of the circuit 33 is electrically connected to the clock signal input terminal of the flip-flop circuit 34. The input terminal (D) of the flip-flop circuit 34 is connected to an inverter circuit 5 The output terminal (Q) of the flip-flop circuit 34 is electrically connected to the output terminal (Q) of the flip-flop circuit 34. is electrically connected to the wiring 67 (DATA[0]). The output terminal (Q) of 4 is electrically connected to the input terminal of the inverter circuit 51.

[0060] The clock signal input terminal of the flip-flop circuit 35 is connected to the output terminal of the selector circuit 56. The first input terminal of the selector circuit 56 is electrically connected to the inverter circuit 5 The second input terminal of the selector circuit 56 and the output terminal of the selector circuit 57 are electrically connected to each other. The input terminal of the inverter circuit 52 is electrically connected to the output terminal (Q) of the flip-flop circuit 34. The selection control signal terminal of the selector circuit 56 is connected to the line 93 (UPDN). are electrically connected.

[0061] In the selector circuit 56, when the signal input from the wiring 93 (UPDN) is “H”, A signal input from the first input terminal becomes an output signal. When the input signal is "L", the signal input from the second input terminal becomes the output signal.

[0062] The input terminal (D) of the flip-flop circuit 35 is electrically connected to the output terminal of the selector circuit 57. The first input terminal of the selector circuit 57 is connected to the output of the inverter circuit 53. The second input terminal of the selector circuit 57 and the inverter The input terminal of the flip-flop circuit 53 is electrically connected to the output terminal (Q) of the flip-flop circuit 35. The selection control signal terminal of the selector circuit 57 is electrically connected to the wiring 97 (COUNT). are connected to the network.

[0063] In the selector circuit 57, when the signal input from the wiring 97 (COUNT) is “H”, A signal input from the first input terminal becomes an output signal. When the signal input from the first input terminal is "L", the signal input from the second input terminal becomes the output signal. When the signal input from the wiring 97 (COUNT) is "L", the counter circuit Not counted.

[0064] The output terminal (Q) of the flip-flop circuit 35 is connected to the wiring 68 (DATA[1]). are electrically connected.

[0065] The clock signal input terminal of the flip-flop circuit 36 ​​is connected to the output terminal of a selector circuit 58. The first input terminal of the selector circuit 58 is electrically connected to the inverter circuit 5 The second input terminal and the output terminal of the selector circuit 58 are electrically connected to each other. The input terminal of the inverter circuit 54 is electrically connected to the output terminal (Q) of the flip-flop circuit 35. The selection control signal terminal of the selector circuit 58 is connected to the line 93 (UPDN). The selector circuit 58 operates in the same manner as the selector circuit 56. This can be done.

[0066] The input terminal (D) of the flip-flop circuit 36 ​​is electrically connected to the output terminal of the selector circuit 59. The first input terminal of the selector circuit 59 is connected to the output of the inverter circuit 55. The second input terminal of the selector circuit 59 and the inverter The input terminal of the flip-flop circuit 55 is electrically connected to the output terminal (Q) of the flip-flop circuit 36. The selection control signal terminal of the selector circuit 59 is electrically connected to the wiring 97 (COUNT). The selector circuit 59 operates in the same manner as the selector circuit 57. can.

[0067] The output terminal (Q) of the flip-flop circuit 36 ​​is connected to the wiring 69 (DATA[2]). are electrically connected.

[0068] Wire 67 (DATA[0]), Wire 68 (DATA[1]), Wire 69 (DATA[2] The signal output to the DATA[2:0] pin is the output value of the counter circuit. By setting the line 96 (RST) to "H", the counter circuit is reset and The output value DATA[2:0] is assumed to be "000".

[0069] In addition, the flip-flop circuits 34, 35, and 36 are circuits having an inverting output terminal (Q bar). When the above-mentioned circuit is used, the inverter circuits 52 and 54 can be omitted as shown in FIG.

[0070] The pixel 20 used in the imaging device according to one embodiment of the present invention is a pixel that is obtained by detecting imaging data of a reference frame acquired in advance. The imaging data of the current frame (second imaging data) is stored. It is desirable to have a configuration that can output the difference between the

[0071] The pixel 20 can have a configuration shown in the circuit diagram of FIG. Element PD, transistor 41, transistor 42, transistor 43, transistor 44 , a transistor 45, a capacitance element C1, and a capacitance element C2. is preferably larger than the capacitance value of the capacitive element C2. 6 shows a configuration having a current source constituted by a transistor 46. The read-out circuit 26 may be provided with a sample-and-hold circuit.

[0072] One electrode of the photoelectric conversion element PD (photodiode) is connected to the source electrode of the transistor 41. The source electrode of the transistor 41 is electrically connected to one of the drain electrodes. The other of the drain electrodes is connected to one of the source and drain electrodes of the transistor 42. and one electrode of the capacitance element C1. The electrode is either the source electrode or the drain electrode of the transistor 43, or the gate electrode of the transistor 44. The gate electrode of the transistor 4 is electrically connected to one of the electrodes of the capacitance element C2. One of the source electrode or drain electrode of transistor 45 is connected to the source electrode or drain electrode of transistor 46. Also, the source electrode or drain electrode of the transistor 45 is electrically connected to the The other of the input electrodes is electrically connected to one of the source electrode or the drain electrode of the transistor 46. Connected.

[0073] The other electrode of the photoelectric conversion element PD is electrically connected to a wiring 71 (VPD). The other of the source electrode or the drain electrode of the transistor 42 is electrically connected to the wiring 72 (VPR). The other of the source electrode and the drain electrode of the transistor 43 is connected to a wiring 73 ( The other electrode of the capacitance element C2 is electrically connected to the wiring 74 (VC). The other of the source electrode and the drain electrode of the transistor 44 is connected to a wiring 75 (VO) is electrically connected to the source electrode or drain electrode of transistor 46. One of the electrodes is electrically connected to a wiring 76 (VR).

[0074] Here, the wiring 71 (VPD), the wiring 72 (VPR), the wiring 73 (VFR), and the wiring 74 (V C) The wiring 75 (VO) and the wiring 76 (VR) can function as power supply lines. For example, the wiring 71 (VPD), the wiring 74 (VC) and the wiring 76 (VR) are low-voltage The wiring 72 (VPR), the wiring 73 (VFR), and The wiring 75 (VO) can function as a high power supply potential line.

[0075] The gate electrode of the transistor 41 is electrically connected to a wiring 61 (TX). The gate electrode of the transistor 42 is electrically connected to the wiring 62 (PR). The gate electrode of the transistor 45 is electrically connected to the wiring 63 (FR). The electrode is electrically connected to the wiring 64 (SEL). It is electrically connected to the wiring 65 (RBIAS).

[0076] Here, the wiring 61 (TX), the wiring 62 (PR), the wiring 63 (FR), and the wiring 64 (SEL) and wiring 65 (RBIAS) functions as a signal line to control the on / off of the transistor. It can be done.

[0077] The transistor 41 controls the potential of the charge holding unit (FD1) in response to the output of the photoelectric conversion element PD. The transistor 42 can function as a transfer transistor for controlling the This functions as a reset transistor that initializes the potential of the charge storage section (FD1). The transistor 43 serves as a reset circuit for initializing the potential of the charge detection unit (FD2). The transistor 44 can also function as a charge detection transistor. The transistor (FD2) can function as an amplifier that outputs an output according to the potential of the The transistor 45 can also function as a selection transistor for selecting the pixel 20. In addition, the transistor 46 can be electrically connected to one of the source electrode and the drain electrode. a current source transistor for supplying an appropriate signal potential to the wiring 90 (OUT) connected to It can be made to function as such.

[0078] The above-described configurations of the circuit 25, the pixel 20, and the readout circuit 26 are merely examples. , some transistors, some capacitance elements, some wirings, etc. may not be included. Alternatively, a circuit, a transistor, a capacitor, a wiring, etc. that are not included in the above configuration may be included. Also, the connection form of some of the wiring may differ from the above-mentioned configuration.

[0079] Next, the above-described pixel 20 and circuit 10 will be described with reference to the timing charts shown in FIGS. The operation of the wiring 71 (VPD), wiring 74 (VC) and wiring 76 ( VR) is set to a low potential, and wiring 72 (VPR), wiring 73 (VFR) and wiring 75 (VO) is the high potential.

[0080] At times T01 to T04 and times T11 to T14, the imaging data of the reference frame is Obtain the data.

[0081] Between time T01 and time T02, the wiring 62 (PR) is set to "H" and the wiring 63 (FR) is set to " At this time, the potential of the charge detection unit FD2 is set to "H" on the line 73 The potential of the charge storage unit FD1 is set to the potential VFR of the wiring 72 (VPR). The VPR is set to the highest.

[0082] Between time T02 and time T03, the wiring 62 (PR) is set to "L" and the wiring 63 (FR) is set to " In this case, in response to light irradiated to the photoelectric conversion element PD, As a result, the potential of the charge storage unit FD1 drops by VP' to VPR-VP'. The stronger the light irradiating the element PD, the smaller the potential of the charge storage unit FD1 becomes. The potential of the unit FD2 is maintained at the potential VFR.

[0083] Between time T03 and time T04, the wiring 62 (PR) is set to "L" and the wiring 63 (FR) is set to " At this time, in response to light irradiated to the photoelectric conversion element PD, As a result, the potential of the charge storage unit FD1 further drops by VP' to VPR-2VP'. Due to the capacitive coupling between the capacitive element C1 and the capacitive element C2, the potential of the charge detection unit FD2 drops by VP. The stronger the light irradiating the photoelectric conversion element PD, the greater the charge retention portion FD The potential of the charge detection unit FD1 and the potential of the charge detection unit FD2 become smaller.

[0084] In the above operation, the interval between time T02 and time T03 and the interval between time T03 and time T The interval between time T02 and time T03 is set to T, and the intervals between the two are assumed to be equal. Between time T03 and time T04, the amount of light irradiated onto the photoelectric conversion element PD can be regarded as being the same. This shall be the case.

[0085] Between time T11 and time T12, the wiring 62 (PR) is set to "H" and the wiring 63 (FR) is set to " At this time, the potential of the charge storage unit FD1 is VPR- The potential VPR of the wiring 72 (VPR) is set from 2VP'. That is, the charge holding unit FD In the case of 1, the potential rises by 2VP', which is the voltage drop from time T02 to time T04. On the other hand, the potential of the charge detection unit FD2 is VFR-VP, and the potential of the capacitance element C1 and the capacitance element C2 are The potential of the charge detection unit FD2 increases by 2VP due to the capacitive coupling of the wire 7. 3 (VFR) and the voltage drop between time T03 and time T04 The potential is VFR+VP, which is the sum of -VP and the potential 2VP.

[0086] Between time T13 and time T14, the wiring 64 (SEL) is set to "H". By applying an appropriate potential to the line 65 (RBIAS), the potential VFR+ of the charge detection unit FD2 In response to VP, a voltage corresponding to the imaging data is output to the wiring 90 (OUT).

[0087] At time T131, the wiring 96 (RST) is set to “H”. The counter circuit of 5 is reset, and the wire 69 (DATA[2]) and the wire 68 (DATA[ 1]), and DATA[2:0] output to wire 67 (DATA[0]) is "000". do.

[0088] After that, by time T132, the line 97 (COUNT) is set to “H” and the line 93 (UPDN) is set to "H" to operate the counter circuit as an up-counter, and the wire 92 ( CEN) is set to "H" to operate the comparator circuit 31. The potential of (RAMP) is set to a low potential, which is lower than the potential of the wiring 90 (OUT). The output signal COMP of the comparator circuit 31 becomes "H".

[0089] Note that the potential of the wiring 94 (EN) is (UPDN) is "H" and the output signal COMP of the comparator circuit 31 is "H". When the line 93 (UPDN) is at "L" and the output signal of the comparator circuit 31 is The configuration is such that the signal COMP becomes "H" when the condition for "L" is met. Since the above condition is satisfied between time T131 and time T132, the wiring 94 (E N), i.e., the control signal EN becomes "H", and the circuit 32 outputs a signal of "H". It becomes possible to do so.

[0090] In addition, the control signal EN is transmitted through the line 93 (UPDN ) is "H" and the output signal COMP of the comparator circuit 31 is "L". Or, the wiring 93 (UPDN) is “L” and the output signal COMP of the comparator circuit 31 is “L”. When the condition for "H" is satisfied, the signal becomes "L". When the control signal EN is "L", the control signal EN is "L". When the line 92 (CEN) is at "L", the output signal COMP of the comparator circuit 31 is at "L". The wiring 94 (EN) is connected to the control signal shown in the following table with respect to the potential of each wiring. All you have to do is connect the circuit that generates EN.

[0091] [Table 1]

[0092] At time T132, the potential of the wiring 91 (RAMP) starts to rise. (CLK) supplies a clock signal CLK1 to the circuit 33. Initially, the output signal of the circuit 32 Since the clock signal CLK1 is at "H", the circuit 33 outputs a clock signal having the same waveform as the clock signal CLK1. The clock signal CLK2 is output and the counter circuit starts counting.

[0093] At time T13X, the potential of the wiring 91 (RAMP) is higher than the potential of the wiring 90 (OUT). The output signal COMP of the comparator circuit 31 becomes "L". The signal CLK2 goes to "L" and the counter circuit stops counting. After the comparator circuit 31 is turned off, the signal line CEN is set to "L" to stop the operation of the comparator circuit 31. Also, when the potential of the wiring 91 (RAMP) reaches a maximum value, the clock is immediately turned off. It is desirable to stop the supply of the clock signal CLK1. By doing so, power consumption can be reduced. At time T13X, DATA[2:0] is set to "110". become.

[0094] The period from time T21 to time T25 corresponds to the acquisition of imaging data in the first frame and the The difference data between the imaging data of the current frame and the imaging data of the reference frame is obtained during the period. Here, the imaging data of the reference frame and the first frame are the same, i.e., the difference The case where the data is 0 is illustrated.

[0095] Between time T21 and time T22, the wiring 62 (PR) is set to "H" and the wiring 63 (FR) is set to " At this time, the potential of the charge storage unit FD1 is set to "L" and the potential of the wiring 72 (TX) is set to "H". On the other hand, the potential of the charge detection unit FD2 is set to VFR+VP. become.

[0096] Between time T22 and time T23, the wiring 62 (PR) is set to "L" and the wiring 63 (FR) is set to " At this time, in response to light irradiated to the photoelectric conversion element PD, As a result, the potential of the charge storage unit FD1 drops. The potential of the charge detection unit FD2 also decreases due to the coupling.

[0097] In the above operation, the interval between time T22 and time T23 is the same as the interval between time T02 and time T03. The time T03 or the interval T between time T03 and time T04 is equal to the time T2. The amount of light irradiated to the photoelectric conversion element PD from time T02 to time T23 is 3 or the amount of light irradiated to the photoelectric conversion element PD at time T03 to time T04. It shall be possible.

[0098] At this time, the potential VP2' corresponding to the voltage drop of the charge storage unit FD1 is The potential VP' corresponds to the voltage drop at time T03 or between time T03 and time T04. The potential VP2 corresponding to the voltage drop of the charge detection unit FD2 is This is the same as the voltage drop VP at time T04. Therefore, the charge detection unit FD The potential VFR+VP-VP2 of the line 2 becomes the same potential as the potential of the line 73 (VFR). The difference between the imaging data of the reference frame and the imaging data of the first frame is zero. Corresponds to.

[0099] Between time T24 and time T25, the wiring 64 (SEL) is set to "H". By applying an appropriate potential to the line 65 (RBIAS), the potential VFR+ of the charge detection unit FD2 According to VP-VP2 (=VFR), a voltage corresponding to the image data is applied to wire 90 (OUT). is output.

[0100] Here, at time T241, the wiring 96 (RST) is set to “H”. At this time, the circuit 2 The counter circuit of 5 is reset, and the wire 69 (DATA[2]) and the wire 68 (DATA[ 1]), and DATA[2:0] output to wire 67 (DATA[0]) is "000". do.

[0101] After that, by time T242, the line 97 (COUNT) is set to “H” and the line 93 (UPDN) is set to "H" to operate the counter circuit as an up-counter, and the wire 92 ( CEN) is set to "H" to put the comparator circuit 31 into operation.

[0102] At time T242, the potential of the wiring 91 (RAMP) is set to the first reference potential, and then the wiring 9 The potential of the line 95 (CLK) is gradually increased. Supply LK1.

[0103] The first reference potential is the potential of the wiring 90 when the potential of the charge detection unit FD2 is the potential VFR. The potential is slightly higher than the potential of the charge detector FD2 (OUT). More specifically, the potential of the charge detector FD2 When the potential VFR is reached, the potential of the comparator circuit 31 is higher than the potential of the wiring 90 (OUT). This can be said to be the lowest potential that can be determined.

[0104] Initially, the potential of the wiring 91 (RAMP) is higher than the potential of the wiring 90 (OUT). The output signal COMP of the data circuit 31 becomes "L". At this time, the wiring 94 (EN) is "L". The clock signal CLK2 goes to "L" and the counter circuit does not count. Since the counting circuit has stopped, wire 92 (CEN) is set to "L" to turn on the comparator circuit. It is effective to configure the operation of the 31 to be stopped. By doing so, it is possible to reduce power consumption. This can be done.

[0105] Between time T243 and time T244, the wiring 97 (COUNT) is set to "L". After that, by time T244, wire 93 (UPDN) is set to "L" and then wire 97 (COUNT ) is set to "H" to make the counter circuit operate as a down counter. The wiring 92 (CEN) is set to "H" to put the comparator circuit 31 into an operating state.

[0106] At time T244, the potential of the wiring 91 (RAMP) is set to the second reference potential, and then the wiring 9 1 (RAMP) is gradually lowered, and the clock signal CLK1 is applied to the wiring 95 (CLK). Supply.

[0107] The second reference potential is the potential of the wiring 90 when the potential of the charge detection unit FD2 is the potential VFR. The potential is slightly lower than the potential of the charge detection unit FD2 (OUT). When the potential VFR is lower than the potential of the wiring 90 (OUT), the comparator circuit 31 This can be said to be the highest potential that can be determined.

[0108] During this time, the potential of the wiring 91 (RAMP) becomes lower than the potential of the wiring 90 (OUT). When this occurs, the output signal COMP of the comparator circuit 31 becomes "H".

[0109] At this time, the line 94 (EN) is at "L" and the clock signal CLK2 is at "L". The counter circuit does not count. At this point, the counting of the counter circuit is stopped, so the line 92 (CEN ) to "L" to stop the operation of the comparator circuit 31. When the potential of the line 91 (RAMP) reaches the lowest value, the supply of the clock signal CLK1 is immediately stopped. It is desirable to stop the supply of electricity. This will reduce power consumption. Here, the output of the circuit 25, DATA[2:0], becomes "000".

[0110] The period from time T31 to time T35 corresponds to the acquisition of imaging data in the second frame and the The difference data between the imaging data of the current frame and the imaging data of the reference frame is obtained during the period. Here, we take the example of a case where the difference between the reference frame and the second frame is finite (positive). The imaging data of the second frame is obtained by subtracting the imaging data of the reference frame from the imaging data of the second frame. The value can be obtained by subtracting the

[0111] Between time T31 and time T32, the wiring 62 (PR) is set to "H" and the wiring 63 (FR) is set to " At this time, the potential of the charge storage unit FD1 is set to "L" and the potential of the wiring 72 (TX) is set to "H". On the other hand, the potential of the charge detection unit FD2 is set to VFR+VP. become.

[0112] Between time T32 and time T33, the wiring 62 (PR) is set to "L" and the wiring 63 (FR) is set to " At this time, in response to light irradiated to the photoelectric conversion element PD, As a result, the potential of the charge storage unit FD1 drops. The potential of the charge detection unit FD2 also decreases due to the coupling.

[0113] In the above operation, the interval between time T32 and time T33 is the same as the interval between time T02 and time T03. The time T03 is equal to the interval T between time T03 and time T04. The amount of light irradiated to the photoelectric conversion element PD from time T02 to time T33 is 3 or the amount of light irradiated to the photoelectric conversion element PD at time T03 to time T04. It is decided.

[0114] At this time, the potential VP3' corresponding to the voltage drop of the charge storage unit FD1 is From the potential VP' corresponding to the voltage drop at time T03 or between time T03 and time T04 In addition, the potential VP3 corresponding to the voltage drop of the charge detection unit FD2 is also small from time T03 to time T04. This is smaller than the voltage drop VP at time T04. Therefore, the potential VF of the charge detection unit FD2 R+VP-VP3 has a higher potential than the potential of the wiring 73 (VFR). The difference between the imaging data in the first frame and the imaging data in the second frame is finite (positive value). This corresponds to the following.

[0115] Between time T34 and time T35, the wiring 64 (SEL) is set to "H". By applying an appropriate potential to the line 65 (RBIAS), the potential VFR+ of the charge detection unit FD2 Depending on VP-VP3 (>VFR), a voltage corresponding to the image data is applied to wire 90 (OUT). is output.

[0116] Here, at time T341, the wiring 96 (RST) is set to “H”. The counter circuit of 5 is reset, and the wire 69 (DATA[2]) and the wire 68 (DATA[ 1]), and DATA[2:0] output to wire 67 (DATA[0]) is "000". do.

[0117] After that, by time T342, the line 97 (COUNT) is set to “H” and the line 93 (UPDN) is set to "H" and wiring 94 (EN) is set to "H" to operate the counter circuit as an up-counter. The wiring 92 (CEN) is set to "H" to operate the comparator circuit 31. This is the state.

[0118] At time T342, the potential of the wiring 91 (RAMP) is set to the first reference potential, and then the wiring 9 The potential of the line 95 (CLK) is gradually increased. Supply LK1.

[0119] Initially, the potential of the wiring 91 (RAMP) is lower than the potential of the wiring 90 (OUT). The output signal COMP of the data circuit 31 becomes "H". At this time, the clock signal CLK2 This signal has the same waveform as the clock signal CLK1, and the counter circuit counts up.

[0120] At time T34X, the potential of the wiring 91 (RAMP) is higher than the potential of the wiring 90 (OUT). The output signal COMP of the comparator circuit 31 becomes "L". (EN) goes to "L", the clock signal CLK2 goes to "L", and the counter circuit stops counting. After the counter circuit stops counting, the line 92 (CEN) is set to "L" to It is effective to configure the comparator circuit 31 to stop operating. The force can be reduced.

[0121] Between time T343 and time T344, the wiring 97 (COUNT) is set to "L". After that, by time T344, wire 93 (UPDN) is set to "L" and then wire 97 (COUNT ) is set to "H" to make the counter circuit operate as a down counter. The wiring 92 (CEN) is set to "H" to put the comparator circuit 31 into an operating state.

[0122] Until time T344, the potential of the wiring 91 (RAMP) is set to be equal to or lower than the second reference potential. Also, a clock signal CLK1 is supplied to the wiring 95 (CLK). During this period, the potential of the wiring 91 (RAMP) becomes lower than the potential of the wiring 90 (OUT). At this time, the output signal COMP of the comparator circuit 31 becomes "H".

[0123] At this time, the line 94 (EN) is at "L" and the clock signal CLK2 is at "L". The counter circuit does not count. At this point, the counting of the counter circuit is stopped, so the line 92 (CEN ) to "L" to stop the operation of the comparator circuit 31. When the potential of the line 91 (RAMP) reaches the lowest value, the supply of the clock signal CLK1 is immediately stopped. It is desirable to stop the supply of electricity. This will reduce power consumption. Here, DATA[2:0] at time T34X is "010".

[0124] The period from time T41 to time T45 corresponds to the acquisition of imaging data in the third frame and the The difference data between the imaging data of the current frame and the imaging data of the reference frame is obtained during the period. Here, we take the example where the difference between the reference frame and the third frame is finite (negative). The imaging data of the third frame is obtained by subtracting the imaging data of the reference frame from the imaging data of the third frame. The value can be obtained by subtracting the

[0125] Between time T41 and time T42, the wiring 62 (PR) is set to "H" and the wiring 63 (FR) is set to " At this time, the potential of the charge storage unit FD1 is set to "L" and the potential of the wiring 72 (TX) is set to "H". On the other hand, the potential of the charge detection unit FD2 is set to VFR+VP. become.

[0126] Between time T42 and time T43, the wiring 62 (PR) is set to "L" and the wiring 63 (FR) is set to " At this time, in response to light irradiated to the photoelectric conversion element PD, As a result, the potential of the charge storage unit FD1 drops. The potential of the charge detection unit FD2 also decreases due to the coupling.

[0127] In the above operation, the interval between time T42 and time T43 is the same as the interval between time T02 and time T03. The time T03 or the interval T between time T03 and time T04 is equal to the time T4. The amount of light irradiated onto the photoelectric conversion element PD from time T02 to time T0 3 or the amount of light irradiated to the photoelectric conversion element PD from time T03 to time T04. Let us assume that.

[0128] At this time, the potential VP4' corresponding to the voltage drop of the charge storage unit FD1 is From the potential VP' corresponding to the voltage drop at time T03 or between time T03 and time T04 In addition, the potential VP4 corresponding to the voltage drop of the charge detection unit FD2 is also large from time T03 to time T04. This is larger than the voltage drop VP at time T04. Therefore, the potential VF of the charge detection unit FD2 R+VP-VP4 is at a potential lower than the potential of the wiring 73 (VFR). The difference between the imaging data of the first frame and the imaging data in the third frame is finite (the value is negative). This corresponds to that.

[0129] At time T44 to time T45, set the wiring 64 (SEL) to "H". At this time, by applying an appropriate potential to the wiring 65 (RBIAS), the potential VFR+ of the charge detection unit FD2 According to VP - VP4 (<VFR), a voltage corresponding to the imaging data is output to the wiring 90 (OUT). Output.

[0130] Here, at time T441, set the wiring 96 (RST) to "H". At this time, the counter circuit of circuit 2 5 is reset, and DATA[2:0] output to the wiring 69 (DATA[2]), wiring 68 (DATA 1]), and wiring 67 (DATA[0]) becomes "000".

[0131] After that, by time T442, set the wiring 97 (COUNT) to "H" and the wiring 93 (UPDN) to "H", and operate the counter circuit as an up - counter, and set the wiring 92( CEN) to "H" to operate the comparator circuit 31.

[0132] At time T442, after setting the potential of the wiring 91 (RAMP) to the first reference potential, gradually increase the potential of the wiring 9 1 (RAMP). Also, supply the clock signal C LK1 to the wiring 95 (CLK).

[0133] Initially, since the potential of the wiring 91 (RAMP) is higher than the potential of the wiring 90 (OUT), the output signal COMP of the comparator circuit 31 becomes "L". At this time, the wiring 94 (EN) is "L" , the clock signal CLK2 is "L", and the counter circuit does not count. Here, the counter ​​Since the counting circuit has stopped, wire 92 (CEN) is set to "L" to turn on the comparator circuit. It is effective to configure the operation of the 31 to be stopped. By doing so, it is possible to reduce power consumption. This can be done.

[0134] Between time T443 and time T444, the wiring 97 (COUNT) is set to "L". After that, by time T444, wire 93 (UPDN) is set to "L" and then wire 97 (COUNT ) to "H" and wiring 94 (EN) to "H", and the counter circuit operates as a down counter. In addition, the wiring 92 (CEN) is set to “H” to operate the comparator circuit 3 1 is the operating state.

[0135] During the period up to time T444, the potential of the wiring 91 (RAMP) is set to the second reference potential, and then the wiring The potential of 91 (RAMP) is gradually decreased, and the clock signal CLK1 is applied to the wiring 95 (CLK). supplies.

[0136] At time T444, the potential of the wiring 91 (RAMP) is higher than the potential of the wiring 90 (OUT). Therefore, the output signal COMP of the comparator circuit 31 becomes "L". The clock signal CLK2 has the same waveform as the clock signal CLK1, and the counter circuit counts up. .

[0137] If the potential of the wiring 91 (RAMP) is further decreased after time T444, then at time T44X, In this case, the potential of the wiring 91 (RAMP) becomes lower than the potential of the wiring 90 (OUT), The output signal COMP of the regulator circuit 31 becomes "H".

[0138] At this time, the signal line EN is "L" and the clock signal CLK2 is "L", and the counter circuit At this point, the counting of the counter circuit is stopped, so the wire 92 (CEN) is L” to stop the operation of the comparator circuit 31. When the potential of (RAMP) reaches the minimum value, the supply of the clock signal CLK1 is stopped immediately. In this way, power consumption can be reduced. So, at time T44X, DATA[2:0] becomes "101".

[0139] With the above circuit configuration and operation, the image data and the difference data are converted into digital data. Therefore, it is possible to reduce the power consumption in the A / D conversion process of converting It is possible to provide an imaging device capable of performing data compression processing with low power consumption.

[0140] The circuit of the pixel 20 is not limited to the configuration shown in FIG. 3, but may have the configurations shown in FIGS. 6(A) to 6(C). FIG. 6A shows a configuration in which the connection direction of the photoelectric conversion element PD is opposite to that shown in FIG. In this configuration, the wiring 71 (VPD) is set to a high potential, the wiring 72 (VPR) and the wiring 7 The potential of 3 (VFR) can be set to a low potential. In this configuration, the potential of the wiring 71 (VPD) is set to a high potential. The charge holding unit FD1 can be reset by this. The other of the source electrode and the drain electrode is connected to a wiring 90 (OUT).

[0141] In addition, the transistors used in the pixel circuits are as shown in FIG. A back gate may be provided to the transistors 41 to 46. A) is a structure in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. As an example, the back gate is connected to a wiring 66 (VSS) and a wiring 74 ( VC) or the source side of the transistor, FIG. 7B shows a case where the same potential as that of the front gate is applied to the back gate. This structure allows the on-current to be increased. The configurations of Figure 7(A) and Figure 7(B) are combined so that the transistor has suitable electrical characteristics. The configuration in FIG. 7(C) is an example. The configurations of Figs. 6(A) to 6(C) and the configurations of Figs. 7(A) to 7(C) may be combined as necessary. This can be done.

[0142] In addition, the circuit of the pixel 20 includes multiple transistors 42 to 45 as shown in FIG. FIG. 8 shows a configuration in which the transistor 42 is shared by multiple pixels in the vertical direction. 1 to 45 are shown as examples of shared transistors, The transistors 42 to 45 may be shared among multiple pixels. By doing so, it is possible to reduce the number of transistors per pixel. In FIG. 8, the other of the source electrode or the drain electrode of the transistor 43 is connected to a wiring 72 (VPR). However, a wiring 73 (VFR) may be provided to connect to the wiring. In FIG. 8, the other electrode of the capacitance element C1 is connected to the wiring 74 (VC). However, the electrode may be connected to the wiring 71 (VPD). .

[0143] In addition, FIG. 8 illustrates a configuration in which the transistors 42 to 45 are shared by four pixels. However, it may be shared by two, three, five or more pixels. The configuration, the configuration shown in FIG. 6(A) to FIG. 6(C), and the configuration shown in FIG. 7(A) to FIG. The configurations can be combined in any manner.

[0144] Next, a specific configuration example of the imaging device of one embodiment of the present invention will be described with reference to the drawings. FIG. 9A shows the photoelectric conversion element PD, the transistor 41, and the transistor 9 shows an example of a specific connection form of the transistor 42 and the capacitance element C1. In FIG. 2A, transistors 43 to 45 are not shown. a layer 1100 in which the transistors 41 to 45 and the capacitor C1 are provided; and It has a layer 1200 in which the photoelectric conversion element PD is provided.

[0145] In the cross-sectional views described in this embodiment, each wiring, each electrode, and each conductor 81 is individually Although shown as separate elements, when they are electrically connected they may be considered to be the same. In some cases, the gate electrode, source electrode, or The embodiment in which the drain electrode is connected to each wiring via the conductor 81 is an example. Each of the gate electrode, source electrode, and drain electrode of the transistor functions as a wiring. In some cases.

[0146] In addition, an insulating layer 82 having a function as a protective film, an interlayer insulating film, or a planarizing film is formed on each element. For example, the insulating layer 82 and the insulating layer 83 are made of silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic film can be used. Alternatively, an organic insulating film such as a resin or a polyimide resin may be used. The top surface of the 3rd class may be polished by CMP (Chemical Mechanical Polishing) if necessary. It is preferable to perform a flattening process by a flattening method or the like.

[0147] In addition, in some cases, wiring, etc., not shown in the drawings may not be provided, or wiring, etc., not shown in the drawings may not be provided. Each layer may contain transistors, etc. Also, layers not shown in the drawings may be included. Also, some layers shown in the drawings may not be included.

[0148] The transistors 41 to 45 are transistors including an oxide semiconductor (hereinafter It is particularly preferable to use an OS transistor.

[0149] OS transistors have extremely low off-state current characteristics, expanding the dynamic range of imaging. In the circuit configuration of the pixel 20 shown in FIG. When the intensity of the light received is high, the potential of the charge storage unit FD1 becomes low. The extremely low off-state current means that even when the gate potential is extremely low, Therefore, the level of illuminance that can be detected is This allows the imaging device to expand its dynamic range.

[0150] In addition, the transistors 41, 42, and 43 each have a low off-current characteristic. This makes it possible to extremely extend the period during which the charge can be held in the charge holding section FD1 and the charge detection section FD2. Therefore, all pixels can be simultaneously controlled without complicating the circuit configuration or operation method. A global shutter system that accumulates electric charges can be applied.

[0151] Generally, in an imaging device in which pixels are arranged in a matrix, the following is performed for each row as shown in FIG. A rolling driving method for performing an imaging operation 12, a data holding operation 13, and a read operation 14. When using the rolling shutter method, the simultaneity of imaging is Since this is lost, if the subject moves, the image will be distorted.

[0152] Therefore, one embodiment of the present invention is to perform imaging operation 12 and data simultaneously on all rows shown in FIG. A global shutter method in which a holding operation 13 is performed and a read operation 14 is performed for each row is performed. By using the global shutter method, each pixel of the image pickup device This ensures simultaneous imaging of the object, and reduces distortion even when the object moves. Therefore, clear images can be easily obtained.

[0153] An OS transistor is a transistor that uses silicon in the active region or active layer (hereafter referred to as Because the temperature dependency of the electrical characteristics is smaller than that of silicon transistors (see below), Therefore, imaging devices and semiconductor devices having OS transistors can be used in a wide range of applications. The conductor device is also suitable for installation in automobiles, aircraft, spacecraft, and the like.

[0154] In addition, the OS transistor has a higher drain withstand voltage than a Si transistor. In photoelectric conversion elements that use selenium-based materials as the photoelectric conversion layer, the avalanche phenomenon is likely to occur. It is preferable to apply a relatively high voltage (e.g., 10 V or more) so that Combining an S transistor with a photoelectric conversion element that uses a selenium-based material as a photoelectric conversion layer Thus, a highly reliable imaging device can be obtained.

[0155] In FIG. 9A, each transistor has a back gate. However, as shown in FIG. 9(B), a configuration without a back gate is also possible. As shown in (C), only some of the transistors, for example, the transistor 41, are provided with a back gate. The back gate may be provided on the opposite side of the transistor. In some cases, the back gate may be electrically connected to the front gate of the In some cases, a fixed potential different from that of the back gate may be supplied. This embodiment can also be applied to other pixel configurations described in this embodiment.

[0156] The photoelectric conversion element PD provided in the layer 1200 can be an element of various types. FIG. 9A illustrates a mode in which a selenium-based material is used for the photoelectric conversion layer 561. Photoelectric conversion elements PD using such materials have the characteristic of having high external quantum efficiency for visible light. In addition, since the selenium-based material has a high light absorption coefficient, it has the advantage that the photoelectric conversion layer 561 can be easily made thin. In the photoelectric conversion element PD using selenium-based materials, the incident light is absorbed by the avalanche phenomenon. It is possible to make a highly sensitive sensor with a large amplification of electrons relative to the amount of light. By using this material for the photoelectric conversion layer 561, it is possible to obtain a sufficient photocurrent even if the pixel area is reduced. In addition, the photoelectric conversion element PD using selenium-based materials is suitable for imaging in low-light environments. is also considered appropriate.

[0157] The selenium-based material may be amorphous or crystalline selenium. For example, amorphous selenium can be obtained by forming a film of amorphous selenium and then performing a heat treatment. By making the grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variation between pixels is reduced. Crystalline selenium also has a higher spectral sensitivity to visible light than amorphous selenium. It has the characteristics of high optical absorption coefficient.

[0158] Although the photoelectric conversion layer 561 is illustrated as a single layer, the selenium-based material is a material having a hole injection layer on the light receiving surface side. Gallium oxide or cerium oxide is provided as an electron injection blocking layer on the electrode 566 side. The stop layer may be made of nickel oxide or antimony sulfide.

[0159] The photoelectric conversion layer 561 is a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. In CIS and CIGS, the avalanche phenomenon can be utilized in the same way as in the case of elemental selenium. It is possible to form a photoelectric conversion element that can be used.

[0160] The photoelectric conversion element PD using a selenium-based material has an electrode 56 formed of, for example, a metal material. A photoelectric conversion layer 561 may be provided between the insulating layer 6 and the light-transmitting conductive layer 562. In addition, CIS and CIGS are p-type semiconductors and require sulfurization of n-type semiconductors to form a junction. Cadmium, zinc sulfide, or the like may be provided in contact with the metal.

[0161] In order to generate the avalanche phenomenon, a relatively high voltage (e.g., 10 It is preferable to apply a voltage of 100 V or more to the OS transistor. Because it has high withstand voltage characteristics, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, we have developed an OS transistor with high drain withstand voltage and a selenium-based material for photoelectric conversion. By combining this with a photoelectric conversion element with a layer of SiO2, a highly sensitive and reliable imaging device can be obtained. It is possible.

[0162] In FIG. 9A, the photoelectric conversion layer 561 and the light-transmitting conductive layer 562 are separated between the pixel circuits. However, as shown in FIG. 11A, the circuits may be separated from each other. In addition, a partition wall 567 made of an insulator is provided in the area between the pixels where the electrode 566 is not provided. It is preferable to prevent cracks from occurring in the photoelectric conversion layer 561 and the transparent conductive layer 562. However, as shown in FIG. 11(B), a configuration may be adopted in which the partition wall 567 is not provided. ) has a structure in which a wiring 88 and a conductor 81 are interposed between the transparent conductive layer 562 and the wiring 87. 11(C) and (D), the light-transmitting conductive layer 562 and the wiring 87 are A direct contact form may also be used.

[0163] The electrode 566 and the wiring 87 may be multi-layered. For example, as shown in FIG. As shown in FIG. 1, the electrode 566 is formed of two layers, a conductive layer 566a and a conductive layer 566b, and the wiring 87 is formed of the conductive layer In the structure shown in FIG. 12(A), For example, the conductive layer 566a and the conductive layer 87a are formed by selecting a low-resistance metal or the like, and the conductive layer 566b and the conductive layer 87b are formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 561. By adopting such a configuration, the electrical characteristics of the photoelectric conversion element PD can be improved. In addition, some metals may be electrolytically corroded by contacting the transparent conductive layer 562. Even if such a metal is used for the conductive layer 87a, the conductive layer 87b may cause a This can prevent electrolytic corrosion.

[0164] The conductive layer 566b and the conductive layer 87b are made of, for example, molybdenum or tungsten. The conductive layer 566a and the conductive layer 87a may be made of, for example, aluminum. , titanium, or stacks such as aluminum sandwiched between titanium can be used.

[0165] Also, the insulating layer 82 may have a multi-layer structure. For example, as shown in FIG. The insulating layer 82 has an insulating layer 82a and an insulating layer 82b, and the insulating layer 82a and the insulating layer 8 If the etching rate of the conductor 81 is different from that of the layer 2b, the conductor 81 will have a step. In the case where other insulating layers used for the interlayer insulating film or the planarizing film are multi-layered, the conductor 81 is also In this embodiment, the insulating layer 82 has two layers. The insulating layers 82 and other layers may be made up of three or more layers.

[0166] The partition wall 567 can be formed using an inorganic insulator, an insulating organic resin, or the like. In addition, the partition 567 is provided for blocking light from a transistor or the like and / or for preventing the number of pixels per pixel from increasing. The light receiving portion may be colored black or the like to define the area of ​​the light receiving portion.

[0167] In addition, the photoelectric conversion element PD is a pin A diode element or the like may also be used.

[0168] For example, FIG. 13 shows an example in which a pin-type thin-film photodiode is used as the photoelectric conversion element PD. The photodiode includes an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type The i-type semiconductor layer 564 has an amorphous structure. It is preferable to use silicon. In addition, the p-type semiconductor layer 563 and the n-type semiconductor layer 5 65 is made of amorphous silicon or microcrystalline silicon containing dopants that impart the respective conductivity types. Photodiodes that use amorphous silicon as a photoelectric conversion layer has high sensitivity in the visible light wavelength range and is easy to detect weak visible light.

[0169] In the photoelectric conversion element PD shown in FIG. 13, an n-type semiconductor layer 565 acting as a cathode is It has an electrical connection to an electrode 566 which has an electrical connection to a transistor 41. The p-type semiconductor layer 563 acting as a gate is electrically connected to the wiring 87 via the conductor 81. has.

[0170] As shown in FIG. 6A, the connection of the photoelectric conversion element PD is opposite to that shown in FIG. Therefore, in FIG. 13, the anode and In some cases, the connection between the cathode and the electrode layer and the wiring may be reversed.

[0171] In either case, the photoelectric conversion element is arranged so that the p-type semiconductor layer 563 serves as a light receiving surface. It is preferable to form a photodiode PD on the p-type semiconductor layer 563. The output current of the converter PD can be increased.

[0172] Also, the configuration of a photoelectric conversion element PD having a pin-type thin-film photodiode, and The photoelectric conversion element PD and the wiring connection form are shown in Fig. 14(A), (B), (C), (D), The examples shown in (E) and (F) may also be used. The connection form between the PD and the wiring is not limited to these, and other forms may be used.

[0173] FIG. 14A shows a light-transmitting conductive layer 562 in contact with a p-type semiconductor layer 563 of a photoelectric conversion element PD. The transparent conductive layer 562 acts as an electrode and outputs the photoelectric conversion element PD. The current can be increased.

[0174] The transparent conductive layer 562 is made of, for example, indium tin oxide or indium stannate containing silicon. zinc oxide, zinc oxide, zinc oxide containing gallium, aluminum oxide, Zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, or graphite The light-transmitting conductive layer 562 is not limited to a single layer, but may be a stack of different films. It may be.

[0175] FIG. 14B shows that the p-type semiconductor layer 563 of the photoelectric conversion element PD and the wiring 88 are electrically connected. It is a configuration in which it is directly included.

[0176] FIG. 14C shows a light-transmitting conductive layer 562 in contact with a p-type semiconductor layer 563 of a photoelectric conversion element PD. The wiring 87 and the light-transmitting conductive layer 562 are electrically connected to each other.

[0177] FIG. 14D shows an opening in the insulating layer covering the photoelectric conversion element PD, through which the p-type semiconductor layer 563 is exposed. A light-transmitting conductive layer 562 covering the opening is electrically connected to the wiring 88. It is a composition.

[0178] FIG. 14E shows a configuration in which a conductor 81 is provided to penetrate the photoelectric conversion element PD. In this configuration, the wiring 87 is electrically connected to the p-type semiconductor layer 563 via the conductor 81 . In the drawing, the wiring 87 and the electrode 566 are apparently connected via the n-type semiconductor layer 565. However, the lateral resistance of the n-type semiconductor layer 565 is Therefore, if an appropriate distance is provided between the wiring 87 and the electrode 566, the resistance between them is extremely high. Therefore, the photoelectric conversion element PD does not short-circuit the anode and cathode, It can have diode characteristics. There may be a plurality of conductors 81 .

[0179] FIG. 14F shows a photoelectric conversion element PD in FIG. 14E, which is connected to a p-type semiconductor layer 563. In this embodiment, a light-transmitting conductive layer 562 is provided.

[0180] In the photoelectric conversion element PD shown in FIG. 14(D), FIG. 14(E), and FIG. 14(F), Since the light receiving region does not overlap with wiring, etc., this has the advantage that a wide light receiving area can be secured.

[0181] As shown in FIG. 15, the photoelectric conversion element PD has a silicon substrate 600 as a photoelectric conversion layer. A photodiode having a capacitance of 100 .mu.m may also be used.

[0182] The photoelectric conversion element PD formed using the above-mentioned selenium-based material and amorphous silicon is formed by film deposition. It is manufactured using general semiconductor manufacturing processes such as the process of lithography and etching. In addition, selenium-based materials have high resistance, and as shown in FIG. The switching layer 561 may be configured not to separate the circuits. The imaging device can be manufactured at a high yield and low cost. When forming a photodiode with 600 as the photoelectric conversion layer, the polishing process and bonding process are This requires highly difficult processes such as

[0183] In addition, the imaging device according to one embodiment of the present invention includes a silicon substrate 600 on which a circuit is formed. For example, as shown in FIG. 16(A), an active region may be formed on a silicon substrate 600. A layer 1400 having a transistor 610 and a transistor 620 overlaps the pixel circuit. Note that FIG. 16B is a cross-sectional view in the channel width direction of a transistor. This corresponds to a surface view.

[0184] Here, in FIG. 16(A) and (B), the Si transistor is illustrated as having a fin-type structure. However, it may be a planar type as shown in FIG. 17(A). As shown in FIG. 6, the transistor may have an active layer 650 made of a silicon thin film. The active layer 650 is made of polycrystalline silicon or SOI (Silicon on Insulator). r) single crystal silicon.

[0185] The circuit formed on the silicon substrate 600 has a function of reading out the signal output by the pixel circuit and a function of detecting the corresponding It can have a function of performing a process of converting a signal, for example, the circuit shown in FIG. The transistor 610 ( The gates of transistors 610 (n-ch type) and 620 (p-ch type) are electrically connected. In addition, either the source or drain of one transistor is connected to the source of the other transistor. The source or drain of both transistors is electrically connected to the The other of the drains is electrically connected to a different wiring.

[0186] The circuits formed on the silicon substrate 600 are, for example, the circuits 23 and 24 shown in FIG. and circuit 25, etc.

[0187] In addition, the silicon substrate 600 is not limited to a bulk silicon substrate, but may be a germanium or silicon germanium substrate. Rumanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide Substrates made of gallium nitride or organic semiconductors may also be used.

[0188] Here, as shown in FIG. 15 and FIG. 16A, a transistor including an oxide semiconductor The area where a Si device (Si transistor or Si photodiode) is formed. An insulating layer 80 is provided between the regions where the electrodes are to be formed.

[0189] Water in the insulating layer provided near the active regions of transistor 610 and transistor 620 The hydrogen terminates the dangling bonds of silicon. Therefore, the hydrogen This has the effect of improving the reliability of transistor 10 and transistor 620. Hydrogen in the insulating layer provided near the oxide semiconductor layer, which is the active layer, such as the oxide semiconductor This hydrogen is one of the factors that generate carriers in the layer. Therefore, it is recommended to use silicon-based semiconductor materials. One layer has a transistor using an oxide semiconductor, and the other layer has a transistor using an oxide semiconductor. When layers are stacked, an insulating layer 80 having a function of preventing hydrogen diffusion is provided between the layers. It is preferable that the insulating layer 80 confines hydrogen to one layer, thereby preventing the transistor 6 from being damaged. The reliability of the transistor 620 and the semiconductor device 10 can be improved. The diffusion of hydrogen into the other layer is suppressed, thereby improving the reliability of the transistor 41, etc. can be done.

[0190] The insulating layer 80 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0191] In the configuration shown in FIG. 16(A), a circuit (for example, For example, a driving circuit, a transistor 41, etc., and a photoelectric conversion element PD are formed so as to overlap each other. This allows for a higher pixel density. For example, the number of pixels can be increased to 4k2k, 8k4k, or 16k8k. The transistor 44 of the pixel 20 is preferably a Si transistor. The transistor 41, the transistor 42, the photoelectric conversion element PD, etc. are overlapped with each other. It is also possible to have a configuration having a region.

[0192] An imaging device according to one embodiment of the present invention can have a structure shown in FIG.

[0193] The imaging device shown in FIG. 18 is a modified example of the imaging device shown in FIG. 16(A), and includes an OS transistor. The figure shows an example of constructing a CMOS inverter using a silicon transistor and a silicon transistor.

[0194] Here, the transistor 620, which is a Si transistor provided in the layer 1400, is a p-ch type. The OS transistor 610 provided in the layer 1100 is an n-channel transistor. By providing only p-ch type transistors on the silicon substrate 600, well formation and n-type Steps such as forming an impurity layer can be omitted.

[0195] In the imaging device shown in FIG. 18, selenium or the like is used for the photoelectric conversion element PD. Similar to 13, a pin type thin film photodiode may be used.

[0196] In the imaging device shown in FIG. 18, the transistor 610 is a transistor formed in the layer 1100. The transistor 41 and the transistor 42 can be fabricated in the same process. The manufacturing process of the imaging device can be simplified.

[0197] As shown in FIG. 19, the imaging device according to one embodiment of the present invention is formed on a silicon substrate 660. The pixel is composed of a photoelectric conversion element PD and an OS transistor formed on the element. Alternatively, the semiconductor device may have a structure in which the semiconductor device is laminated to a silicon substrate 600 on which a circuit is formed. With this configuration, the photoelectric conversion element PD formed on the silicon substrate 660 can be effectively In addition, it is easy to miniaturize the circuits formed on the silicon substrate 600. By increasing the integration density of these Si transistors, it is possible to provide high-performance semiconductor devices. .

[0198] 19, as shown in FIGS. 20 and 21, an OS transistor and The circuit may be configured with a silicon transistor and a silicon transistor. Therefore, it is easy to increase the effective area of ​​the photoelectric conversion element PD formed on the silicon substrate 660. In addition, the circuits formed on the silicon substrate 600 are highly integrated using miniaturized Si transistors. By integrating the semiconductor device, a high performance semiconductor device can be provided.

[0199] In the configuration of FIG. 20, the OS transistor and the Si transistor on the silicon substrate 600 Since OS transistors have an extremely low off-state current, CMOS circuits can be constructed using these transistors. This makes it possible to construct a CMOS circuit with extremely low static leakage current.

[0200] In the configuration of FIG. 21, the OS transistor on the silicon substrate 660 and the silicon substrate 6 CMOS circuits can be constructed using silicon transistors above 00.

[0201] Note that the configuration of the transistor and the photoelectric conversion element included in the imaging device in this embodiment is This is just an example. For example, any of the transistors 41 to 45 Alternatively, one or more of the transistors may be configured with silicon or the like in the active region or active layer. Alternatively, both or either of the transistors 610 and 620 may be activated. The transistor may also have an oxide semiconductor layer.

[0202] FIG. 22(A) is a cross-sectional view of an example of an imaging device to which a color filter or the like is added. The cross-sectional view shows a part of an area having pixel circuits for three pixels. On the layer 1200 to be formed, an insulating layer 2500 is formed. The insulating layer 2500 is irradiated with visible light. A highly transparent silicon oxide film can be used for the passivation. The anti-reflection film may be a silicon nitride film. A configuration in which a dielectric film such as fluorine is laminated may also be used.

[0203] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 may include an upper The light shielding layer 2510 has a function of preventing the mixing of colors of light passing through the color filter. A metal layer such as tungsten or aluminum, or a dielectric layer that functions as an anti-reflective coating The film may be laminated.

[0204] An organic resin layer 2520 is provided on the insulating layer 2500 and the light-shielding layer 2510 as a planarizing film. In addition, a color filter 2530 (color filter 25 30a, color filter 2530b, and color filter 2530c) are formed. For example, , color filter 2530a, color filter 2530b, and color filter 2530 c: R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0205] A light-transmitting insulating layer 2560 or the like may be provided on the color filter 2530. do.

[0206] Also, as shown in FIG. 22B, an optical conversion layer 255 is used instead of the color filter 2530. 0 may be used. With this configuration, images in various wavelength regions can be obtained. It is possible to provide an imaging device having such a configuration.

[0207] For example, if a filter that blocks light with wavelengths shorter than visible light is used for the optical conversion layer 2550, infrared The optical conversion layer 2550 can be used as an imaging device. If a filter having such a structure is used, a far-infrared imaging device can be obtained. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. .

[0208] In addition, if a scintillator is used for the optical conversion layer 2550, it is possible to use a radiation detector such as an X-ray imaging device. It is possible to make an imaging device that can obtain an image that visualizes the strength of lines. When radiation strikes a scintillator, it emits a large amount of light due to a phenomenon called photoluminescence. The light is converted into visible light, ultraviolet light, or other light (fluorescence). The light is then converted into Image data is obtained by detecting the radiation. A position may also be used.

[0209] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy and It is made of a substance that emits visible or ultraviolet light or a material that contains such a substance. For example, Gd2O 2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, C Materials such as sI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, and their The material dispersed in resin or ceramics can be used.

[0210] In addition, in photoelectric conversion elements PD that use selenium-based materials, radiation such as X-rays is directly converted into electric charges. Since the light can be converted, a configuration can be made in which a scintillator is not required.

[0211] As shown in FIG. 22C, the color filter 2530a and the color filter 2530 A microlens array 2540 may be provided on color filter 2530b and color filter 2530c. The light passing through each lens of the microlens array 2540 hits the color filter directly below. As shown in Figs. 22(A), (B), and (C), The area other than the layer 1200 shown in FIG.

[0212] FIG. 23 illustrates a pixel 20 according to one embodiment of the present invention and the microlens array 2 shown in FIG. FIG. 23 is a diagram illustrating a specific laminated structure such as 540. This is an example using the pixel configuration shown in FIG. 20. When using the pixel shown in FIG. 24, It becomes.

[0213] In this manner, the photoelectric conversion element PD, the transistor or the capacitor that constitutes the circuit of the pixel 20 Since the respective quantum elements can be configured to have mutually overlapping regions, the imaging device The device can be made smaller.

[0214] In addition, as shown in FIG. 23 and FIG. 24, a diffraction grating is provided above the microlens array 2540. The image of the subject through the diffraction grating 1500 (diffraction image) may be The input image (image of the subject) is calculated from the captured image at the pixel. In addition, by using a diffraction grating 1500 instead of a lens, the imaging device can be This can reduce the cost of installation.

[0215] The diffraction grating 1500 can be made of a material having optical transparency. For example, silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic resin film can be used. Alternatively, an organic insulating film such as a resin or a polyimide resin may be used. It may be laminated with an organic insulating film.

[0216] The diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. It can also be formed by using a lithography process and an etching process. It can also be formed by using nanoimprint lithography, laser scribing, or the like. do.

[0217] A distance X may be provided between the diffraction grating 1500 and the microlens array 2540. The interval X can be set to 1 mm or less, preferably 100 μm or less. The partition may be a space, or a light-transmitting material may be provided as a sealing layer or an adhesive layer. For example, an inert gas such as nitrogen or a rare gas can be sealed in the gap. Alternatively, a resin such as acrylic resin, epoxy resin, or polyimide resin may be provided in the space. A liquid such as silicone oil may be used. Even when the color filter 2530 and the diffraction grating 1500 are not arranged in the same manner, the distance X is set between the color filter 2530 and the diffraction grating 1500. It is okay.

[0218] The imaging device may also be curved as shown in FIG. 25(A1) and FIG. 25(B1). FIG. 25(A1) shows the imaging device bent in the direction of the two-dot chain line X1-X2 in the figure. FIG. 25(A2) shows the portion indicated by the two-dot chain line X1-X2 in FIG. 25(A1). FIG. 25(A3) is a cross-sectional view of the area indicated by the two-dot chain line Y1-Y2 in FIG. 25(A1). FIG.

[0219] FIG. 25(B1) shows a case where the imaging device is bent in the direction of the two-dot chain line X3-X4 in the same figure, and FIG. 25(B2) shows a state where the wire is bent in the direction of the two-dot chain line Y3-Y4 in the figure. FIG. 25(B3) is a cross-sectional view of a portion indicated by a two-dot chain line X3-X4 in FIG. 25(B1) is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG. 25(B1).

[0220] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the lenses and other components used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, which contributes to the miniaturization of electronic devices that use imaging devices. In addition, the quality of the captured image can be improved. do.

[0221] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. However, the present invention is not limited to this embodiment. In some cases or depending on the situation, one aspect of the present invention may be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. For example, in one embodiment of the present invention, a channel formation region, a source / drain region, etc. of a transistor However, one embodiment of the present invention is not limited thereto. In some cases, or depending on the situation, various transistors in one aspect of the present invention may be used. A transistor channel forming region, a transistor source drain region, etc. may comprise a variety of semiconductors. Various transistors, channel formation regions of transistors, or The source and drain regions of the transistor are made of, for example, silicon, germanium, silicon gel, etc. manium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, The semiconductor may have at least one of gallium nitride and organic semiconductors. For example, in some cases or circumstances, various transistors in one aspect of the present invention may be A transistor channel forming region, a transistor source drain region, etc. The layer 100 may not include an oxide semiconductor.

[0222] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0223] (Embodiment 2) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be given with reference to the drawings. Note that, in the drawings in this embodiment, the For ease of illustration, some elements may be enlarged, reduced, or omitted.

[0224] 26A and 26B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 26(A) is a top view, and FIG. 26(A) is a cross-sectional view taken along the dashed line B1-B2 shown in FIG. corresponds to FIG. 26(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 26(A) is 28(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is called the channel width direction.

[0225] The transistor 101 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; layer 150, the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 1 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0226] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0227] In addition, a region 231 shown in FIG. 26(B) is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are conductive regions. The conductive layers 140 and 150 are in contact with each other. If a conductive material that easily bonds with oxygen is used as the electrode, the resistance of the region 231 and the region 232 can be reduced. It is possible.

[0228] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0229] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. In addition, the term "electrode layer" can be replaced with "wiring." can.

[0230] In addition, the conductive layer 170 is illustrated as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0231] In addition, although the conductive layer 140 and the conductive layer 150 are illustrated as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may be applied to other transistors described in this embodiment. can.

[0232] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 26C is a top view of the transistor 102. The cross section in the 1-C2 direction corresponds to FIG. 26(D). Also, the dashed line C3 shown in FIG. The cross section in the -C4 direction corresponds to FIG. 28(B). The direction of the dashed dotted line C3-C4 is referred to as the channel width direction.

[0233] The transistor 102 is formed by connecting the end of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the ends of the conductive layer 170 acting as a gate electrode are not aligned with each other. The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layer 140, the conductive layer 150, and the conductive layer 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0234] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. In this structure, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high. This makes it easier to form small transistors.

[0235] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 26E is a top view of the transistor 103. The cross section in the 1-D2 direction corresponds to FIG. 26(F). Also, the dashed line D3 shown in FIG. The cross section in the -D4 direction corresponds to FIG. 28(A). The direction of the dashed dotted line D3-D4 is referred to as the channel width direction.

[0236] The transistor 103 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0237] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0238] In addition, a region 231 shown in FIG. 26(F) is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are insulators. If an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0239] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0240] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 27A is a top view of the transistor 104. The cross section in the 1-E2 direction corresponds to FIG. 27(B). Also, the dashed line E3 shown in FIG. The cross section in the -E4 direction corresponds to FIG. 28(A). The direction of the dashed dotted line E3-E4 is referred to as the channel width direction.

[0241] In the transistor 104, the conductive layer 140 and the conductive layer 150 are disposed at the end of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0242] In addition, the regions 331 and 334 shown in FIG. 27(B) are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. .

[0243] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. As with 2, the resistance can be reduced.

[0244] Regions 334 and 335 correspond to regions 231 and 232 in the transistor 103. The resistance of the region 334 in the channel length direction can be reduced in the same manner as the region 232. When the width of the region 335 is 100 nm or less, preferably 50 nm or less, the gate voltage The on-current does not decrease significantly due to the contribution of the field. Therefore, the regions 334 and 335 In some cases, the resistance of the capacitor may not be reduced.

[0245] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. This makes it suitable for high-speed operation.

[0246] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 27C is a top view of the transistor 105. The cross section in the 1-F2 direction corresponds to FIG. 27(D). Also, the dashed line F3 shown in FIG. The cross section in the -F4 direction corresponds to FIG. 28(A). The direction of the dashed dotted line F3-F4 is referred to as the channel width direction.

[0247] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0248] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0249] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0250] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 27E is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 27(F). The cross section in the -G4 direction corresponds to FIG. 28(A). The direction of the dashed dotted line G3-G4 is called the channel width direction.

[0251] The transistor 106 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; a conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer 162 in contact with the insulating layer 160; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The conductive layer 141 and the conductive layer 142 are formed through the openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, an insulating layer 180, an insulating layer (planarizing film) in contact with the conductive layer 142 and the conductive layer 152, ) and the like.

[0252] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0253] The transistor 106 has the same structure as the transistor 106 except that it has a conductive layer 141 and a conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0254] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 Since the insulating layer 120 is not in contact with the conductive layer 140, the oxygen in the insulating layer 120 is The oxide semiconductor layer 130 is less likely to be deprived of oxygen by the conductive layer 150. This makes it easier to supply the raw material.

[0255] Regions 231 and 232 in transistor 103, transistors 104 and In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed to increase the electrical conductivity. As the impurity that forms oxygen vacancies in the oxide semiconductor layer, Examples of these elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, and helix. Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more selected from zinc and carbon can be used. The methods of adding the metal oxide include plasma treatment, ion implantation, ion doping, plasma ion implantation, etc. A deposition ion implantation method or the like can be used.

[0256] When the above-mentioned element is added to the oxide semiconductor layer as an impurity element, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes an oxide The conductivity of the semiconductor layer can be increased.

[0257] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of an impurity element, the oxygen vacancies Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor Here, an oxide semiconductor that has been made into a conductor is referred to as an oxide conductor. Note that an oxide conductor has a light-transmitting property like an oxide semiconductor.

[0258] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0259] In addition, the transistor of one embodiment of the present invention can be formed as shown in FIG. 28(C) and (D) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0260] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 may be electrically connected via a contact hole.

[0261] In addition, in the transistors 101 to 106 in FIG. 26 and FIG. 27, Although the oxide semiconductor layer 130 is illustrated as a single layer, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 may be formed as shown in FIG. 30(B), (C), or 30(D), (E) may be replaced with the oxide semiconductor layer 130 shown in FIG. This can be done.

[0262] FIG. 30A is a top view of the oxide semiconductor layer 130, and FIGS. 30B and 30C are top views of the two-layer structure. 30(D) and (E) are cross-sectional views of an oxide semiconductor layer 130 having a three-layer structure. 1 is a cross-sectional view of an oxide semiconductor layer 130 having a structure.

[0263] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers having different compositions can be used.

[0264] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 31A is a top view of the transistor 107. The cross section in the 1-H2 direction corresponds to FIG. 31(B). Also, the dashed line H3 shown in FIG. The cross section in the -H4 direction corresponds to FIG. 33(A). The direction of the dashed line H1-H2 is the channel The longitudinal direction, the direction of the dashed dotted line H3-H4, is referred to as the channel width direction.

[0265] The transistor 107 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 140 and the conductive layer 150 connected to each other, 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170; and an insulating layer 180 that functions as a flattening film, if necessary. A function may be added.

[0266] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 101 .

[0267] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 31C is a top view of the transistor 108. The cross section in the 1-I2 direction corresponds to FIG. 31(D). Also, the dashed line I3 shown in FIG. The cross section in the -I4 direction corresponds to FIG. 33(B). The longitudinal direction, the direction of the dashed dotted line I3-I4, is referred to as the channel width direction.

[0268] In the transistor 108, the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the end of 0.

[0269] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 31E is a top view of the transistor 109. The cross section in the 1-J2 direction corresponds to FIG. 31(F). Also, the dashed line J3 shown in FIG. The cross section in the -J4 direction corresponds to FIG. 33(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, is referred to as the channel width direction.

[0270] The transistor 109 includes an insulating layer 120 in contact with a substrate 115 and an oxide semiconductor layer in contact with the insulating layer 120. A stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. a second insulating layer 160 in contact with the oxide semiconductor layer 130c; 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covers the conductive layer 170, an insulating layer 180 contacts the insulating layer 175, and the insulating layer 175 is and a conductive layer 14 electrically connected to the stack through an opening in the insulating layer 180. 0 and conductive layer 150. Also, as required, insulating layer 180, conductive layer 140 and An insulating layer (planarizing film) in contact with the conductive layer 150 may be provided.

[0271] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 has a second insulating layer 130c.

[0272] The transistor of one embodiment of the present invention may have a structure shown in FIGS. FIG. 32A is a top view of the transistor 110. The cross section in the 1-K2 direction corresponds to FIG. 32(B). Also, the dashed line K3 shown in FIG. The cross section in the -K4 direction corresponds to FIG. 33(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, is referred to as the channel width direction.

[0273] The transistor 110 has two oxide semiconductor layers 130 in the regions 331 and 332. In the region 333, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 104 has a similar structure to the transistor 104, except that the transistor 104 has a second insulating layer 130c.

[0274] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 32C is a top view of the transistor 111. The cross section in the 1-K2 direction corresponds to FIG. 32(D). Also, the dashed line K3 shown in FIG. The cross section in the -K4 direction corresponds to FIG. 33(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, is referred to as the channel width direction.

[0275] The transistor 111 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 141 and the conductive layer 151 connected to each other, and the laminate, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the laminate, the conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 in contact with the insulating layer 175 and the openings provided in the insulating layer 175 and the insulating layer 180 are Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 may also include an insulating layer 180, a conductive layer 142, and a conductive layer 153. An insulating layer (flattening film) or the like may be provided in contact with 52 .

[0276] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 141 and the conductive layer 151 are the insulating layer 16. 0, except that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between The transistor has a similar structure to that of the transistor 105 .

[0277] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 32E is a top view of the transistor 112. The cross section in the 1-M2 direction corresponds to FIG. 32(F). Also, the dashed line M3 shown in FIG. The cross section in the -M4 direction corresponds to FIG. 33(A). The longitudinal direction, the direction of the dashed dotted line M3-M4, is referred to as the channel width direction.

[0278] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (the oxide semiconductor layer 130a, the oxide 130a and 130b, and an oxide semiconductor layer 130c). They have a similar configuration.

[0279] In addition, the transistor of one embodiment of the present invention is shown in FIG. 33(C) and (D) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0280] Further, the transistor of one embodiment of the present invention has the structure shown in FIG. FIG. 35(A) is a top view, and FIG. 35(B) is a top view of the 35 is a cross-sectional view corresponding to the dashed line N1-N2 and the dashed line N3-N4. In the top view of (A), some elements are omitted for clarity.

[0281] The transistor 113 shown in FIG. 35(A) and FIG. 35(B) is a transistor including a substrate 115 and a substrate 11 5, and the oxide semiconductor layer 130 on the insulating layer 120 (the oxide semiconductor layer 130 a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) and a The conductive layer 140 and the conductive layer 150 are spaced apart from each other, and the oxide semiconductor layer 130 is c, and a conductive layer 170 in contact with the insulating layer 160. The semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 form an insulating layer on the transistor 113. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b and the insulating layer 12 provided in the It is provided at an opening that reaches 0.

[0282] The configuration of the transistor 113 is different from the configurations of the other transistors described above in that the source Since the overlapping area between the conductor that will become the electrode or drain electrode and the conductor that will become the gate electrode is small, Therefore, the parasitic capacitance can be reduced. The upper surface of the transistor 113 is shown in FIG. As shown in (B), CMP (Chemical Mechanical Polishing) It is preferable to flatten the surface by using a method such as ng), but it is also possible to adopt a structure in which flattening is not performed. .

[0283] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is a top view (oxide semiconductor layer 1) shown in FIG. 30, conductive layer 140 and conductive layer 150 are shown), O S ) of the conductive layer 140 and the conductive layer 150. SD ) may be formed long However, it may be formed short. OS ≧W SD (W SD W OS (below) The gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electrical characteristics of the transistor are improved. Also, as shown in FIG. 36(C), the conductive layer 140 and the conductive layer The insulating film 150 may be formed only in the region overlapping with the oxide semiconductor layer 130 .

[0284] In the transistors of one embodiment of the present invention (transistors 101 to 113), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0285] In addition, a transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In the transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By passing a current through the conductor layer 130b, the device is less susceptible to the effects of interface scattering and a high on-current can be obtained. Therefore, the on-current can be improved by making the oxide semiconductor layer 130b thicker. This may be the case.

[0286] With the above structure, the electrical characteristics of the transistor can be improved.

[0287] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0288] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0289] The substrate 115 may be a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a substrate with an insulating surface. A metal substrate with a surface treatment can be used. Alternatively, a transistor or a photodiode can be used. A silicon substrate on which a metal oxide film is formed, and an insulating layer, wiring, contact plug, etc. are formed on the silicon substrate. A conductive material having a function as a guide may be used. When forming a p-ch type transistor on the substrate, n - Silicon substrate having a conductivity type It is preferable to use a plate. - SOI substrate with type or i-type silicon layer In addition, when the transistor provided on the silicon substrate is a p-ch type, The surface orientation of the surface on which the transistor is formed is a (110) silicon substrate. It is preferable to form a p-ch transistor on the (110) surface to increase the mobility. It is possible.

[0290] The insulating layer 120 serves to prevent the diffusion of impurities from the elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The edge layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. The insulating layer 120 is preferably an insulating film containing a fluorine atom equivalent measured by a TDS method. The calculated amount of oxygen released is 1.0 x 10 19 atoms / cm 3 More preferably, it is equal to or greater than this. The surface temperature of the film during the TDS analysis was 100°C to 700°C or 10 The temperature range is from 0° C. to 500° C. In addition, the substrate 115 is a substrate on which other devices are formed. In this case, the insulating layer 120 also functions as an interlayer insulating film. It is preferable to perform planarization treatment by CMP or the like so that the surface becomes flat.

[0291] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or other oxide insulating films. , silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. A laminate of the above materials can be used. This is also possible.

[0292] In this embodiment, the oxide semiconductor layer 130 of the transistor is a) The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are stacked in this order from the insulating layer 120 side. The details will be mainly explained for the three-layer structure.

[0293] Note that in the case where the oxide semiconductor layer 130 is a single layer, Simply use the layer corresponding to 0b.

[0294] In addition, when the oxide semiconductor layer 130 has two layers, the oxide semiconductor layer 13 shown in this embodiment is A layer corresponding to oxide semiconductor layer 130a and a layer corresponding to oxide semiconductor layer 130b are formed in this order from the insulating layer 120 side. In this structure, the oxide semiconductor layer 130a and the oxide semiconductor layer It can also be interchanged with 130b.

[0295] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is added to the oxide semiconductor layer 130 having a three-layer structure. can be done.

[0296] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). The electron affinity is the energy difference between the vacuum level and the top of the valence band (ionic The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the value of

[0297] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum of the oxide semiconductor layer 13 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be made of a thin oxide semiconductor.

[0298] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It can also be said that the nucleus has a region that functions in a specific manner.

[0299] The oxide semiconductor layer 130a contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface state may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a can reduce the threshold voltage. As a result, variations in electrical characteristics such as the threshold voltage of the transistors can be reduced. In addition, the reliability of the transistor can be improved.

[0300] The oxide semiconductor layer 130c contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0301] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may include, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf is a material having a higher atomic number than the oxide semiconductor layer 130b. Specifically, a material containing the atomic ratio of 1.5 times or more of the atomic ratio can be used. The amount is preferably at least two times, and more preferably at least three times. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0302] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also installed. It is preferred that it includes

[0303] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and G. Examples include d, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0304] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0305] In addition, for example, In-Ga-Zn oxide is a material with In, Ga, and Zn as the main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0306] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It denotes a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and and n is an integer) may be used.

[0307] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are At least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La When the oxide semiconductor layer 1 is an In-M-Zn oxide containing a metal such as Ce or Hf, The oxide semiconductor layer 130a is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c is In:M:Z If n=x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 are y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1.0 times greater than y2 / x2. The thickness is set to 5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the conductor layer 130b, when y2 is equal to or larger than x2, the electrical characteristics of the transistor are stabilized. However, if y2 is three times or more larger than x2, the field effect mobility of the transistor Therefore, it is preferable that y2 is less than three times x2.

[0308] When Zn and O are excluded from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0309] The oxide semiconductor layer 130b is a semiconductor layer including the oxide semiconductor layer 130a and the oxide semiconductor layer 130. It is preferable to have a higher indium content than c. In oxide semiconductors, the s orbital of heavy metals is the The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are formed. Because the paths overlap, oxides with a composition in which In is greater than M have compositions in which In is equal to or less than M. Therefore, the mobility of the oxide semiconductor layer 130b is higher than that of the oxide semiconductor layer 130b. By using oxides with a high content of sodium, a transistor with high field effect mobility can be realized. It is possible.

[0310] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 5 The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 5 nm or more and 150 nm or less, more preferably More preferably, the thickness of the oxide semiconductor layer 130c is 10 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. Thicker than 0c is preferred.

[0311] In order to provide a transistor having an oxide semiconductor layer as a channel with stable electrical characteristics, The impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic (i-type) or substantially Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is Degree is 1 x 10 19 / cm 3 Less than 1 × 10 15 / cm 3 Less than 1 ×10 13 / cm 3 Less than or equal to 1 × 10 8 / cm 3 Less than 1 x 10 -9 / cm 3 It means that it is more than this.

[0312] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and degrade the electrical characteristics of a transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in layer 130c and at each interface.

[0313] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) The hydrogen concentration estimated by ion mass spectrometry (Ion Mass Spectrometry) analysis is 2 ×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 below, More preferably, 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 a toms / cm 3 Less than or equal to 1×10 17 atoms / cm 3 It has an area where The nitrogen concentration is controlled to be 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 Less than or equal to 5×10 16 atoms / cm 3 The control is performed so as to have a region where the above is satisfied.

[0314] In addition, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer is decreased. In order not to deteriorate the crystallinity of the oxide semiconductor layer, the silicon concentration is set to 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1× 10 18 atoms / cm 3 The carbon concentration is controlled to have a region where the carbon concentration is equal to or higher than the range. 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 Less than 6 × 10 17 ato ms / cm 3 The control is performed so as to have a region where the above is satisfied.

[0315] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or 10V, the off-state current per channel width of the transistor is several It is possible to reduce the resistance to yA / μm to several zA / μm.

[0316] Since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is In this way, it is preferable that the gate insulating film does not contact the semiconductor layer. When a channel is formed at the interface between the oxide semiconductor layer and the silicon oxide semiconductor layer, carrier scattering occurs at the interface. From this viewpoint, the field effect mobility of the transistor may be reduced. It is preferable to separate the region of the semiconductor layer that becomes the channel from the gate insulating film.

[0317] Therefore, the oxide semiconductor layer 130 is divided into an oxide semiconductor layer 130a and an oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel is formed in the oxide semiconductor layer 130b. Thus, a transistor having high field effect mobility and stable electrical characteristics can be formed. It is possible to form a

[0318] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers having different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dotted line.

[0319] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, a U-shaped junction in which the energy of the conduction band edge changes continuously between layers) The layers are fabricated so that a well structure (U Shape Well) is formed. There are no impurities at the interface that would form defect levels such as trap centers or recombination centers. If impurities are mixed between the stacked oxide semiconductor layers, When the interface is in a non-uniform state, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. It will disappear when combined.

[0320] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxide with an atomic ratio of 9:6 can be used. The compound semiconductor layer 130b has a composition of In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or Alternatively, an In-Ga-Zn oxide having an atomic ratio of 3:1:2 or the like can be used. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The atomic ratios of c each include a variation of ±40% of the above atomic ratios as an error. nothing.

[0321] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well, and The oxide semiconductor layer 130 has an energy level at the bottom of the conduction band. Since the temperature changes continuously, it can also be called a U-shaped well. The channel formed in this configuration may also be referred to as a buried channel.

[0322] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a method of forming a silicon oxide film or the like. In the vicinity of the interface with the insulating layer, trap levels due to impurities or defects may be formed. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c makes it possible to form the oxide semiconductor layer 13 This makes it possible to keep 0b away from the trap level.

[0323] However, the energy minimum of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the conduction band minimum of the oxide semiconductor layer 130b and the energy of the oxide semiconductor layer 130c is small, Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap levels, negative charges are generated at the interface of the insulating layer, causing the transistor to turn off. The threshold voltage of the transistor is shifted in the positive direction.

[0324] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor It is possible to give stable electrical properties to the crystals. In addition, the crystals oriented along the c-axis are resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0325] A conductive layer 140 acts as a source electrode layer and a conductive layer 141 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Representative examples include Ti, which is particularly susceptible to bonding with oxygen, and the fact that the subsequent process temperature can be relatively high. For these reasons, it is more preferable to use W, which has a high melting point. In addition, Cu and Cu-M, which have low resistance, are also preferable. A stack of an alloy such as n and the above material may be used. 06, transistor 111, and transistor 112, for example, conductive layer 141 and The conductive layer 142 and the conductive layer 152 are made of a laminated film of Ti and Al. There can be.

[0326] The above material has a property of extracting oxygen from the oxide semiconductor film. In some regions of the oxide semiconductor layer, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0327] In addition, when W is used for the conductive layer 140 and the conductive layer 150, it is possible to dope the W with nitrogen. By doping with nitrogen, the oxygen-pulling property can be moderately weakened, resulting in n-type In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding to the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By contacting the n-type region with the For the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc. can be used.

[0328] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. etc. may be contained as impurities.

[0329] An example of a layered structure of the insulating layer 160 will be described. The insulating layer 160 is made of, for example, oxygen. , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0330] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 can be reduced. Since the gate insulating film can be made large, the leakage current due to the tunnel current can be reduced. In addition, it is possible to realize a transistor with a small leakage current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic crystals. However, one aspect of the present invention is not limited to these.

[0331] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When the conductor comes into contact with the insulating layer 120, the density of states caused by nitrogen oxides may increase. The insulating layer 160 is made of, for example, a silicon oxynitride film or An oxide insulating layer such as an aluminum oxynitride film can be used.

[0332] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it outputs, typically releasing 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The amount of ammonia released is as follows: Heat treatment at a surface temperature of the film of 50°C or more and 650°C or less, preferably 50°C or more and 550°C or less. The amount of release is considered to be the amount of release by

[0333] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0334] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a fluorine atom.

[0335] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0336] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the transistors 107, 108, and 111, the insulating layer 175 is formed of an oxide layer. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Aluminum oxide has a high barrier effect of preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. Prevents oxygen from being mixed into the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and prevents the insulating layer 1 It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen from 20. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. do.

[0337] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0338] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than the stoichiometric composition. It is preferable that oxygen released from the insulating layer 180 is transported through the insulating layer 160 to the oxide semiconductor Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical properties can be obtained.

[0339] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width decreases. When the gate electrode shrinks, the on-current decreases.

[0340] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and the on-state voltage of the transistor is The flow can be increased.

[0341] In the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side in addition to the gate electric field from the direction perpendicular to the top surface. The gate electric field is applied from a direction perpendicular to the channel formation layer. Since the gate electric field is applied to the MOSFET, the effective channel width is enlarged, and the on-current is further increased. Can be enhanced.

[0342] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. First, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. In addition, the oxidation of the oxide film according to one embodiment of the present invention has an effect of making it difficult for an interface state to be formed. In a transistor having a three-layer structure of the oxide semiconductor layer 130, the oxide semiconductor layer 130b is disposed in the middle of the three-layer structure. By placing the layer in the position above the object, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor, the threshold voltage is stabilized. This allows the gate to be more stable and the S value (subthreshold value) to be reduced. The current when the voltage VG is 0V can be reduced, and power consumption can be reduced. Since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device is improved. In addition, the electrical characteristics of the transistor according to one embodiment of the present invention can be improved with miniaturization. Since deterioration of the semiconductor device can be suppressed, the present invention is suitable for forming a highly integrated semiconductor device.

[0343] The various films such as the metal film, the semiconductor film, and the inorganic insulating film described in this embodiment are typically The thin film can be formed by a deposition method or a plasma CVD method, but other methods, such as thermal CVD, are also possible. An example of the thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Atom These include the ic Layer Deposition method.

[0344] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0345] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0346] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber. The film is formed by repeatedly introducing and reacting the raw material gas into the inert gas ( For example, two or more kinds of gases (argon, nitrogen, etc.) may be introduced as a carrier gas. The source gases may be supplied to the chamber in sequence. In this case, multiple source gases are not mixed. In this manner, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is exhausted by evacuation, and then the second source gas is introduced. The first source gas may be introduced into the substrate so as to adsorb and react with the surface of the substrate to form a first layer. The second source gas is introduced later and adsorbed and reacted with the second layer, which is then formed on the first layer. The gas introduction sequence is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is injected. This is suitable for fabricating miniaturized FETs.

[0347] The thermal CVD method such as the MOCVD method or the ALD method may be used as described above in the embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and triethyl gallium may be used in place of trimethyl gallium. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0348] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide hafnium Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide The raw material gas is made by vaporizing hafnium (such as hafnium amide) and ozone ( Two types of gases are used:

[0349] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas made by vaporizing ethanol, etc., and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, and aluminium. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0350] For example, when forming a silicon oxide film using a deposition system that uses ALD, The silane is adsorbed on the surface to be coated and the radicals of oxidizing gases (O2, nitrous oxide) are provided. is fed to react with the adsorbate.

[0351] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The tungsten film is formed by sequentially introducing the two gases. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0352] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced in sequence to form a GaO layer, and Then, Zn(CH3)2 gas and O3 gas are introduced in sequence to form a ZnO layer. The order of these layers is not limited to this example. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. Alternatively, H2O gas obtained by bubbling an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0353] A facing target sputtering device can also be used to form the oxide semiconductor layer. The film formation method using this facing target sputtering device is called VDSP (vapor deposition). It can also be called deposition SP).

[0354] An oxide semiconductor layer is formed using a facing target sputtering apparatus, It is possible to reduce plasma damage during the formation of the oxide semiconductor layer. In addition, the oxygen deficiency in the film can be reduced by using a facing target sputtering device. Since this enables deposition at low pressure, the impurity concentration (e.g. For example, hydrogen, rare gases (such as argon), water, etc.) can be reduced.

[0355] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0356] (Embodiment 4) A structure of an oxide semiconductor film that can be used in one embodiment of the present invention will be described below. .

[0357] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0358] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0359] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0360] Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned (CAAC-OS) crystalline oxide semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l ike oxide semiconductor and amorphous oxide semiconductor. do.

[0361] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- Examples of such materials include OS, polycrystalline oxide semiconductors, and nc-OS.

[0362] Amorphous structures are generally isotropic, have no inhomogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and the short-range order is not fixed. It is said that...

[0363] From the other perspective, a stable oxide semiconductor can be considered as completely amorphous. In addition, it is not isotropic (for example, in a small area) and cannot be called an oxide semiconductor. An oxide semiconductor having a periodic structure in a crystal structure cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic but has voids (also called voids) and is unstable. In terms of instability, a-like OS is physically an amorphous oxide. Close to semiconductors.

[0364] <caac-os> First, let me explain about CAAC-OS.

[0365] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0366] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals is analyzed by the out-of-plane method. As shown in FIG. 37(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the upper surface. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the center are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not show such a peak.

[0367] On the other hand, in-pla, X-rays are incident on the CAAC-OS in a direction parallel to the surface on which the film is to be formed. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I The lattice constant is assigned to the (110) plane of the nGaZnO4 crystal. The 2θ is fixed at around 56°. The analysis (φ scan) is performed while rotating the sample around the axis (φ axis) of the normal vector of the sample surface. Even if the measurement is performed, no clear peak appears, as shown in FIG. When φ is scanned with 2θ fixed at around 56° for nO4, as shown in Figure 37(C). As shown in Fig. 1, six peaks are observed that are attributable to crystal planes equivalent to the (110) plane. From the structural analysis using RD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0368] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the CAAC-OS surface. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (control pattern) as shown in FIG. This is also called the limited-area electron diffraction pattern.) may appear. This diffraction pattern includes In The spots are due to the (009) plane of the GaZnO4 crystal. In some cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the material is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident vertically is shown in Figure 37(E). As shown in Fig. 37(E), a ring-shaped diffraction pattern is observed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the pellets in the CAAC-OS It can be seen that the a-axis and b-axis of the slit have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. It is considered that the second ring in Figure 37(E) is due to the (110) plane, etc. It is possible.

[0369] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and the diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. In some cases, it may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0370] Figure 38(A) shows a high-resolution T The TEM image is shown. For high-resolution TEM imaging, spherical aberration correction is used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, the atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that.

[0371] From FIG. 38(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used with CANC (C-Axis Aligned nan The pellets are also called oxide semiconductors with CAAC -OS surface or top surface unevenness, and CAAC-OS surface or top surface unevenness is parallel to the surface.

[0372] In addition, Fig. 38(B) and Fig. 38(C) show CAAC images observed from a direction approximately perpendicular to the sample surface. 38(D) and 38(E) show Cs-corrected high-resolution TEM images of the -OS plane. These are images obtained by processing the images of Figures 38(B) and 38(C), respectively. First, the method of performing the fast Fourier transform (FFT) on FIG. Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the FFT image, the origin is used as the reference point, and the distance is 2.8 nm. -1 From 5.0 nm -1 Remaining range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT: Inverse Fast Fourier Transform (IFFT) processing is used to The image thus obtained is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. The sequence is shown.

[0373] In FIG. 38(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the dashed line is the connection between the pellets. The broken line indicates a hexagonal shape, so it can be seen that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0374] In FIG. 38(E), a dotted line separates an area with a uniform lattice arrangement from an area with a different uniform lattice arrangement. The lattice arrangement direction is indicated by a dotted line. If you connect the lattice points around the dotted line, you will get a distorted hexagon. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the ab-plane direction. The substitution of metal elements causes the bond distance between atoms to change, resulting in distortion. This is believed to be because it is acceptable.

[0375] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an ane-anchored crystal. do.

[0376] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is improved by the incorporation of impurities. In other words, the CAAC-OS can be regarded as an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0377] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0378] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0379] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be a high-purity intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and is a substantially high-purity intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0380] <nc-os> Next, we will explain nc-OS.

[0381] The following describes the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of the nc-OS do not have any orientation.

[0382] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region shown in FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nm) when an electron beam with a probe diameter of 1 nm was incident on the same sample was The electron diffraction pattern (B) is shown in FIG. 39(B). From FIG. 39(B), a ring-shaped region Therefore, nc-OS has a probe diameter of 50 nm. Although no order was observed by irradiating the electron beam, the order was observed by irradiating the electron beam with a probe diameter of 1 nm. By projecting the images, order is confirmed.

[0383] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 39(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals have highly crystalline regions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0384] FIG. 39(D) shows the Cs-corrected high resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. As shown in Fig. 1, there are areas where crystals can be confirmed, and areas where no clear crystals can be confirmed. The crystal part in the nc-OS has a size of 1 nm to 10 nm. In particular, the size of the crystal part is often between 1 nm and 3 nm. An oxide semiconductor having a diameter of more than 0 nm and less than 100 nm is called a microcrystalline oxide semiconductor. It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be called a pellet.

[0385] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. There is no regularity in the crystal orientation between different pellets. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0386] In addition, since the crystal orientation between pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor can be called an oxide semiconductor.

[0387] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0388] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0389] Figure 40 shows a high-resolution cross-sectional TEM image of the a-like OS. This is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. ) is 4.3 × 10 8 e - / nm 2 Electrons (e - ) High a-like OS after irradiation 40(A) and 40(B) show that the a-like OS It can be seen that from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. It can be seen that the shape of the bright regions changes after electron irradiation. It is estimated to be in the degree range.

[0390] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0391] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample in is also an In-Ga-Zn oxide.

[0392] First, high-resolution cross-sectional TEM images of each sample are obtained. Each of the above has a crystalline portion.

[0393] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that the structure has a total of nine layers, including six O layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is about 0.29 nm, which is determined by crystal structure analysis. In the figure below, the areas where the lattice spacing is between 0.28 nm and 0.30 nm are InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0394] Figure 41 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. From Figure 41, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was a nucleus (also called the initial nucleus) is filled with electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the nc The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals in the range from The size of the crystalline parts of the nc-OS and CAAC-OS was The results show that the thicknesses are approximately 1.3 nm and 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. Electron beam irradiation conditions The acceleration voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0395] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. That is, compared with the nc-OS and CAAC-OS, the a-like OS It is clear that this is an unstable structure.

[0396] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0397] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0398] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions. The density can be estimated by using a weighted average. It is preferable to estimate them together.

[0399] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0400] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0401] (Embodiment 5) In this embodiment, an example of a package and a module containing an image sensor chip is The image sensor chip uses the configuration of the imaging device according to one embodiment of the present invention. There can be.

[0402] FIG. 42A is a perspective view showing the appearance of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 810 for fixing an image sensor chip 850, a cover It has a bar glass 820 and an adhesive 830 for bonding the two together.

[0403] FIG. 42(B) is a perspective view of the bottom surface of the package. The structure of BGA (Ball grid array) with solder balls as bumps 840 is used. In addition to BGA, LGA (Land grid array) and PGA (P in Grid Array) etc.

[0404] FIG. 42(C) shows a package in which the cover glass 820 and part of the adhesive 830 are omitted. FIG. 42(D) is a cross-sectional view of the package. An electrode pad 860 is formed on the substrate 810, and the electrode pad 860 and the bump 840 are The electrode pad 860 is electrically connected to the electrode pad 860 via a hole 880 and a land 885. is electrically connected to the electrodes of the image sensor chip 850 by wires 870. is.

[0405] FIG. 43(A) shows a camera in which an image sensor chip is housed in a lens-integrated package. FIG. 1 is a perspective view of the appearance of the upper surface side of a camera module. A package substrate 811 that fixes the cap 851, a lens cover 821, and a lens 835 In addition, between the package substrate 811 and the image sensor chip 851, An IC chip 890 having functions such as a driving circuit for the image device and a signal conversion circuit is also provided. It has a SiP (System in package) configuration.

[0406] FIG. 43B is a perspective view showing the appearance of the lower surface side of the camera module. The bottom surface and four side surfaces of the package 11 are provided with lands 841 for mounting. The structure is a lat no-lead package. Note that this structure is just an example. It can be QFP (Quad flat package) or the BGA mentioned above. stomach.

[0407] FIG. 43C shows a module with the lens cover 821 and a portion of the lens 835 omitted. FIG. 43(D) is a cross-sectional view of the camera module. A part of the electrode pad 861 is used as the image sensor chip. The electrodes of the chip 851 and the IC chip 890 are electrically connected by wires 871. is.

[0408] By housing the image sensor chip in a package of the above type, mounting becomes easy. Therefore, the semiconductor device and the electronic device can be incorporated in various semiconductor devices and electronic devices.

[0409] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0410] (Embodiment 6) An imaging device according to one aspect of the present invention and an electronic device including the imaging device are A personal computer, an image reproducing device equipped with a recording medium (typically DVD: Digital A display that can play recording media such as Versatile Discs and display the images. In addition, the imaging device and Electronic devices that can use the electronic device including the imaging device include mobile phones, mobile phones, Game consoles, including those of the 1990s, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of such electronic devices are shown in Figure 44.

[0411] FIG. 44A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 909, etc. The portable game machine shown in FIG. and a display unit 904, the number of display units that the portable game machine has is not limited to this. The imaging device of one embodiment of the present invention can be used as the camera 909.

[0412] FIG. 44B shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. The imaging device of one embodiment of the present invention can be used as the camera 919.

[0413] FIG. 44C shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 33, operation buttons 935, a crown 936, a camera 939, etc. The camera 939 may be a touch panel. It is possible.

[0414] FIG. 44D shows a surveillance camera having a housing 951, a lens 952, a support portion 953, etc. An imaging device according to one embodiment of the present invention can be provided at the focal position of the lens 952.

[0415] FIG. 44(E) shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 9 The lens 965 has a focal point of the present invention. The imaging device according to the present invention may include an imaging device according to the present invention.

[0416] FIG. 44(F) shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, The operation key 974, the lens 975, the connection part 976, etc. 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. The first housing 971 and the second housing 972 are connected by a connection portion 976. The angle between the first housing 971 and the second housing 972 can be changed by the connection part 976. The image on the display unit 973 is transmitted between the first housing 971 and the second housing 97 at the connection unit 976. 2. The focal point of the lens 975 may be set to the position shown in FIG. can be equipped with an imaging device according to one aspect of the present invention.

[0417] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0418] 12 Imaging operation 13 Data retention operation 14 Read Operation 20 pixels 23 Circuit 24 circuits 25 Circuit 26 Circuit 31 Comparator Circuit 32 Circuit 33 Circuit 34 Flip-flop circuit 35 Flip-flop circuit 36 Flip-Flop Circuit 41 Transistor 42 Transistor 43 Transistor 44 Transistor 45 Transistor 46 Transistor 51 Inverter circuit 52 Inverter circuit 53 Inverter circuit 54 Inverter circuit 55 Inverter circuit 56 Selector Circuit 57 Selector Circuit 58 Selector Circuit 59 Selector Circuit 61 Wiring 62 Wiring 63 Wiring 64 Wiring 65 Wiring 66 Wiring 67 Wiring 68 Wiring 69 Wiring 71 Wiring 72 Wiring 73 Wiring 74 Wiring 75 Wiring 76 Wiring 80 Insulating layer 81 Conductors 82 Insulating layer 82a Insulating layer 82b Insulating layer 83 Insulating Layer 87 Wiring 87a Conductive layer 87b Conductive layer 88 Wiring 90 Wiring 91 Wiring 92 Wiring 93 Wiring 94 Wiring 95 Wiring 96 Wiring 97 Wiring 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 113 Transistor 115 Substrate 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide semiconductor layer 130c Oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive Layer 150 Conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating layer 170 Conductive Layer 171 Conductive Layer 172 Conductive Layer 173 Conductive Layer 175 Insulating Layer 180 Insulating layer 190 Insulating Layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 561 Photoelectric conversion layer 562 Transparent conductive layer 563 Semiconductor Layer 564 Semiconductor Layer 565 Semiconductor Layer 566 Electrode 566a conductive layer 566b Conductive layer 567 Bulkhead 600 Silicon substrate 610 Transistor 620 Transistor 650 active layer 660 Silicon Substrate 810 Package Substrate 811 Package Substrate 820 Cover Glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 rand 850 Image Sensor Chip 851 Image sensor chip 860 Electrode Pads 861 Electrode Pads 870 Wire 871 Wire 880 through hole 885 rand 890 IC chips 901 Case 902 Case 903 Display section 904 Display section 905 Mike 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 Case 912 Display section 919 Camera 931 Case 932 Display section 933 Wristband 935 Button 936 Crown 939 Camera 951 Case 952 Lens 953 Support part 961 Case 962 Shutter button 963 Mike 965 Lens 967 Light emitting part 971 Case 972 Case 973 Display section 974 Operation Key 975 Lens 976 Connection 1100 layers 1200 layers 1400 layers 1500 Diffraction Grating 1600 layers 2500 Insulation Layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filter 2530a Color Filter 2530b Color Filter 2530c Color Filter 2540 Microlens Array 2550 Optical conversion layer 2560 Insulation layer

Claims

1. a plurality of pixels each including a photoelectric conversion element and a first transistor; a signal processing circuit having a second transistor; a region in which a layer including the first transistor is disposed above a layer including the second transistor; an imaging device having a region in which the photoelectric conversion element is disposed above the first transistor, a first insulating layer having a region disposed so as to cover a side surface of the photoelectric conversion element; a second insulating layer having a region disposed so as to fill a gap between the cathodes of the photoelectric conversion elements of adjacent first and second pixels among the plurality of pixels, and having a region not overlapping with the cathodes; a light-shielding layer having a region overlapping the second insulating layer and a region disposed above the first insulating layer; The second insulating layer has a region in contact with the first insulating layer. Imaging device.

2. a plurality of pixels each including a photoelectric conversion element and a first transistor; a signal processing circuit having a second transistor; a region in which a layer including the first transistor is disposed above a layer including the second transistor; an imaging device having a region in which the photoelectric conversion element is disposed above the first transistor, a first insulating layer having a region facing a side surface of the photoelectric conversion element; a second insulating layer having a region disposed so as to fill a gap between the cathodes of the photoelectric conversion elements of adjacent first and second pixels among the plurality of pixels, and having a region not overlapping with the cathodes; a light-shielding layer having a region overlapping the second insulating layer and a region disposed above the first insulating layer; the second insulating layer has a region in contact with the first insulating layer, A side surface of the photoelectric conversion element overlaps with the light-shielding layer. Imaging device.

3. In claim 1 or 2, The first insulating layer includes oxygen and silicon. Imaging device.

4. In any one of claims 1 to 3, a conductor having a region facing a side surface of the photoelectric conversion element via the first insulating layer; Imaging device.

Images