Semiconductor device

Abstract

To provide a semiconductor device having a configuration that can suppress reduction in electric characteristics that becomes remarkable with microfabrication.SOLUTION: A semiconductor device comprises: an oxide semiconductor layer in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are laminated on a substrate in this order from the substrate side; a source electrode layer and a drain electrode layer contacted with the oxide semiconductor layer; a gate insulating film formed on the oxide semiconductor layer, the source electrode layer and the drain electrode layer; and a gate electrode layer formed on the gate insulating film. The first oxide semiconductor layer has a first region. The gate insulating film has a second region. When a film thickness of the first region is defined as TS1, and a film thickness of the second region is defined as TGI, a relation of TS1≥TGI is satisfied.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, a manufacturing method, a process, a machine, manufacture, or an assembly. In particular, the present invention relates to a composition of matter, e.g., a semiconductor device. The present invention relates to a display device, a light-emitting device, a driving method thereof, or a manufacturing method thereof. The present invention relates to, for example, a semiconductor device, a display device, or a light-emitting device having an oxide semiconductor. do.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology for constructing thin-film transistors (also called thin-film transistors (TFTs)) is attracting attention. It is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material for this, oxide semiconductors have been attracting attention.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] In general, miniaturization of transistors is an essential technology for forming highly integrated circuits. As transistors are miniaturized, the transistors such as threshold voltage and S value (subthreshold value) It is known that the electrical characteristics of the transistor deteriorates.

[0007] Therefore, one embodiment of the present invention is a structure capable of suppressing deterioration of electrical characteristics that becomes significant with miniaturization. Another object of the present invention is to provide a semiconductor device having a low power consumption. Another object of the present invention is to provide a semiconductor device having high reliability. Alternatively, one aspect of the present invention is to reduce the deterioration of the S value (subthreshold value). Another object of the present invention is to provide a semiconductor device having a reduced Another object of the present invention is to provide a semiconductor device that reduces deterioration of low voltage. An object of one embodiment of the present invention is to provide a semiconductor device in which a parasitic channel is reduced. Another embodiment of the present invention is to provide a semiconductor device in which data is retained even when power is cut off. One of the objectives of this project is to

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention relates to a semiconductor device including stacked oxide semiconductor layers.

[0010] One embodiment of the present invention is a semiconductor device including a substrate having an insulating surface and a first oxide semiconductor layer formed on the substrate from the substrate side. a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer stacked in this order; A source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, A gate insulating film formed on the gate electrode layer and the drain electrode layer, and a gate insulating film formed on the gate insulating film a gate electrode layer, the first oxide semiconductor layer having a first region, and the gate insulating film having a second region. The first region has a thickness of T S1 , the thickness of the second region is T GI Then, T S 1 ≧ T GI The semiconductor device is characterized in that

[0011] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of illustration only and are not intended to be limiting.

[0012] In the above structure, the first oxide semiconductor layer and the third oxide semiconductor layer are The vacuum level is reached when the energy of the conduction band minimum is in the range of 0.05 eV to 2 eV below the semiconductor layer. It is preferable that the value is close to .

[0013] The first to third oxide semiconductor layers are each formed of an In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and the first oxide semiconductor The oxide semiconductor layer and the third oxide semiconductor layer have an atomic ratio of M to In that is equal to or larger than that of the second oxide semiconductor layer. It is preferable that it is greater than .

[0014] The source electrode layer includes a first source electrode layer in contact with the oxide semiconductor layer and a first source electrode layer. a second source electrode layer formed to cover the electrode layer and in contact with the oxide semiconductor layer; The drain electrode layer includes a first drain electrode layer in contact with the oxide semiconductor layer, and a second drain electrode layer A second drain electrode layer is formed to cover the oxide semiconductor layer and is in contact with the oxide semiconductor layer. Good too.

[0015] The source electrode layer includes a second source electrode layer in contact with the oxide semiconductor layer and a second source electrode layer. a first source electrode layer formed on the electrode layer and in contact with the oxide semiconductor layer; a second drain electrode layer in contact with the oxide semiconductor layer and a second drain electrode layer formed on the second drain electrode layer; In addition, a first drain electrode layer may be provided in contact with the oxide semiconductor layer.

[0016] Here, the first source electrode layer and the first drain electrode layer are made of Al, Cr, Cu, Ta, A second source electrode layer made of Ti, Mo, W, or an alloy material containing these as a main component. and the second drain electrode layer is a material containing tantalum nitride, titanium nitride, or ruthenium. It is preferable that the insulating layer is made of a material other than PTFE.

[0017] Another embodiment of the present invention is a substrate having an insulating surface, and a first oxide film formed on the substrate. a second oxide semiconductor layer formed on the first oxide semiconductor layer; A first source electrode layer and a first drain electrode layer formed on the oxide semiconductor layer, and a second oxide a third oxide layer formed on the oxide semiconductor layer, the first source electrode layer, and the first drain electrode layer; a second source electrode layer formed to cover the first source electrode layer; A second drain electrode layer is formed so as to cover the first drain electrode layer, and a third oxide semiconductor a gate insulating film formed on the semiconductor layer, the second source electrode layer, and the second drain electrode layer; a gate electrode layer formed on the gate insulating film, and a first source electrode layer and a first The drain electrode layer is in contact with the first to third oxide semiconductor layers and is The first oxide semiconductor layer is in contact with the second drain electrode layer and the second oxide semiconductor layer is in contact with the third oxide semiconductor layer. The conductor layer has a first region, the gate insulating film has a second region, and the thickness of the first region is T S 1. The thickness of the second region is T GI Then, T S1 ≧T GI A semiconductor device characterized in that It is a body device.

[0018] In the above structure, the first oxide semiconductor layer and the third oxide semiconductor layer are The vacuum level is reached when the energy of the conduction band minimum is in the range of 0.05 eV to 2 eV below the semiconductor layer. It is preferable that the value is close to .

[0019] The first to third oxide semiconductor layers are each formed of an In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and the first oxide semiconductor The oxide semiconductor layer and the third oxide semiconductor layer have an atomic ratio of M to In that is equal to or larger than that of the second oxide semiconductor layer. It is preferable that it is greater than .

[0020] The first source electrode layer and the first drain electrode layer are made of Al, Cr, Cu, Ta, T It is preferable that the material be i, Mo, W or an alloy material containing these as a main component.

[0021] The second source electrode layer and the second drain electrode layer are formed of tantalum nitride, titanium nitride, Alternatively, it is preferably formed of a material containing ruthenium. Effect of the Invention

[0022] By using one embodiment of the present invention, it is possible to suppress deterioration of electrical characteristics that becomes significant with miniaturization. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a highly reliable semiconductor device can be provided. It is possible to provide a semiconductor device in which the deterioration of the threshold voltage (subthreshold voltage) is reduced. In this way, it is possible to provide a semiconductor device in which the deterioration of the threshold voltage is reduced. It is possible to provide a semiconductor device with reduced channel. It is possible to provide a semiconductor device in which the capacitor is held. [Brief description of the drawings]

[0023] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 2] 1A to 1C are diagrams illustrating band structures of oxide semiconductor layers. [Diagram 3] FIG. 1 is an enlarged cross-sectional view of a transistor. [Figure 4] FIG. 1 is an enlarged cross-sectional view of a transistor. [Diagram 5] 1A and 1B are a top view and a cross-sectional view illustrating a transistor, and a diagram illustrating a band structure of an oxide semiconductor layer. [Figure 6] FIG. 1 is an enlarged cross-sectional view of a transistor. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating a model used in device simulation. [Figure 9]1A and 1B are a top view and a cross-sectional view illustrating a model used in device simulation. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating a model used in device simulation. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating a model used in device simulation. [Figure 12] FIG. 13 is a diagram for explaining the results of device simulation. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating a model used in device simulation. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a model used in device simulation. [Figure 15] FIG. 13 is a diagram for explaining the results of device simulation. [Figure 16] FIG. 13 is a diagram for explaining the results of device simulation. [Figure 17] FIG. 13 is a diagram for explaining the results of device simulation. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating a model used in device simulation. [Figure 19] FIG. 13 is a diagram for explaining the results of device simulation. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 22] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 23] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 24] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 25] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device. [Figure 26] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 27] FIG. 1 is a block diagram of a semiconductor device. [Figure 28] FIG. 1 is a circuit diagram illustrating a memory device. [Figure 29]4 is a timing chart illustrating the operation of the storage device. [Diagram 30] 1A to 1C are diagrams illustrating electronic devices to which a semiconductor device can be applied. [Diagram 31] 1A and 1B are cross-sectional views of a transistor illustrating shapes of a source electrode and a drain electrode. [Diagram 32] 1A and 1B are cross-sectional views of a transistor illustrating shapes of a source electrode and a drain electrode. [Diagram 33] FIG. 13 is a diagram for explaining the results of device simulation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The following explanations may be omitted.

[0025] In this specification, when it is explicitly stated that X and Y are connected, When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are This includes the case where X and Y are directly connected. Here, X and Y are objects (e.g. For example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc. In this case, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence, but may be applied to any other connection relationship shown in a drawing or a sentence. This also includes connections other than those shown in the text.

[0026] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. It has the function of switching between these modes.

[0027] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if

[0028] In addition, when it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (That is, there is another element or circuit between X and Y.) (i.e., there is a separate circuit between X and Y) and (i.e., X and Y are functionally connected). When X and Y are connected functionally through a gap, they are connected in a straight line. (When X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it does not simply mean that it is connected. "" is the same as if it were expressly stated that

[0029] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0030] In this specification and the like, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. An example of the substrate is a semiconductor substrate. Substrates (e.g. single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, plastic Includes stick substrate, metal substrate, stainless steel substrate, stainless steel foil Substrates with tungsten foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated substrates Examples of the substrate include a glass substrate, a paper containing a fibrous material, or a base film. Examples of glass include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of flexible substrates include polyethylene terephthalate (PET), polystyrene (PS), and polystyrene (PS). Polyethylene naphthalate (PEN) and polyethersulfone (PES) are typical examples of The materials used for the adhesive include flexible plastics, acrylics, and other synthetic resins with flexibility. Examples of suitable materials include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, Inorganic deposition films, paper, etc. In particular, semiconductor substrates, single crystal substrates, or SOI substrates By manufacturing transistors using a plate or the like, the characteristics, size, shape, etc. This allows the manufacture of small-sized transistors with low fluctuations and high current capability. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or High integration can be achieved.

[0031] Note that a transistor is formed using a certain substrate and then transferred to another substrate. However, the transistor may be disposed on another substrate. In addition to the substrate on which the above-mentioned transistors can be formed, the substrates include paper substrates, cellophane substrates, and the like. substrates made of natural fibers (silk, cotton, hemp), synthetic fibers (nylon, Polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon, regenerated The substrates used are made of synthetic polyester, leather, or rubber. This allows the formation of transistors with good characteristics and low power consumption. It is possible to manufacture devices that are less likely to break, heat resistant, lightweight, or thin.

[0032] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0033] 1A, 1B, 1C, and 1D are top views of a transistor of one embodiment of the present invention. Fig. 1(A) is a top view, and is a cross-sectional view taken along dashed line A1-A2 shown in Fig. 1(A). 1(B), the cross section along the dashed line A3-A4 is shown in FIG. 1(C), and the cross section along the dashed line A5-A6 is shown in FIG. 1(D). In the top view of FIG. 1(A), some elements are shown in order to clarify the drawing. The dashed line A1-A2 direction is the channel width direction, and the dashed line A5- The A6 direction may be referred to as the channel length direction.

[0034] The transistor 100 shown in FIGS. 1A, 1B, 1C, and 1D is formed on a substrate 110. and an oxide semiconductor layer 130 formed on the base insulating film 120. The source electrode layer 140 and the drain electrode layer 15 are formed on the oxide semiconductor layer 130. 0, and on the source electrode layer 140, the drain electrode layer 150 and the oxide semiconductor layer 130 A gate insulating film 160 is formed, and a gate electrode layer 1 is formed on the gate insulating film 160. 70. Also, an oxide insulating film is formed on the gate insulating film 160 and the gate electrode layer 170. The oxide insulating layer 180 may be formed. The oxide insulating layer 180 may be provided as necessary. , and further, another insulating layer may be formed on top of it.

[0035] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It is possible to use it.

[0036] The substrate 110 is not limited to being a simple support material, but may also be a substrate on which other devices such as transistors are formed. In this case, the gate electrode layer 170 of the transistor 100, the source electrode At least one of the layers 140 and the drain electrode layer 150 is electrically connected to the other devices described above. The input / output terminals may be electrically connected to each other.

[0037] The base insulating film 120 has a role of preventing the diffusion of impurities from the substrate 110 and also prevents oxidation. Since the insulating film contains oxygen, it can supply oxygen to the organic semiconductor layer 130. It is preferable that the insulating film contains excess oxygen, and more preferable that the insulating film contains excess oxygen. When the substrate 10 is a substrate on which other devices are formed, the base insulating film 120 serves as an interlayer insulating film. In this case, CMP (Chemical Mechanical Polishing) is used to make the surface flat. It is preferable to perform a planarization process by a method such as mechanical polishing.

[0038] The oxide semiconductor layer 130 is made up of a first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a The semiconductor device has a structure in which an oxide semiconductor layer 132 and a third oxide semiconductor layer 133 are stacked. Here, as an example, the second oxide semiconductor layer 132 includes a first oxide semiconductor layer 1 31 and the third oxide semiconductor layer 133, The electron affinity is determined by the relationship between the vacuum level and the top of the valence band. From the energy difference between the lower end of the conduction band and the upper end of the valence band (ionization potential), It can be calculated by subtracting the energy difference (energy gap).

[0039] In this embodiment, the oxide semiconductor layer 130 is a stack of three layers. However, the oxide semiconductor layer 130 may be one layer, two layers, or four or more layers. For example, a layer corresponding to the second oxide semiconductor layer 132 may be used. For example, a layer corresponding to the second oxide semiconductor layer 132 is used on the substrate 110 side, and a gate insulating film 1 A layer corresponding to the first oxide semiconductor layer 131 or the third oxide semiconductor layer 133 is provided on the 60 side. The structure to be used, or the first oxide semiconductor layer 131 or the third oxide semiconductor layer 132 on the substrate 110 side. A layer corresponding to the conductor layer 133 is used, and the second oxide semiconductor layer 132 is formed on the gate insulating film 160 side. In the case of four or more layers, for example, the present embodiment As described above, the second oxide semiconductor layer 132 is a first oxide semiconductor layer 131 or The insulating film 130 may have a structure in which the insulating film 130 is sandwiched between layers corresponding to the oxide semiconductor layer 133 of FIG.

[0040] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are The layer 132 includes one or more metal elements, and the energy of the conduction band minimum is, for example, The oxide semiconductor layer 132 has a refractive index of 0.05 eV, 0.07 eV, 0.1 eV, and 0.15 eV. and in the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV or less. It is preferable that the insulating film be formed using an oxide semiconductor having a temperature close to a vacuum level in the vicinity of the insulating film.

[0041] In such a structure, when an electric field is applied to the gate electrode layer 170, the oxide semiconductor layer 13 0, the second oxide semiconductor layer 132 has the smallest energy at the bottom of the conduction band. That is, a first oxide semiconductor layer 132 is formed between the second oxide semiconductor layer 132 and the gate insulating film 160. The third oxide semiconductor layer 133 is formed, and thus the channel of the transistor is connected to the gate. Therefore, the insulating film 160 can be prevented from contacting the insulating film 160.

[0042] The first oxide semiconductor layer 131 contains the metal element constituting the second oxide semiconductor layer 132. Since the second oxide semiconductor layer 132 and the first oxide semiconductor layer The interface state is unlikely to be formed at the interface of 131. The interface state may form a channel. Therefore, the threshold voltage of the transistor may vary. By providing the semiconductor layer 131, the variation in electrical characteristics such as the threshold voltage of the transistor can be reduced. This can reduce adhesion.

[0043] The third oxide semiconductor layer 133 contains the metal element constituting the second oxide semiconductor layer 132. Since the second oxide semiconductor layer 132 and the third oxide semiconductor layer Therefore, the third oxide semiconductor By providing the dielectric layer 133, the field effect mobility of the transistor can be increased. .

[0044] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 may contain, for example, Al, T The second oxide semiconductor layer 132 is made of one of i, Ga, Ge, Y, Zr, Sn, La, Ce, and Hf. A material having an atomic ratio higher than 1. The amount is 5 times or more, preferably 2 times or more, and more preferably 3 times or more. The above elements are oxygen and Since the bond is strong, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. That is, the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are It can be said that oxygen deficiency is less likely to occur in this layer than in the organic semiconductor layer 132.

[0045] Note that the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor The layer 133 is made of at least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr When the first oxide is an In-M-Zn oxide containing a metal such as In, Sn, La, Ce or Hf, The oxide semiconductor layer 131 is In:M:Zn=x1:y1:z1 [atomic ratio], and the second oxide The compound semiconductor layer 132 is In:M:Zn=x2:y2:z2 [atomic ratio], and the third oxide semiconductor The layer 133 is In:M:Zn=x 3: y 3: z3 [atomic ratio], y1 / x1 and It is preferable that y1 / x1 and y3 / x3 are greater than y2 / x2. 3 is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more, than y2 / x2. At this time, in the second oxide semiconductor layer 132, when y2 is equal to or larger than x2, However, if y2 is more than three times larger than x2, y2 must be less than three times x2, otherwise the field effect mobility of the transistor will be reduced. is preferred.

[0046] In addition, the In and M atoms of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 The ratio of the number of In is preferably 50 when the sum of In and M is 100 atomic %. atomic %, M is 50 atomic % or more, and more preferably In is 25 atomic % or more. % or more, and M is 75 atomic % or more. The atomic ratio of In and M is preferably 100 atomic % when the sum of In and M is 100 atomic %. Or preferably, In is 25 atomic % or more and M is less than 75 atomic %. In is 34 atomic % or more, and M is less than 66 atomic %.

[0047] The thickness of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 is 3 nm or more. The thickness of the second oxide semiconductor layer is preferably 3 nm to 50 nm. The thickness of 132 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably More preferably, it is 3 nm or more and 50 nm or less.

[0048] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor The layer 133 is made of, for example, an oxide semiconductor containing indium, zinc, and gallium. In particular, when the second oxide semiconductor layer 132 contains indium, the carrier This is preferred because it increases the mobility.

[0049] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, The present invention relates to a method for manufacturing an oxide semiconductor layer, comprising: reducing an impurity concentration in the oxide semiconductor layer to make the oxide semiconductor layer intrinsic or substantially intrinsic; Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is But 1×10 17 / cm 3 Preferably less than 1 × 10 15 / cm 3 is less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0050] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and carrier In addition, silicon forms an impurity level in the oxide semiconductor layer. The impurity levels become traps and may degrade the electrical characteristics of a transistor. Therefore, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132 and the third oxide semiconductor layer It is preferable to reduce the impurity concentration in the compound semiconductor layer 133 and at the interface between the layers. I wish.

[0051] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) In the case of oxide semiconductors, for example, The silicon concentration at a certain depth in the semiconductor layer or in a certain region of the oxide semiconductor layer is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 The fact that it has a portion that is less than In addition, the hydrogen concentration is preferably adjusted at a certain depth in the oxide semiconductor layer or at a certain concentration in the oxide semiconductor layer. In a certain region of the nitride semiconductor layer, 20 atoms / cm 3 Less than or equal to 5, preferably ×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below Lower, and more preferably 5×10 18 atoms / cm 3 The following parts are included: In addition, the nitrogen concentration is preferably, for example, at a certain depth in the oxide semiconductor layer or In a region of the oxide semiconductor layer, 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 It has the following parts: is preferred.

[0052] In addition, when the oxide semiconductor layer contains crystals and contains silicon or carbon at a high concentration, the oxide In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, For example, at a certain depth in the oxide semiconductor layer or in a certain region of the oxide semiconductor layer In this case, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than In addition, for example, at a certain depth of the oxide semiconductor layer, , the carbon concentration in a certain region of the oxide semiconductor layer is set to 1×10 19 atoms / cm 3 less than , preferably 5 x 10 18 atoms / cm 3 less than 1×10 18 at oms / cm 3 It is sufficient that the part is less than

[0053] In addition, a transistor using the purified oxide semiconductor layer as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small, and the off-state current normalized by the channel width of the transistor is several It is possible to reduce the radiation energy to yA / μm to several zA / μm. The voltage between the drain and the transistor is, for example, about 0.1V, 5V, or 10V.

[0054] In addition, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region of the oxide semiconductor layer that will become the channel must not be in contact with the gate insulating film. In addition, it is preferable that a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer. When a hole is formed, carrier scattering occurs at the interface, and the field effect mobility of the transistor decreases. From this viewpoint, the region of the oxide semiconductor layer that becomes the channel may be It is preferable to separate it from the gate insulating film.

[0055] Therefore, the oxide semiconductor layer 130 is divided into a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132. By using a stacked structure of the oxide semiconductor layer 132 and the third oxide semiconductor layer 133, The second oxide semiconductor layer 132 in which the hole is formed can be separated from the gate insulating film. It is possible to form a transistor having a field effect mobility and stable electrical characteristics.

[0056] Next, the band structure of the oxide semiconductor layer 130 will be described. The energy gallium nitride semiconductor layer 131 and the third oxide semiconductor layer 133 are layers corresponding to the energy gallium nitride semiconductor layer 131 and the third oxide semiconductor layer 133. The In-Ga-Zn oxide having a peak at 3.5 eV corresponds to the second oxide semiconductor layer 132. The In-Ga-Zn oxide layer has an energy gap of 3.15 eV. In this case, a stacked layer corresponding to the oxide semiconductor layer 130 is fabricated. The layers constituting the stack are called a first oxide semiconductor layer 131, In the following description, they will be referred to as a second oxide semiconductor layer 132 and a third oxide semiconductor layer 133.

[0057] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 13 The film thickness of each of the layers was set to 10 nm, and the energy gap was measured using a spectroscopic ellipsometer (HOR The measurements were performed using a IBA JOBIN YVON UT-300. The energy difference at the top of the valence band is measured by ultraviolet photoelectron spectroscopy (UPS). Photoelectron Spectroscopy (PHI Ver. Measurements were performed using saProbe.

[0058] Figure 2(A) shows the energy difference between the vacuum level and the top of the valence band, and the energy gap of each layer. Schematic from the energy difference between the vacuum level and the conduction band minimum (electron affinity) calculated as the difference FIG. 2A shows a part of a band structure of the first oxide semiconductor layer 131 and 13 is a band diagram in the case where a silicon oxide film is provided in contact with the third oxide semiconductor layer 133. FIG. Here, Ev is the energy of the vacuum level, EcI1 and EcI2 are the conductances of the silicon oxide film. EcS1 is the energy of the conduction band of the first oxide semiconductor layer 131. , EcS2 is the energy of the bottom of the conduction band of the second oxide semiconductor layer 132, and EcS3 is the energy of the third oxide semiconductor layer 133. This is the energy of the bottom of the conduction band of the oxide semiconductor layer 133. In this case, the gate electrode layer (corresponding to gate electrode layer 170 in transistor 100) has EcI2. The silicon oxide film is in contact with the silicon oxide film.

[0059] As shown in FIG. 2A, a first oxide semiconductor layer 131, a second oxide semiconductor layer 132, In the third oxide semiconductor layer 133, the energy of the conduction band minimum changes continuously. The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 are This can also be understood from the fact that the similar composition of the layers 133 facilitates mutual diffusion of oxygen. Therefore, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, the third oxide semiconductor layer Although the semiconductor layer 133 is a laminate of layers with different compositions, it is physically continuous. In the drawings of this specification, the interfaces of the laminate are represented by dotted lines.

[0060] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, a U-shaped junction in which the energy of the conduction band edge changes continuously between layers) The layers are fabricated so that a well structure (U Shape Well) is formed. There are no impurities at the interface that would form defect levels such as trap centers or recombination centers. If impurities are mixed between the stacked oxide semiconductor layers, When the interface is in a non-uniform state, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. It will disappear when combined.

[0061] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. It is necessary to use a sputtering device to stack each layer in succession without exposing them to the air. Each chamber in the sputtering device is designed to remove impurities such as water that can be harmful to oxide semiconductors. In order to remove as much as possible, a high-purity vacuum pump such as a cryopump is used. Empty exhaust (1×10 -4Pa~5×10 -7 Pa) and the film can be formed. It is preferable that the substrate can be heated to 100° C. or higher, preferably 500° C. or higher. A combination of a molecular pump and a cold trap is used to extract carbon components and other substances from the exhaust system into the chamber. It is preferable to prevent gas containing moisture and the like from flowing backward.

[0062] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of the sputtering gas. , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using a highly purified gas, moisture or the like is prevented from being taken into the oxide semiconductor layer as much as possible. This can be prevented.

[0063] In FIG. 2(A), the case where EcS1 and EcS3 are the same is shown. For example, if EcS1 has a higher energy than EcS3, In this case, a part of the band structure is shown in FIG. 2(B).

[0064] For example, when EcS1=EcS3, the first oxide semiconductor layer 131 and the third oxide semiconductor layer The compound semiconductor layer 133 has a composition of In:Ga:Zn=1:3:2, 1:6:4 or 1:9:6 ( The second oxide semiconductor layer 132 has a composition ratio of In:Ga:Zn=1:1:1 or 3:1: In-Ga-Zn oxide with an atomic ratio of 2 can be used. In the case of EcS3, the first oxide semiconductor layer 131 has a composition of In:Ga:Zn=1:6:4 or less. or 1:9:6 (atomic ratio), and the second oxide semiconductor layer 132 has In:Ga:Zn=1:1 Zn:Ga:Zn=3:1 or 3:1:2 (atomic ratio), and the third oxide semiconductor layer 133 An In-Ga-Zn oxide having an atomic ratio of 1:3:2 can be used.

[0065] 2A and 2B, the second oxide semiconductor layer 132 in the oxide semiconductor layer 130 This serves as a well, and in a transistor using the oxide semiconductor layer 130, It can be seen that the oxide semiconductor layer 130 is formed in the second oxide semiconductor layer 132. Since the energy of the conduction band edge changes continuously, it can also be called a U-shaped well. A channel formed in this manner can also be called a buried channel. .

[0066] Note that the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are made of silicon oxide. Trap levels due to impurities and defects can be formed near the interface with an insulating film such as a silicon film. The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are provided. 2 and the trap level. When the energy difference between S1 or EcS3 and EcS2 is small, the second oxide semiconductor layer An electron of 132 can cross the energy difference and reach the trap level. When electrons are trapped in the insulating film, a negative charge is generated at the interface of the insulating film, causing the transistor threshold voltage to rise. The voltage value is shifted in the positive direction.

[0067] Therefore, the energy difference between EcS1 and EcS3 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the change in the threshold voltage of the transistor This reduces the vibration and provides stable electrical characteristics.

[0068] Note that the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer It is preferable that one or more layers of the conductor layer 133 include a crystalline portion. For example, The first oxide semiconductor layer 131 is amorphous, and the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 are amorphous. The second oxide semiconductor layer 133 is a layer including a crystal portion. The conductive layer 132 includes a crystalline portion, which provides the transistor with stable electrical characteristics. This can be done.

[0069] In particular, the crystal parts included in the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 It is preferable that the crystal has a c-axis oriented in a direction substantially perpendicular to the surface.

[0070] In the transistor having the structure shown in FIG. 1, the third oxide semiconductor layer 133 serves as a source electrode layer. 140 and the drain electrode layer 150. It is preferable that the gap is not as large as that of an insulator, and that the film thickness is thin. When an In-Ga-Zn oxide is used for the oxide semiconductor layer 130, the In gate insulating film In order to prevent the diffusion of the oxide semiconductor layer 132, the third oxide semiconductor layer 133 is It is preferable to have a composition with a small amount of In.

[0071] In order to fabricate a semiconductor device with low power consumption, it is necessary to reduce the off-state current of a transistor, particularly when the gate voltage is 0 It is effective to reduce the current (also called Icut) at V. When a transistor is miniaturized, the threshold voltage, S value (subthreshold value), and other It is known that the electrical characteristics of the device deteriorate when the temperature is increased, and it is therefore desirable to achieve both miniaturization and low power consumption. Ta.

[0072] In the transistor of one embodiment of the present invention, as shown in the enlarged cross-sectional view of FIG. The thickness of the first region, which is a part of the oxide semiconductor layer 131, is T S1 , the gate insulating film 160 The thickness of the second region is T GI Then, T S1 ≧T GI (T S1 is T GI End In this way, the gate electrode layer 170 is formed on the gate insulating film 160. The side surface of the second oxide semiconductor layer 132 is covered through the insulating film 134.

[0073] The second oxide semiconductor layer 132 is a layer in which a channel is formed. By providing a structure in which an electric field can be easily applied from the gate electrode layer 170 to the side surface of the second An electric field is applied to the entire oxide semiconductor layer 132 of the transistor. The threshold voltage and S value can be improved. This is particularly effective when the length is short, so Icut can be reduced even when the transistor is miniaturized. This allows for a reduction in power consumption. In addition, the threshold voltage of the transistor is stable. This can improve the long-term reliability of the semiconductor device.

[0074] In addition, in the transistor of one embodiment of the present invention, as shown in a top view of the transistor in FIG. As shown in FIG. 1, the length of the source electrode layer 140 and the drain electrode layer 150 in the channel width direction is The length of the oxide semiconductor layer 130 in the channel width direction is shorter than the length of the oxide semiconductor layer 130 in the channel width direction. It is preferable to form the gate so as to cover the end portion in the longitudinal direction. The obstacle to the application of an electric field from the second electrode layer 170 to the side surface of the second oxide semiconductor layer 132 is reduced. In order to reduce S1 ≧T GI By improving the threshold voltage and S value of the transistor This can enhance the effect of

[0075] As shown in an enlarged cross-sectional view of a transistor in FIG. 4A (a part of a cross section in the channel length direction), As shown in FIG. 1, a region 134 having a curved surface may be provided at an end portion of the oxide semiconductor layer 130. The conductor layer 130 is an In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Zr, La, Ce, When the second oxide semiconductor layer 132 is made of Nd or Hf, the M (M S2 ) and M(M S4 The quantitative relationship between S4 >M S2 It is preferable that More preferably, M S4 is M (M S1 ) With such a structure, the second oxide semiconductor layer 132 can be protected. It is possible.

[0076] The region 134 at the end of the oxide semiconductor layer 130 is etched by a dry etching method to remove the first oxide The composition of the semiconductor layer 131 is redeposited, that is, the so-called rabbit ear is used to form the layer. Furthermore, the oxidation process removes the etching gas components that adhere to the rabbit ear during the formation of the ear. By removing the M component and oxidizing the M component, the insulating properties of the region 134 can be improved.

[0077] In addition, an end portion of the oxide semiconductor layer 130 overlapping with the gate electrode layer is oxidized by impurities due to an external factor. It is easy for the material to become n-type due to contamination or oxygen vacancies, and this can lead to parasitic channels. The second oxide semiconductor layer 132 having a small energy gap is easily converted to an n-type. Therefore, the enlarged cross-sectional view of the transistor shown in FIG. By forming the region 134 as shown in FIG. 1, the occurrence of a parasitic channel can be suppressed. This can be done.

[0078] FIG. 5A is a top view of a transistor including a region 134 and an oxide semiconductor layer 130. When the main components of the first oxide semiconductor layer 131 and the region 134 are the same, The energy of the conduction band minimum of the oxide semiconductor layer 132 (EcS2) and the conduction band The larger the difference (ΔE) in the lower-end energy (EcS4), the more the occurrence of parasitic channels is suppressed. The thickness of the region 134 is preferably 100% or more than that of the first oxide semiconductor layer 131 or the third oxide semiconductor layer 132. It is preferable that the thickness of the second oxide semiconductor layer 132 is thicker than that of the second oxide semiconductor layer 133. This can suppress the occurrence of parasitic channels caused by the n-type transistor.

[0079] The region 134 includes the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, the third oxide semiconductor layer 133, and the third oxide semiconductor layer 134. Since the composition of the oxide semiconductor layer 133 is similar to that of the oxide semiconductor layer 132, the band structure of the oxide semiconductor layer 132 is uniform. As shown in Fig. 5(B), the energy of the conduction band minimum changes continuously. A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 133 The region 134 can be said to be a continuous junction. -D2 is in the dashed line D1-D2 direction shown in the cross-sectional view of the oxide semiconductor layer 130 in FIG. 5B corresponds to the direction of the dashed line E1-E2 in FIG. 5A. do.

[0080] The source electrode layer 140 and the drain electrode layer 150 are made of a conductive material that easily bonds with oxygen. For example, it is preferable to use Al, Cr, Cu, Ta, Ti, Mo, W, etc. Among the above materials, Ti, which is particularly prone to bonding with oxygen, and It is more preferable to use W, which has a high melting point, because it can be bonded to oxygen. The easily conductive materials also include materials through which oxygen easily diffuses.

[0081] When a conductive material that easily bonds with oxygen is brought into contact with an oxide semiconductor layer, the oxygen in the oxide semiconductor layer The phenomenon occurs whereby oxygen diffuses into the conductive material, which is more likely to bond with oxygen. This phenomenon becomes more pronounced as the temperature increases. The manufacturing process of a transistor involves several heating steps, so the above phenomenon Due to this, a region of the oxide semiconductor layer in contact with the source electrode layer or the drain electrode layer and in the vicinity of the region is Oxygen vacancies occur and the region becomes n-type. Therefore, the n-type region becomes a transistor. The MOS transistor can act as a source or drain of a transistor.

[0082] The n-type region is shown in the enlarged cross-sectional view (cross-section in the channel length direction) of the transistor in FIG. The boundary 135 indicated by the dotted line in the oxide semiconductor layer 130 is the boundary between the intrinsic semiconductor region and the n-type The boundary between the semiconductor regions is the source electrode layer 140 or the drain electrode layer 140 in the oxide semiconductor layer 130. The region in contact with the in-electrode layer 150 is an n-type region. This is a schematic representation and may not be clear in practice. 5 is positioned so as to extend laterally in the second oxide semiconductor layer 132. However, the boundary 135 is in the first oxide semiconductor layer 131 or the third oxide semiconductor layer 13 3, the source of the oxide semiconductor layer 130 may be located so as to extend in the lateral direction. A film in a region sandwiched between the electrode layer 140 or the drain electrode layer 150 and the base insulating film 120 The entire thickness direction may become n-type.

[0083] However, when forming a transistor with a very short channel length, the occurrence of the oxygen vacancies is As a result, the n-type region may extend in the channel length direction of the transistor. In this case, the electrical characteristics of the transistor include the shift in threshold voltage and the on / off switching with gate voltage. An uncontrollable state (conducting state) appears. This is why transistors with extremely short channel lengths In the case of forming a source electrode layer and a drain electrode layer, a conductive material that easily bonds with oxygen is used. It is not necessarily desirable for

[0084] Therefore, a transistor such as transistor 200 shown in FIGS. The source electrode layer and the drain electrode layer may be stacked. 7(A) is a cross section taken along the dashed line B1-B2 in FIG. 7(B), and the cross section taken along the dashed line B3-B4 in FIG. The cross section corresponds to FIG. 7(C), and the cross section along the dashed line B5-B6 corresponds to FIG. 7(D). The B1-B2 direction is called the channel width direction, and the dashed line B5-B6 direction is called the channel length direction. There are cases.

[0085] The first source electrode layer 141 and the first drain electrode layer 151 are formed of the titanium film described above. The second source electrode layer 142 and the second drain electrode layer 152 are used to define the channel length. A conductive material that does not easily bond with oxygen is used for the conductive material. It is preferable to use a material containing titanium, titanium nitride, or ruthenium. Conductive materials that are difficult to bond with oxygen also include materials through which oxygen is difficult to diffuse.

[0086] In the transistor having the structure shown in FIG. 7, the channel length is the distance from the second source electrode layer 142 and the second drain electrode layer 152.

[0087] In the transistor having the structure of FIG. 7, the channel is a region between the second source electrode layer 142 and This refers to the second oxide semiconductor layer 132 between the second drain electrode layers 152.

[0088] In the transistor having the structure of FIG. 7, the channel forming region is the second source electrode layer The first oxide semiconductor layer 131 between the first drain electrode layer 142 and the second drain electrode layer 152 The oxide semiconductor layer 132 and the third oxide semiconductor layer 133 are referred to as the oxide semiconductor layer 132 and the third oxide semiconductor layer 133.

[0089] The conductive material that is difficult to bond with oxygen is formed on the second source electrode layer 142 and the second drain electrode By using the layer 152, a channel formation region formed in the oxide semiconductor layer 130 can be formed. It is possible to suppress the formation of oxygen vacancies, and to suppress the channel from becoming n-type. Therefore, even a transistor with a very short channel length can have good electrical characteristics. can be done.

[0090] The source electrode layer and the drain electrode layer are formed only from the conductive material that is difficult to bond with oxygen. Then, the contact resistance with the oxide semiconductor layer 130 becomes too high, and As shown in FIG. 1, the first source electrode layer 141 and the first drain electrode layer 151 are formed of an oxide A first source electrode layer 141 and a first drain electrode layer 15 are formed on the semiconductor layer 130. A second source electrode layer 142 and a second drain electrode layer 152 are formed to cover the first electrode layer 1. It is preferred.

[0091] At this time, the first source electrode layer 141, the first drain electrode layer 151, and the oxide semiconductor The second source electrode layer 142 and the second drain electrode layer 130 are formed with a large contact area. It is preferable that the contact area between the layer 152 and the oxide semiconductor layer 130 is small. A region where the electrode layer 141 and the first drain electrode layer 151 contact the oxide semiconductor layer 130 The first source becomes an n-type region due to the generation of oxygen vacancies. The contacts between the first drain electrode layer 141 and the oxide semiconductor layer 130 and the first drain electrode layer 151 are Therefore, the resistance of the first source electrode layer 141 and the first drain electrode layer 142 can be reduced. By increasing the contact area between the n-type electrode layer 151 and the oxide semiconductor layer 130, The area can also be made large.

[0092] However, the second source electrode layer 142 and the second drain electrode layer 152 may be made of tantalum nitride or This is not the case when using nitrides such as titanium nitride. The nitrogen diffuses slightly to the vicinity of the interface with the oxide semiconductor layer 130, and nitrogen acts as a donor in the oxide semiconductor layer 130. This acts to form an n-type region and reduce the contact resistance.

[0093] Here, the distance between the first source electrode layer 141 and the first drain electrode layer 151 is 0.8 μm. The interval is set to 1.0 μm or more, preferably 1.0 μm or more. If the interval is less than 0.8 μm, the channel The effect of oxygen vacancies occurring in the formation region cannot be eliminated, and the electrical characteristics of the transistor deteriorate. will decrease.

[0094] On the other hand, the distance between the second source electrode layer 142 and the second drain electrode layer 152 is, for example, 3 Even if the thickness is 0 nm or less, good electrical characteristics can be obtained.

[0095] In addition, the parasitic capacitance between the gate and drain and between the gate and source is reduced, and the In order to improve frequency characteristics, the gate electrode layer and the source electrode layer or the drain electrode layer are It is preferable to have a structure that does not cause a heavy load.

[0096] In addition, the ends of the source electrode layer 140 and the drain electrode layer 150 of the transistor 100 Ends of the first source electrode layer 141 and the first drain electrode layer 151 of the transistor 200 It is preferable that the step-like shape is provided with a plurality of steps. By forming the shape of the junction, the coverage of the film formed above the junction is improved, and the electrical properties of the transistor are improved. The characteristics and long-term reliability can be improved. 31(B), the source electrode layer 140 and the drain electrode layer 142 are formed as in the transistor 202 shown in FIG. The end of the in-electrode layer 150, or the first source electrode layer 141 and the first drain electrode layer The end portion of 151 may have a shape that does not include the stepped steps.

[0097] The gate insulating film 160 may be formed of aluminum oxide, magnesium oxide, silicon oxide, or nitride oxide. Silicon oxide, silicon nitride, silicon oxide, gallium oxide, germanium oxide, Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and The insulating film 160 may be made of a material containing at least one type of tantalum oxide. It may also be a laminate of the above materials.

[0098] The gate electrode layer 170 is made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, A conductive film such as Ag, Ta, and W can be used. It may also be a laminate of the above materials.

[0099] An oxide insulating layer 180 is formed on the gate insulating film 160 and the gate electrode layer 170. The oxide insulating layer 180 may include aluminum oxide, magnesium oxide, or Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, gallium oxide Rumanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium and tantalum oxide can be used. The oxide insulating layer 180 may be a stack of the above materials.

[0100] Here, the oxide insulating layer 180 preferably contains excess oxygen. The insulating layer refers to an oxide insulating layer that can release oxygen by heat treatment or the like. Preferably, the amount of oxygen released, calculated as oxygen atoms, is 1.0x or more by thermal desorption spectroscopy. 10 19 atoms / cm 3 The oxide insulating layer 180 is a film having the above structure. The oxygen diffuses through the gate insulating film 160 into the channel formation region of the oxide semiconductor layer 130. Therefore, oxygen can be supplied to compensate for oxygen vacancies that have been unintentionally formed. Therefore, stable electrical characteristics of the transistor can be obtained.

[0101] The above is a transistor according to one embodiment of the present invention. As a result, a semiconductor device with high long-term reliability can be provided.

[0102] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0103] (Embodiment 2) In this embodiment, the structure of the transistor according to one embodiment of the present invention described in Embodiment 1 will be described. The results of the simulation will be explained below.

[0104] Figure 8(A), (B), (C), (D), Figure 9(A), (B), (C), (D), Figure 10( A), (B), (C), (D), Figure 11 (A), (B), (C), (D) are the first stains. FIG. 8(A) is a top view of the device model used in the simulation. The cross section of the dashed line H1-H2 shown in FIG. 8(A) is FIG. 8(B), and the cross section of the dashed line H3-H4 shown in FIG. FIG. 8(C) and the cross section taken along the dashed line H5-H6 correspond to FIG. 8(D). 9(A) is a cross-sectional view taken along the dashed line J1-J2 in FIG. 9(B), and the cross-sectional view taken along the dashed line J3- The cross section of J4 corresponds to FIG. 9(C), and the cross section of the dashed line J5-J6 corresponds to FIG. 9(D). 10(A) is a top view, and the cross section taken along the dashed line K1-K2 shown in FIG. 10(A) is shown in FIG. ), the cross section along the dashed line K3-K4 is shown in FIG. 10(C), and the cross section along the dashed line K5-K6 is shown in FIG. 10(D 11A is a top view, and the dashed line M1- The cross section of M2 is shown in FIG. 11(B), the cross section of the dashed line M3-M4 is shown in FIG. 11(C), and the cross section of the dashed line M5- The cross section of M6 corresponds to FIG. 11(D). K2, M1-M2 direction is the channel width direction, dashed lines H5-H6, J5-J6, K5-K6 The M5-M6 direction may be referred to as the channel length direction.

[0105] Device model 1 (DM1) shown in Fig. 8(A), (B), (C), and (D) is a A first oxide semiconductor layer 531, a second oxide semiconductor layer 532, a third oxide semiconductor layer 533, and a third oxide semiconductor layer 534 are formed on an insulating film 520. The oxide semiconductor layer 530 is made of an oxide semiconductor layer 533, a source electrode layer 540, and a drain electrode The gate electrode layer 570 is a gate insulating film 560. 0 covers the end portion of the oxide semiconductor layer 530 in the channel width direction.

[0106] In DM1, the transistor channel length L is 30 nm, the channel width W is 40 nm, and the oxide The semiconductor layer 530 and the source electrode layer 540 or the drain electrode layer 550 are arranged in the channel length direction. The overlap length is 30 nm, the thickness of the base insulating film 520 is 300 nm, and the ratio of the gate insulating film 560 is The dielectric constant is 4.1, the film thickness is 20 nm, the work function of the gate electrode layer is 4.9 eV, and the source electrode layer is The work function of the first oxide layer 540 and the drain electrode layer 550 was set to 4.4 eV. A semiconductor layer 531 (S1), a second oxide semiconductor layer 532 (S2), and a third oxide semiconductor layer The atomic ratio (In:Ga:Zn) of the In-Ga-Zn oxide used as 533(S3) and The values ​​used in the simulation are shown in Table 1. The Sentaurus Device manufactured by Synopsys was used for the FET. The existence of fixed charges and electron traps localized in the lattice is not assumed.

[0107] [Table 1]

[0108] Device model 2 (DM2) shown in Fig. 9(A), (B), (C), and (D) is a DM 1 and the gate electrode layer 570 have a different shape. That is, the top surface shape is the same as that of the oxide semiconductor layer 530. Other conditions were the same as those for DM1.

[0109] Device model 3 (DM3) shown in Fig. 10(A), (B), (C), and (D) is an acid The compound semiconductor layer 580 is a single layer having the same conditions as those of S2 shown in Table 1, and the other conditions are the same as those of DM1. (The gate electrode layer 570 covers the end of the oxide semiconductor layer 530 in the channel width direction.) ).

[0110] Device model 4 (DM4) shown in Fig. 11(A), (B), (C), and (D) is an acid The compound semiconductor layer 580 is a single layer having the same conditions as those of S2 shown in Table 1, and the other conditions are the same as those of DM2. (The gate electrode layer 570 does not cover the end portion of the oxide semiconductor layer 530 in the channel width direction. (Configuration).

[0111] Figure 12 (A) and (B) show the device models (DM1, DM2, DM3, DM4) under the above conditions. The Id-Vg characteristics obtained by simulation using

[0112] First, in a comparison between DM1 and DM2, in which the oxide semiconductor layer has a stacked structure, Characteristics of DM1 in which DM1 has a structure in which the end of the oxide semiconductor layer 530 is covered in the channel width direction In addition, the oxide semiconductor layer in the DM3 In comparison between DM4 and DM5, the gate electrode layer 570 is located closer to the oxide semiconductor layer 58 in the channel width direction. The characteristics of DM3, which has a configuration covering the end of 0, were good (see FIG. 12(B)). In comparing DM1 and DM3, DM1 has better S value and threshold voltage. Therefore, in order to reduce Icut, the structure of DM1, i.e., oxidation The oxide semiconductor layer has a laminated structure, and the gate electrode layer is formed of an oxide semiconductor layer in the channel width direction. It can be said that a configuration in which the ends are covered is advantageous.

[0113] This is because a part of the first oxide semiconductor layer 531 and the gate insulating film 560 in the DM1 This is because the thicknesses of the oxide semiconductor layer 530 and the oxide semiconductor layer 530 are set to be the same. In the second oxide semiconductor layer 532, the relative position of the second oxide semiconductor layer 532 in which a channel is formed is increased. The end of the second oxide semiconductor layer 532 is covered with a gate electrode layer 570 via a gate insulating film 560. Therefore, the electric field from the gate electrode layer 570 is not applied to the entire second oxide semiconductor layer 532. On the other hand, in DM2, DM3, and DM4, the oxide semiconductor layers 530 and 5 The end of the gate electrode 80 is not covered with the gate electrode layer 570 via the gate insulating film 560. Therefore, both of them have insufficient Id-Vg characteristics.

[0114] Therefore, from the first simulation result, it is considered that the oxide semiconductor layer has a stacked structure, and the stacked structure The relative position of the layer that becomes the channel in the layer structure is raised, and It is effective to configure the layer so that an electric field can be easily applied from the gate electrode layer laterally. Specifically, in a part of the layer located below the layer that becomes the channel, The thickness of the insulating film is set to be equal to or larger than the thickness of a part of the gate insulating film, and the insulating film is set to cover the end of the oxide semiconductor layer. The gate electrode layer may be formed as shown in FIG.

[0115] Figures 13(A), (B), (C), (D), and Figures 14(A), (B), (C), (D) are the first FIG. 13(A) is a diagram illustrating a device model used in the simulation of 2. 13(A) is a cross section taken along the dashed line N1-N2 in FIG. 13(B), and the cross section taken along the dashed line N3 in FIG. The cross section of the line N5-N6 corresponds to FIG. 13(D). 14(A) is a top view, and the cross section taken along the dashed line P1-P2 shown in FIG. 4(B), the cross section along the dashed line P3-P4 is shown in FIG. 14(C), and the cross section along the dashed line P5-P6 is shown in FIG. 4(D). The dashed lines N1-N2 and P1-P2 correspond to the channel width direction, The directions of the dotted lines N5-N6 and P5-P6 may be referred to as the channel length direction.

[0116] Device model 5 (DM5) shown in Fig. 13(A), (B), (C), and (D) is D M1 and the source electrode layer 540 or the drain electrode layer 550 have different shapes. 40 or the drain electrode layer 550 covers the end of the oxide semiconductor layer 530 in the channel length direction. The other conditions are the same as DM1.

[0117] Device model 6 (DM6) shown in Fig. 14(A), (B), (C), and (D) is M1 and the source electrode layer 540 or the drain electrode layer 550 have different shapes. 40 or the drain electrode layer 550 is disposed at the end of the oxide semiconductor layer 530 in the channel length direction and The structure covers part of the end in the channel width direction. Other conditions are the same as DM1. That is, in DM5 and DM6, the source electrode layer 540 or the drain electrode layer 550 is The difference is whether or not a part of the end in the channel width direction is covered.

[0118] Figure 15 shows the results of a simulation using the device models (DM1, DM5, and DM6) under the above conditions. The Id-Vg characteristics obtained by the above experiment are shown in Fig. 15. The source electrode layer 540 or the drain electrode layer 550 is disposed in the channel width direction of the oxide semiconductor layer 530. The characteristics of DM5, which does not cover the end of the DM1, were better than those of DM1. Although the threshold voltage is slightly on the negative side compared to the conventional MOSFET, the S value is the same and a high on-current is achieved. Therefore, if the aim is to improve characteristics including the on-current, the DM5 In other words, the source electrode layer or the drain electrode layer is disposed in the channel length direction of the oxide semiconductor layer. It is preferable that the end portions in the channel width direction are covered, but the end portions in the channel width direction are not covered.

[0119] This is because the end of the oxide semiconductor layer 530 in the channel width direction is connected to the source electrode layer 540 or the drain electrode layer 540. By covering the gate electrode layer 570 with the in-electrode layer 550, a part of the electric field from the gate electrode layer 570 is blocked, The oxide semiconductor layer 530, particularly the second oxide semiconductor layer 532 in which a channel is formed, is This is because it becomes difficult to apply a magnetic field.

[0120] Therefore, from the second simulation result, it is considered that the oxide semiconductor layer has a stacked structure and the channel It is effective to have a structure that does not prevent the application of an electric field from the gate electrode layer to the layer that becomes the gate. Specifically, the source electrode layer or the drain electrode layer is a channel of the oxide semiconductor layer. The end portions in the channel length direction may be covered, and the end portions in the channel width direction may not be covered. The length of the source electrode layer or the drain electrode layer in the channel width direction is equal to the channel width of the oxide semiconductor layer. It can also be said that the configuration is such that the length in the direction is equal to or smaller than that in the direction.

[0121] Next, using a device model based on the DM5 configuration, we performed a calculation of the W length of the transistor. The third simulation was performed. In the device model of the third simulation, , the length of the oxide semiconductor layer 530 in the channel width direction and the source electrode layer or the drain electrode The lengths of the pole layers in the channel width direction were made equal to each other, and the length was defined as W length. Then, W= The simulation conditions were 300nm, 40nm, 30nm, and 10nm. The conditions are the same as for DM5.

[0122] Figure 16 shows the Id-V curve obtained by simulation using the device model under the above conditions. When the W length is 300 nm, the off characteristic is very poor, but when the W length is 40 nm or less It can be seen that the S value is improved significantly by doing so.

[0123] This is because the second oxide semiconductor layer 532 is formed in a region where a channel is to be formed. This is because the contribution of the electric field applied from the side surface of the compound semiconductor layer 532 increases as the W length decreases. 33(A) and (B) are cross sections in the channel width direction of the DM5 corresponding to FIG. 13(B). 1 is a schematic vector representation of the electric field strength received by the second oxide semiconductor layer 532 from the lateral direction. As shown in FIG. 33A, when the W length is small, the second oxide semiconductor layer 53 The electric field applied laterally to 2 extends across the entire channel, but as shown in FIG. However, when the W length is long, the electric field does not reach the entire channel. It can be said that the effect of reducing the width is more effective for transistors with smaller W lengths.

[0124] Next, using a device model based on the configuration of DM5, A fourth simulation was performed regarding the thickness of the second oxide semiconductor layer 532. In the simulation of 4, the first The simulation conditions were such that the thickness of the oxide semiconductor layer 532 in the second embodiment was 5 nm to 90 nm. In the device model with L / W=30nm / 300nm, the second oxide The simulation conditions were such that the thickness of the semiconductor layer 532 was 5 nm to 50 nm. Other conditions were the same as DM5.

[0125] Figures 17(A), (B), and (C) show simulation results using a device model under the above conditions. The Id-Vg characteristics were obtained by L / W=30 nm / 4. The simulation results of the Id-Vg characteristics in the 0 nm device model are shown in Fig. 17. In FIG. 1A, the thickness of the second oxide semiconductor layer 532 is 5 nm, 10 nm, 15 nm, 20 nm, The results for 25 nm, 30 nm, 40 nm, and 50 nm are shown, and the second oxide film is shown in FIG. The results are shown for the thicknesses of the conductor layer 532 of 60 nm, 70 nm, 80 nm, and 90 nm. FIG. 17(C) shows the Id-V curve for a device model with L / W=30 nm / 300 nm. 10 is a simulation result of g characteristics when the thickness of the second oxide semiconductor layer 532 is 5 nm and Results shown are 0nm, 15nm, 20nm, 25nm, 30nm, 40nm, and 50nm. In each figure, the film thickness increases gradually from the start point of the arrow to the end point of the arrow. It is as follows.

[0126] As shown in FIG. 17(A), in a device model with L / W=30 nm / 40 nm, The S value and the θ value of the second oxide semiconductor layer 532 are decreased as the thickness of the second oxide semiconductor layer 532 increases up to about 50 nm. As a result, the on-current was improved. As shown in FIG. 17(B), When the thickness of the nitride semiconductor layer 532 is 60 nm or more, the S value and the threshold voltage hardly change. Only the on-current tended to increase with increasing film thickness.

[0127] On the other hand, as shown in FIG. 17(C), the device model with L / W=30 nm / 300 nm In the above, the thickness of the second oxide semiconductor layer 532 is in the range of 5 nm to 50 nm. However, the S value and threshold voltage did not improve, and their dependence on the film thickness was This is the opposite trend to the 40nm device model.

[0128] This is because the thicker the second oxide semiconductor layer 532 is, the larger the area of ​​the side surface becomes. An electric field is easily applied from the gate electrode layer 570 to the entire oxide semiconductor layer 532. On the other hand, when the W length is long, the second oxide The electric field applied from the gate electrode layer 570 to the side of the oxide semiconductor layer 532 Since the Id-Vg characteristic is improved, the Id-Vg characteristic is improved. do not.

[0129] Therefore, by making the W length extremely short and increasing the thickness of the second oxide semiconductor layer 532, Therefore, the DM5 structure is a fin-type transistor structure (with an oxide semiconductor layer It can be said that this method is also suitable for making the film thickness of 530 > W length, and the on-state current that accompanies miniaturization It is also effective in preventing a decrease in flow.

[0130] Next, we compared a device model in which the active layer of a transistor is made of oxide semiconductor (OS) and a device model in which the active layer is made of silicon ( The fifth simulation was a comparison of the device models in which the active layer is Si. The device model 7 (DM7) to be reconstructed is shown in Fig. 18(A), (B), (C), and (D). As shown in Fig. 1D, the silicon active layer 630 is n + type region 632, p - The structure has a mold region 631. Here, n + The donor impurity density (N D ) at 1E20 / cm 3 Let p - The acceptor impurity density (N A ) to 1E1 7 / cm 3 , 1E18 / cm 3 , 1E19 / cm 3 Simulation was carried out as follows.

[0131] Figure 19 shows the Id For comparison, the D The Id-Vg characteristics of M5 are shown.

[0132] In DM7, N A When is relatively small, the off characteristic is very poor and the on / off ratio is almost the same. In addition, N A When is relatively large, the on / off ratio can be obtained. However, the off-state current was not reduced sufficiently compared to DM5.

[0133] From the first to fifth simulation results described in the present embodiment, it is clear that the active layer is The layer structure is a stack of semiconductor layers, and the layer structure is a layer of an intermediate layer that serves as a channel. The opposing position is raised so that an electric field can be easily applied from the side of the intermediate layer to the gate electrode layer. The source electrode layer or the drain electrode layer does not cover the end portion of the active layer in the channel width direction. In addition, the transistor can be formed in such a structure that the electric field applied from the gate electrode layer to the active layer is not blocked. It was found that this is significant for improving the characteristics of the It is also clear that making the channel smaller and thickening the intermediate layer are effective. Therefore, the semiconductor device according to one embodiment of the present invention described in another embodiment Even though it has a fine structure, it has good electrical properties and is highly reliable.

[0134] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0135] (Embodiment 3) In this embodiment, a transistor having a structure different from that of the transistor described in the first embodiment is used. This article explains:

[0136] 20A, 20B, 20C, and 20D are top views and diagrams of a transistor of one embodiment of the present invention. 20(A) is a top view, and the dashed line C1-C2 shown in FIG. The cross section of the dashed line C3-C4 is shown in FIG. 20(C), the cross section of the dashed line C5-C6 is shown in FIG. The cross section of FIG. 20(D) corresponds to FIG. 20(A). In addition, the direction of the dashed line C1-C2 is the channel width direction, The direction of the dashed dotted line C5-C6 may be referred to as the channel length direction.

[0137] The transistor 300 shown in FIGS. 20(A), (B), (C), and (D) is formed on a substrate 110. and an oxide semiconductor layer 130 formed on the base insulating film 120. A second source electrode layer 142 and a second drain electrode layer 143 are formed on the oxide semiconductor layer 130. the second source electrode layer 142 and the second drain electrode layer 152 A first source electrode layer 141 and a first drain electrode layer 15 are formed on each of the 1, the first source electrode layer 141, the second source electrode layer 142, the first drain electrode A gate insulating film is formed on the drain electrode layer 151, the second drain electrode layer 152, and the oxide semiconductor layer 130. a gate insulating film 160, a gate electrode layer 170 formed on the gate insulating film 160, The oxide insulating layer 180 formed on the gate insulating film 160 and the gate electrode layer 170 is Note that the oxide insulating layer 180 may be provided as necessary, and other An insulating layer may be formed.

[0138] The transistor 200 shown in FIGS. 7A, 7B, 7C, and 7D and the transistor 200 shown in FIGS. The transistor 300 shown in (C) and (D) has a first source electrode layer 141 and a second source electrode layer 142. The stacking order of the first drain electrode layer 151 and the second drain electrode layer 142 and the The stacking order with the pole layer 152 is different, but the rest is the same.

[0139] The transistor 300 includes an oxide semiconductor layer 130, a first source electrode layer 141, and a second Since the first drain electrode layer 151 is not in contact with the first source electrode layer 141 and The occurrence of oxygen vacancies in the oxide semiconductor layer 130 due to the first drain electrode layer 151 is Therefore, the oxygen vacancy does not cause n-type No regions are formed.

[0140] In the transistor 300, the second source electrode layer 142 and the second drain electrode layer The conductive nitride (tantalum nitride or titanium nitride) described in the first embodiment is used for 152. Therefore, nitrogen atoms acting as donors are introduced from the nitride into the vicinity of the interface of the oxide semiconductor layer 130. The nitrogen-diffused region can be used as a source or drain. It should be noted that nitrogen can also diffuse in the channel length direction, as shown in the figure. It is preferable to remove a part of the channel forming region as follows. The etching process for forming the second source electrode layer 142 and the second drain electrode layer 152 It is to be noted that nitrogen can be removed by a process such as the above. It is not necessary to diffuse the GaN layer into the vicinity of the interface. The GaN layer can be diffused in the vicinity of the interface to function as a source or drain. It is possible to do so.

[0141] In the transistor 300, the first source electrode layer 141 and the first drain electrode layer Since the generation of oxygen vacancies in the oxide semiconductor layer 130 due to the oxide 151 does not occur, The distance between the first source electrode layer 141 and the first drain electrode layer 151 is set to be larger than that of the transistor 100. For example, the distance between the end face of the second source electrode layer 142 and the end face of the first source electrode layer 143 can be shortened. The end face of the second drain electrode layer 152 and the end face of the first drain electrode layer 141 are The end face of the source electrode layer and the drain electrode layer 51 may be aligned. The resistance of the electrode layer as a whole can be reduced.

[0142] In addition, the first source electrode layer 141 and the first drain electrode layer 15 of the transistor 300 It is preferable that the end of the first portion is shaped like a staircase with multiple steps. By providing the above-mentioned shape, the coverage of the film formed thereon is improved, and the transistor The electrical characteristics and long-term reliability of the transistor shown in FIG. As in the transistor 302, the first source electrode layer 141 and the first drain electrode layer 151 The end portion may be shaped without having any stepped steps.

[0143] In order to fabricate a semiconductor device with low power consumption, it is necessary to reduce the off-state current of a transistor, particularly when the gate voltage is 0 It is effective to reduce the current (also called Icut) at V. When a transistor is miniaturized, the threshold voltage, S value (subthreshold value), and other It is known that the electrical characteristics of the device deteriorate when the temperature is increased, and it is therefore desirable to achieve both miniaturization and low power consumption. Ta.

[0144] In the transistor of one embodiment of the present invention, the first region which is a part of the first oxide semiconductor layer 131 The thickness of the film in the region is T S1 The thickness of the second region, which is a part of the gate insulating film 160, is T GI If we assume that K, T S1 ≧T GI (T S1 is T GI In this way, the gel is formed as The gate electrode layer 170 covers the side surface of the second oxide semiconductor layer 132 via the gate insulating film 160. It becomes like this.

[0145] The second oxide semiconductor layer 132 is a layer in which a channel is formed. By providing a structure in which an electric field can be easily applied from the gate electrode layer 170 to the side surface of the second An electric field is applied to the entire oxide semiconductor layer 132 of the transistor. The threshold voltage and S value can be improved. This is particularly effective when the length is short, so Icut can be reduced even when the transistor is miniaturized. This allows for a reduction in power consumption. In addition, the threshold voltage of the transistor is stable. This can improve the long-term reliability of the semiconductor device.

[0146] In addition, in the transistor of one embodiment of the present invention, In this way, the length of the source electrode layer 140 and the drain electrode layer 150 in the channel width direction is The length of the oxide semiconductor layer 130 in the channel width direction is shorter than the length of the oxide semiconductor layer 130 in the channel width direction. It is preferable to form the gate electrode so as to cover the end of the gate electrode in the longitudinal direction. There is an obstacle to the application of an electric field from the side electrode layer 170 to the side surface of the second oxide semiconductor layer 132. To reduce the above T S1 ≧T GI Improved transistor threshold voltage and S value This can enhance the effect of

[0147] The above is a transistor according to one embodiment of the present invention. As a result, a semiconductor device with high long-term reliability can be provided.

[0148] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0149] (Embodiment 4) In this embodiment, a transistor different from those described in the first and third embodiments is used. A transistor having the following structure will be described.

[0150] 21A, 21B, 21C, and 21D are top views and diagrams of a transistor of one embodiment of the present invention. FIG. 21(A) is a top view, and the dashed line D1-D2 shown in FIG. The cross section of FIG. 21(B) is shown, the cross section of the dashed line D3-D4 is shown in FIG. 21(C) and the cross section of the dashed line D5-D6 is shown in FIG. The cross section of FIG. 21(D) corresponds to FIG. 21(A). In addition, the direction of the dashed line D1-D2 is the channel width direction, The direction of the dashed dotted line D5-D6 may be referred to as the channel length direction.

[0151] The transistor 400 shown in FIGS. 21(A), (B), (C), and (D) is formed on a substrate 110. and a first oxide semiconductor layer formed on the base insulating film 120. 131 and a second oxide semiconductor layer 132, and a second oxide semiconductor layer formed on the second oxide semiconductor layer 132. The first source electrode layer 141 and the first drain electrode layer 151 are formed by the second oxide semiconductor. On the conductor layer 132, the first source electrode layer 141, and the first drain electrode layer 151 The third oxide semiconductor layer 133 is formed so as to cover and overlap with the first source electrode layer 141. and contacts the first source electrode layer 141 and the third oxide semiconductor layer 133. The second source electrode layer 142 overlaps with the first drain electrode layer 151 so as to cover the first The second drain electrode layer 151 and the third oxide semiconductor layer 133 are in contact with each other. The drain electrode layer 152, the third oxide semiconductor layer 133, the second source electrode layer 142, and and a gate insulating film 160 formed on the second drain electrode layer 152. A gate electrode layer 170 formed on the gate insulating film 160 and the gate electrode layer The oxide insulating layer 180 is formed on the insulating layer 170. Note that the oxide insulating layer 180 may be formed as needed. It is acceptable to provide an insulating layer on top of it.

[0152] The transistor 200 shown in FIGS. 7A, 7B, 7C, and 7D and the transistor 200 shown in FIGS. The transistor 400 shown in FIGS. 1C and 1D has a third oxide semiconductor layer 133 formed on the first oxide semiconductor layer 134. The difference is that it is formed on the source electrode layer 141 and the first drain electrode layer 151. , all other points being the same.

[0153] In the transistor 400, the second oxide semiconductor layer 132 in which a channel is formed and the first The first drain electrode layer 151 is in contact with the source electrode layer 141. A high density of oxygen vacancies is generated in the semiconductor layer 132, forming an n-type region. The path has few resistance components, allowing carriers to move efficiently.

[0154] The third oxide semiconductor layer 133 is connected to the first source electrode layer 141 and the first drain electrode layer 142. The first source electrode layer 141 and the first drain electrode layer 151 are formed after the formation of the electrode layer 151. There is no over-etching of the third oxide semiconductor layer 133 when the gate electrode layer 151 is formed. Therefore, the second oxide semiconductor layer 132 in which the channel is to be formed is sufficiently separated from the gate insulating film 160. This can increase the effect of suppressing the influence of impurity diffusion from the interface. .

[0155] In addition, the first source electrode layer 141 and the first drain electrode layer 15 of the transistor 400 It is preferable that the end of the first portion is shaped like a staircase with multiple steps. By providing the above-mentioned shape, the coverage of the film formed thereon is improved, and the transistor The electrical characteristics and long-term reliability of the transistor can be improved. As in the transistor 402, the first source electrode layer 141 and the first drain electrode layer 151 The end portion may be shaped without having any stepped steps.

[0156] In order to fabricate a semiconductor device with low power consumption, it is necessary to reduce the off-state current of a transistor, particularly when the gate voltage is 0 It is effective to reduce the current (also called Icut) at V. When a transistor is miniaturized, the threshold voltage, S value (subthreshold value), and other It is known that the electrical characteristics of the device deteriorate when the temperature is increased, and it is therefore desirable to achieve both miniaturization and low power consumption. Ta.

[0157] In the transistor of one embodiment of the present invention, the first region which is a part of the first oxide semiconductor layer 131 The thickness of the film in the region is T S1 The thickness of the second region, which is a part of the gate insulating film 160, is T GI If we assume that K, T S1 ≧T GI (T S1 is T GI In this way, the gel is formed as The gate electrode layer 170 covers the side surface of the second oxide semiconductor layer 132 via the gate insulating film 160. It becomes like this.

[0158] The second oxide semiconductor layer 132 is a layer in which a channel is formed. By providing a structure in which an electric field can be easily applied from the gate electrode layer 170 to the side surface of the second An electric field is applied to the entire oxide semiconductor layer 132 of the transistor. The threshold voltage and S value can be improved. This is particularly effective when the length is short, so Icut can be reduced even when the transistor is miniaturized. This allows for a reduction in power consumption. In addition, the threshold voltage of the transistor is stable. This can improve the long-term reliability of the semiconductor device.

[0159] In addition, in the transistor of one embodiment of the present invention, Thus, the first source electrode layer 141, the second source electrode layer 142, the first drain electrode layer The lengths of the first drain electrode layer 151 and the second drain electrode layer 152 in the channel width direction are 130 in the channel width direction, and It is preferable to form the gate electrode layer 1 so as to cover the gate electrode portion. 70 to the side surface of the second oxide semiconductor layer 132, , the above-mentioned T S1 ≧T GI The effect of improving the threshold voltage and S value of transistors It can be encouraged.

[0160] The above is a transistor according to one embodiment of the present invention. As a result, a semiconductor device with high long-term reliability can be provided.

[0161] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0162] (Embodiment 5) In this embodiment, the method for manufacturing the transistor 200 illustrated in FIG. 7 described in Embodiment 1 will be described. This will be described with reference to FIGS.

[0163] The substrate 110 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate can be used. Substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On In It is also possible to use a quartz crystal integrator substrate, on which semiconductor elements are mounted. The provided one may be used.

[0164] The base insulating film 120 is formed by depositing aluminum oxide or Magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide , yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide insulating films such as tantalum oxide, silicon nitride, silicon nitride oxide, and aluminum nitride. The insulating film is made of a nitride such as niobium, aluminum oxide nitride, or a mixture of the above materials. The above-mentioned materials may be laminated, and the insulating layer may be formed of at least an oxide semiconductor. The upper layer in contact with the oxide semiconductor layer 130 contains oxygen that can be a source of oxygen to the oxide semiconductor layer 130. It is preferable to form the material.

[0165] Note that the surface of the substrate 110 is an insulator, and impurities are diffused into the oxide semiconductor layer 130 to be provided later. If there is no effect of diffusion, the base insulating film 120 may not be provided.

[0166] Next, a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 are formed on the base insulating film 120. The third oxide semiconductor layer 133 is formed by a sputtering method, a CVD method, an MBE method, an ALD method, or the like. The oxide semiconductor layer 130 is formed by forming the oxide semiconductor layer 130 using a PLD method and selectively etching the oxide semiconductor layer 130. (See FIG. 22(A)). Note that a heating step may be carried out before the etching.

[0167] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor The layer 133 can be made of the material described in the first embodiment. For example, the first oxide The compound semiconductor layer 131 is formed of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2. The second oxide semiconductor layer 132 is made of In- Ga-Zn oxide, the third oxide semiconductor layer 133 is In:Ga:Zn=1:3:2 [atomic In-Ga-Zn oxide having a ratio of [0.1 to 0.2] can be used.

[0168] In addition, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The oxide semiconductor that can be used as the semiconductor layer 133 contains at least indium (In It is preferable that the alloy contains In (In) or zinc (Zn). Alternatively, the alloy may contain both In and Zn. In addition, in order to reduce variation in electrical characteristics of a transistor using the oxide semiconductor, Therefore, it is preferable to include a stabilizer therewith.

[0169] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, with other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0170] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. , Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0171] In addition, for example, In-Ga-Zn oxide is a material with In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. In this specification, the term "In-Ga-Z" refers to a metal element other than In and Zn. A film made of n-oxide is also called an IGZO film.

[0172] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one metal element selected from Ga, Fe, Mn, and Co, or indicates multiple metal elements. Also, In2SnO5(ZnO) n (n>0 and n is an integer ) may be used.

[0173] However, as described in detail in the first embodiment, the first oxide semiconductor layer 131 and the third The oxide semiconductor layer 133 is formed so as to have a larger electron affinity than the second oxide semiconductor layer 132. Select the material accordingly.

[0174] Note that the oxide semiconductor layer is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used. DC sputtering is the most popular method because it can reduce the amount of dust generated during film formation and also makes the film thickness uniform. It is preferable to use:

[0175] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 13 When In-Ga-Zn oxide is used as 3, the atomic ratio of In, Ga, and Zn is as follows: For example, In:Ga:Zn=1:1:1, In:Ga:Zn=2:2:1, In:Ga: Zn=3:1:2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:4:3, I n:Ga:Zn=1:5:4, In:Ga:Zn=1:6:6, In:Ga:Zn=2: 1:3, In:Ga:Zn=1:6:4, In:Ga:Zn=1:9:6, In:Ga: The first oxide layer is made of either Zn=1:1:4 or In:Ga:Zn=1:1:2. The electron affinity of the oxide semiconductor layer 131 and the third oxide semiconductor layer 133 is smaller than that of the second oxide semiconductor It is sufficient to make it larger than layer 132.

[0176] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C =1), a, b, and c are in the vicinity of the oxide composition (aA)2+(bB)2+ (cC)2≦r2 is satisfied. For example, r may be set to 0.05. The same is true for other oxides.

[0177] The second oxide semiconductor layer 132 is a semiconductor layer including the first oxide semiconductor layer 131 and the third oxide semiconductor layer. The indium content is preferably higher than that of the semiconductor layer 133. The s orbitals of heavy metals contribute to carrier conduction, and by increasing the In content, Since more s orbitals overlap, oxides with a composition in which In is more abundant than Ga have the same composition as In and Ga. The mobility is higher compared to oxides with equal or lesser composition. Therefore, the second oxide By using an oxide with a high indium content for the semiconductor layer 132, a transistor with high mobility can be obtained. It is possible to realize the above-mentioned.

[0178] The structure of the oxide semiconductor film will be described below.

[0179] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Straight" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This also includes cases where the angle is between 85° and 95°.

[0180] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0181] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline This refers to films such as oxide semiconductor films.

[0182] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in a microscopic area, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0183] The microcrystalline oxide semiconductor film is, for example, a microcrystal having a size of 1 nm or more and less than 10 nm (nanocrystal). Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher molecular weight than the amorphous oxide semiconductor film. Also, the defect level density is low.

[0184] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with one side less than 100 nm. The crystals contained in the S film are in the form of cubes with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than a microcrystalline oxide semiconductor film. The CAAC-OS film has a low density of recessed states. .

[0185] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a quartz microscope, clear boundaries between the crystals were observed. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0186] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer has a surface on which the CAAC-OS film is formed (also called a surface on which the film is formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS film is aligned parallel to the surface on which the film is formed or the top surface.

[0187] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0188] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0189] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0190] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0191] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0192] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0193] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of differing crystallinity may be formed.

[0194] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0195] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0196] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminate film having two or more kinds of films.

[0197] The CAAC-OS film can be formed, for example, by using a polycrystalline oxide semiconductor sputtering target. The film can be formed by sputtering.

[0198] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0199] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be reduced. Also, impurities in the deposition gas should be reduced. Specifically, the dew point should be -80℃. Hereinafter, a deposition gas having a temperature of -100°C or less is preferably used.

[0200] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably 20 The film is formed at a temperature between 0 and 500°C. By increasing the substrate heating temperature during film formation, a flat plate-shaped When sputtered particles reach the substrate, migration occurs on the substrate, and the sputtered particles The flat surface of the substrate is attached to the substrate.

[0201] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0202] As the sputtering target, for example, an In-Ga-Zn-O compound target is used. The In-Ga-Zn-O compound target is InO X powder, GaO Y powder Powder and ZnO Z The powders are mixed in a specified molar ratio, pressurized, and then heated at 1000°C (1500°F) or higher. It is made polycrystalline by heat treatment at a temperature of 100°C or less. X, Y, and Z are arbitrary positive integers. Moreover, the smaller the grain size of the polycrystal, for example, 1 μm or less, the more preferable it is. Here, the type of powder and the molar ratio of the powder to be mixed are determined according to the sputtering target to be produced. Therefore, it may be changed appropriately.

[0203] Next, a first heat treatment is preferably performed. The first heat treatment is performed at a temperature of 250° C. or higher and 650° C. or lower. The temperature is preferably 300°C or higher and 500°C or lower, and the inert gas atmosphere and the oxidizing gas atmosphere are The first heat treatment may be performed in an atmosphere containing 10 ppm or more or under reduced pressure. The gas is heated in an inert gas atmosphere, and then an oxidizing gas is pumped in to replace the oxygen that has been removed. The first heat treatment may be performed in an atmosphere containing 0 ppm or more of fluorine. The crystallinity of the oxide semiconductor layer 132 is improved, and the base insulating film 120, the first oxide semiconductor layer 131, and the Impurities such as hydrogen and water can be removed from the third oxide semiconductor layer 133. Before the etching for forming the oxide semiconductor layer 130, a first heating step may be performed.

[0204] In the case where the oxide semiconductor layer 130 is a laminated layer, if an amorphous layer is formed in the lower layer, C Therefore, the first oxide semiconductor layer 131 is amorphous. In this case, the second oxide semiconductor layer 132 may be a CAAC-OS film.

[0205] Next, a first source electrode layer 141 and a first drain electrode layer 142 are formed on the oxide semiconductor layer 130. A first conductive film 151 is formed. The first conductive film is made of Al, Cr, Cu, Ta, etc. , Ti, Mo, W, or alloy materials containing these as main components can be used. For example, Then, a titanium film of 100 nm is formed by a sputtering method or the like.

[0206] Next, the first conductive film is etched so as to be divided on the oxide semiconductor layer 130 to form a first section. A source electrode layer 141 and a first drain electrode layer 151 are formed (see FIG. 22(B)). Here, the ends of the first source electrode layer 141 and the first drain electrode layer 151 are not shown in the figure. It is preferable to form the end in a stepped shape as shown in FIG. The step of recessing the mask and the step of etching are alternately performed multiple times to form the can.

[0207] At this time, the first conductive film is over-etched, so that the oxide semiconductor layer However, the first conductive film and the oxide semiconductor layer 130 are not covered with the insulating film. When the etching selectivity of the oxide semiconductor layer 30 is large, the oxide semiconductor layer 130 is almost entirely etched. The shape will not be correct.

[0208] Next, the oxide semiconductor layer 130, the first source electrode layer 141 and the first drain electrode layer 1 On the second conductive layer 51, a second conductive layer is formed to become a second source electrode layer 142 and a second drain electrode layer 152. The second conductive film 800 (not shown in FIG. 22C) is formed. The material can be selected from titanium, titanium nitride, ruthenium, or alloys containing these as the main components. For example, a tantalum nitride film of 20 nm is formed by sputtering or the like.

[0209] Next, the second conductive film 800 is etched so as to be divided on the oxide semiconductor layer 130. A second source electrode layer 142 and a second drain electrode layer 152 are formed (see FIG. 22(C)). At this time, a part of the oxide semiconductor layer 130 may be etched.

[0210] In addition, the channel length (between the second source electrode layer 142 and the second drain electrode layer 152) is When forming a very short transistor, first, as shown in the top view of FIG. A second conductive layer is formed in a shape that covers the source electrode layer 141 and the first drain electrode layer 151. The film 800 is etched.

[0211] Then, an electron beam is applied to a region 900 that divides the second conductive film 800 shown in FIG. A resist mask is processed using a method suitable for fine line processing such as beam exposure, and then an etching process is performed. The region 900 is etched by the process to form the second source electrode layer 142 and the second drain electrode layer 143. An electrode layer 152 is formed. Note that a positive resist is used as the resist mask. This allows the exposure area to be minimized, improving throughput. Using this method, it is possible to fabricate transistors with channel lengths of 30 nm or less. can.

[0212] Next, a second heat treatment is preferably performed. The second heat treatment is performed in the same manner as the first heat treatment. By the second heat treatment, the oxide semiconductor layer 130 is further Impurities such as hydrogen and water can be removed.

[0213] Next, the oxide semiconductor layer 130, the second source electrode layer 142 and the second drain electrode layer 1 A gate insulating film 160 is formed on the insulating film 52 (see FIG. 23(A)). , aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. The gate insulating film 160 may be a laminate of the above materials. The insulating film 160 is formed by using a method such as a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method. It can be formed by:

[0214] Next, a third conductive film is formed on the gate insulating film 160. The third conductive film is made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, or these The third conductive film can be formed by sputtering or the like. Then, etching is performed so as to overlap the channel forming region, and a gate A first electrode layer 170 is formed (see FIG. 23(B)).

[0215] Next, an oxide insulating layer 180 is formed on the gate insulating film 160 and the gate electrode layer 170 (FIG. The oxide insulating layer 180 is formed using the same material and method as the base insulating film 120. The oxide insulating layer 180 can be formed by using aluminum oxide, magnesium oxide, or the like. Sium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Uses oxide insulating layers containing oxydimium, hafnium oxide, and tantalum oxide, or nitrogen The oxide insulating layer 180 may be formed by a sputtering method, a CVD method, an MBE method, an ALD method, or a PL method. The oxide semiconductor layer 130 can be formed by using a method D. It is preferable for the film to contain an excess of oxygen.

[0216] In addition, the oxide insulating layer 180 is subjected to ion implantation, ion doping, plasma immersion, etc. Oxygen may be added by using an ion implantation method or the like. This makes it easier to supply oxygen from the oxide insulating layer 180 to the oxide semiconductor layer 130. It is possible.

[0217] Next, a third heat treatment is preferably performed. The third heat treatment is performed in the same manner as the first heat treatment. The third heat treatment can be performed under the following conditions. 60, excess oxygen is easily released from the oxide insulating layer 180, and the oxide semiconductor layer 130 The oxygen deficiency can be reduced.

[0218] Through the above steps, the transistor 200 shown in FIG. 7 can be manufactured.

[0219] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0220] (Embodiment 6) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is used in a non-power-supply state. A semiconductor device (memory device) that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. An example of the device will be described with reference to the drawings.

[0221] FIG. 25A shows a cross-sectional view of the semiconductor device, and FIG. 25B shows a circuit diagram of the semiconductor device. .

[0222] The semiconductor device shown in FIG. 25(A) and FIG. 25(B) uses a first semiconductor material in the lower part. A transistor 3300 having a transistor 3200 and a second semiconductor material on top of the transistor 3300; and a capacitor 3400. The transistors described in the first, third, and fourth embodiments can be used. 25A shows an example of applying the transistor 200 shown in FIG. 7 of the first embodiment. includes a cross section at the position indicated by the dashed dotted line B5-B6 shown in FIG.

[0223] The capacitor 3400 has one electrode connected to the source electrode layer or the drain electrode layer of the transistor 3300. The other electrode is the gate electrode layer of the transistor 3300, and the dielectric is the transistor By using the same material as the gate insulating film 160 of the transistor 3300, 300 can be formed at the same time.

[0224] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be the oxide semiconductor described in Embodiment 1. Transistors using materials other than oxide semiconductors can easily operate at high speeds. Semiconductor transistors have electrical characteristics that allow them to retain charge for long periods of time due to their low off-state current. Let us assume that.

[0225] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. In order to hold the transistor, an oxide semiconductor is used as in the transistors described in the first, third, and fourth embodiments. In addition to using the above, specific details of the semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, are also considered. The specific configurations need not be limited to those shown here.

[0226] The transistor 3200 in FIG. 25(A) is made of a semiconductor material (e.g., crystalline silicon). A channel forming region is provided on a substrate 3000 including a semiconductor device, and the channel forming region is sandwiched between the semiconductor device and the semiconductor device. an impurity region provided in the semiconductor substrate, an intermetallic compound region in contact with the impurity region, and a channel forming region a gate insulating film provided on the gate electrode layer; and a gate electrode layer provided on the gate insulating film. In addition, in the drawings, the source electrode layer and the drain electrode layer may not be explicitly shown. For convenience, this state may be referred to as a transistor. In order to explain the connection relationship of the transistor, the source electrode including the source region and drain region is That is, in this specification, the source electrode layer and the drain electrode layer are sometimes referred to as a source electrode layer and a drain electrode layer. The description may include a source region.

[0227] An element isolation insulating layer 3100 is provided on a substrate 3000 so as to surround a transistor 3200. An insulating layer 3150 is provided to cover the transistor 3200. The element isolation insulating layer 3100 is formed by LOCOS (Local Oxidation of Silicon licon) and STI (Shallow Trench Isolation) It can be formed by using element isolation technology.

[0228] For example, when a crystalline silicon substrate is used, the transistor 3200 can operate at high speed. Therefore, by using the transistor as a readout transistor, The readout can be performed at high speed.

[0229] A transistor 3300 is provided on the insulating layer 3150, and its source electrode layer or drain One of the electrode layers extends and acts as one electrode of the capacitance element 3400. The electrode is electrically connected to the gate electrode layer of the transistor 3200 .

[0230] The transistor 3300 illustrated in FIG. 25A has a channel formed in an oxide semiconductor layer. The transistor 3300 is a top-gate transistor. Since the off-state current of the transistor 3300 is low, By using the REFLECTION function, it is possible to retain memory contents for a long period of time. A semiconductor memory device that does not require a refresh operation or requires a refresh operation very infrequently. Since it is possible to provide a single device, power consumption can be reduced sufficiently.

[0231] In addition, an electrode 3250 is provided so as to overlap with the transistor 3300 with an insulating layer 3150 interposed therebetween. By applying an appropriate potential to the electrode, the threshold voltage of the transistor 3300 is increased. In addition, the long-term reliability of the transistor 3300 can be improved. It is possible to adopt a configuration in which the electrode 3250 is not provided.

[0232] As shown in FIG. 25A, a transistor 3200 and a transistor 3300 or a capacitor Since the chip 3400 can be formed so as to overlap, the area occupied by the chip 3400 can be reduced. Therefore, the degree of integration of the semiconductor device can be increased.

[0233] An example of a circuit configuration corresponding to FIG. 25(A) is shown in FIG. 25(B).

[0234] In FIG. 25B, a first wiring 3001 is connected to a source electrode layer of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode layer of the transistor 3200. The third wiring 3003 is connected to the source electrode layer of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrode layers of the transistor 33. 00 and the gate electrode layer of the transistor 3200. The other of the source electrode layer and the drain electrode layer of the transistor 3300 is a capacitor. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. 0 electrode.

[0235] In the semiconductor device shown in FIG. 25B, the potential of the gate electrode layer of the transistor 3200 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0236] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode layer of the transistor 3200 and and the capacitor 3400. That is, the gate electrode layer of the transistor 3200 A certain charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is given. After that, the potential of the fourth wiring 3004 is set to a value that turns off the transistor 3300. By applying a potential to the transistor 3300 to turn it off, the transistor 3200 The charge applied to the gate electrode layer is retained (retention).

[0237] Since the off-state current of the transistor 3300 is extremely low, the gate electrode of the transistor 3200 The charge on the layer is retained for a long period of time.

[0238] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the transistor Depending on the amount of charge held in the gate electrode layer of the capacitor 3200, the second wiring 3002 has different potentials. In general, if the transistor 3200 is an n-channel type, then the transistor 320 The apparent threshold voltage V when a high-level charge is applied to the gate electrode layer of th_H In the figure, a low-level charge is applied to the gate electrode layer of the transistor 3200. The apparent threshold voltage V th_L This is because the apparent The low voltage is the voltage required to turn on the transistor 3200. Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential V0 between For example, in writing, a high-level charge is applied. In this case, the potential of the fifth wiring 3005 is V0 (>V th_H ) Then, Trans If a low level charge is applied, the fifth The potential of the wiring 3005 is V0( <V th_L ), transistor 3200 is "off" Therefore, by determining the potential of the second wiring 3002, The information stored in the memory can be read out.

[0239] When memory cells are arranged in an array, only the information in a desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 3200 is in the "off state" regardless of th_ HA smaller potential may be applied to the fifth wiring 3005. Regardless of the potential, transistor 3200 is in the "on" state, i.e., V th_L A larger potential may be applied to the fifth wiring 3005 .

[0240] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using transistors with extremely low capacitance, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. This makes it possible to reduce the frequency of the power consumption significantly. In addition, even if there is no power supply (although it is preferable that the potential is fixed), Even if the memory is changed, the stored contents can be retained for a long period of time.

[0241] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0242] As described above, a semiconductor device that realizes miniaturization and high integration and has excellent electrical characteristics is developed. An apparatus can be provided.

[0243] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0244] (Embodiment 7) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is A semiconductor device that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. A semiconductor device having a structure different from that shown in the sixth embodiment will be described.

[0245] FIG. 26 is an example of a circuit configuration of a semiconductor device. In the semiconductor device, the first wiring 4 The source electrode layer of the transistor 4300 is electrically connected to the second wiring 460. 0 and the first gate electrode layer of the transistor 4300 are electrically connected to each other. The drain electrode layer of the transistor 300 and one terminal of the capacitor element 4400 are electrically connected to each other. The transistor 4300 included in the semiconductor device is the transistor according to any one of the first, third, and fourth embodiments. The transistor described in 2 can be used. Note that the first wiring 4500 is a bit line, The second wiring 4600 can function as a word line.

[0246] The semiconductor device (memory cell 4250) includes a transistor 3300 and a capacitor 3301 shown in FIG. The capacitance element 4400 can be connected in the same manner as the capacitance element 3400. The transistor 4300 can be manufactured in the same manner as the capacitor 3400 described in Embodiment 6. can be simultaneously produced.

[0247] Next, data is written and held in the semiconductor device (memory cell 4250) shown in FIG. The following describes how to do this.

[0248] First, a potential that turns on the transistor 4300 is supplied to the second wiring 4600. The transistor 4300 is turned on. As a result, the potential of the first wiring 4500 is The potential of the second wiring 4600 is then applied to the first terminal of the first wiring 4400 (write). is set as a potential at which the transistor 4300 is turned off, By setting the potential at the first terminal of the capacitor 4400 in this state, the potential at the first terminal of the capacitor 4400 is held (retained).

[0249] The transistor 4300 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 4300 is turned off, The potential of the first terminal (or the charge stored in the capacitor 4400) is kept constant for an extremely long period of time. It is possible to hold it upright.

[0250] Next, reading of information will be described. When the transistor 4300 is turned on, The first wiring 4500 in the free state and the capacitor element 4400 are electrically connected to each other. Charge is redistributed between the capacitors 4400. As a result, the potential of the first wiring 4500 changes. The change in the potential of the first wiring 4500 is proportional to the change in the potential of the first terminal of the capacitor 4400 ( Alternatively, it takes a different value depending on the charge stored in the capacitor element 4400.

[0251] For example, the potential of the first terminal of the capacitance element 4400 is V, the capacitance of the capacitance element 4400 is C, The capacitance component of the first wiring 4500 before the charge is redistributed is CB. If the potential is VB0, the potential of the first wiring 4500 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of memory cell 4250 is Assume that the potential of the first terminal of the capacitance element 4400 has two states, V1 and V0 (V1>V0). Then, the potential of the first wiring 4500 when the potential V1 is held is (=(CB×VB0+C ×V1) / (CB+C) is the potential of the first wiring 4500 when the potential V0 is maintained. It can be seen that this is higher than (=CB×VB0+C×V0) / (CB+C)).

[0252] Then, the potential of the first wiring 4500 is compared with a predetermined potential, thereby reading out information. can be done.

[0253] In this manner, the semiconductor device (memory cell 4250) shown in FIG. Since the off-state current of the capacitor 4400 is extremely low, the charge stored in the capacitor 4400 is retained for a long time. This means that no refresh operation is required or the data can be retained for a long time. Since the frequency of refresh operations can be reduced significantly, power consumption can be reduced significantly. In addition, even if there is no power supply, the memory contents can be maintained for a long period of time. It is possible to have it.

[0254] The memory cell 4250 shown in FIG. 26 includes a drive circuit for driving the memory cell 4250. It is preferable to stack a substrate on which the memory cell 4250 and the driver circuit are formed. In this way, the semiconductor device can be miniaturized. The number of driving circuits is not limited.

[0255] The transistors included in the driver circuit are made of a different semiconductor material from the transistor 4300. For example, silicon, germanium, silicon germanium, silicon carbide, It is preferable to use a single crystal semiconductor. A transistor using such a semiconductor material is a transistor using an oxide semiconductor. This allows for faster operation than the conventional MOS transistor, and is suitable for use in configuring a drive circuit for the memory cell 4250. is doing.

[0256] As described above, a semiconductor device that realizes miniaturization and high integration and has excellent electrical characteristics is developed. An apparatus can be provided.

[0257] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0258] (Embodiment 8) In this embodiment, at least the transistors described in the first, third and fourth embodiments are used. The following describes a CPU including the storage device described in the sixth embodiment.

[0259] FIG. 27 shows a CP using the transistors described in the first, third and fourth embodiments at least in part. 1 is a block diagram showing an example of a configuration of U.

[0260] The CPU shown in FIG. 27 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 27 is merely a simplified example of its configuration, and in reality CPUs have a wide variety of configurations depending on their applications. For example, the CPU shown in FIG. Alternatively, a configuration including an arithmetic circuit is regarded as one core, and multiple cores are included, each of which is parallel It is also possible to configure the system so that it operates in a row. The number of bits that can be used can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc. can.

[0261] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0262] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0263] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. Supplied to various circuits.

[0264] In the CPU shown in FIG. 27, a register 1196 is provided with a memory cell. The transistors shown in the above embodiment can be used as the memory cells of 1196. do.

[0265] In the CPU shown in FIG. 27, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, a power supply voltage is applied to the memory cells in the register 1196. If data retention is selected in the capacitive element, rewriting data to the capacitive element This allows the supply of the power supply voltage to the memory cells in the register 1196 to be stopped. .

[0266] FIG. 28 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 700 includes a circuit 701 in which stored data is volatilized when the power is cut off, and a A circuit 702 in which data is not volatile, a switch 703, a switch 704, and a logic element 706. The circuit 702 includes a capacitor 707 and a circuit 720 having a selection function. The memory element 708, a transistor 709, and a transistor 710. 700 may include other elements, such as diodes, resistors, inductors, etc., as needed. It may also have.

[0267] Here, the memory device described in Embodiment 6 can be used for the circuit 702. When the supply of the power supply voltage to the element 700 is stopped, the first gate of the transistor 709 in the circuit 702 The ground potential (0V) or a potential that turns off the transistor 709 is continuously input to the output. For example, the first gate of the transistor 709 is grounded via a load such as a resistor. The configuration will be as follows.

[0268] The switch 703 is configured using a transistor 713 of one conductivity type (for example, an n-channel type). The switch 704 is a transistor of the opposite conductivity type (e.g., p-channel type). Here, the first terminal of the switch 703 is a transistor 714. The second terminal of the switch 703 corresponds to one of the source and drain of the transistor 713. The switch 703 corresponds to the other of the source and drain of the transistor 713. A control signal RD input to the gate of the transistor controls conduction between the first and second terminals or The non-conducting state (i.e., the on or off state of the transistor 713) is selected. The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714. The second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714. The transistor 704 is connected to a first terminal of the transistor 714 in response to a control signal RD input to the gate of the transistor 714. and the second terminal (i.e., the on or off state of the transistor 714). The off state is selected.

[0269] One of the source and drain of the transistor 709 is connected to one of the pair of electrodes of the capacitor 708. On the other hand, the transistor 710 is electrically connected to the gate of the transistor 710. One of the source and drain of the transistor 710 is connected to a low potential power supply. The other is electrically connected to a wiring (for example, a GND line) that can be connected to the switch 703. It is electrically connected to the first terminal (one of the source and drain of the transistor 713). The second terminal of the switch 703 (the other of the source and drain of the transistor 713) is 704 (one of the source and drain of the transistor 714). The second terminal of the switch 704 (the other of the source and drain of the transistor 714) is The switch 703 is electrically connected to a wiring that can supply a power supply potential VDD. 2 terminal (the other of the source and drain of the transistor 713) and the first terminal of the switch 704 A terminal (either the source or drain of the transistor 714) and an input terminal of the logic element 706 The connection portion is electrically connected to one of a pair of electrodes of the capacitor 707. The other of the pair of electrodes of the capacitor 707 is a node M1. For example, a low power supply potential (GND, etc.) or a high power supply potential (V DD, etc.) can be input to the other of the pair of electrodes of the capacitor 707. The other side is electrically connected to the wiring that can supply low potential power (for example, the GND line). A constant potential is input to the other of the pair of electrodes of the capacitor 708. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 708 is supplied with a low potential power supply. The power supply is electrically connected to a wiring (for example, a GND line) that can supply power.

[0270] Note that the capacitors 707 and 708 are formed by actively reducing the parasitic capacitance of transistors and wirings. It is also possible to omit it by using it in a more practical way.

[0271] A control signal WE is input to a first gate (first gate electrode layer) of the transistor 709. The switches 703 and 704 are controlled by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by the When the first terminal and the second terminal of the switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no continuity between the terminals.

[0272] The other of the source and drain of the transistor 709 is connected to a data input terminal of the circuit 701. In FIG. 28, a signal output from the circuit 701 is input to the transistor The second terminal of the switch 703 is connected to the other of the source and drain of the switch 709. The signal output from the other of the source and drain of the transistor 713 is 6, the logical value of which is inverted to become an inverted signal, and the inverted signal is input to the circuit 701 via the circuit 720. Be encouraged.

[0273] In FIG. 28, the second terminal of the switch 703 (the source and drain of the transistor 713) The signal output from the other input terminal is input to the circuit 701 via the logic element 706 and the circuit 720. The second terminal of the switch 703 (transistor The signal output from the other of the source and drain of the transistor 713 can be inverted in logical value. For example, the signal input from the input terminal may be input to the circuit 701. When there is a node that holds a signal with the logic value of the signal that has been inverted, the switch 703 The signal output from the second terminal (the other of the source and drain of the transistor 713) is The node can be input.

[0274] The transistor 709 in FIG. 28 is the transistor described in the first, third, or fourth embodiment. As described in the sixth embodiment, the second gate (second gate voltage A control signal WE is input to the first gate, and a control signal WE is input to the second gate. A control signal WE2 can be input to the gate. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, a ground potential GND or the potential of the transistor 709. A potential smaller than the source potential is selected. This is a potential signal for controlling the threshold voltage, and is used to lower Icut of the transistor 709. The transistor 709 may be a transistor without a second gate. A resistor can also be used.

[0275] In addition, in FIG. 28, among the transistors used in the memory element 700, the transistor The transistors other than 709 are formed on a layer or a substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a silicon layer or a silicon transistor in which a channel is formed. The memory element 70 may be a transistor in which a channel is formed in a conductive substrate. All the transistors used in 0 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 700 may include a transistor other than the transistor 709. The panel may include a transistor formed of an oxide semiconductor layer, and the remaining transistors The transistor is a layer made of a semiconductor other than an oxide semiconductor or a substrate 1190 in which a channel is formed. It can also be a transistor.

[0276] For example, a flip-flop circuit can be used for the circuit 701 in FIG. In addition, the logic element 706 may be, for example, an inverter or a clocked inverter. can be done.

[0277] This concludes the description of the configuration of the memory element 700. Next, a method for driving the memory element 700 will be described. He explains.

[0278] In the memory element 700, the power consumption during data retention after the supply of the power supply voltage is reduced. The driving method when the supply voltage is stopped and then supplied again is shown in Figure 29. The following description will be given with reference to a timing chart. In the timing chart of FIG. indicates data held in the circuit 701, WE indicates the potential of the control signal WE, and WE2 indicates the potential of the control signal WE2, RD indicates the potential of the control signal RD, and SEL indicates the potential of the circuit 720 VDD indicates the power supply potential VDD. M1 indicates the potential of the node M1, and M2 indicates the potential of the node M2. The one path in this case is a path that connects the output side of the circuit 702 and the input side of the circuit 701 .

[0279] In the driving method described below, in the configuration shown in FIG. 28, the switch 703 is a control signal When RD is at a high level potential, the first terminal and the second terminal of the switch 703 are in a conductive state. The switch 704 is in a non-conductive state between the first terminal and the second terminal, and the control When the signal RD is at a low level potential, the first terminal and the second terminal of the switch 703 are not connected to each other. An example in which the first terminal and the second terminal of the switch 704 are in a conductive state When the control signal SEL is at a high potential, the first When the connection between the first terminal and the second terminal is in a conductive state and the control signal SEL is at a low level potential, In this example, the first terminal and the second terminal are not electrically connected to each other. As an n-channel transistor, when the control signal WE is at a high level potential, the transistor When the control signal WE is at a low potential, the transistor 709 is turned on. An example in which 9 is in the off state is shown below.

[0280] However, the method for driving the semiconductor device according to one embodiment of the present invention is not limited thereto, and may be modified as described below. The states of the switch 703, the switch 704, the circuit 720, and the transistor 709 in The potential of each control signal can be set to be the same.

[0281] First, the operation during the period T1 in FIG. 29 will be described. During T1, the power supply voltage VDD While the power supply voltage is being supplied to the memory element 700, The circuit 701 holds the data (denoted as dataX in FIG. 29). is set to a low level potential, and the first terminal and the second terminal of one path of the circuit 720 are not connected to each other. The first and second terminals of the switches 703 and 704 are in a conductive state. The state between the children (conducting state, non-conducting state) can be either state. That is, the control signal RD may be at a high level potential or a low level potential (denoted as A in FIG. 29). In addition, the state of the transistor 709 (on state or off state) may be either state. That is, the control signal WE may be either a high level potential or a low level potential (see FIG. 29, denoted as A). At T1, node M1 may be at any potential (see FIG. 2). 9, denoted as A). At T1, node M2 ​​may be at any potential (see FIG. 29). The operation of T1 is called normal operation. The control signal WE2 is constant regardless of the period. The potential is set to a low level potential such as the ground potential.

[0282] Next, the operation during the period T2 in FIG. 29 will be described. Before the supply of the signal is stopped, the control signal WE is set to a high level potential to turn on the transistor 709. In this way, the signal corresponding to the data (dataX) held in the circuit 701 is A signal is input to the gate of a transistor 710 via a transistor 709. The signal input to the gate of the transistor 710 is held by the capacitor 708. The potential of the node M2 ​​is a signal potential corresponding to the data held in the circuit 701 (in FIG. 29, After that, the control signal WE is set to a low level potential, and the transistor 709 In this way, a signal corresponding to the data held in the circuit 701 is output to the circuit 70 During T2, the first signal in one path of the circuit 720 is held at 0.2 by the control signal SEL. The first terminal and the second terminal of the switch 703 and the switch 704 are in a non-conductive state. The state between the first and second terminals of That is, the control signal RD may be a high level potential or a low level potential. (In FIG. 29, this is indicated as A). At T2, the node M1 may be at any potential ( (Indicated as A in FIG. 29.) The operation at T2 is called the operation before the power supply voltage is stopped.

[0283] Next, the operation during the period T3 in FIG. 29 will be described. After this, at the beginning of T3, the supply of the power supply voltage to the storage element 700 is stopped. When the supply is stopped, the data (dataX) held in the circuit 701 is lost. Even after the supply of the power supply voltage to the memory element 700 is stopped, the memory element 700 is The signal potential (VX) corresponding to the data (dataX) held in the circuit 701 is The transistor 709 has a channel formed of an oxide semiconductor layer. The leakage current (off current) is extremely small. Enhancement type (normally off type) Therefore, the supply of the power supply voltage to the memory element 700 When the transistor 709 is turned off, the gate of the transistor 709 is connected to the ground potential (0V) or the Since the potential at which the power supply voltage to the memory element 700 is turned off is continuously input, Even after the supply is stopped, the transistor 709 can be kept in the off state, and the capacitance element 7 The potential held by the potential 08 (potential VX of node M2) can be maintained for a long period of time. The memory element 700 retains the data (dataX) even after the supply of the power supply voltage is stopped. T3 corresponds to a period during which the supply of power supply voltage to the storage element 700 is stopped.

[0284] Next, the operation during the period T4 in FIG. 29 will be described. After the supply of the current is resumed, the control signal RD is set to a low level potential to turn on the first terminal of the switch 704. and the first terminal and the second terminal of the switch 703 are in a non-conductive state. At this time, the control signal WE is at a low level potential, and the transistor 709 is in a conductive state. The control signal SEL is at a low potential, and one of the circuits 720 remains in the off state. There is no electrical continuity between the first terminal and the second terminal of the path. A power supply voltage VDD is input to a second terminal of the switch 703 and a first terminal of the switch 704. Therefore, the potential of the second terminal of the switch 703 and the potential of the first terminal of the switch 704 (node The potential of the transistor M1 can be set to a constant potential (here, VDD). This is called a recharge operation. Note that the potential of the node M1 is held by the capacitor 707. .

[0285] After the above precharge operation, during the period T5, the control signal RD is set to a high level potential. As a result, a state of conduction is established between the first terminal and the second terminal of the switch 703, and the switch The first terminal and the second terminal of 704 are in a non-conductive state. At this time, the control signal WE is low. The control signal Vcc is maintained at the same potential level, and the transistor 709 is maintained in the off state. SEL is at a low level potential, and the first and second terminals of one path of the circuit 720 In response to the signal held in the capacitance element 708 (potential VX of node M2), The on or off state of the transistor 710 is selected according to the input voltage, and the second The potential of the terminal of the transistor 702 and the first terminal of the switch 704, that is, the potential of the node M1, is determined. When the transistor 710 is in an on state, a low power supply potential (for example, GND) is input to the node M1. On the other hand, when the transistor 710 is in an off state, the potential of the node M1 is The recharge operation maintains the voltage at a constant level (for example, VDD). Thus, depending on whether the transistor 710 is on or off, the potential at the node M1 is For example, the signal held in the circuit 701 is "1", When the potential at the node M1 corresponds to a high level potential (VDD), the potential at the node M1 corresponds to a signal "0". On the other hand, the signal held in the circuit 701 becomes "0". , which corresponds to a low-level potential (GND), the potential of the node M1 is a signal "1" In other words, the signal stored in the circuit 701 becomes a high-level potential (VDD) corresponding to the The inverted signal of the signal is held at node M1. That is, for the data (dataX) input from the circuit 701 at T2, The corresponding signal is converted to the potential (VXb) of node M1.

[0286] After that, in a period T6, the control signal SEL is set to a high level potential, A state of conduction is established between the first terminal and the second terminal in the path. At this time, the control signal RD is The control signal WE remains at a low level potential. The resistor 709 remains in the off state. Then, the second terminal of the switch 703 and the A signal corresponding to the potential of the first terminal of the switch 704 (the potential of the node M1 (VXb)) is The inverted signal can be input to the circuit 701 via the element 706 . In this way, the circuit 701 stores the data that was held before the supply of the power supply voltage to the memory element 700 was stopped. The data (dataX) can be retained again.

[0287] In addition, the potential of the node M1 is set to a constant potential (FIG. 29) by the precharge operation at T4. Then, after the voltage Vdd is applied to the power supply, at T5, the voltage Vxb corresponding to the data (dataX) Since the precharge operation is performed, the potential of the node M1 is set to a predetermined potential VXb. In this way, the time required for the circuit 701 to be turned on after the power supply voltage is resumed can be shortened. This can shorten the time it takes to restore the original data.

[0288] This completes the description of the method for driving the memory element.

[0289] In a method for driving a semiconductor device according to one embodiment of the present invention, a power supply voltage is supplied to the memory element 700. While the data stored in the circuit 701 is not being read, the data stored in the circuit 702 is It can be retained by 08.

[0290] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 709, the memory element 70 The signal held in the capacitor 708 is maintained for a long period of time even while the power supply voltage is not supplied to the capacitor 708. In this way, the memory element 700 can retain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to retain it.

[0291] In addition, by providing the switches 703 and 704, the precharger Since the memory element is characterized by performing a write operation, after the supply of the power supply voltage is resumed, the circuit 701 This can shorten the time it takes to restore the original data.

[0292] In the circuit 702, the signal held by the capacitor 708 is Therefore, after the supply of the power supply voltage to the memory element 700 is resumed, The signal held by the capacitor 708 is input to the transistor 710 in the on state (or The capacitance element 702 can be read out by converting the capacitance element 702 to a positive or negative state (OFF state). Even if the potential corresponding to the signal held in 08 fluctuates slightly, the original signal can be read out accurately. It is possible.

[0293] Such a memory element 700 may be a memory such as a register or cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the device can quickly return to the state it was in before the power supply was stopped. Therefore, the entire processor, or one of the components of the processor, or Power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. It is possible to do so.

[0294] Here, we have taken the CPU as an example, but the same can also be said for DSP (Digital Signal Processor). processor), custom LSI, FPGA (Field Programmable Gauge It can also be applied to LSIs such as MOSFET's (MOSFET gate arrays).

[0295] (Embodiment 9) In this embodiment, the transistors described in the first, third and fourth embodiments and the transistors described in the sixth and seventh embodiments are Electronic device capable of using the storage device described above or the CPU described in the eighth embodiment An example of the above will be described.

[0296] The transistor described in the first, third, or fourth embodiment, the memory device described in the sixth or seventh embodiment, Alternatively, the CPU described in the eighth embodiment can be applied to various electronic devices (including gaming machines). The electronic devices include televisions, monitors, and other display devices, lighting devices, and personal computers. computers, word processors, image playback devices, portable audio players, Geo, tape recorder, stereo, telephone, cordless telephone, mobile phone, car phone, truck transceivers, walkie-talkies, game consoles, calculators, personal digital assistants, electronic organizers, electronic books, electronic translators, Voice input devices, video cameras, digital still cameras, electric shavers, IC chips, electronic Microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, air conditioners air conditioning equipment, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, Vacuum freezers, electric refrigerator-freezers, freezers for DNA storage, radiation measuring devices, dialysis machines, X-ray diagnostic equipment In addition, smoke detectors, heat detectors, gas alarms, security alarms, etc. In addition, emergency lights, traffic lights, conveyor belts, elevators, etc. Examples of industrial equipment include elevators, escalators, industrial robots, and power storage systems. In addition, the vehicle is propelled by an engine using fuel or an electric motor using power from a non-aqueous secondary battery. Mobile objects and the like are also included in the category of electronic devices. Automobiles (EV), hybrid vehicles (HEV) that combine internal combustion engines and electric motors, plug-in Hybrid vehicles (PHEVs), tracked vehicles that use these tires and wheels as tracks, electric a Motorbikes, including self-propelled bicycles, motorcycles, electric wheelchairs, golf carts, small or or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes and planets Examples of electronic devices include probes and spacecraft. Some specific examples of these electronic devices are shown in Figure 30.

[0297] The alarm device 8100 shown in FIG. 30(A) is a residential fire alarm, and includes a smoke or heat detection unit. 8102 and an example of an electronic device using a microcomputer 8101. The computer 8101 may include the transistor, the memory device, or the CPU shown in the above embodiment. Includes.

[0298] In addition, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 shown in FIG. The integrator may be an electronic device including the transistor, memory device, or CPU described in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU, In FIG. 30A, the CPU 8203 is provided in the indoor unit 8200. In this example, the CPU 8203 is provided in the outdoor unit 8204. Alternatively, a CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The transistor described in the above embodiment may be incorporated in a CPU of an air conditioner. By using this, power consumption can be reduced.

[0299] In addition, the electric refrigerator-freezer 8300 shown in FIG. 30(A) is a transistor shown in the above embodiment. An example of an electronic device that includes a processor, a memory device, or a CPU is an electric refrigerator-freezer. 8300 is a housing 8301, a refrigerator door 8302, a freezer door 8303, and a CPU 8304. In FIG. 30A, a CPU 8304 is provided inside a housing 8301. The transistor described in the above embodiment is applied to a CPU 8304 of an electric refrigerator-freezer 8300. Its use can help save energy.

[0300] 30(B) and (C) show an example of an electric vehicle, which is an example of an electronic device. A secondary battery 9701 is mounted on the car 9700. The power of the secondary battery 9701 is supplied to a circuit The output is adjusted by 9702 and supplied to a driver 9703. The computer is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc., not shown. By using the transistor described in the embodiment for the CPU of the electric vehicle 9700, Electrification is possible.

[0301] The driving device 9703 is a DC motor or an AC motor alone, or a motor and an internal combustion engine, The processing device 9704 is configured by combining the above. Information on driving (acceleration, deceleration, stopping, etc.) and information on driving (uphill and downhill slopes, etc., Based on input information (load information, etc.), the circuit 9702 outputs a control signal. The electric energy supplied from the secondary battery 9701 is controlled by a control signal from the processor 9704. The output of the drive unit 9703 is controlled by adjusting the speed. Although not shown, it also has a built-in inverter that converts direct current to alternating current.

[0302] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0303] (Embodiment 10) The conductive film disclosed in the above embodiment can be formed by a sputtering method. Alternatively, the insulating layer may be formed by other methods, such as a thermal CVD method. D(Metal Organic Chemical Vapor Depositio n) method or ALD (Atomic Layer Deposition) method may also be used. .

[0304] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0305] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The film is formed by feeding the gas into the chamber, reacting it near or on the substrate, and depositing it on the substrate. It is also possible.

[0306] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It is possible to form various films such as conductive films and semiconductor films. For example, InGaZnO X (X> 0) When forming a film, trimethylindium, trimethylgallium, and diethyl Zinc is used. The chemical formula for trimethylindium is (CH3)3In. The chemical formula for trimethylgallium is (CH3)3Ga. The chemical formula for dimethylzinc is The formula is (CH3)2Zn. In addition, it is not limited to these combinations, and trimethyl gas is also available. Triethylgallium (chemical formula (C2H5)3Ga) can be used instead of lithium. Diethylzinc (chemical formula (C2H5)2Zn) can be used instead of dimethylzinc. .

[0307] For example, when forming a hafnium oxide film, a liquid containing a solvent and a hafnium precursor compound is Hafnium alkoxide solution, typically tetrakisdimethylamidohafnium (T Two types of gases are used: vaporized DMAH) as the raw material gas and ozone (O3) as the oxidizing agent. The chemical formula for tetrakisdimethylamidohafnium is Hf[N(CH3)2]4. Other material liquids include tetrakis(ethylmethylamido)hafnium. There is.

[0308] For example, when forming an aluminum oxide film, a solvent and an aluminum precursor compound are used. The raw material gas is made by vaporizing a liquid containing dimethyl ether (DMEA) and an oxidizing agent. Two types of gases, H2O and HO, are used. The chemical formula for trimethylaluminum is Al(CH 3) 3. Other material liquids include tris(dimethylamido)aluminum, Triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3, 5-heptanedionate).

[0309] For example, when forming a silicon oxide film, hexachlorodisilane is adsorbed on the film formation surface. This removes the chlorine contained in the adsorbed matter and provides radicals of oxidizing gases (O2, nitrous oxide). is fed to react with the adsorbate.

[0310] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing B2H6 gas and WF6 Gas and H2 gas are introduced simultaneously to form a tungsten film. Note that instead of B2H6 gas, Alternatively, SiH4 gas may be used. [Explanation of symbols]

[0311] 100 Transistors 102 Transistor 110 Substrate 120 Undercoat insulating film 130 Oxide semiconductor layer 131 First oxide semiconductor layer 132 Second oxide semiconductor layer 133 Third oxide semiconductor layer 134 areas 135 Boundary 140 Source electrode layer 141 First source electrode layer 142 Second source electrode layer 150 Drain electrode layer 151 First drain electrode layer 152 Second drain electrode layer 160 Gate insulating film 170 Gate electrode layer 180 Oxide insulating layer 200 Transistors 202 Transistor 300 Transistors 302 Transistor 400 Transistors 402 Transistor 520 Undercoat insulating film 530 Oxide semiconductor layer 531 First oxide semiconductor layer 532 Second oxide semiconductor layer 533 Third oxide semiconductor layer 540 Source electrode layer 550 Drain electrode layer 560 Gate insulating film 570 Gate electrode layer 580 Oxide Semiconductor Layer 630 Silicon active layer 631 p - type area 632 n + type area 700 memory elements 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logic Elements 707 Capacitive element 708 Capacitive element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 800 Conductive Film 900 areas 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 3000 boards 3001 First Wiring 3002 Second Wiring 3003 Third Wiring 3004 4th Wiring 3005 5th Wiring 3100 Element isolation insulating layer 3150 Insulation layer 3200 Transistors 3250 electrode 3300 Transistors 3400 Capacitive element 4250 memory cells 4300 Transistors 4400 Capacitive element 4500 1st Wiring 4600 Second Wiring 8100 Alarm device 8101 Microcomputer 8102 Detector 8200 indoor unit 8201 Case 8202 Ventilator 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Case 8302 Refrigerator door 8303 Freezer door 8304 CPU 9700 Electric Vehicle 9701 Secondary battery 9702 Circuit 9703 Drive unit 9704 Processing Equipment

Claims

1. A first transistor having a first channel formation region and a first gate electrode above the first channel formation region; a second transistor including: an oxide semiconductor layer having a second channel formation region; a second gate electrode above the second channel formation region; a third gate electrode below the second channel formation region; and a first conductive layer functioning as one of a source electrode and a drain electrode; a second conductive layer having an area overlapping the first conductive layer; a first insulating layer having a region located above the first gate electrode and a region located above the third gate electrode and below the oxide semiconductor layer; a second insulating layer having a region located above the oxide semiconductor layer and below the second gate electrode, the second conductive layer has a region overlapping the first conductive layer with the second insulating layer interposed therebetween; the first conductive layer is electrically connected to the first gate electrode; the first transistor and the second transistor are arranged such that a channel length direction of the first transistor and a channel length direction of the second transistor are aligned along a first direction; the first channel formation region includes crystalline silicon; the oxide semiconductor layer contains In, Ga, and Zn, a region where the second conductive layer and the first conductive layer overlap with each other and the first channel formation region; a length of the second conductive layer in the first direction being greater than a length of the third gate electrode in the first direction;

2. A first transistor having a first channel formation region and a first gate electrode above the first channel formation region; a second transistor including: an oxide semiconductor layer having a second channel formation region; a second gate electrode above the second channel formation region; a third gate electrode below the second channel formation region; and a first conductive layer functioning as one of a source electrode and a drain electrode; a second conductive layer having an area overlapping the first conductive layer; a first insulating layer having a region located above the first gate electrode and a region located above the third gate electrode and below the oxide semiconductor layer; a second insulating layer having a region located above the oxide semiconductor layer and below the second gate electrode, the second conductive layer has a region overlapping the first conductive layer with the second insulating layer interposed therebetween; the first conductive layer is electrically connected to the first gate electrode; the first transistor and the second transistor are arranged such that a channel length direction of the first transistor and a channel length direction of the second transistor are aligned along a first direction; the first channel formation region includes crystalline silicon; the oxide semiconductor layer contains In, Ga, and Zn, a region where the second conductive layer and the first conductive layer overlap with each other and the first channel formation region; a length of the second conductive layer in the first direction is greater than a length of the third gate electrode in the first direction; a length of the third gate electrode in the first direction being greater than a length of the second gate electrode in the first direction;

3. In claim 1 or 2, It has a capacitance element, the first conductive layer functions as one electrode of the capacitor element, The second conductive layer functions as the other electrode of the capacitor.

Images