Semiconductor device

Abstract

To provide a transistor that uses an oxide semiconductor layer having electrical characteristics required in accordance with applications and to provide a semiconductor device having the transistor.SOLUTION: In a bottom-gate-type transistor in which at least a gate electrode layer, a gate insulating film, and a semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers having different energy gaps from each other is used as the semiconductor layer. Oxygen or / and a dopant may be introduced into the oxide semiconductor stacked layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called TFTs) is attracting attention. It is widely used in electronic devices such as ICs and image display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be applied to transistors. Another material that has attracted attention is oxide semiconductors.

[0004] For example, indium (In), gallium (Ga), and nickel are used as the active layer of a transistor. A transistor using an amorphous oxide containing lead (Zn) has been disclosed (see Patent Document 1). ). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0006] If the on-characteristics of a transistor (for example, on-current and field-effect mobility) are improved, the semiconductor device This enables high-speed response and high-speed driving in devices, resulting in higher performance semiconductor devices. On the other hand, in order to reduce the power consumption of a semiconductor device, the off-state current of a transistor must be sufficiently low. In this way, the electrical properties required for a transistor depend on the application and purpose. These electrical properties vary depending on the material and therefore it is beneficial to have more precise control over these properties.

[0007] The threshold voltage of the transistor using an oxide semiconductor for the channel formation region is plotted. This transistor structure can be used to realize a so-called normally-off switching element. The structure and manufacturing method thereof are one of the objectives.

[0008] The transistor has a gate voltage that is as close to 0V as possible to form a positive threshold voltage. If the threshold voltage of the transistor is negative, the gate voltage Even if the voltage is 0V, current flows between the source and drain electrodes, which is called a normally-on state. In LSIs, CPUs, and memories, the electrical characteristics of the transistors that make up the circuits are important. These electrical characteristics are important and affect the power consumption of the semiconductor device. Among the characteristics, the threshold voltage (Vth) is important. Even if the field-effect mobility is high, If the voltage is negative, it is difficult to control the circuit. A transistor in which a channel is formed and a drain current flows is used in integrated circuits of semiconductor devices. This is not suitable for use as a transistor.

[0009] In addition, depending on the material and manufacturing conditions, the manufactured transistor may not be normally off. Even in this case, it is important to approach the normally-off characteristics, and the threshold voltage value is Even if the transistor is normally on, the threshold voltage approaches zero. It is also an object of the present invention to provide a structure and a manufacturing method thereof.

[0010] Furthermore, in order to realize a semiconductor device with higher performance, it is necessary to improve the on-characteristics of the transistor (for example, This configuration improves the current and field-effect mobility, enabling high-speed response and high-speed operation of semiconductor devices. It is also an object of the present invention to provide a method for manufacturing the same.

[0011] As described above, a transistor using an oxide semiconductor layer having electrical properties required for a particular application can be fabricated. An object of the present invention is to provide a transistor and a semiconductor device including the transistor.

[0012] The object is to solve at least one of the above problems. [Means for solving the problem]

[0013] A bottom gate structure in which at least a gate electrode layer, a gate insulating film, and a semiconductor layer are stacked in this order. In a transistor having such a structure, the semiconductor layer has at least two layers with different energy gaps. The oxide semiconductor layer includes an oxide semiconductor layer.

[0014] When the oxide semiconductor stack has a stacked structure of a first oxide semiconductor layer and a second oxide semiconductor layer, In this case, the first oxide semiconductor layer and the second oxide semiconductor layer have their own energy The stacking order is not limited as long as the caps are different. The layer may have a large gap or a small energy gap.

[0015] Specifically, in the stack of oxide semiconductor layers, the energy gap of one of the oxide semiconductor layers is The energy gap of the other oxide semiconductor layer is set to be 3 eV or more, and the energy gap of the other oxide semiconductor layer is set to be less than 3 eV. In this specification, the term "energy gap" refers to "band gap" or " It is used in the same sense as "forbidden band width."

[0016] When the oxide semiconductor stack has a stack structure of three or more layers, all the oxide semiconductor layers are different from each other. The structure may have the same energy gap as the material, or may have approximately the same energy gap as the material. The oxide semiconductor layer may be used in a stack of a plurality of oxide semiconductor layers.

[0017] For example, the oxide semiconductor stack may be formed by stacking a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer. In the stacked structure of oxide semiconductor layers, the energy gap of the second oxide semiconductor layer is set to be larger than that of the first oxide semiconductor layer. The energy gap of the first oxide semiconductor layer is set to be smaller than that of the second oxide semiconductor layer and the third oxide semiconductor layer. The electron affinity of the second oxide semiconductor layer is calculated by comparing the electron affinity of the first oxide semiconductor layer and the electron affinity of the third oxide semiconductor layer. In this case, the electron affinity of the first oxide semiconductor layer and the third oxide semiconductor layer is set to be larger than that of the second oxide semiconductor layer. The energy gap and electron affinity of the semiconductor layer can be made equal. The second oxide semiconductor layer having a small energy gap is formed on the first oxide semiconductor layer having a large energy gap. By using a structure in which the second oxide semiconductor layer is sandwiched between the first oxide semiconductor layer and the second oxide semiconductor layer, the transistor This has the effect of reducing the off-state current (leak current). Here, the electron affinity is the relationship between the vacuum level and This represents the energy difference with the conduction band of an oxide semiconductor.

[0018] In a transistor including an oxide semiconductor layer, the energy gap of the oxide semiconductor layer For example, in a transistor using an oxide semiconductor layer, In a transistor, if the energy gap of the oxide semiconductor layer is small, the on-characteristics (for example, On the other hand, the energy gap of the oxide semiconductor layer is large. If the gate insulating film is thin, the off-state current can be reduced.

[0019] In the case of a single oxide semiconductor layer, the size of the energy gap of the oxide semiconductor layer determines the transistor Since the electrical characteristics of the transistor are almost determined, it is necessary to give the transistor the desired electrical characteristics. It's difficult.

[0020] A stack of oxide semiconductor layers with different energy gaps was used. This allows for more precise control of the electrical characteristics of the transistor, resulting in a desired It is possible to impart electrical properties to the transistor.

[0021] Therefore, it is possible to provide semiconductor devices that meet various purposes, such as high functionality, high reliability, or low power consumption. It is possible.

[0022] One embodiment of the configuration of the invention disclosed in this specification is a gate insulating film formed on a gate electrode layer. A first oxide semiconductor layer and a second oxide semiconductor layer having different energy gaps are formed on the gate insulating film overlapping the electrode layer. an oxide semiconductor stack including the oxide semiconductor layer of 2, and a source electrode layer and a and a drain electrode layer.

[0023] One embodiment of the configuration of the invention disclosed in this specification is a gate insulating film formed on a gate electrode layer. a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer on a gate insulating film overlapping the electrode layer; and a source electrode layer and a gate electrode layer formed on the oxide semiconductor stack. and a drain electrode layer, and the second oxide semiconductor layer is a gate electrode layer of the first oxide semiconductor layer and the third oxide semiconductor layer. Semiconductor device having an energy gap smaller than the energy gap of an oxide semiconductor layer is.

[0024] One embodiment of the configuration of the invention disclosed in this specification is a gate insulating film on a gate electrode layer. A source electrode layer and a drain electrode layer are formed on the insulating film, and a gate insulating film, a source electrode layer, and a drain electrode layer are formed on the insulating film. a first oxide semiconductor layer overlapping the gate electrode layer and having a different energy gap; The semiconductor device includes an oxide semiconductor stack including a first oxide semiconductor layer and a second oxide semiconductor layer.

[0025] One embodiment of the configuration of the invention disclosed in this specification is a gate insulating film on a gate electrode layer. On the insulating film, a source electrode layer and a drain electrode layer are formed, and a gate insulating film overlapping the gate electrode layer is formed. a first oxide semiconductor layer, a second oxide semiconductor layer, and a gate electrode layer on the source electrode layer and the drain electrode layer; and a third oxide semiconductor layer. The energy gap of the first oxide semiconductor layer is smaller than that of the third oxide semiconductor layer. It is a semiconductor device having a gap.

[0026] In the oxide semiconductor stack, the upper oxide semiconductor layer is formed on the upper and side surfaces of the lower oxide semiconductor layer. For example, in the above structure, the first oxide semiconductor layer may be covered with the second oxide semiconductor layer. a structure in which the top and side surfaces of the oxide semiconductor layer are covered by the third oxide semiconductor layer; the upper surface of the oxide semiconductor layer, and the second oxide semiconductor layer (or the first oxide semiconductor layer and The side surfaces of the oxide semiconductor layer (2) can be covered.

[0027] In addition, in the oxide semiconductor stack, a region that does not overlap with the source electrode layer or the drain electrode layer a region having a higher oxygen concentration than a region overlapping with the source electrode layer or the drain electrode layer; It may also be possible to use the following.

[0028] In addition, in the oxide semiconductor stack, a region that does not overlap with the gate electrode layer contains a dopant. The semiconductor device may have a low resistance region.

[0029] In one embodiment of the invention disclosed in this specification, a gate insulating film is formed on a gate electrode layer, A first oxide semiconductor layer having a different energy gap is formed on a gate insulating film overlapping the gate electrode layer. and forming an oxide semiconductor stack including a first oxide semiconductor layer and a second oxide semiconductor layer on the oxide semiconductor stack. The present invention relates to a method for manufacturing a semiconductor device in which a source electrode layer and a drain electrode layer are formed.

[0030] In one embodiment of the invention disclosed in this specification, a gate insulating film is formed on a gate electrode layer, a first oxide semiconductor layer is formed on the gate insulating film overlapping the gate electrode layer; A second oxide semiconductor layer having a smaller energy gap than the first oxide semiconductor layer is formed on the semiconductor layer. a third oxide semiconductor layer having a larger energy gap than the second oxide semiconductor layer; and forming a source electrode layer and a drain electrode layer on the oxide semiconductor stack. This is a method for manufacturing a semiconductor device in which a pole layer is formed.

[0031] In one embodiment of the invention disclosed in this specification, a gate insulating film is formed on a gate electrode layer, A source electrode layer and a drain electrode layer are formed on the gate insulating film, and a gate electrode layer overlapping the gate electrode layer is formed. A first oxide film having different energy gaps is formed on the insulating film, the source electrode layer, and the drain electrode layer. US201301292333A1 - Method for fabricating a semiconductor device having an oxide semiconductor stack including a first oxide semiconductor layer and a second oxide semiconductor layer - Google Patents This is the manufacturing method.

[0032] In one embodiment of the invention disclosed in this specification, a gate insulating film is formed on a gate electrode layer, A source electrode layer and a drain electrode layer are formed on the gate insulating film, and a gate electrode layer overlapping the gate electrode layer is formed. A first oxide semiconductor layer is formed over the insulating film, the source electrode layer, and the drain electrode layer. A second oxide semiconductor layer having a smaller energy gap than the first oxide semiconductor layer is formed on the oxide semiconductor layer. a third oxide semiconductor layer having a larger energy gap than the second oxide semiconductor layer; The present invention relates to a method for manufacturing a semiconductor device in which semiconductor layers are formed to form a stack of oxide semiconductor layers.

[0033] In addition, a dopant is selectively introduced into the oxide semiconductor stack, and a channel is formed in the oxide semiconductor stack. The low-resistance region containing dopants has a lower resistance than the channel-forming region and is sandwiched between the panel-forming region. The dopant is an impurity that changes the electrical conductivity of the oxide semiconductor stack. Dopant introduction methods include ion implantation, ion doping, plasma imaging, and For example, a ion implantation method can be used.

[0034] The semiconductor device has a stack of oxide semiconductor layers including a low-resistance region sandwiching a channel formation region in the channel length direction. As a result, the transistor has high on-state characteristics (for example, on-state current and field-effect mobility). This enables high-speed operation and high-speed response.

[0035] Further, heat treatment (dehydration or dehydrogenation treatment) for releasing hydrogen or water from the oxide semiconductor layer may be performed. The dehydration or dehydrogenation treatment may also be used as a heat treatment to form a mixed region. In addition, when a crystalline oxide semiconductor layer is used as the oxide semiconductor layer, the mixed region The heat treatment for forming the film can also serve as a heat treatment for crystallization.

[0036] Furthermore, the dehydration or dehydrogenation treatment can remove oxygen, which is a main component material of the oxide semiconductor. In the oxide semiconductor film, oxygen is released and the amount of oxygen is reduced. Oxygen vacancies exist in the areas where the oxide has been removed, and these oxygen vacancies cause fluctuations in the electrical characteristics of the transistor. Therefore, a donor level is generated.

[0037] Therefore, oxygen is preferably supplied to the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment. By supplying oxygen to the oxide semiconductor layer, oxygen vacancies in the film can be filled. Cut.

[0038] For example, an oxide insulating film containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, may be used as an oxide semiconductor layer. By providing the oxide insulating film in contact with the oxide semiconductor layer, oxygen can be supplied from the oxide insulating film to the oxide semiconductor layer. In the above structure, the oxide semiconductor is subjected to a heat treatment as a dehydration or dehydrogenation treatment. The oxide insulating film is oxidized by performing a heat treatment while the oxide insulating film and the film are at least partially in contact with each other. Oxygen may be supplied to the compound semiconductor layer.

[0039] Further, the oxide semiconductor layer that has been subjected to the dehydration or dehydrogenation treatment is not subjected to oxygen (at least oxygen radicals). Oxygen may be supplied to the film by introducing oxygen atoms or oxygen ions. The oxygen introduction method includes ion implantation, ion doping, plasma immersion, and The ion implantation method, plasma treatment, etc. can be used.

[0040] Furthermore, the oxide semiconductor layer provided in the transistor is preferably a crystalline oxide semiconductor. The film contains a region in which the oxygen content is excessive relative to the stoichiometric composition ratio in the state. In this case, the oxygen content is preferably the content in the stoichiometric composition ratio of the oxide semiconductor. Alternatively, the oxygen content is set to a level exceeding that of a single crystal. Oxygen may exist between the lattices of oxide semiconductors.

[0041] Hydrogen or water is removed from the oxide semiconductor, and the oxide semiconductor is highly purified to minimize the amount of impurities contained therein. By supplying oxygen to compensate for oxygen vacancies, an I-type (intrinsic) oxide semiconductor or an I-type ( By doing so, it is possible to obtain an oxide semiconductor that is as close to intrinsic as possible. It is possible to make the Fermi level (Ef) of a conductor the same as the intrinsic Fermi level (Ei). Therefore, by using the oxide semiconductor layer in a transistor, the oxide semiconductor layer can be effectively prevented from being generated due to oxygen vacancies. To reduce the variation in the threshold voltage Vth of transistors and the threshold voltage shift ΔVth It is possible.

[0042] One embodiment of the present invention is a transistor or a circuit including a transistor. For example, the present invention relates to a semiconductor device, a transistor in which a channel formation region is formed of an oxide semiconductor, The present invention relates to a semiconductor device having a circuit including a transistor. , LSI, CPU, power devices mounted on power supply circuits, memory, thyristors, converters, semiconductor integrated circuits including image sensors, and electronic devices such as liquid crystal display panels. The present invention relates to electronic equipment that incorporates, as a component, a light-emitting display device having an electro-optical device or a light-emitting element. [Effects of the Invention]

[0043] A stack of oxide semiconductor layers with different energy gaps was used. This allows for more precise control of the electrical characteristics of the transistor, resulting in a desired It is possible to impart electrical properties to the transistor.

[0044] Therefore, it is possible to provide semiconductor devices that meet various purposes, such as high functionality, high reliability, or low power consumption. It is possible. [Brief explanation of the drawings]

[0045] [Figure 1] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 2] 1A to 1C illustrate one embodiment of a semiconductor device and a manufacturing method thereof; [Figure 3] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 4] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 5] 1A to 1C illustrate one embodiment of a semiconductor device and a manufacturing method thereof; [Figure 6] 1A to 1C illustrate one embodiment of a semiconductor device and a manufacturing method thereof; [Figure 7] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 8] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 9] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 10] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 11] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 12] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 13] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 14] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 15] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 16] 1A and 1B are diagrams illustrating electronic devices. [Figure 17] TEM photographs and schematic diagrams of the samples in Example 1. [Figure 18] TEM photographs and schematic diagrams of the samples in Example 1. [Figure 19] FIG. 1 is a diagram showing ionization potential. [Figure 20] FIG. 1 is a diagram showing an energy band diagram. [Figure 21] FIG. 1 is a diagram showing ionization potential. [Figure 22] FIG. 1 is a diagram showing an energy band diagram. [Figure 23] FIG. 10 is a graph showing off-state current values ​​of transistors. [Figure 24] 10A and 10B are graphs showing field-effect mobility of transistors. [Figure 25] FIG. 10 is a graph showing off-state current values ​​of transistors. [Figure 26] 10A and 10B are graphs showing field-effect mobility of transistors. DETAILED DESCRIPTION OF THE INVENTION

[0046] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the accompanying drawings. However, the invention disclosed in this specification is not limited to the following description, and various forms and details may be used. It will be readily understood by those skilled in the art that the invention disclosed in this specification can be modified in any manner. The present invention is not limited to the following embodiments. The ordinal numbers such as 2 are used for convenience and do not indicate the order of processes or stacking. Furthermore, the present specification does not indicate specific names as matters for identifying the invention. do not have.

[0047] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor having an oxide semiconductor film will be described as an example of a semiconductor device. This indicates a transistor.

[0048] The transistor may have a single gate structure in which one channel formation region is formed, or two gate structures in which two channel formation regions are formed. The gate structure may be a double gate structure in which three gates are formed, or a triple gate structure in which three gates are formed. The semiconductor device has two gate electrode layers arranged above and below the channel forming region with a gate insulating film interposed therebetween. A dual gate type may also be used.

[0049] The transistor 440a and the transistor 440b shown in FIGS. 1A and 1B are bottom gate 1 is an example of an inverted staggered transistor having a structure.

[0050] As shown in FIGS. 1A and 1B, the transistor 440a and the transistor 440b are insulated A gate electrode layer 401 and a gate insulating film 402 are provided in this order on a substrate 400 having a surface. The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 have different energy gaps. 02, a source electrode layer 405a, and a drain electrode layer 405b. An insulating film 407 is formed over the transistor 440a and the transistor 440b. are.

[0051] In FIG. 1, the interface between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 is shown by a dotted line, which is a schematic representation of the oxide semiconductor stack 403. Depending on the material, film formation conditions, and heat treatment, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 may be separated. In some cases, the interface between the oxide layer 102 and the oxide layer 102 may become unclear. A mixed region or layer of the semiconductor layer may be formed. The same applies to the other drawings in this specification.

[0052] For example, a mixed region 101 is formed between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102. A transistor 449 having 05 is shown in FIG.

[0053] In the oxide semiconductor stack 403 of the transistor 449, the first oxide semiconductor layer 101 and the The interface between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 is unclear. The mixed region 105 is formed between the first oxide semiconductor layer 102 and the second oxide semiconductor layer 102. Note that the interface is unclear when For example, cross-sectional observation of the oxide semiconductor stack 403 using a high-resolution transmission electron microscope (TEM image) When a clear, continuous, linear interface cannot be observed between the stacked oxide semiconductor layers, Refers to...

[0054] The mixed region 105 is formed by stacking the first oxide semiconductor layer 101 and the second oxide semiconductor layer 10 2 are mixed, and the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are mixed. The oxide semiconductor layer 102 is different from the oxide semiconductor layer 101 in at least the composition of constituent elements. 403 is a first oxide semiconductor layer containing indium, tin, and zinc and a second oxide semiconductor layer containing indium, gallium, and zinc. In the case of using a stacked structure of a first oxide semiconductor layer containing aluminum and a second oxide semiconductor layer containing zinc, a mixture containing indium, tin, gallium, and zinc between the first oxide semiconductor layer and the second oxide semiconductor layer; The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 can be formed. The mixed region 105 contains the same elements as the semiconductor layer 102 but has a different composition (composition ratio). Therefore, the energy gap of the mixed region 105 can be formed as follows. The energy gaps of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are different. The energy gap of the mixed region 105 is The energy gap of the oxide semiconductor layer 102 is between the energy gap of the oxide semiconductor layer 102 and the energy gap of the second oxide semiconductor layer 102.

[0055] Therefore, by providing the mixed region 105, the oxide semiconductor stack 403 has an energy band diagram The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are stacked in a continuous junction. It is possible to suppress scattering at the interface of the layer 102. It is possible to suppress interface scattering. Therefore, the transistor 449 including the oxide semiconductor stack 403 in which the mixed region 105 is provided can improve the field effect mobility.

[0056] By providing the mixed region 105, the first oxide semiconductor layer 10 A gradient can be formed between the first and second oxide semiconductor layers 101 and 102. The gradient can be a multi-step gradient. may be.

[0057] The first oxide semiconductor layer 101, the mixed region 105, and the second oxide semiconductor layer 102 The interface is shown by a dotted line, but this is because the interface is unclear in the oxide semiconductor stack 403 ( This is a schematic diagram showing that the

[0058] The mixed region 105 is formed by performing heat treatment on the oxide semiconductor stack 403 including the plurality of oxide semiconductor layers. The heat treatment is performed to remove elements contained in the oxide semiconductor layer. The temperature is set to a temperature at which the oxide semiconductor layer can be diffused by heat, and the oxide semiconductor layer to be laminated is set to a temperature at which the oxide semiconductor layer can be diffused by heat. The process is carried out under conditions that do not result in a mixed region with a uniform composition (composition ratio).

[0059] In the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor The layers 102 may be stacked in any order as long as they have different energy gaps. I can't.

[0060] Specifically, in the oxide semiconductor stack 403, the energy gap between one of the oxide semiconductor layers is the energy gap of the other oxide semiconductor layer is set to 3 eV or more, and the energy gap of the other oxide semiconductor layer is set to less than 3 eV. .

[0061] The transistor 440a illustrated in FIG. 1A has a second oxide semiconductor layer formed on the first oxide semiconductor layer 101. In this example, the compound semiconductor layer 102 has a larger energy gap than the compound semiconductor layer 102. The first oxide semiconductor layer 101 in the transistor 440a is formed of an In—Sn—Zn-based oxide. oxide film (energy gap 2.6 eV to 2.9 eV, typically 2.8 eV), The oxide semiconductor layer 102 is an In-Ga-Zn oxide film (energy gap 3.0 eV to 3.4 eV, typically 3.2 eV) is used.

[0062] On the other hand, the transistor 440b illustrated in FIG. 1B has a second oxide semiconductor layer 101 and a second oxide semiconductor layer 102. In this example, the oxide semiconductor layer 102 has a smaller energy gap than the oxide semiconductor layer 102 in this embodiment. In the transistor 440b, the first oxide semiconductor layer 101 is made of In-Ga-Z The second oxide semiconductor layer 102 is an n-type oxide film (energy gap 3.2 eV). An In-Sn-Zn oxide film (energy gap 2.8 eV) is used.

[0063] In this manner, in the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are The oxide semiconductor layer 102 has a larger energy gap on the side in contact with the gate insulating film 402. It may be a layer having a small energy gap.

[0064] In FIG. 4A, the oxide semiconductor stack 403 includes a first oxide semiconductor layer 101 and a second oxide semiconductor layer 102. A transistor using a three-layer stack of a semiconductor layer 102, a third oxide semiconductor layer 103, and a second oxide semiconductor layer 104. 480 is shown.

[0065] The transistor 480 includes a gate electrode layer 401 and a gate insulating layer 402, which are provided in sequence on a substrate 400 having an insulating surface. 401, a gate insulating film 402, a first oxide semiconductor layer 101, a second oxide semiconductor layer 10 the oxide semiconductor stack 403 including the second and third oxide semiconductor layers 103, the source electrode layer 40 The transistor 480 has a drain electrode layer 405a and a drain electrode layer 405b. It has been completed.

[0066] In the oxide semiconductor stack 403 of the transistor 480, the first oxide semiconductor layer 101, The energy gaps of the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103 are They are not all the same and contain at least two different energy gap values.

[0067] When the oxide semiconductor stack 403 has a stacked structure of three or more layers, all of the oxide semiconductor layers The energy gaps may be different, or may be approximately the same. The oxide semiconductor stack 403 may include an oxide semiconductor layer having a groove.

[0068] FIG. 9A illustrates a transistor 410 as another mode of a semiconductor device. The sta 410 is a bottom gate type called a channel protection type (also called a channel stop type). This is one type of structure and is also called an inverted staggered transistor.

[0069] As shown in FIG. 9A, a transistor 410 is formed on a substrate 400 having an insulating surface. The gate electrode layer 401, the gate insulating film 402, and the second gate insulating film 403 having different energy gaps are provided. An oxide semiconductor stack 40 including a first oxide semiconductor layer 101 and a second oxide semiconductor layer 102 3, an insulating film 427, a source electrode layer 405a, and a drain electrode layer 405b. An insulating film 409 is formed on the sta 410 .

[0070] The insulating film 427 is provided over the oxide semiconductor stack 403 overlapping with the gate electrode layer 401. It functions as a channel protection film.

[0071] The insulating film 427 may be formed using a material and a method similar to those of the insulating film 407. A typical example of the insulating film 427 is an oxide film. Silicon film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, silicon oxide film gallium oxide film, silicon nitride film, aluminum nitride film, silicon nitride oxide film Single layer or multilayer of inorganic insulating films such as aluminum oxide nitride film, aluminum oxide film, etc. can be used.

[0072] The insulating film 427 (when the insulating film 427 has a stacked-layer structure, When the oxide semiconductor stack 403 is made to contain a large amount of oxygen, the oxide semiconductor stack It can suitably function as a source of oxygen to supply layer 403 .

[0073] The insulating film 409 can be formed using a material and a method similar to those of the insulating film 407. .

[0074] As another example of the semiconductor device, a bottom-gate transistor 4 shown in FIG. Shows 30.

[0075] As shown in FIG. 10A, a transistor 430 is formed on a substrate 400 having an insulating surface. A gate electrode layer 401, a gate insulating film 402, a source electrode layer 405a, and a drain electrode layer 406 are provided on the substrate. the first oxide semiconductor layer 101 and the second oxide semiconductor layer 405b, which have different energy gaps; The transistor 430 includes an oxide semiconductor stack 403 including the oxide semiconductor layer 102. An insulating film 407 is formed on the insulating film 407 .

[0076] The transistor 430 includes an energy storage device (E2) on the source electrode layer 405a and the drain electrode layer 405b. The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 have different gate gaps. The oxide semiconductor stack 403 is provided.

[0077] The oxide semiconductor stack 403 (the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, The oxide semiconductor used for the third oxide semiconductor layer 103) is at least indium ( It is preferable that the material contains In (In) or zinc (Zn). It is particularly preferable that the material contains In and Zn. In addition, a stabilizer for reducing variations in the electrical characteristics of a transistor using the oxide is also provided. It is preferable to have gallium (Ga) as an additive in addition to these. It is preferable to have tin (Sn) as a riser. It is preferable that the alloy contains aluminum (A) as a stabilizer. It is preferable to have zirconium (Zr) as a stabilizer. It is preferable that

[0078] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0079] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides Oxides such as In-Ga-Zn oxides, In-Al-Zn oxides, and In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides Oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides , In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxides and In-Hf-Ga-Zn oxides, which are oxides of the base metals oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn In-Hf-Zn based oxides and In-Hf-Al-Zn based oxides can be used.

[0080] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than a and Zn may be included.

[0081] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In2SnO5 (ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0082] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn oxide with a molecular ratio or an oxide with a composition close to that.

[0083] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the following appropriate.

[0084] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0085] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1) is close to the oxide composition by r, and a, b, and c are (aA) 2 +(bB ) 2 +(cC) 2 ≦r 2 For example, if r is set to 0.05, The same is true for other oxides.

[0086] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. In addition, it may be a structure containing a crystalline portion in an amorphous state or a non-amorphous state. That's fine too.

[0087] Amorphous oxide semiconductors can be easily flattened, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high efficiency. High mobility can be obtained.

[0088] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form it on the surface of 0.1 nm or less.

[0089] Note that Ra is defined in JIS B0601:2001 (ISO4287:1997). It is a three-dimensional extension of the arithmetic mean roughness, which is currently used, so that it can be applied to curved surfaces. It can be expressed as "the average of the absolute values ​​of the deviations from the surface to the specified surface" and is defined by the following formula.

[0090]

number

[0091] Here, the specified surface is the surface to be measured for roughness, and has coordinates ((x1, y1, f(x1, y1)),(x1,y2,f(x1,y2)),(x2,y1,f(x2,y1)),( The specified surface is the xy plane, and the rectangular area is represented by four points x2, y2, f(x2, y2)). The area of ​​the rectangle projected onto the surface is S0, and the average height of the specified surface is Z0. Ra is the atomic force microscope This can be measured using an AFM (Atomic Force Microscope).

[0092] The oxide semiconductor stack 403 (the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, The third oxide semiconductor layer 103) is an oxide semiconductor layer containing crystals and having crystallinity (crystal The crystalline state of the crystalline oxide semiconductor layer can be The crystal axes may be in a random state or may have a certain orientation.

[0093] For example, the crystalline oxide semiconductor layer may be formed of an oxide semiconductor containing crystals having a c-axis approximately perpendicular to the surface. A nitride semiconductor layer can be used.

[0094] The oxide semiconductor layer including crystals having a c-axis approximately perpendicular to the surface does not have a single-crystal structure, but has a It is not an amorphous structure, but a crystalline oxide semiconductor with c-axis orientation (C Axis Aligned Crystalline Oxide Semiconductor; It is a membrane (also called CAAC-OS).

[0095] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure in which the amorphous phase contains crystalline and amorphous parts. The crystal part must be small enough to fit inside a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the amorphous part contained in the CAAC-OS film were The boundary between the crystal and the CAAC-OS film is not clear. Therefore, the CAAC-OS film has no grain boundary. The resulting decrease in electron mobility is suppressed.

[0096] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the hole or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. The range of 5° to 95° is also included. This also includes the range of 5° or more and 5° or less.

[0097] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0098] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0099] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0100] There are three methods for obtaining a crystalline oxide semiconductor layer having a c-axis orientation. The oxide semiconductor layer is formed at a film formation temperature of 200° C. to 500° C., and the surface is roughly The second method is to form a thin film and then heat it at 200°C or higher for 70 The third method is to align the c-axis approximately perpendicular to the surface by heat treatment at 0°C or below. After forming a thin film of the first layer, heat treatment is performed at 200℃ to 700℃. This method involves forming a film and orienting the c-axis approximately perpendicular to the surface.

[0101] A first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 10 The thickness of the film 3 is 1 nm or more and 10 nm or less (preferably 5 nm or more and 30 nm or less), and the thickness of the film 3 is 1 nm or more and 10 nm or less (preferably 5 nm or more and 30 nm or less). tarring method, MBE (Molecular Beam Epitaxy) method, CVD method , pulsed laser deposition method, ALD (Atomic Layer Deposition) method The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 can be formed of, for example, a SiO 2 film or the like. The layer 102 and the third oxide semiconductor layer 103 are approximately Even if a film is formed using a sputtering device that performs film formation on multiple substrate surfaces set vertically, good.

[0102] In a transistor including an oxide semiconductor layer, the energy gap of the oxide semiconductor layer For example, in a transistor using an oxide semiconductor layer, In a transistor, if the energy gap of the oxide semiconductor layer is small, the on-characteristics (for example, On the other hand, the energy gap of the oxide semiconductor layer is large. If the gate insulating film is thin, the off-state current can be reduced.

[0103] Oxide semiconductor stack 40 using multiple oxide semiconductor layers having different energy gaps 3, transistor 440a, transistor 440b, transistor The electrical characteristics of the transistor 480 can be controlled more precisely, and the desired electrical characteristics can be obtained by 40a, transistor 440b, and transistor 480.

[0104] For example, in the oxide semiconductor stack 403 of the transistor 480 illustrated in FIG. 4A, The energy gap of the oxide semiconductor layer 102 is set to be equal to that of the first oxide semiconductor layer 101 and the third oxide semiconductor layer 102. The energy gap of the first oxide semiconductor layer 103 is set to be smaller than that of the oxide semiconductor layer 103. The energy gaps of the conductor layer 101 and the third oxide semiconductor layer 103 are set to be approximately the same. This can be done.

[0105] Figure 4(C) shows the energy band diagram in the film thickness direction (between E1 and E2) in Figure 4(A). In the transistor 480, the first The first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 10 However, if a buried channel is formed in the conduction band, In order to obtain a sufficient effect, it is not necessary to have depressions in both the conduction band and the valence band as shown in Figure 4(C). For example, the energy band diagram may be an energy band diagram having a depression only in the conduction band. The configuration may be such that an energy band diagram can be obtained.

[0106] For example, the first oxide semiconductor layer 101 in the transistor 480 may be formed of In-Ga-Z The second oxide semiconductor layer 102 is an n-type oxide film (energy gap 3.2 eV). In-Sn-Zn oxide film (energy gap 2.8 eV), third oxide semiconductor layer An In-Ga-Zn oxide film (energy gap 3.2 eV) is used as 103.

[0107] The three-layer oxide semiconductor stack 403 in the transistor 480 may be formed as follows: The first oxide semiconductor layer 101 is an In-Ga-Zn oxide film, and the second oxide semiconductor layer The third oxide semiconductor layer 102 is an In-Zn oxide film, and the third oxide semiconductor layer 103 is an In-Ga- a Ga-Zn-based oxide film as the first oxide semiconductor layer 101; The oxide semiconductor layer 102 is an In—Sn—Zn-based oxide film, and the third oxide semiconductor layer 1 03 as a stack of Ga-Zn oxide films, and Ga-Zn as a first oxide semiconductor layer. a Zn-based oxide film as the second oxide semiconductor layer 102; an In—Zn-based oxide film as the third oxide semiconductor layer 103; The semiconductor layer 103 is a stack of Ga—Zn-based oxide films, and the first oxide semiconductor layer 101 is a In-Ga-based oxide film, In-Ga-Zn-based oxide as the second oxide semiconductor layer 102 a stack of an In-Ga-based oxide film as the third oxide semiconductor layer 103, or a stack of an In-Ga-based oxide film as the first oxide semiconductor layer The semiconductor layer 101 is an In-Ga-Zn oxide film, and the second oxide semiconductor layer 102 is an In-Ga-Zn oxide film. The third oxide semiconductor layer 102 is an In-Ga- A stack of Zn-based oxide films can be used.

[0108] The second oxide semiconductor layer 102 having a small energy gap is The first oxide semiconductor layer 101 and the third oxide semiconductor layer 103 sandwich the insulating film. This can further reduce the off-state current (leakage current) of the transistor 480. do.

[0109] An example of a manufacturing method using the transistor 440a is shown in FIGS.

[0110] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 401 is formed by a process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0111] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In either case, it is necessary to have heat resistance to the extent that it can withstand subsequent heat treatment. Glass substrates such as aluminoborosilicate glass and aluminoborosilicate glass, ceramic substrates, A quartz substrate, a sapphire substrate, etc. can be used. Also, silicon or silicon carbide substrates can be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium A substrate, an SOI substrate, or the like can also be used, and a semiconductor element is provided on such a substrate. may be used as the substrate 400.

[0112] Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture a semiconductor device, a transistor including an oxide semiconductor stack 403 is formed over a flexible substrate. The gate 440a may be directly formed, or a gate including the oxide semiconductor stack 403 may be formed on another substrate. The transistor 440a may be fabricated, and then peeled off and transferred to a flexible substrate. In order to peel and transfer the transistor from the substrate to a flexible substrate, A release layer may be provided between the substrate 440a and the heat sink 440b.

[0113] An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 401. , which has the function of preventing the diffusion of impurity elements from the substrate 400, and The insulating film is made of one or more films selected from a silicon film, a silicon nitride oxide film, and a silicon oxynitride film. The base film can be formed by a laminated structure. Formed using aluminum nitride, hafnium oxide, gallium oxide, or a mixture of these materials The undercoat film can be formed by plasma CVD or sputtering. good.

[0114] The material of the gate electrode layer 401 is formed by plasma CVD or sputtering. Molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium It is formed in a single layer or laminated form using metal materials such as aluminum or alloy materials that contain these as the main components. The gate electrode layer 401 can be formed by doping an impurity element such as phosphorus. Semiconductor films, such as polycrystalline silicon films, and silicide films, such as nickel silicide, are used. The gate electrode layer 401 may have either a single-layer structure or a stacked-layer structure.

[0115] The gate electrode layer 401 is made of an indium tin oxide or an indium oxide containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, silicon oxide Conductive materials such as indium tin oxide doped with the above-mentioned conductive material can also be used. It is also possible to use a laminated structure of an electrically conductive material and the above-mentioned metal material.

[0116] The gate electrode layer 401 has a laminated structure, and one layer of the layer is made of In—Sn-based -Zn series, In-Al-Zn series, Sn-Ga-Zn series, Al-Ga-Zn series, Sn-Al -Zn-based, In-Zn-based, Sn-Zn-based, Al-Zn-based, In-based, Sn-based, and Zn-based metals An oxide may also be used.

[0117] In addition, a layer of the gate electrode layer 401 in contact with the gate insulating film 402 is made of a metal oxide containing nitrogen. oxides, specifically, nitrogen-containing In-Ga-Zn-O films and nitrogen-containing In-Sn-O films , In-Ga-O films containing nitrogen, In-Zn-O films containing nitrogen, and Sn- O film, In-O film containing nitrogen, and metal nitride film (InN, SnN, etc.) can be used. These films have a resistivity of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, the threshold voltage of the electrical characteristics of a transistor is The voltage can be made positive, and a so-called normally-off switching element can be realized.

[0118] For example, the gate electrode layer 401 may have a laminated structure, and one layer of the laminated structure may be made of a material with a particularly large work function. It is preferable to use an oxynitride film containing indium, gallium, and zinc. The oxynitride film containing gallium, zinc, and gallium was grown under a mixed gas atmosphere of argon and nitrogen. This can be obtained by forming a film using the following method.

[0119] For example, the gate electrode layer 401 may be formed by depositing a copper film, a tungsten film, and an indium film from the substrate 400 side. a laminated structure of a tungsten film and an oxynitride film containing tungsten, gallium, and zinc; A laminated structure of a stainless steel film, a copper film, and a titanium film can be used.

[0120] Next, a gate insulating film 402 is formed over the gate electrode layer 401 (see FIG. 2A). The gate insulating film 402 is formed according to the size of the transistor to be manufactured and the step coverage of the gate insulating film 402. It is preferable to form the insulating film in consideration of the above.

[0121] The thickness of the gate insulating film 402 is set to 1 nm or more and 20 nm or less, and is formed by sputtering or MBE. The method, CVD method, pulsed laser deposition method, ALD method, etc. can be used as appropriate. The insulating film 402 is formed by forming a plurality of substrate surfaces approximately perpendicular to the sputtering target surface. The film may be formed using a sputtering device that performs film formation in a set state.

[0122] The material of the gate insulating film 402 is a silicon oxide film, a gallium oxide film, an aluminum oxide film, or the like. a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or an aluminum nitride film It can be formed using a silicon film.

[0123] The gate insulating film 402 may be made of hafnium oxide, yttrium oxide, or hafnium. Silicate (HfSi x O y x>0, y>0), nitrogen-doped hafnium silicate HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and high-k materials such as lanthanum oxide are used to The current can be reduced.

[0124] The gate insulating film 402 may be a single layer or a stacked layer. In this embodiment, a silicon oxide insulating film is used as the gate insulating film 402. Use a con membrane.

[0125] In addition, when the gate insulating film 402 is a laminated film, for example, a silicon oxide film is formed on the gate electrode layer 401. Alternatively, a silicon film, an In-Hf-Zn-based oxide film, and an oxide semiconductor stack 403 may be stacked in this order. On the gate electrode layer 401, a silicon oxide film and an In:Zr:Zn=1:1:1 atomic ratio were formed. The n-Zr-Zn oxide film and the oxide semiconductor stack 403 may be stacked in this order. On the electrode layer 401, a silicon oxide film, an In-Gd- A Zn-based oxide film and an oxide semiconductor stack 403 may be stacked in this order.

[0126] Next, the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed on the gate insulating film 402. A stack 493 of oxide semiconductor films made of the oxide semiconductor films 92 is formed (see FIG. 2B).

[0127] The gate insulating film 402 is in contact with the stack 493 of oxide semiconductor films (the stack 403 of oxide semiconductor films). Therefore, it is preferable that oxygen exists in the film (bulk) in an amount exceeding the stoichiometric ratio. For example, when a silicon oxide film is used as the gate insulating film 402, SiO 2+α (where α>0). By using such a gate insulating film 402, oxidation Oxygen can be supplied to the oxide semiconductor film stack 493 (oxide semiconductor stack 403), and the characteristics The oxide semiconductor film stack 493 (the oxide semiconductor stack 403) can be favorably By supplying oxygen, oxygen vacancies in the film can be compensated for.

[0128] For example, the gate insulating film 402 containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, is formed as an oxide semiconductor. By providing the gate insulating film 493 in contact with the gate insulating film 493 (the oxide semiconductor stack 403), Oxygen is supplied from the insulating film 402 to the stacked oxide semiconductor film 493 (the stacked oxide semiconductor film 403). The oxide semiconductor film stack 493 (the oxide semiconductor stack 403) and the gate insulating film The insulating film 402 is heated in a state where the insulating film 402 is at least partially in contact with the oxide semiconductor film. Oxygen may be supplied to the stack 493 (the oxide semiconductor stack 403).

[0129] The stack of oxide semiconductor films 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 1 In the step of forming the oxide semiconductor film stack 493 (first oxide semiconductor film 191 and the second oxide semiconductor film 192) to prevent hydrogen or water from being contained in the second oxide semiconductor film 193. 4, a stack of oxide semiconductor films 493 (a first oxide semiconductor film 191 and a second oxide semiconductor film As a pretreatment for forming the gate insulating film 40 in the preheating chamber of the sputtering device, The substrate on which the gate insulating film 402 is formed is preheated to remove hydrogen, water, etc. adsorbed on the substrate and the gate insulating film 402. It is preferable to desorb and exhaust the impurities. Opump is preferred.

[0130] In the gate insulating film 402, the stacked layer 493 of oxide semiconductor films (the stacked layer 403 of oxide semiconductor films) The contact region may be subjected to a planarization treatment. However, polishing processes (e.g., chemical mechanical polishing) Polishing (CMP), dry etching, and plasma treatment are used. It is possible.

[0131] The plasma treatment may be, for example, a reverse plasma treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma near the substrate, thereby modifying the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the cleaning is performed, powdery substances (particles, dust, etc.) adhering to the surface of the gate insulating film 402 are removed. (also called) can be removed.

[0132] As a planarization process, polishing, dry etching, and plasma treatment may be performed multiple times. In addition, when the steps are combined, there is no particular limitation on the order of the steps. It is not limited to this value, and may be set appropriately according to the unevenness of the surface of the gate insulating film 402.

[0133] Note that the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed using oxygen. It is formed by sputtering under conditions where a large amount of oxygen is contained (for example, in an atmosphere of 100% oxygen). The oxide semiconductor is preferably formed in a crystalline state. The film contains a region in which the oxygen content is excessive relative to the stoichiometric composition ratio. preferable.

[0134] In this embodiment, the first oxide semiconductor film 191 is formed by a sputtering method. For example, the target for this purpose is a target having a composition ratio of In:Sn:Zn in atomic ratio. , 1:2:2, 2:1:3, 1:1:1, or 20:45:35, etc. Using the get, an In—Sn—Zn—O film is formed.

[0135] In this embodiment, the second oxide semiconductor film 192 is formed by a sputtering method. For example, the target for this purpose is a composition ratio of In2O3:Ga2O3:Zn. Using an oxide target with a molar ratio of 0 = 1:1:2, an In-Ga-Zn oxide film was formed. The material and composition of the target are not limited to those mentioned above, and examples thereof include In2O3:G A metal oxide target of a2O3:ZnO=1:1:1 [molar ratio] may also be used.

[0136] The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more. By using a metal oxide target with a high filling rate, the film is formed. In addition, the oxide semiconductor film can be a dense film.

[0137] The first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed by a sintering furnace. The sputtering gas is a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. It is preferable to use

[0138] The substrate is held in a film-forming chamber that is kept in a reduced pressure state, and the remaining moisture in the film-forming chamber is removed. The sputtering gas from which hydrogen and water have been removed is introduced, and the substrate 400 is sputtered using the target. On the other hand, a stack of oxide semiconductor films 493 (a first oxide semiconductor film 191 and a second oxide semiconductor film To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. As an exhaust means, a turbo molecular pump with a cold trap added is preferable. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms, water (H 2O) and other compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) are exhausted. Therefore, the stack 493 of oxide semiconductor films formed in the film formation chamber (first oxide semiconductor film 1) The concentration of impurities contained in the oxide semiconductor film 91 and the second oxide semiconductor film 192 can be reduced.

[0139] In addition, a stack 493 of the gate insulating film 402 and the oxide semiconductor film (first oxide semiconductor film 191 and the second oxide semiconductor film 192) are preferably formed successively without being exposed to the air. The gate insulating film 402 and the stacked layer 493 of the oxide semiconductor film (the first oxide semiconductor film 191 and When the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed in succession without exposure to the atmosphere, the gate insulating film 191 is This can prevent impurities such as hydrogen and water from being adsorbed onto the surface of the film 402 .

[0140] The CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions contained in the sputtering target cleave from the ab plane, forming a -b: Detached as flat or pellet-shaped sputtered particles with surfaces parallel to the plane In this case, the plate-like sputtered particles may be transferred to the substrate while maintaining their crystalline state. By reaching the plate, a CAAC-OS film can be formed.

[0141] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0142] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0143] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably The film is formed at a temperature between 200°C and 500°C. When a plate-shaped sputtering particle reaches the substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0144] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0145] As an example of a sputtering target, an In-Ga-Zn-O compound target is The following are the results:

[0146] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. After that, it is heat-treated at a temperature between 1000℃ and 1500℃ to form polycrystalline In-G The target is a-Zn-O compound, where X, Y, and Z are any positive numbers. The predetermined mole ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 The type of powder and the molar ratio of the powder to be mixed depend on the sputtering temperature to be prepared. You can change it as needed depending on the target.

[0147] The stack of oxide semiconductor films 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 1 92) by a photolithography process to form an island-shaped oxide semiconductor stack 403 (first oxide semiconductor The resulting semiconductor layer is processed into a conductor layer 101 and a second oxide semiconductor layer 102 (see FIG. 2C).

[0148] In addition, a resist mask for forming an island-shaped oxide semiconductor stack 403 was formed by inkjet printing. If the resist mask is formed by the ink-jet method, a photomask can be used. Since no external wiring is used, manufacturing costs can be reduced.

[0149] Note that the etching of the oxide semiconductor film may be dry etching or wet etching. For example, an etching method used for wet etching of an oxide semiconductor film may be used. The cleaning solution can be a mixture of phosphoric acid, acetic acid, and nitric acid. O07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0150] In this embodiment, the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed of the same Since the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are formed by etching using a mask, The oxide semiconductor layer 102 has the same shape as the oxide semiconductor layer 102, with the end portions of the side surfaces aligned. In the conductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 The sides (ends) are exposed.

[0151] Note that in one embodiment of the disclosed invention, the oxide semiconductor stack is It may be processed into an island shape, or may remain in a film shape without being processed into a shape.

[0152] In addition, when forming a contact hole in the gate insulating film 402, the process is performed by This can be performed simultaneously when the semiconductor film 191 and the second oxide semiconductor film 192 are processed.

[0153] Note that like the transistor 449 in FIG. 3C, the oxide semiconductor stack 403 is subjected to heat treatment. A mixed region 10 is formed between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102. The heat treatment may be performed to form the first oxide semiconductor layer 101 and the second oxide semiconductor layer 5. The temperature is set to a temperature at which the elements in the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 can be diffused by heat. The second oxide semiconductor layer 102 has a uniform composition throughout the entire oxide semiconductor stack 403. It is sufficient to perform the process under conditions that do not result in a merged region.

[0154] Heat treatment can be carried out under reduced pressure, nitrogen atmosphere, oxygen atmosphere, air (ultra-dry air), or rare gas atmosphere. The heat treatment can be carried out under various conditions (temperature, atmosphere, time, etc.). For example, the heat treatment may be performed at a temperature of 650° C. in a nitrogen atmosphere. After heating under an oxygen atmosphere for 1 hour,

[0155] The step of performing heat treatment to form the mixed region 105 is performed on the first oxide semiconductor film 191 and the second oxide semiconductor film 192. The method is not particularly limited as long as it is after the formation of the first oxide semiconductor film 192 and the second oxide semiconductor film 193. The second oxide semiconductor film 191 and the second oxide semiconductor film 192 may be formed by the same method as in this embodiment. The island-shaped first oxide semiconductor layer 101 and the island-shaped second oxide semiconductor layer 102 may be formed as shown in FIG. In addition, the heat treatment may be performed after other heat treatments (e.g., dehydration or The heat treatment may also serve as a heat treatment for dehydrogenation or a heat treatment for crystallization.

[0156] In addition, excessive hydrogen (water or hydrogen) is added to the oxide semiconductor stack 403 (the oxide semiconductor film stack 493). Heat treatment may be carried out to remove (dehydrate or dehydrogenate) the acid groups (including the acid groups). The treatment temperature is between 300°C and 700°C, or below the distortion point of the substrate. This can be done under reduced pressure or a nitrogen atmosphere. The substrate is placed in a furnace, and the oxide semiconductor stack 403 (the oxide semiconductor film stack 493) is Heat treatment is carried out at 450°C for 1 hour in a nitrogen atmosphere.

[0157] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device that heats the object to be treated by radiation may be used. For example, a GRTA (Gas Reactor Tank Apparatus) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp or other lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment An active gas is used.

[0158] For example, as a heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650 to 700°C. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0159] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not contained. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than 1 ppm.

[0160] In addition, after the oxide semiconductor stack 403 (the oxide semiconductor film stack 493) is heated by heat treatment, In the same furnace, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (CRDS ( The moisture content measured using a cavity ring-down laser spectroscopy (CDR) dew point meter is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, more preferably 10 It is also possible to introduce oxygen gas or nitrous oxide gas containing water, hydrogen, etc. It is preferable that the oxygen gas or the dioxide gas introduced into the heat treatment device is not contained. The purity of the nitrogen gas is 6N or more, preferably 7N or more (i.e., oxygen gas or nitrous oxide gas). It is preferable to keep the impurity concentration in the gas to 1 ppm or less, preferably 0.1 ppm or less. Impurities due to dehydration or dehydrogenation treatment by the action of oxygen gas or nitrous oxide gas The oxide, which is the main component material of the oxide semiconductor, was also reduced during the removal process. By supplying the element, the oxide semiconductor stack 403 (the oxide semiconductor film stack 493) is formed. It can be highly purified and made into Type I (intrinsic).

[0161] Note that the heat treatment for dehydration or dehydrogenation is performed after the stack 493 of oxide semiconductor films (first oxide film) is removed. After the formation of the first oxide semiconductor film 191 and the second oxide semiconductor film 192, and before the formation of the insulating film 407 In this case, the step may be performed at any timing in the manufacturing process of the transistor 440a. For example, a stack of oxide semiconductor films 493 (a first oxide semiconductor film 191 and a second oxide semiconductor film 192) After the formation of the oxide semiconductor layer 192, or after the formation of the island-shaped oxide semiconductor stack 403 (first oxide semiconductor layer 10 This can be performed after the first and second oxide semiconductor layers 102) are formed.

[0162] The heat treatment for dehydration or dehydrogenation may be carried out multiple times, or may be carried out in combination with other heat treatments. For example, after the first oxide semiconductor film 191 is formed and after the second oxide semiconductor film 19 2 After formation, heat treatment may be carried out twice.

[0163] The heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor stack 403 (first oxide semiconductor Before being processed into islands as the oxide semiconductor layer 101 and the second oxide semiconductor layer 102, The stack 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 192) is a gate electrode. If the heat treatment is performed with the insulating film 402 covering the gate insulating film 402, oxygen contained in the gate insulating film 402 is decomposed by the heat treatment. This is preferable because it can prevent the release of the hydroxybenzoates.

[0164] Next, a source electrode layer and a drain electrode layer are formed on the gate insulating film 402 and the oxide semiconductor stack 403. A conductive film is formed to become the electrode layer (including the wiring formed in the same layer). A conductive film used for the source electrode layer and the drain electrode layer is made of a material that can withstand heat treatment. Examples of the metal include a metal containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. metal film, or metal nitride film containing the above elements (titanium nitride film, molybdenum nitride film) tungsten nitride film) can be used. Also, the underside of a metal film such as Al or Cu Or, on one or both sides of the upper side, a high melting point metal film such as Ti, Mo, W, or a metal nitride film of these It is a structure in which a layer of metal films (titanium nitride film, molybdenum nitride film, tungsten nitride film) is stacked. Further, as the conductive film used for the source electrode layer and the drain electrode layer, a conductive gold film may be used. It may be formed of a metal oxide. An example of a conductive metal oxide is indium oxide (In2O3). , tin oxide (SnO2), zinc oxide (ZnO), indium oxide tin oxide (In2O3- SnO2), indium oxide zinc oxide (In2O3-ZnO) or these metal oxides A material containing silicon oxide can be used.

[0165] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed. After forming the source electrode layer 405a and the drain electrode layer 405b by this method, a resist mask Remove.

[0166] In the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor Since the side surfaces (ends) of the layer 102 are exposed, the source electrode layer 405a and the drain electrode layer 4 05b is formed on part of the side surfaces of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102. It is formed so as to be in contact with the

[0167] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0168] Note that when the conductive film is etched, the oxide semiconductor stack 403 is etched and divided. However, it is desirable to optimize the etching conditions so that the conductive film does not and the oxide semiconductor stack 403 is not etched at all. Therefore, the oxide semiconductor stack 403 is only partially etched during etching of the conductive film. As a result, the oxide semiconductor stack 403 may have a groove (depression).

[0169] In this embodiment, a Ti film is used as the conductive film, and an In-Ga -Zn-based oxide semiconductor was used, so the etching solution was ammonia hydrogen peroxide (ammonia, A mixture of water and hydrogen peroxide is used.

[0170] Through the above steps, the transistor 440a of this embodiment is manufactured (see FIG. 2D). A plurality of oxide semiconductor layers having different energy gaps (first oxide semiconductor layer 101 The oxide semiconductor stack 403 using the first oxide semiconductor layer 102 and the second oxide semiconductor layer 103 is used. This allows for more precise control of the electrical characteristics of the transistors 440a and 440b. This allows the transistors 440a and 440b to have desired electrical characteristics.

[0171] Next, an insulating film 407 is formed in contact with part of the oxide semiconductor stack 403 (see FIG. 2(E)). see).

[0172] The insulating film 407 is formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like. The insulating film 407 is typically a silicon oxide film, a silicon oxynitride film, or a silicon oxynitride film. For example, an inorganic insulating film such as an aluminum oxide film or a gallium oxide film can be used.

[0173] The insulating film 407 may be an aluminum oxide film, a hafnium oxide film, or a magnesium oxide film. film, zirconium oxide film, lanthanum oxide film, barium oxide film), or metal nitride film (e.g. For example, an aluminum nitride film can also be used.

[0174] The insulating film 407 may be a single layer or a laminated layer, and may be, for example, a silicon oxide film and an aluminum oxide film. A stack of the above can be used.

[0175] An aluminum oxide film that can be used as the insulating film 407 provided over the oxide semiconductor stack 403 The aluminum membrane has a blocking effect that prevents impurities such as hydrogen and water, as well as oxygen, from passing through the membrane. High blocking effect.

[0176] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The inclusion of impurities such as water in the oxide semiconductor stack 403 and the inclusion of the main components constituting the oxide semiconductor The oxide semiconductor film functions as a protective film that prevents oxygen, which is a material, from being released from the oxide semiconductor stack 403 .

[0177] The insulating film 407 is formed by mixing impurities such as water and hydrogen into the insulating film 407 by a method such as sputtering. It is preferable to form the insulating film 407 by using a method other than the above. If the insulating film in contact with the conductive stack 403 is a film containing excess oxygen, the oxide semiconductor stack 40 This is preferred because it provides a source of oxygen to 3.

[0178] In this embodiment, a silicon oxide film having a thickness of 100 nm is deposited as the insulating film 407 by sputtering. The silicon oxide film is formed by sputtering. Typically, under an atmosphere of argon, oxygen, or a mixture of rare gases and oxygen. This can be done.

[0179] In addition, when the insulating film 407 is a stacked layer, for example, an In—Hf A Zn-based oxide film and a silicon oxide film may be stacked in this order. In-Zr-Zn oxide film with an atomic ratio of In:Zr:Zn=1:1:1, silicon oxide Alternatively, a layer of In:Gd:Zn=1:1:1 may be stacked on the oxide semiconductor stack 403. Alternatively, an In-Gd-Zn-based oxide film having the atomic ratio of 100 to 150 and a silicon oxide film may be laminated in this order.

[0180] In order to remove residual moisture in the deposition chamber of the insulating film 407, similarly to the deposition of the oxide semiconductor film, It is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating film 407 formed in the film formation chamber evacuated using a pump can be reduced. In addition, as an exhaust means for removing residual moisture in the film forming chamber of the insulating film 407, a turbo A molecular pump with a cold trap added may also be used.

[0181] The insulating film 407 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or hydrogen. It is preferable to use a high-purity gas from which impurities such as oxides have been removed.

[0182] As shown in FIGS. 3A and 3B, an interlayer insulating film is formed on the transistors 440c and 440d. As a result, even if a planarization insulating film 416 is formed to reduce the surface irregularities caused by the transistor, The planarization insulating film 416 may be formed of a material such as polyimide, acrylic resin, or benzocyclobutene-based In addition to the above organic materials, low dielectric constant materials (e.g., resins) can be used. It is possible to use insulating films made of these materials. The planarization insulating film 416 may be formed by stacking.

[0183] The insulating film 407 and the planarization insulating film 416 are covered with the source electrode layer 405a and the drain electrode layer 405b. An opening is formed in the opening, and the source electrode layer 405a and the drain electrode layer 405b are formed in the opening. A wiring layer may be formed to electrically connect the transistor to another transistor. This allows various circuits to be configured.

[0184] The source electrode layer 405a and the drain electrode layer 405b are The etching process for forming the opening reaching the layer 405b results in partial over-etching. The source electrode layer and the drain electrode layer may have a stacked structure, and the opening-shaped The conductive film also functions as an etching stopper during the formation of the source and drain electrode layers. It can be set as:

[0185] As shown in FIG. 3A, the transistor 440c has a source electrode layer and a drain electrode layer stacked thereon. This is an example of a layer structure, and the source electrode layer is a source electrode layer 404a and a source electrode layer 40 5a, the drain electrode layer 404b and the drain electrode layer 405b are stacked as the drain electrode layer. As in the transistor 440c, the planarization insulating film 416, the insulating film 407, and The source electrode layer 405a and the drain electrode layer 405b are connected to the source electrode layer 404a and the drain electrode layer 404b. An opening is formed to reach the source electrode layer 404a and the drain electrode layer 404b. Alternatively, wiring layers 465a and 465b may be formed to electrically connect to the wiring layers 465a and 465b.

[0186] In the transistor 440c, the source electrode layer 404a and the drain electrode layer 404b are formed as openings. The source electrode layer 404a and the drain electrode layer 404b also function as an etching stopper during the formation of the source electrode layer 404a. The source electrode layer 405a is a tungsten film or a tantalum nitride film. The drain electrode layer 405b can be formed using a copper film, an aluminum film, or the like. Cut.

[0187] As shown in FIG. 3B, a transistor 440d includes a source electrode layer 405a, a drain electrode layer 405b, and a The gate electrode layer 405b is provided only on the oxide semiconductor stack 403, and the gate electrode layer 405b is provided on the side of the oxide semiconductor stack 403. The structure shown by the transistor 440d is formed by a multi-tone mask. It can also be fabricated by performing an etching process using a resist mask formed by With this structure, the source electrode layer 405a and The leakage current (parasitic channel) of the drain electrode layer 405b can be further reduced. .

[0188] The wiring layer 465a and the wiring layer 465b are connected to the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b. The wiring layer 405b can be formed using the same material and method as the wiring layer 405b. 465a, and a wiring layer 465b, which is a laminate of a tantalum nitride film and a copper film, or a tantalum nitride film and A lamination with a tungsten film can be used.

[0189] The oxide semiconductor stack 403, which is highly purified and has oxygen vacancies filled, is free from impurities such as hydrogen and water. The hydrogen concentration in the oxide semiconductor stack 403 was 5×10 19 atom s / cm 3 Less than or equal to 5 x 10 18 atoms / cm 3 The oxides are as follows: The hydrogen concentration in the semiconductor stack 403 was measured by secondary ion mass spectroscopy (SIMS). It is measured by ion mass spectrometry (Ion Mass Spectrometry).

[0190] The oxide film produced by this embodiment is highly purified and contains excess oxygen to compensate for the oxygen deficiency. The transistor 440a using the compound semiconductor stack 403 has a current value in an off state (off voltage The current value was set at 100 zA / μm (1 zA (zeptoampere)) per μm of channel width at room temperature. ) is 1 × 10 -21 A) or less, preferably 10 zA / μm or less, more preferably 1 zA / It is possible to reduce the intensity to a level of 100 yA / μm or less, more preferably to a level of 100 yA / μm or less.

[0191] As described above, semiconductor devices suitable for various purposes such as high functionality, high reliability, and low power consumption can be provided. can be provided.

[0192] (Embodiment 2) In this embodiment mode, another embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. 11. The same parts as those in the above embodiment or parts having similar functions, The steps and processes can be performed in the same manner as in the above embodiment, and repeated explanations will be omitted. A detailed explanation of the same points will be omitted.

[0193] In this embodiment, in the stack of oxide semiconductor layers, an upper oxide semiconductor layer is formed on the lower oxide semiconductor layer. An example of a structure that covers the side of the body layer is shown below.

[0194] The transistor 340 shown in FIGS. 7A to 7C is an inverted staggered transistor having a bottom gate structure. 7A is a plan view of an example of a transistor of this type. The cross section cut along -Y corresponds to Fig. 7(B), and the cross section cut along the dashed line VW in Fig. 7(A) corresponds to Fig. 7(B). The surface corresponds to FIG. 7(C).

[0195] As shown in FIG. 7B, which is a cross-sectional view in the channel length direction, the transistor 340 has an insulating surface. A gate electrode layer 401, a gate insulating film 402, and a gate insulating film 403 are provided in this order on a substrate 400 having a surface. A first oxide semiconductor layer 101 and a second oxide semiconductor layer 10 having different energy gaps 2, a source electrode layer 405a, and a drain electrode layer 405b. Note that an insulating film 407 is formed over the transistor 340.

[0196] The first oxide semiconductor layer 101 is formed on and in contact with the gate insulating film 402. The semiconductor layer 102 is formed to cover the top and side surfaces of the first oxide semiconductor layer 101. The periphery of the oxide semiconductor layer 102 is in contact with the gate insulating film 402. The oxide semiconductor layer 101 is in contact with the source electrode layer 405a or the drain electrode layer 405b. By using a structure in which the source electrode layer 405a and the drain electrode layer 405b of the transistor 340 are not This reduces the occurrence of leakage current (parasitic channel) in the pole layer 405b.

[0197] FIG. 7C is a cross-sectional view in the channel width direction, and similarly to FIG. 7B, the first oxide semiconductor The edge (side surface) of the layer 101 is covered with the edge of the second oxide semiconductor layer 102, and the edge (side surface) of the first oxide semiconductor layer 102 is covered with the edge of the second oxide semiconductor layer 102. The conductor layer 101 is not in contact with the insulating film 407 .

[0198] The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 have different energy gaps. In this embodiment, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 The second oxide semiconductor layer 102 has a different composition from the first oxide semiconductor layer 102, and the energy gap of the second oxide semiconductor layer 102 is This is an example in which the energy gap is larger than that of the layer 101.

[0199] 8A to 8C show an oxide semiconductor stack 403 including a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, a third oxide semiconductor layer 103, a fourth oxide semiconductor layer 104, a fourth oxide semiconductor layer 105, and a fourth oxide semiconductor layer 106. The second oxide semiconductor layer 102, the third oxide semiconductor layer 103, and the third oxide semiconductor layer 104 are stacked. Transistor 380a is shown.

[0200] The transistor 380a shown in FIGS. 8A to 8C is an inverted transistor having a bottom gate structure. 8A is a plan view of an example of a gate-type transistor. The cross section cut along XY corresponds to Fig. 8(B), and the cross section cut along the dashed line VW in Fig. 8(A) corresponds to Fig. 8(B). The cross section corresponds to FIG. 8(C).

[0201] As shown in FIG. 8B, which is a cross-sectional view in the channel length direction, the transistor 380a is an insulating A gate electrode layer 401 and a gate insulating film 402 are provided in this order on a substrate 400 having a surface. , a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer The oxide semiconductor stack 403 including the layer 103, the source electrode layer 405a, and the drain electrode layer 405 An insulating film 407 is formed over the transistor 380a.

[0202] The first oxide semiconductor layer 101 is formed on and in contact with the gate insulating film 402. A second oxide semiconductor layer 102 is stacked on the semiconductor layer 101. 03 indicates the side surface of the first oxide semiconductor layer 101 and the upper surface and The peripheral portion of the third oxide semiconductor layer 103 is formed so as to cover the gate insulating film 402. The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are in contact with each other. is not in contact with the source electrode layer 405a or the drain electrode layer 405b. , leakage current of the source electrode layer 405a and the drain electrode layer 405b of the transistor 380a It reduces the generation of current (parasitic channel).

[0203] FIG. 8C is a cross-sectional view in the channel width direction, and similarly to FIG. 8B, the first oxide semiconductor The end portions (side surfaces) of the layer 101 and the second oxide semiconductor layer 102 are connected to the third oxide semiconductor layer 103. The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are covered with the end of the insulating film. The structure is such that it does not connect to 407.

[0204] The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 have different energy gaps. In this embodiment, the energy gap of the second oxide semiconductor layer 102 is set to be equal to that of the first oxide semiconductor layer 102. This is an example in which the energy gap is smaller than that of the compound semiconductor layer 101.

[0205] The second oxide semiconductor layer 102 and the third oxide semiconductor layer 103 have an energy gap. In this embodiment, the energy gap of the third oxide semiconductor layer 103 is different from that of the second oxide semiconductor layer 102. This is an example in which the energy gap is larger than that of the oxide semiconductor layer 102.

[0206] In this embodiment, the energy gap of the third oxide semiconductor layer 103 is The energy gap is almost the same as that of the first oxide semiconductor layer 101.

[0207] For example, the first oxide semiconductor layer 101 in the transistor 380a may be formed of In-Ga- Zn-based oxide film (energy gap 3.2 eV) as the second oxide semiconductor layer 102 is an In-Sn-Zn oxide film (energy gap 2.8 eV), and the third oxide semiconductor The layer 103 is an In-Ga-Zn oxide film (energy gap 3.2 eV). .

[0208] The three-layer oxide semiconductor stack 403 of the transistor 380a may be formed by the first The oxide semiconductor layer 101 is an In-Ga-Zn oxide film, and the second oxide semiconductor layer 10 The second oxide semiconductor layer 2 is an In-Zn oxide film, and the third oxide semiconductor layer 103 is an In-Ga-Zn a Ga—Zn-based oxide film as the first oxide semiconductor layer 101; The oxide semiconductor layer 102 is an In—Sn—Zn-based oxide film, and the third oxide semiconductor layer 103 is an In—Sn—Zn-based oxide film. a Ga-Zn-based oxide film as the first oxide semiconductor layer 101; an In—Zn-based oxide film as the second oxide semiconductor layer 102; an In—Zn-based oxide film as the third oxide semiconductor layer 103; The first oxide semiconductor layer 101 is a stack of Ga—Zn-based oxide films. an In—Ga—Zn-based oxide film as the second oxide semiconductor layer 102; The third oxide semiconductor layer 103 may be a stack of an In—Ga-based oxide film or a stack of a first oxide semiconductor film. The first oxide semiconductor layer 101 is an In-Ga-Zn oxide film, and the second oxide semiconductor layer 102 is an oxide film. an indium nitride (In-based oxide) film as the third oxide semiconductor layer 103; A stack of oxide films containing fluorine atoms can be used.

[0209] The second oxide semiconductor layer 102 is surrounded by the first oxide semiconductor layer 101 and the third oxide semiconductor layer 102. By covering the second oxide semiconductor layer 102 with the semiconductor layer 103, an increase in oxygen vacancies in the second oxide semiconductor layer 102 is suppressed. The threshold voltage of the transistor 380a can be made close to zero. The second oxide semiconductor layer 102 serves as a buried channel, thereby insulating the channel formation region. This reduces the scattering of carriers at the interface and allows for a high field efficiency. High mobility can be achieved.

[0210] The transistor 380b illustrated in FIG. 11A includes a first oxide semiconductor layer 101 and a second oxide semiconductor layer 102. When the nitride semiconductor layer 102 is processed into islands, the same mask is used (or the same mask is used during processing). The island-shaped first oxide semiconductor layer 101 and the island-shaped second oxide semiconductor layer 102 were used as a mask. In addition, a part of the gate insulating film 402 is etched to make it thinner. In 80b, the gate insulating film 402 is formed between the island-shaped first oxide semiconductor layer 101 and the island-shaped second oxide semiconductor layer 102. The region overlapping with the nitride semiconductor layer 102 is thicker than the other region (non-overlapping region). The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 have an island-like thickness. During the process, the first oxide film is formed by etching a part of the gate insulating film 402. By removing etching residues such as residues of the compound semiconductor layer 101, the occurrence of leakage current can be reduced. This can be done.

[0211] The transistor 380c shown in FIG. 11B is formed by three photolithography steps. The oxide semiconductor stack 403 is formed in the transistor 380c. The oxide semiconductor stack 403 is formed by forming a first oxide semiconductor film and then forming an island-like oxide semiconductor layer using a first mask. A first oxide semiconductor layer 101 is formed, and a second oxide is deposited on the island-shaped first oxide semiconductor layer 101. After the oxide semiconductor film is formed, a second mask is used to form an island-shaped second oxide semiconductor layer 102. Then, a third oxide semiconductor layer is formed on the island-shaped first oxide semiconductor layer 101 and the island-shaped second oxide semiconductor layer 102. After forming the oxide semiconductor film, the oxide semiconductor film is processed into an island-shaped third oxide semiconductor layer 103 using a third mask. It is formed by

[0212] Note that in the transistor 380c, the end faces of the first oxide semiconductor layer 101 are The third oxide semiconductor layer 103 is formed on the side of the conductor layer 102. In this example, the insulating layer 104 is in contact with a part of the upper surface of the compound semiconductor layer 101.

[0213] As another mode of the semiconductor device, a channel protector having a bottom gate structure is shown in FIG. 9(B). A protection transistor 418 is shown.

[0214] As shown in FIG. 9B, which is a cross-sectional view in the channel length direction, the transistor 418 has an insulating surface. A gate electrode layer 401, a gate insulating film 402, and a gate insulating film 403 are provided in this order on a substrate 400 having a surface. A first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer an oxide semiconductor stack 403 including the insulating film 103; an insulating film 427 serving as a channel protective film; The transistor 418 has a source electrode layer 405a and a drain electrode layer 405b. A veneer 409 is formed.

[0215] The first oxide semiconductor layer 101 is formed on and in contact with the gate insulating film 402. A second oxide semiconductor layer 102 is stacked on the semiconductor layer 101. 03 indicates the side surface of the first oxide semiconductor layer 101 and the upper surface and The peripheral portion of the third oxide semiconductor layer 103 is formed so as to cover the gate insulating film 402. The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are in contact with each other. is not in contact with the source electrode layer 405a or the drain electrode layer 405b. , the leakage current of the source electrode layer 405a and the drain electrode layer 405b of the transistor 418 This reduces the occurrence of currents (parasitic channels).

[0216] As another example of the semiconductor device, a bottom-gate transistor 4 shown in FIG. Shows 38.

[0217] As shown in FIG. 10B, the transistor 438 is formed in order on a substrate 400 having an insulating surface. A gate electrode layer 401, a gate insulating film 402, a source electrode layer 405a, and a drain electrode layer 406 are provided on the substrate. the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and The transistor 438 includes an oxide semiconductor stack 403 including the oxide semiconductor layer 103 of the third embodiment. An insulating film 407 is formed thereon.

[0218] The transistor 438 has a first oxide film formed over the source electrode layer 405a and the drain electrode layer 405b. The oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 are The oxide semiconductor stack 403 includes a first oxide semiconductor layer 101 and a second oxide semiconductor layer 102. At least one of the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103 is The energy gap is different.

[0219] In the transistor 438, the first oxide semiconductor layer 101 is a second oxide semiconductor layer 101 formed on and in contact with the drain electrode layer 405b; The third oxide semiconductor layer 103 is formed on the first oxide semiconductor layer 102. the first oxide semiconductor layer 101 and the upper and side surfaces of the second oxide semiconductor layer 102; The periphery of the third oxide semiconductor layer 103 is surrounded by the source electrode layer 405a and the drain electrode layer 405b. It is designed to be in contact with 5b.

[0220] In this way, the shapes of the stacked oxide semiconductor layers are different for each oxide semiconductor layer. The oxide semiconductor stack may have various shapes and structures.

[0221] As described above, semiconductor devices suitable for various purposes such as high functionality, high reliability, and low power consumption can be provided. can be provided.

[0222] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0223] (Embodiment 3) In this embodiment mode, another embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The same parts as those in the above embodiment or parts and steps having similar functions are the same as those in the above embodiment. The same operations can be performed as in the first embodiment, and the repeated explanation will be omitted. The literal meaning is omitted.

[0224] In this embodiment, in a manufacturing method of a semiconductor device according to the disclosed invention, The oxide semiconductor stack that has been subjected to the oxidation treatment is subjected to oxidation treatment with oxygen (at least oxygen radicals, oxygen atoms, and oxygen atoms). An example of supplying oxygen into the film by introducing oxygen ions (including either ions or non-ions) will be shown.

[0225] By the dehydration or dehydrogenation treatment, oxygen, which is the main component material of the oxide semiconductor, is simultaneously In the oxide semiconductor stack, oxygen may be released from the region where oxygen is released, resulting in a decrease in the amount of oxygen. Oxygen vacancies exist in the donor region, which cause fluctuations in the electrical characteristics of the transistor. -level occurs.

[0226] Therefore, it is preferable to supply oxygen to the oxide semiconductor stack that has been subjected to dehydration or dehydrogenation treatment. By supplying oxygen to the oxide semiconductor stack, oxygen vacancies in the film can be compensated for. By using the oxide semiconductor stack in a transistor, a transistor caused by oxygen vacancies can be prevented. By reducing the variation in the threshold voltage Vth of the transistor and the threshold voltage shift ΔVth, In addition, the threshold voltage can be shifted in the positive direction to make the transistor normally off. You can also do this.

[0227] FIG. 5(A) corresponds to FIG. 2(C), and shows a gate electrode formed on a substrate 400 having an insulating surface. A pole layer 401, a gate insulating film 402, a first oxide semiconductor layer 1 having a different energy gap An oxide semiconductor stack 403 including the oxide semiconductor layer 01 and the second oxide semiconductor layer 102 is formed.

[0228] Next, oxygen 431 (at least oxygen radicals, oxygen atoms, and oxygen atoms) is added to the oxide semiconductor stack 403. ions) to form a first oxide semiconductor layer 101 and a second oxide semiconductor layer 102. Oxygen excess regions 111 and 112 are formed in the oxide semiconductor stack 403 including the oxide semiconductor layer 102. Then, oxygen is supplied (see FIG. 5(B)).

[0229] The oxygen-excess regions 111 and 112 have a stoichiometric composition when the oxide semiconductor is in a crystalline state. The region includes at least a portion where the oxygen content is in excess of the ratio. The oxygen 431 supplied to the excess regions 111 and 112 causes the first oxide semiconductor layer 101 and oxygen vacancies present in the oxide semiconductor stack 403 including the second oxide semiconductor layer 102. It can be compensated.

[0230] On the gate insulating film 402 and the oxide semiconductor stack 403 having the oxygen excess regions 111 and 112 A source electrode layer 405a and a drain electrode layer 405b are formed to fabricate a transistor 443a. (See Figure 5(C)).

[0231] The oxygen 431 introduction step is performed after the formation of the source electrode layer 405a and the drain electrode layer 405b. 5D shows the structure of the source electrode layer 405a and the drain electrode layer 405b. After the formation, an oxide semiconductor stack including the oxide semiconductor layer 101 and the second oxide semiconductor layer 102 is formed. A transistor 443b is shown as an example of a transistor manufactured by introducing oxygen into 403.

[0232] As shown in FIG. 5D, oxygen 431 is introduced into the source electrode layer 405a and the drain electrode layer 405b. The oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are formed on the oxide semiconductor layer 101 as a mask. It is selectively introduced into the channel forming region of the conductor stack 403. Oxidation of transistor 443b In the compound semiconductor stack 403, the source electrode layer 405a or the drain electrode layer 405b is overlapped with the The non-overlapping region is larger than the region overlapping with the source electrode layer 405a or the drain electrode layer 405b. This results in a configuration with a higher oxygen concentration than that of the conventional configuration.

[0233] As another mode of the semiconductor device, oxygen is introduced into the oxide semiconductor stack 403 as shown in FIG. 4A shows a transistor 483 having a bottom-gate structure. The layer 403 includes the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103. A transistor 480 using a three-layer stack of the oxide semiconductor layer 103 is shown.

[0234] The transistor 483 includes a gate electrode layer 484 and a gate insulating layer 485, which are provided in order over a substrate 400 having an insulating surface. 401, a gate insulating film 402, a first oxide semiconductor layer 101 having an oxygen excess region 111 The second oxide semiconductor layer 102 including the oxygen excess region 112 and the second oxide semiconductor layer 104 including the oxygen excess region 113 are an oxide semiconductor stack 403 including the third oxide semiconductor layer 103; a source electrode layer 405a; The transistor 483 has a drain electrode layer 405b. are.

[0235] In the oxide semiconductor stack 403 of the transistor 483, the first oxide semiconductor layer 101, The energy gaps of the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103 are They are not all the same and contain at least two different energy gap values.

[0236] The transistor 483 is an example in which oxygen is introduced into the entire oxide semiconductor stack 403. The first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 In the above, the oxygen excess region 111, the oxygen excess region 112, or the oxygen excess region 113 is provided.

[0237] As another mode of the semiconductor device, a semiconductor device in which oxygen is introduced into the oxide semiconductor stack 403 is shown in FIG. 4 shows a channel-protective transistor 413 having a bottom gate structure.

[0238] The transistor 413 includes a gate electrode layer 414 and a gate insulating layer 415, which are provided in this order over a substrate 400 having an insulating surface. 401, a gate insulating film 402, a first oxide semiconductor layer 101 including an oxygen excess region 111, The second oxide semiconductor layer 102 includes the oxygen excess region 112, and the second oxide semiconductor layer 102 includes the oxygen excess region 113. The oxide semiconductor stack 403 including the third oxide semiconductor layer 103 functions as a channel protective film. The transistor has an insulating film 427, a source electrode layer 405a, and a drain electrode layer 405b. An insulating film 409 is formed on the stanchion 413 .

[0239] A first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer At least one of the oxide semiconductor layers 103 has a different energy gap from the other oxide semiconductor layers. In the transistor 413, the energy gap of the second oxide semiconductor layer 102 is This is an example in which the oxide semiconductor layer 101 is smaller than the oxide semiconductor layer 101 and the third oxide semiconductor layer 103.

[0240] The transistor 413 is an example in which oxygen is introduced into the entire oxide semiconductor stack 403. The first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 In the above, the oxygen excess region 111, the oxygen excess region 112, or the oxygen excess region 113 is provided.

[0241] In the transistor 413, the first oxide semiconductor layer 101 is formed on the gate insulating film 40. 2, and the second oxide semiconductor layer 102 is formed on the first oxide semiconductor layer 101. The third oxide semiconductor layer 103 is formed on the side surfaces of the first oxide semiconductor layer 101 and The third oxide semiconductor layer 102 is formed to cover the top and side surfaces of the second oxide semiconductor layer 102. The peripheral portion of the first oxide semiconductor layer 103 is in contact with the gate insulating film 402. The oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are connected to the source electrode layer 405a or the drain electrode layer 40 5b of the transistor 413. The generation of leakage current (parasitic channel) in the drain electrode layer 405b is reduced.

[0242] As another mode of the semiconductor device, a semiconductor device in which oxygen is introduced into the oxide semiconductor stack 403 is shown in FIG. 4 shows a bottom gate structure transistor 433.

[0243] As shown in FIG. 10C, the transistor 433 is formed in order on a substrate 400 having an insulating surface. A gate electrode layer 401, a gate insulating film 402, a source electrode layer 405a, and a drain electrode layer 406 are provided on the substrate. the first oxide semiconductor layer 101 including the oxygen excess region 111; The second oxide semiconductor layer 102 includes an oxygen-excess region 112, and the third oxide semiconductor layer 102 includes an oxygen-excess region 113. The transistor 433 includes an oxide semiconductor stack 403 including an oxide semiconductor layer 103. An insulating film 407 is formed.

[0244] The transistor 433 has a first oxide film formed over the source electrode layer 405a and the drain electrode layer 405b. an oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer; The first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the second oxide semiconductor layer 103 are provided. At least one of the oxide semiconductor layer 102 and the third oxide semiconductor layer 103 is an energy The gap between the second oxide semiconductor layer 1 and the second oxide semiconductor layer 2 is different from that between the other oxide semiconductor layers. The energy gap of the first oxide semiconductor layer 101 and the third oxide semiconductor layer 10 Here is an example that is smaller than 3.

[0245] The transistor 433 is an example in which oxygen is introduced into the entire oxide semiconductor stack 403. The first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 In the above, the oxygen excess region 111, the oxygen excess region 112, or the oxygen excess region 113 is provided.

[0246] In the transistor 433, oxygen is introduced directly into the exposed oxide semiconductor stack 403. Alternatively, the insulating film 407 may be passed through the insulating film 407 .

[0247] Note that the upper oxide semiconductor layer described in Embodiment 2 covers the side surfaces of the lower oxide semiconductor layer. In the transistor 340 and the transistor 380a having the structure, the oxide semiconductor stack 40 An example in which oxygen is introduced into 3 to provide an oxygen excess region is shown in FIG. 7(D) and FIG. 8(D).

[0248] The transistor 343 in FIG. 7D is provided in order over a substrate 400 having an insulating surface. The gate electrode layer 401, the gate insulating film 402, and the first oxide layer 403 having different energy gaps are formed. an oxide semiconductor stack 403 including an oxide semiconductor layer 101 and a second oxide semiconductor layer 102; The transistor 343 has a source electrode layer 405a and a drain electrode layer 405b. In the transistor 343, the oxide semiconductor stack 403 is The first oxide semiconductor layer 101 includes an oxygen excess region 111, and the second oxide semiconductor layer 102 includes an oxygen excess region 112. The second oxide semiconductor layer 102 includes a first oxide semiconductor layer 104 and a second oxide semiconductor layer 102.

[0249] The transistor 383 in FIG. 8D is provided in order over a substrate 400 having an insulating surface. The gate electrode layer 401, the gate insulating film 402, and the first oxide layer 403 having different energy gaps are formed. The oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 are the oxide semiconductor stack 403, the source electrode layer 405a, and the drain electrode layer 405b. An insulating film 407 is formed over the transistor 383. The oxide semiconductor stack 403 includes the first oxide semiconductor layer 10 including the oxygen excess region 111. 1. The second oxide semiconductor layer 102 including the oxygen excess region 112 and the oxygen excess region 113 The third oxide semiconductor layer 103 includes a SiO 2 -based oxide semiconductor layer.

[0250] Note that as shown in the transistors 343 and 383, the lower oxide semiconductor layer In the case of stacking oxide semiconductor layers in which an oxide semiconductor layer having a larger energy gap is stacked on top, In this case, the upper oxide semiconductor layer covers the side surface of the lower oxide semiconductor layer, The generation of leakage current (parasitic channel) in the source and drain electrode layers of the transistor can be reduced.

[0251] Oxygen is introduced into the oxide semiconductor stack 403 that has been subjected to dehydration or dehydrogenation treatment. By supplying the oxide semiconductor stack 403, the oxide semiconductor stack 403 is highly purified and made into an i-type (intrinsic) oxide semiconductor. The transistor having the highly purified and i-type (intrinsic) oxide semiconductor stack 403 can be used. Transistor 443a, transistor 443b, transistor 413, transistor 433, The transistor 343 and the transistor 383 have suppressed fluctuations in electrical characteristics and are electrically stable. It is fixed.

[0252] The oxygen introduction method includes ion implantation, ion doping, and plasma immersion. On-implantation methods, plasma treatment, etc. can be used.

[0253] In the oxygen introduction step, when oxygen is introduced into the oxide semiconductor stack 403, 3 or may be introduced through other films such as the insulating film 407 into the oxide semiconductor stack 40 3. When oxygen is introduced through another membrane, ion implantation, ion doping, etc. The method of plasma immersion ion implantation, etc. can be used. When oxygen is directly introduced into the exposed oxide semiconductor stack 403, plasma treatment or the like may be performed. It can be used.

[0254] Oxygen can be introduced into the oxide semiconductor stack 403 after dehydration or dehydrogenation treatment. The oxide semiconductor stack that has been subjected to the dehydration or dehydrogenation treatment may be a stack of oxide semiconductor layers. Oxygen may be introduced into 403 multiple times.

[0255] For example, in Embodiment 1, oxygen is introduced into the oxide semiconductor stack 403 by The source electrode layer 405 is formed on the stack of the oxide semiconductor films 493 or the stack of the oxide semiconductor films 403. a) After forming the drain electrode layer 405b, after forming the gate insulating film 402, This can be done after the formation of the insulating film 407.

[0256] In addition, oxygen is introduced into the oxygen-excess regions 111 and 112 in the oxide semiconductor stack 403. The oxygen concentration introduced by the process is 1×1018 atoms / cm 3 5x10 or more 21 at oms / cm 3 It is preferable to have the following:

[0257] In an oxide semiconductor, oxygen is one of the main components. It is difficult to accurately estimate the oxygen concentration in the conductor laminate 403 using a method such as SIMS. That is, it is necessary to determine whether oxygen has been intentionally added to the oxide semiconductor stack 403. It can be said that this is difficult.

[0258] By the way, oxygen has 17 O and 18 There are isotopes such as O, and their existence in nature The respective proportions of oxygen atoms are known to be approximately 0.037% and 0.204% of the total oxygen atoms. That is, when these isotopes are intentionally added to the oxide semiconductor stack 403, The concentrations of these isotopes can be estimated by methods such as SIMS. By measuring the oxygen concentration in the oxide semiconductor stack 403, it is possible to estimate the oxygen concentration more accurately. Therefore, by measuring the concentrations of these elements, it is possible to determine whether the oxide semiconductor stack 403 is intentionally formed. Alternatively, it may be determined whether oxygen has been added intentionally.

[0259] After oxygen is introduced into the oxide semiconductor film, heat treatment is preferably performed.

[0260] In the transistors 443a and 443b of this embodiment, oxygen is directly oxidized. When the oxide semiconductor layer 403 is introduced, the gate insulating film 4 02. The insulating film 407 does not necessarily have to be a film containing a large amount of oxygen. In order to prevent the oxide semiconductor stack 403 from being desorbed again and to prevent impurities such as hydrogen and water from being released from the oxide semiconductor stack 403, It has a blocking effect against impurities such as oxygen, hydrogen, and water so that they do not re-enter the semiconductor stack 403. It is preferable to provide a film having a high blocking effect as the insulating film 407. Aluminum oxide has a high blocking effect against both impurities such as water and oxygen. It is preferable to use a silicon film or the like.

[0261] Of course, the gate insulating film 402 and the insulating film 407 in contact with the oxide semiconductor film are formed of a material containing a large amount of oxygen. Further, oxygen is directly introduced into the oxide semiconductor stack 403, and a plurality of oxygen supply methods are performed. It is also possible.

[0262] In this embodiment, oxygen is introduced into the oxide semiconductor stack 403 as an example. The introduction of the element is performed on the gate insulating film 402, the insulating film 407, and the like that are in contact with the oxide semiconductor stack 403. The gate insulating film 402 and the insulating film 407 in contact with the oxide semiconductor stack 403 may be formed of oxygen. By introducing oxygen into the oxide semiconductor stack 403, the oxygen is supplied to the oxide semiconductor stack 403. It is possible.

[0263] As described above, a semiconductor device using an oxide semiconductor stack having stable electrical characteristics is provided. Therefore, a highly reliable semiconductor device can be provided.

[0264] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0265] (Fourth embodiment) In this embodiment mode, another embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The same parts as those in the above embodiment or parts and steps having similar functions are the same as those in the above embodiment. The same operations can be performed as in the first embodiment, and the repeated explanation will be omitted. The literal meaning is omitted.

[0266] In this embodiment, in a method for manufacturing a semiconductor device according to the disclosed invention, This is an example of forming a low-resistance region in a layer. The low-resistance region is formed by changing the conductivity of the oxide semiconductor stack. The layer can be formed by introducing an impurity (also called a dopant) that causes the layer to be in a non-transparent state.

[0267] In this embodiment, an example of a channel protective transistor 420 having a bottom gate structure is 6A to 6C illustrate an example of a method for manufacturing the transistor 420.

[0268] First, a gate electrode layer 401 is formed on a substrate 400 having an insulating surface. A gate insulating film 402 is formed on the substrate 1.

[0269] Then, a first oxide semiconductor layer 101 having a different energy gap is formed on the gate insulating film 402. An oxide semiconductor stack 403 including the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 is formed.

[0270] Note that oxygen is introduced into the oxide semiconductor stack 403 as described in Embodiment 2, and an excess of oxygen is added. The oxide semiconductor stack 403 may include a three-layer structure. The structure may be such that the upper oxide semiconductor layer covers the side surfaces of the lower oxide semiconductor layer. Good too.

[0271] A layer functioning as a channel protective film is formed on the oxide semiconductor stack 403 overlapping with the gate electrode layer 401. An insulating film 427 is formed (see FIG. 6A).

[0272] Next, the oxide semiconductor stack 403 was doped with the dopant 421 using the insulating film 427 as a mask. The low resistance regions 121a, 121b, 122a, and 122b are formed (FIG. 6( See B).

[0273] In this embodiment, the insulating film 427 that functions as a channel protective film is formed by introducing a dopant 421. A separate resist mask is formed to mask the dopant 421. In addition, the transistor 440a, which does not include a channel protective film, In the case of the transistor 430, a separate resist mask is formed to selectively introduce dopants. Just enter.

[0274] Depending on the conditions for introducing the dopant 421, only the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 may be doped. When the dopant 421 is introduced only into the compound semiconductor layer 102 to form a low resistance region, The dopant concentration distribution in the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 Fabric may be present.

[0275] The dopant 421 is an impurity that changes the electrical conductivity of the oxide semiconductor stack 403. Panto 421 includes group 15 elements (typically phosphorus (P), arsenic (As), and ammonium). Sb), boron (B), aluminum (Al), nitrogen (N), argon (Ar ), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (C l), titanium (Ti), and zinc (Zn) are used. can be done.

[0276] The dopant 421 is introduced into the oxide semiconductor stack 403 by an implantation method. The introduction method of 21 is ion implantation, ion doping, plasma immersion In this case, the dopant 421 It is preferable to use the simple ions of fluoride or chloride.

[0277] The dopant 421 introduction process is performed by adjusting the implantation conditions such as acceleration voltage and dose amount, and the mask. The thickness of the insulating film 427 may be appropriately set and controlled. Boron is used as the dopant 1, and boron ions are implanted by ion implantation. The dose of 421 is 1×10 13 ions / cm 2 5x10 or more 16 ions / cm 2 Below Just put it below.

[0278] The concentration of dopant 421 in the low resistance region is 5×10 18 atoms / cm 3 1 x10 22 atoms / cm 3 It is preferable that:

[0279] The dopant 421 may be introduced while the substrate 400 is heated.

[0280] Note that the process of introducing the dopant 421 into the oxide semiconductor stack 403 may be performed multiple times. In addition, a plurality of types of dopants may be used.

[0281] After the introduction of the dopant 421, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be performed.

[0282] When the oxide semiconductor stack 403 is a crystalline oxide semiconductor film, the dopant 421 is introduced. In this case, the dopant 421 may be partially amorphous. By performing this treatment, the crystallinity of the oxide semiconductor stack 403 can be restored.

[0283] Therefore, in the oxide semiconductor stack 403, the low-resistance regions 121c are sandwiched between the channel formation region 121c. The first oxide semiconductor layer 101 provided with the first and second oxide semiconductor layers 121a and 121b and the channel formation region 12 a second oxide semiconductor layer 102 in which low-resistance regions 122a and 122b are provided with a second oxide semiconductor layer 102 and a second oxide semiconductor layer 102c sandwiched therebetween; is formed.

[0284] Next, the source electrode layer 405 is formed in contact with the low resistance regions 121a, 121b, 122a, and 122b. a) Forming the drain electrode layer 405b.

[0285] Through the above steps, the transistor 420 of this embodiment is manufactured (see FIG. 6C).

[0286] Low resistance regions 121a and 121b are provided on either side of a channel formation region 121c in the channel length direction. The first oxide semiconductor layer 101 and the low-resistance region 122c are sandwiched between the first oxide semiconductor layer 101 and the low-resistance region 122b. and a second oxide semiconductor layer 102 on which the oxide semiconductor layers 122a and 122b are provided. By having 403, the transistor 420 has on-characteristics (e.g., on-current and electric field The high effective mobility (e.g., electron mobility) enables high-speed operation and high-speed response.

[0287] In the transistor 420, the low resistance regions 121a, 121b, 122a, and 122b are The low resistance regions 121a and 121b can function as a source region or a drain region. By providing the low resistance regions 121a, 121b, 122a, and 122b, 2a and 122b, the electric field applied to the channel forming regions 121c and 122c formed between the In addition, in the low resistance regions 121a, 121b, 122a, and 122b, The oxide semiconductor stack 403 is electrically connected to the source electrode layer 405a and the drain electrode layer 405b. By electrically connecting the oxide semiconductor stack 403 to the source electrode layer 405a and the drain electrode layer 405b, Therefore, the contact resistance with the drain electrode layer 405b can be reduced. The thermal characteristics can be improved.

[0288] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0289] (Embodiment 5) A semiconductor device having a display function using the transistor as an example described in any of Embodiments 1 to 4 A semiconductor device (also called a display device) can be manufactured. Part or all of the circuitry is integrated onto the same substrate as the pixel section to form a system-on-panel. It is possible.

[0290] In FIG. 12A, a pixel portion 4002 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided on the substrate 4001, and the substrate 4001 is sealed with a second substrate 4006. In FIG. 2(A), the area surrounded by the sealing material 4005 on the first substrate 4001 is A single crystal semiconductor film or a polycrystalline semiconductor film is formed on a separately prepared substrate in a region different from the region. A scanning line driver circuit 4004 and a signal line driver circuit 4003 are mounted on the substrate. A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel portion 4002 are connected to the signal line driver circuit 4003 and the scanning line driver circuit 4004. The various signals and potentials are transmitted through the FPC (Flexible Printed Circuit). It is supplied by 4018a and 4018b.

[0291] In FIG. 12(B) and (C), a pixel portion 4002 is provided on a first substrate 4001, and A sealant 4005 is provided so as to surround the scanning line driver circuit 4004. A second substrate 4006 is provided on the element portion 4002 and the scanning line driver circuit 4004 . Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are formed by the first substrate 4001 and the sealing material. The display element is sealed by the second substrate 4005 and the second substrate 4006. In (C), the area surrounded by the seal material 4005 on the first substrate 4001 A single crystal semiconductor film or a polycrystalline semiconductor film is formed on a separately prepared substrate in a region different from the region. 12(B) and (C), a signal line driver circuit 4003 is mounted. The signal line driver circuit 4003 and the scanning line driver circuit 4004 or the pixel portion 4002 are formed. The various signals and potentials are supplied from the FPC4018.

[0292] In addition, in FIGS. 12B and 12C, a signal line driver circuit 4003 is separately formed. 4001, but the present invention is not limited to this configuration. It may be formed separately and mounted, or only a part of the signal line driver circuit or a part of the scanning line driver circuit may be mounted. may be separately formed and mounted.

[0293] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape A A method such as a fused bonding method can be used. This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the COG method. 12B shows an example in which a signal line driver circuit 4003 is mounted by the COG method. 2(C) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0294] The display device also includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above are mounted.

[0295] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. Also refers to connectors, such as FPC or TAB tape. Modules with TCP attached, TAB tape or TCP with a printed wiring board attached The IC (integrated circuit) is directly mounted on the module or display element using the COG method. All such modules are also included in the display device.

[0296] The pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described as an example in any of Embodiments 1 to 4 can be used. do.

[0297] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element emits light by applying a current or a voltage. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Luminescence, organic electroluminescence, etc. Also, electronic ink, etc. A display medium whose contrast changes depending on use can also be applied.

[0298] One mode of a semiconductor device will be described with reference to FIGS. 12 and 13. FIG. 13 shows the same structure as FIG. B) corresponds to the cross section at MN.

[0299] As shown in FIG. 13, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrodes 4015 and the terminal electrodes 4016 are anisotropic with the terminals of the FPC 4018. The electrodes are electrically connected via a conductive film 4019 .

[0300] The connection terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030. 016 is the same conductor as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011. It is formed of a conductive film.

[0301] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. The pixel portion 4002 includes a plurality of transistors. 4004 and a transistor 4011 included in the scan line driver circuit 4004 are shown as examples. In FIG. 13A, an insulating film 4020 is provided over the transistors 4010 and 4011. In FIG. 13B, an insulating film 4021 is further provided. It is an insulating film that functions as a base film.

[0302] The transistors 4010 and 4011 are the transistors according to any one of Embodiments 1 to 4. In this embodiment, the transistor shown in Embodiment 1 can be applied. 10. An example in which a transistor having a structure similar to that of the transistor 440a is used will be described.

[0303] The transistor 4010 and the transistor 4011 have at least two transistors with different energy gaps. Both transistors have an oxide semiconductor stack including two oxide semiconductor layers. A stack of oxide semiconductor layers having an energy gap is used. This allows for more precise control of the electrical characteristics of the transistor, resulting in the desired electrical characteristics. This makes it possible to impart properties to the transistors 4010 and 4011.

[0304] Therefore, the semiconductor device of this embodiment shown in FIGS. 12 and 13 has high functionality, high reliability, Alternatively, a semiconductor device that meets various objectives, such as low power consumption, can be provided.

[0305] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display, and various display elements can be used. can be used.

[0306] FIG. 13A shows an example of a liquid crystal display device using a liquid crystal element as a display element. In the figure, a liquid crystal element 4013, which is a display element, has a first electrode layer 4030 and a second electrode layer 4040. 031 and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between alignment films. The second electrode layer 4031 is provided with insulating films 4032 and 4033 that function as a second The first electrode layer 4030 and the second electrode layer 4031 are disposed on the substrate 4006 side. The structure is stacked via 008.

[0307] 4035 is a columnar spacer obtained by selectively etching the insulating film. It is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. A pacer may be used.

[0308] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. The liquid crystal material (liquid crystal composition) can be in a cholesteric phase, a smectic phase, or a cubic phase depending on the conditions. The phases shown are nematic, chiral, isotropic, etc.

[0309] In addition, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase is a phase that appears just before the transition from the black phase to the isotropic phase. The blue phase can be expressed by using a liquid crystal composition in which the above-mentioned compounds are mixed. In order to widen the temperature range, a polymerizable monomer and a polymerization initiator are added to the liquid crystal composition that exhibits the blue phase. The liquid crystal layer can be formed by adding a polymer stabilizer. The liquid crystal composition that exhibits this phase has a short response time and is optically isotropic, so alignment treatment is not required. It has little viewing angle dependency. Also, since there is no need to provide an alignment film, rubbing treatment is not required. Therefore, electrostatic breakdown caused by the rubbing process can be prevented, and the manufacturing process This reduces defects and damage to the liquid crystal display device during the manufacturing process, thereby improving the productivity of the liquid crystal display device. A transistor including an oxide semiconductor film can be easily affected by static electricity. This can cause the electrical characteristics of the transistor to fluctuate significantly, potentially causing it to deviate from the design range. Therefore, a liquid crystal display device having a transistor including an oxide semiconductor film exhibits a blue phase. It is more effective to use a crystalline composition.

[0310] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values ​​in this document are those measured at 20°C.

[0311] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period, taking into consideration the current and other factors. The size of the oxide film may be set in consideration of the off-state current of the transistor. By using a transistor with a semiconductor film, the liquid crystal capacitance in each pixel It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0312] The transistor including the oxide semiconductor film disclosed in this specification has a current value ( Therefore, the retention time of electrical signals such as image signals can be controlled to be low. The write interval can be set to a long value when the power is on. This reduces the frequency of flash operations, thereby reducing power consumption.

[0313] In addition, the transistor including the oxide semiconductor film disclosed in this specification has high field-effect mobility. For example, such high-speed driving is possible. By using such a transistor in a liquid crystal display device, it is possible to The driver transistors used in the driver circuit section can be formed on the same substrate. That is, a semiconductor device formed from a silicon wafer or the like is used as a separate driving circuit. Since there is no need for a pixel portion, the number of components in the semiconductor device can be reduced. However, by using transistors that can be driven at high speed, high-quality images can be provided. Therefore, high reliability can be achieved as a semiconductor device.

[0314] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0315] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type. For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV (Advanced Super View) mode, etc. can be used. It can also be applied to VA type liquid crystal display devices. VA type liquid crystal display devices are: It is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. VA type liquid crystal display devices are When no voltage is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. This is called multi-domain or multi-domain design, which is designed to knock down molecules. The following method can be used.

[0316] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0317] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. is not limited to color display devices, but also applies to monochrome display devices. It is also possible.

[0318] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0319] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0320] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0321] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes needs to be light-transmitting. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are various types of light sources, including top emission, bottom emission, and light emission from the substrate side and the opposite side of the substrate. There are light emitting elements with a double-sided emission structure that emits light from both sides, and light emitting elements of any emission structure can be applied. It is possible.

[0322] FIG. 13B shows an example of a light-emitting device using a light-emitting element as a display element. The photoelement 4513 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The light-emitting element 4513 includes a first electrode layer 4030, an electroluminescent layer 4511, The second electrode layer 4031 has a stacked structure, but is not limited to the structure shown. The configuration of the light emitting element 4513 can be changed as needed to suit the direction of the light extracted from 3. Cut.

[0323] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the sidewall of the opening has a continuous curved surface. It is preferable to form the inclined surface so as to have a certain slope.

[0324] The electroluminescent layer 4511 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0325] The second electrode layer 4 is formed so as to prevent oxygen, hydrogen, water, carbon dioxide, etc. from entering the light emitting element 4513. A protective film may be formed on the insulating film 031 and the partition wall 4510. The protective film may be a silicon nitride film. A silicon nitride oxide film, a DLC film, etc. can be formed on the first substrate 4001. A filler 451 is filled in the space sealed by the second substrate 4006 and the sealant 4005. 4 is provided and sealed. In this way, it is highly airtight and degassing is Protective films (laminating films, UV-curing resin films, etc.) and cover materials with low Packaging (enclosure) is preferred.

[0326] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resin, Imide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0327] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0328] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), and is similar to paper. It is possible to have the same readability, lower power consumption than other display devices, and a thinner, lighter form factor. This has the advantage of

[0329] The electrophoretic display device may have various forms, but it has a structure in which first particles having a positive charge and and a second particle having a negative charge. By applying an electric field to the microcapsules, The particles in the cell are moved in opposite directions to each other, and only the color of the particles that gather on one side is displayed. The first particles or the second particles contain a dye, and when there is no electric field, they move. The color of the first particle and the color of the second particle are different (including colorless). )

[0330] In this way, the electrophoretic display device moves materials with high dielectric constants to areas with high electric fields, so-called This is a display that utilizes the dielectrophoretic effect.

[0331] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0332] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0333] In addition, a display device using a twist ball display method can also be applied as electronic paper. The twist ball display method uses spherical particles painted in black and white as the display element. The first electrode layer and the second electrode layer are disposed between the first electrode layer and the second electrode layer. This is a display method that controls the orientation of spherical particles by creating a potential difference between the electrode layers. be.

[0334] 12 and 13, the first substrate 4001 and the second substrate 4006 are: In addition to a glass substrate, a flexible substrate can also be used. For example, a transparent plastic substrate can be used. As for plastic, FRP (Fibre Plastic) can be used. Ass-Reinforced Plastics) plate, PVF (Polyvinyl Fluoride) A film, a polyester film or an acrylic resin film can be used. If transparency is not required, metal substrates such as aluminum and stainless steel (metal filters) can be used. For example, aluminum foil can be used as a PVF film or polyester film. A sheet sandwiched between films can also be used.

[0335] In this embodiment, an aluminum oxide film is used as the insulating film 4020.

[0336] The aluminum oxide film provided as the insulating film 4020 over the oxide semiconductor film is resistant to hydrogen, water, and the like. High blocking effect that prevents both impurities and oxygen from passing through the membrane .

[0337] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The contamination of the oxide semiconductor film with impurities such as water and the main component material of the oxide semiconductor The oxide semiconductor film functions as a protective film for preventing oxygen from being released from the oxide semiconductor film.

[0338] The insulating film 4021 functioning as a planarizing insulating film can be made of acrylic resin, polyimide, or benzophenone. By using heat-resistant organic materials such as cyclobutene resin, polyamide, and epoxy, In addition to the above organic materials, low-k materials and siloxane-based Resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. Note that an insulating film may be formed by stacking a plurality of insulating films made of these materials. stomach.

[0339] The method for forming the insulating film 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, etc.), Printing methods (screen printing, offset printing, etc.), doctor knife, roll coater, car A ten coater, knife coater, or the like can be used.

[0340] A display device transmits light from a light source or a display element to display an image. All thin films such as the substrate, insulating film, and conductive film provided in the part are resistant to light in the visible light wavelength range. It shall be translucent.

[0341] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, a pair of electrodes) that apply a voltage to the display element In the case of a light-emitting diode (also called a counter electrode layer), the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0342] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide , silicon oxide-doped indium tin oxide, graphene, and other transparent conductive materials Fees can be used.

[0343] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), It can be formed by using one or more of the metals, alloys thereof, or metal nitrides thereof. Cut.

[0344] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or or a copolymer consisting of two or more of aniline, pyrrole and thiophene, or a derivative thereof Conductors, etc.

[0345] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0346] As described above, by using the transistor described in any of Embodiments 1 to 4, various It is possible to provide semiconductor devices having various functions.

[0347] (Sixth embodiment) The transistor exemplified in any one of the first to fourth embodiments is used to read information on an object. Therefore, a semiconductor device having an image sensor function for detecting a pixel can be manufactured.

[0348] FIG. 14A shows an example of a semiconductor device having an image sensor function. FIG. 14(B) is a cross-sectional view showing a part of the photosensor. .

[0349] The photodiode 602 has one electrode connected to a photodiode reset signal line 658 and the other One electrode is electrically connected to the gate of transistor 640. One of the source and drain is connected to the photosensor reference signal line 672, and the other of the source and drain is connected to the photosensor reference signal line 673. The other terminal is electrically connected to one of the source and drain of the transistor 656. The transistor 656 has a gate connected to a gate signal line 659 and a source or drain connected to a photodiode. The signal line 671 is electrically connected to the sensor output signal line 671.

[0350] Note that in the circuit diagrams in this specification, a transistor including an oxide semiconductor film is not clearly shown. To make it easy to identify, the symbol for a transistor using an oxide semiconductor film is written as “OS.” In FIG. 14A, a transistor 640 and a transistor 656 are the same as those in Embodiment 1. The transistors described in any of the above to 4 can be used, and are transistors including an oxide semiconductor film. In this embodiment, a transistor having a structure similar to that of the transistor 440a described in Embodiment 1 is used. An example of applying a transistor will be shown.

[0351] FIG. 14B shows a photodiode 602 and a transistor 640 in the photosensor. 6 is a cross-sectional view of a substrate 601 (TFT substrate) having an insulating surface, on which a sensor function is provided. A photodiode 602 and a transistor 640 are provided. A substrate 613 is provided on the board 602 and the transistor 640 using an adhesive layer 608. There are.

[0352] On the transistor 640, an insulating film 631, an insulating film 632, an interlayer insulating film 633, and an interlayer insulating film The photodiode 602 is provided on the interlayer insulating film 633. An electrode layer 641 formed on the interlayer insulating film 633 and an electrode layer provided on the interlayer insulating film 634 642, a first semiconductor film 606a and a second semiconductor film 606b are formed between the first semiconductor film 606a and the second semiconductor film 606b in this order from the interlayer insulating film 633 side. 6b and a third semiconductor film 606c are stacked.

[0353] The electrode layer 641 is electrically connected to a conductive layer 643 formed on the interlayer insulating film 634. 642 is electrically connected to the conductive layer 645 via the electrode layer 641. The conductive layer 645 is The photodiode 602 is electrically connected to the gate electrode layer of the transistor 640. It is electrically connected to the transistor 640 .

[0354] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor film 606b is a high resistance semiconductor film (I-type semiconductor film), and the third semiconductor film 606c is an n-type A pin-type photodiode in which semiconductor films having different conductivity types are stacked is shown as an example.

[0355] The first semiconductor film 606a is a p-type semiconductor film, and is an amorphous film containing an impurity element that imparts p-type. The first semiconductor film 606a can be formed from a group 13 silicon film. Using semiconductor material gas containing impurity elements (e.g., boron (B)), plasma CVD is used. Silane (SiH4) can be used as the semiconductor material gas. Alternatively, i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may be used. In addition, after forming an amorphous silicon film that does not contain impurity elements, the film is formed by diffusion or ion implantation. Impurity elements may be introduced into the amorphous silicon film by using a method such as ion implantation. It is preferable to diffuse the impurity element by heating or the like after introducing the impurity element. In this case, the amorphous silicon film can be formed by LPCVD, vapor phase growth, Alternatively, sputtering or the like may be used. The thickness of the first semiconductor film 606a is 10 nm or more and 5 nm or less. It is preferable to form it so that the thickness is 0 nm or less.

[0356] The second semiconductor film 606b is an I-type semiconductor film (intrinsic semiconductor film) and is made of amorphous silicon. The second semiconductor film 606b is formed by amorphous silicon using a semiconductor material gas. A thick silicon film is formed by plasma CVD. The semiconductor material gas is silane. (SiH4) can be used. Alternatively, Si2H6, SiH2Cl2, SiHCl3, S The second semiconductor film 606b may be formed by LPCVD. The second semiconductor film 606b may be formed by vapor deposition, sputtering, or the like. It is preferable to form the film so that the thickness is 00 nm or more and 1000 nm or less.

[0357] The third semiconductor film 606c is an n-type semiconductor film and is an amorphous film containing an impurity element that imparts n-type. The third semiconductor film 606c is formed of a thick silicon film. It is formed by the plasma CVD method using a semiconductor material gas containing silicon (e.g., phosphorus (P)). Silane (SiH4) can be used as the semiconductor material gas. SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming an amorphous silicon film that does not contain elements, the film is then doped with silicon using diffusion or ion implantation. An impurity element may be introduced into the amorphous silicon film by ion implantation or the like. After the element is introduced, the impurity element may be diffused by heating or the like. The amorphous silicon film can be formed by LPCVD, vapor phase growth, or sputtering. The thickness of the third semiconductor film 606c is 20 nm or more and 200 nm or less. It is preferable to form it so that it faces downward.

[0358] The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are Instead of an amorphous semiconductor, it may be formed using a polycrystalline semiconductor, or a microcrystalline (semi-amorphous) semiconductor. Rufus (Semi Amorphous Semiconductor: SAS) Semiconductor It may also be formed using a conductor.

[0359] Considering the Gibbs free energy, microcrystalline semiconductors are metastable, intermediate between amorphous and single crystal. In other words, a semiconductor with a third state that is stable in terms of free energy It has a short-range order and lattice distortion. Microcrystalline silicon, a typical example of a microcrystalline semiconductor, is characterized by its Raman scattering. The spectrum shows single-crystal silicon at 520 cm -1 It is shifted to the lower wavenumber side. That is, 520 cm, which indicates single crystal silicon -1 and 480 cm, which indicates amorphous silicon - 1 The Raman spectrum of microcrystalline silicon has a peak between these two. Contains at least 1 atomic % or more of hydrogen or halogen to terminate the bonding bonds. It also contains rare gas elements such as helium, argon, krypton, and neon. By increasing the lattice distortion, the stability is increased and a good microcrystalline semiconductor film can be obtained. .

[0360] This microcrystalline semiconductor film is formed by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz, or Alternatively, it can be formed by a microwave plasma CVD device with a frequency of 1 GHz or more. Representative examples include SiH4, Si2H6, SiH2Cl2, SiHCl3, SiCl4, and S It can be formed by diluting silicon-containing compounds such as iF4 with hydrogen. In addition to compounds containing hydrogen (e.g., silicon hydride) and hydrogen, helium, argon, krypton, neon forming a microcrystalline semiconductor film by diluting the semiconductor film with one or more rare gas elements selected from the group consisting of fluorine and fluorine; In these cases, the flow rate ratio of hydrogen to silicon-containing compounds (e.g., silicon hydride) is 5 times or more and 200 times or less, preferably 50 times or more and 150 times or less, and more preferably 100 times Furthermore, in the gas containing silicon, carbide gases such as CH4, C2H6, GeH 4. Germanium gas such as GeF4, F2, etc. may be mixed.

[0361] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so the pin-type The photodiode exhibits better characteristics when the p-type semiconductor film side is used as the light receiving surface. From the surface of the substrate 601 on which the in-type photodiode is formed to the photodiode 602 This shows an example of converting the light received by the semiconductor film into an electrical signal. Since light from the semiconductor film side having a pattern becomes disturbance light, a conductive film with light blocking properties is used for the electrode layer. It is also possible to use the n-type semiconductor film side as the light-receiving surface.

[0362] The insulating film 632, the interlayer insulating film 633, and the interlayer insulating film 634 are made of insulating materials. Depending on the material, methods include sputtering, plasma CVD, SOG, spin coating, and Spray coating, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater It can be formed using a material such as a silicon dioxide particle.

[0363] In this embodiment, an aluminum oxide film is used as the insulating film 631. It can be formed by sputtering or plasma CVD.

[0364] The aluminum oxide film provided as the insulating film 631 over the oxide semiconductor film is resistant to hydrogen, water, and the like. It has a high blocking effect that prevents both impurities and oxygen from passing through the membrane.

[0365] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The contamination of the oxide semiconductor film with impurities such as water and the main component material of the oxide semiconductor The oxide semiconductor film functions as a protective film for preventing oxygen from being released from the oxide semiconductor film.

[0366] The insulating film 632 may be made of an inorganic insulating material such as a silicon oxide layer, a silicon oxynitride layer, An oxide insulating film such as an aluminum oxide layer or an aluminum oxynitride layer, or a silicon nitride layer , a nitride such as a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer A single layer or a stacked layer of insulating films can be used.

[0367] The interlayer insulating films 633 and 634 function as planarizing insulating films to reduce surface irregularities. The interlayer insulating films 633 and 634 are preferably made of, for example, polyimide or acrylic. Heat-resistant organic resins such as resins, benzocyclobutene-based resins, polyamides, and epoxy resins In addition to the organic insulating materials, low-dielectric-constant materials (low- k material), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass), etc. A single layer or a laminated layer can be used.

[0368] By detecting the light incident on the photodiode 602, information on the detected object is read. It is possible to read the information of the detected object using a light source such as a backlight. It is possible.

[0369] As described above, a plurality of oxide semiconductor layers having different energy gaps as semiconductor layers By using an oxide semiconductor stack including This allows for control, making it possible to impart desired electrical characteristics to the transistor. By using such a transistor, various objectives such as high functionality, high reliability, and low power consumption can be achieved. Therefore, it is possible to provide a semiconductor device that meets the requirements.

[0370] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0371] (Embodiment 7) The transistor exemplified in any one of the first to fourth embodiments is a transistor stacked in a plurality of layers. The present invention can be suitably applied to a semiconductor device having an integrated circuit. As an example of a semiconductor device, a storage medium (memory element) will be shown.

[0372] In the embodiment, a transistor that is a first transistor manufactured on a single crystal semiconductor substrate A second transistor 140 is formed using a semiconductor film above the transistor 140 via an insulating film. A semiconductor device including the transistor 162 is manufactured. The transistor 162 may be suitably used as any of the transistors exemplified in any of the above. In this embodiment, the transistor 162 may be the same as that shown in Embodiment 1. 4 shows an example in which a transistor having a structure similar to that of the transistor 440a is used.

[0373] The semiconductor materials and structures of the stacked transistors 140 and 162 may be the same. This embodiment is directed to a material suitable for a circuit of a storage medium (memory element). These are examples using transistors of different materials and structures.

[0374] 15A and 15B show an example of the configuration of a semiconductor device. FIG. 15A shows a cross section of the semiconductor device. 15(B) shows a plan view of the semiconductor device. This corresponds to the cross section taken along lines C1-C2 and D1-D2 in FIG. 15(B). An example of a circuit diagram in the case where the semiconductor device is used as a memory element is shown in FIG. The semiconductor device shown in FIG. 15(B) has a transistor using a first semiconductor material in the lower part. The second semiconductor material is used as the second transistor 162. In the embodiment, the first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material is The oxide semiconductor is a semiconductor material other than the oxide semiconductor. Compound semiconductors such as ruthenium, silicon germanium, silicon carbide, or gallium arsenide A single crystal semiconductor can be used, and it is preferable to use an organic semiconductor. A transistor using such a semiconductor material can easily operate at high speed. On the other hand, transistors using oxide semiconductors can maintain charge for a long time due to their characteristics. Allows retention.

[0375] The semiconductor device in FIG. 15 will be described with reference to FIGS.

[0376] The transistor 140 is disposed on a substrate 185 that includes a semiconductor material (e.g., silicon). The channel forming region 116 is formed by doping the impurity ions 116. The region 120, the metal compound region 124 in contact with the impurity region 120, and the channel forming region 1 A gate insulating film 108 is provided on the gate electrode 16, and a gate electrode 109 is provided on the gate insulating film 108. The electrode 110 is a ferroelectric material.

[0377] The substrate 185 containing the semiconductor material may be a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, or a The substrates used include crystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates. Generally, an "SOI substrate" is a substrate in which a silicon semiconductor film is provided on an insulating surface. However, in this specification, it refers to a substrate having a structure in which a material other than silicon is formed on an insulating surface. In other words, the semiconductor film of the "SOI substrate" The film is not limited to a silicon semiconductor film. In addition, the SOI substrate can be made of an insulating material such as a glass substrate. The term "semiconductor film" includes a structure in which a semiconductor film is provided on a substrate via an insulating film.

[0378] The SOI substrate is fabricated by implanting oxygen ions into a mirror-polished wafer and then heating it at high temperature. By doing so, an oxide layer is formed at a certain depth from the surface, and the cracks that have occurred in the surface layer are removed. a method for eliminating microvoids formed by hydrogen ion irradiation and a method for forming microvoids by heat treatment A method of cleaving a semiconductor substrate by using a length, or a method of forming a single crystal semiconductor film by crystal growth on an insulating surface. A method for forming the above-mentioned film or the like can be used.

[0379] For example, ions are added from one surface of a single crystal semiconductor substrate to form a single crystal semiconductor substrate. A weakened layer is formed at a certain depth from the surface of the single crystal semiconductor substrate, and the single crystal semiconductor substrate is An insulating film is formed on either one of the single crystal semiconductor substrate and the element substrate. While the substrates are stacked together, a crack is generated in the weakened layer, and the single crystal semiconductor substrate is separated at the weakened layer. A heat treatment is performed to form a single crystal semiconductor film on the element substrate as a semiconductor film from the single crystal semiconductor substrate. The SOI substrate manufactured by the above method can also be suitably used.

[0380] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 140. In order to achieve high integration, the transistor 140 may be It is desirable to have a structure that does not have a sidewall insulating layer that becomes a sidewall. When the characteristics of the gate electrode 140 are important, a side wall is formed on the side surface of the gate electrode 110. A wall insulating layer may be provided to provide impurity regions 120 including regions with different impurity concentrations.

[0381] The transistor 140 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a readout transistor, it is possible to read out information at high speed. Two insulating films are formed to cover the transistor 140. As a process before forming the capacitor 162 and the capacitor element 164, the two insulating layers are subjected to CMP. Then, the planarized insulating film 128 and the insulating film 130 are formed, and at the same time, the upper surface of the gate electrode 110 is Expose.

[0382] The insulating film 128 and the insulating film 130 are typically made of a silicon oxide film, a silicon oxynitride film, or an oxide Aluminum film, aluminum oxynitride film, silicon nitride film, aluminum nitride film, nitride An inorganic insulating film such as a silicon oxide film or an aluminum nitride oxide film can be used. The film 128 and the insulating film 130 are formed by using a plasma CVD method, a sputtering method, or the like. It is possible.

[0383] In addition, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition to the above organic materials, low-dielectric-constant materials (low-k materials) can also be used. When organic materials are used, insulating films can be formed by wet methods such as spin coating and printing. 128 and an insulating film 130 may be formed.

[0384] Note that the insulating film 130 that is in contact with the semiconductor film is a silicon oxide film.

[0385] In this embodiment, the insulating film 128 is formed by sputtering an oxynitride film having a thickness of 50 nm. A silicon film is formed, and an oxide film having a thickness of 550 nm is formed by a sputtering method as the insulating film 130. A silicon film is formed.

[0386] A gate electrode layer 148 is formed on the insulating film 130 that has been sufficiently planarized by CMP processing. The gate electrode layer 148 is formed by forming a conductive layer and then selectively etching the conductive layer. It can be formed by:

[0387] A gate insulating film 146 is formed on the gate electrode layer 148 .

[0388] The gate insulating film 146 is formed by depositing an oxide film using a plasma CVD method, a sputtering method, or the like. Silicon film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide Aluminum film, aluminum nitride film, aluminum oxynitride film, aluminum nitride oxide film, aluminum oxide film A gallium oxide film or a gallium oxide film can be formed.

[0389] On the gate insulating film 146, oxide semiconductor films having different energy gaps are stacked. In this embodiment, the gate insulating film 146 is formed by sputtering as a stack of oxide semiconductor films. An In-Sn-Zn oxide layer and an In-Ga-Zn oxide layer are laminated in this order on top of the above.

[0390] Next, the stack of oxide semiconductor films is selectively etched to form an island-shaped stack of oxide semiconductor films 144. Complete.

[0391] The source or drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor stack 144. The drain electrode 142b is formed.

[0392] A gate electrode layer 148, a source electrode or a drain electrode 142a, a source electrode or a drain electrode The conductive layer that can be used for the electrode 142b can be formed by PVD such as sputtering. The conductive layer can be formed by a CVD method such as a plasma CVD method. The material may be an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the above-mentioned Alloys containing elements such as Mn, Mg, Zr, Be, Nd, and Sc can be used. Any one of these materials or a combination of two or more of these materials may be used.

[0393] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The source or drain electrode 142a and the source or drain electrode 142 It has the advantage of being easy to process into b.

[0394] Next, an insulating film is formed on the gate electrode layer 148, the gate insulating film 146, and the oxide semiconductor stack 144. In this embodiment, an aluminum oxide film is formed as the insulating film 150. do.

[0395] The aluminum oxide film provided as the insulating film 150 on the oxide semiconductor stack 144 is Blocking effect that prevents both impurities such as water and oxygen from passing through the membrane is high.

[0396] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The inclusion of impurities such as water in the oxide semiconductor stack 144 and the inclusion of the main component constituting the oxide semiconductor The oxide semiconductor film functions as a protective film that prevents oxygen, which is a material, from being released from the oxide semiconductor stack 144 .

[0397] Alternatively, a separate insulating film may be formed on the insulating film 150 .

[0398] The insulating film is a silicon oxide film formed by plasma CVD or sputtering. Silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum nitride film, oxide Aluminum film, aluminum oxynitride film, aluminum nitride oxide film, hafnium oxide film Alternatively, a gallium oxide film can be used.

[0399] On the insulating film 150, an electrode is formed in a region overlapping with the source electrode or the drain electrode 142a. A layer 153 is formed.

[0400] Next, the insulating film 152 is formed over the transistor 162 and the electrode layer 153. The layer 2 can be formed by sputtering or CVD. Inorganic insulators such as silicon oxide nitride, silicon nitride, hafnium oxide, and aluminum oxide The material may be polyimide, acrylic, benzophenone, or the like. Organic materials such as cyclobutene resins can be used. The organic materials can be applied by coating or printing. A wet method such as a printing method or an ink jet method can be used.

[0401] Next, a source electrode or a drain electrode is formed on the gate insulating film 146, the insulating film 150, and the insulating film 152. An opening is formed that reaches the inner electrode 142b. The opening is formed using a mask or the like. This is done by selective etching.

[0402] Thereafter, a wiring 156 that contacts the source electrode or drain electrode 142b is formed in the opening. 15 shows the connection point between the source electrode or drain electrode 142b and the wiring 156. is not shown.

[0403] The wiring 156 is formed by a PVD method such as a sputtering method, or a C method such as a plasma CVD method. After forming a conductive layer using the VD method, the conductive layer is etched to form The material of the conductive layer is selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The elements mentioned above and alloys containing the elements mentioned above can be used. Any one of R, Be, Nd, and Sc, or a combination of these materials may be used. The details are similar to those of the source electrode or drain electrode 142a.

[0404] Through the above steps, the transistor 162 and the capacitor 164 are formed. The transistor 162 has at least two oxide semiconductor layers with different energy gaps. The transistor has an oxide semiconductor stack 144 including different energy layers. The oxide semiconductor stack 144 is made up of a plurality of oxide semiconductor layers having a gap. This allows for more precise control of the electrical characteristics of the transistor 162, It is possible to impart electrical characteristics to the transistor 162. In this case, the oxide semiconductor stack 144 is highly purified and an oxide semiconductor layer containing excess oxygen is formed to compensate for oxygen vacancies. Therefore, the off-state current of the transistor 162 is reduced and the electrical characteristics are changed. The capacitance element 164 is electrically stable because the capacitance is suppressed by the source electrode or the drain electrode. The insulating film 150 and the electrode layer 153 constitute the semiconductor device.

[0405] If capacitance is not required, the capacitor 164 may not be provided.

[0406] FIG. 15C shows an example of a circuit diagram in the case where the semiconductor device is used as a memory element. In FIG. 15C, one of the source electrode and the drain electrode of the transistor 162 is One of the electrodes of the capacitor 164 and the gate electrode of the transistor 140 are electrically connected. In addition, the first wiring (also called the source line) and the transistor The source electrode of 140 is electrically connected to the second wiring (2nd Line: bit line The drain electrode of the transistor 140 is electrically connected to the drain electrode of the transistor 140. The third wiring (also called the first signal line) and the source of the transistor 162 The other of the drain electrode and the drain electrode is electrically connected to a fourth wiring (4th Line The second signal line (also referred to as a second signal line) and the gate electrode of the transistor 162 are electrically connected to each other. The fifth line (also called a word line) and the capacitor element 16 The other of the four electrodes is electrically connected.

[0407] The transistor 162 including an oxide semiconductor has an extremely low off-state current. Therefore, by turning off the transistor 162, the source of the transistor 162 One of the electrodes or drain electrodes of the capacitor 164 and the transistor 140 The potential of the node (hereinafter referred to as node FG) electrically connected to the gate electrode of Furthermore, by having the capacitance element 164, This makes it easier to retain the charge given to the gate FG and to read out the retained information. becomes.

[0408] When storing (writing) information in the semiconductor device, first, the potential of the fourth wiring is set to This sets the potential at which the transistor 162 is turned on, turning the transistor 162 on. As a result, the potential of the third wiring is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. Here, the charges that give two different potential levels (hereinafter referred to as low level Either a charge or a high level charge is given. The potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off 162, node FG is in a floating state, so As described above, a predetermined amount of charge is stored in the node FG. By storing and holding information, the memory cell can store information.

[0409] Since the off-state current of the transistor 162 is controlled to be extremely small, the The charge stored in the memory is retained for a long time, so that no refresh operation is required. Alternatively, the frequency of refresh operations can be reduced significantly, and power consumption can be reduced sufficiently. In addition, even if there is no power supply, the memory can be stored for a long period of time. The content can be preserved.

[0410] When reading out the stored information (reading), a predetermined potential (constant potential) is applied to the first wiring. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the potential is held at the node FG. Depending on the amount of charge transferred, transistor 140 assumes different states. If 40 is an n-channel type, when a high level charge is held at node FG, The apparent threshold voltage V of transistor 140 th_H A low-level charge is applied to node FG. The apparent threshold voltage V of transistor 140 when held th_L It became lower Here, the apparent threshold is the voltage at which the transistor 140 is turned on. Therefore, the potential of the fifth wiring is V th _H and V th_L By setting the potential V0 between For example, if a high level charge is applied during writing, The potential of the wire 5 is V0 (> V th_H ), transistor 140 is in the "on state" When a low level charge is applied, the potential of the fifth wire becomes V0( <V th _L ), transistor 140 remains in the "off state." The potential of the wiring is controlled to read out the on / off state of the transistor 140 (second The stored information can be read out by reading out the potential of the wiring.

[0411] When the stored information is rewritten, a predetermined amount of electricity is consumed by the rewriting. By supplying a new potential to node FG, which holds the load, node FG is connected to the new information. Specifically, the potential of the fourth wiring is set to a value corresponding to the potential of the fourth wiring when the transistor 162 is turned on. This turns on the transistor 162. A potential (potential related to new information) is supplied to node FG, and a predetermined amount of charge is accumulated in node FG. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off the transistor 162, the node FG receives the new information. That is, a predetermined amount of charge is stored in the node FG by the first write. While the charge is held, the same operation as the first write (second write) is performed. , it is possible to overwrite the stored information.

[0412] The transistor 162 described in this embodiment has at least two layers with different energy gaps. and the off-state current is controlled to be sufficiently low. By using such a transistor, it is possible to A semiconductor device capable of retaining memory contents is obtained.

[0413] As described above, an oxide semiconductor including a plurality of oxide semiconductor layers having different energy gaps can be fabricated. By using a conductor stack, it is possible to control the electrical characteristics of a transistor with greater precision. This makes it possible to provide the transistor with the desired electrical characteristics. It is possible to provide semiconductor devices that meet various objectives such as reliability and low power consumption.

[0414] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0415] (Embodiment 8) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), ), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples of electronic devices including the semiconductor device described in the above embodiment will be described. By providing the semiconductor device described in the above embodiment, high performance and high reliability can be achieved. To provide electronic devices that are endowed with qualities suited to various purposes, such as high performance or low power consumption. can be done.

[0416] 16A shows a table 9000 having a display section. A display portion 9003 is incorporated in a housing 9001. The semiconductor device can be used for the display portion 9003, and an image can be displayed on the display portion 9003. It is possible to display the image. The housing 9001 is supported by four legs 9002. The housing 9001 has a power cord 9005 for power supply. do.

[0417] The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000 By touching the displayed display button 9004 with a finger or the like, the screen can be operated or information can be input. It can also communicate with other home appliances or control them, improving the quality of images. It may also be a control device that controls other home appliances by surface operation. If the semiconductor device having the image sensor function shown in Embodiment 6 is used, the display portion 9003 It can have a touch input function.

[0418] In addition, the screen of the display unit 9003 can be vertically fixed to the floor by a hinge provided in the housing 9001. It can also be set upright and used as a television set. If you install a large screen television, the free space will be narrow, but it is possible to install it on a table. If the display unit is built in, the space in the room can be used more effectively.

[0419] FIG. 16(B) shows a television device 9100. The television device 9100 A display portion 9103 is incorporated in a housing 9101. The semiconductor device can be used for the display portion 9103, and an image can be displayed by the display portion 9103. In this case, the housing 9101 is supported by a stand 9105. This shows a configuration that maintains the same level of accuracy.

[0420] The television device 9100 can be operated using an operation switch provided on the housing 9101 or a separate remote control. This can be done by the remote control operation device 9110. The channel and volume can be controlled by the 9109, and the information displayed on the display 9103 is In addition, the remote control unit 9110 can be used to operate the video. A display unit 9107 for displaying information output from 9110 may be provided.

[0421] The television device 9100 shown in FIG. 16(B) includes a receiver, a modem, and the like. The broadcasting device 9100 can receive general television broadcasts using a receiver. Furthermore, by connecting to a wired or wireless communication network via a modem, One-way (sender to receiver) or two-way (sender to receiver, or receiver to receiver) It is also possible to carry out information communication.

[0422] By applying the semiconductor device described in any of Embodiments 1 to 7 to the display portion 9103, This results in a television device with higher performance and reliability.

[0423] FIG. 16C shows a computer, which includes a main body 9201, a housing 9202, a display portion 9203, and a keyboard. keyboard 9204, external connection port 9205, pointing device 9206, etc. The computer displays a semiconductor device manufactured using one embodiment of the present invention on the display portion 9203. It is produced by using

[0424] By applying the semiconductor device described in any of Embodiments 1 to 7 to the display portion 9203, This results in a computer with higher performance and reliability.

[0425] FIG. 16D shows an example of a mobile phone. The mobile phone 9500 has a housing 9501. In addition to the display unit 9502 incorporated in the The device is equipped with a speaker 9505, a microphone 9506, an operation button 9507, etc. By applying the semiconductor device described in any one of the above to the display portion 9502, This results in a highly functional and reliable mobile phone.

[0426] In a mobile phone 9500 shown in FIG. 16D, information can be displayed by touching a display portion 9502 with a finger or the like. You can perform operations such as entering information, making calls, or composing emails.

[0427] The screen of the display unit 9502 has three main modes. The first is a mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. It is a combination of two modes: display mode and input mode.

[0428] For example, when making a call or creating an email, the display 9502 is used to input characters. The main input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 9502. stomach.

[0429] In addition, the mobile phone 9500 is equipped with sensors that detect tilt, such as a gyro and an acceleration sensor. By providing a detection device having the above, the orientation of the mobile phone 9500 (portrait or landscape) can be determined. In this way, the screen display on the display portion 9502 can be automatically switched.

[0430] The screen mode can be switched by touching the display portion 9502 or by pressing the operation button on the housing 9501. The button 9503 is operated. Also, depending on the type of image displayed on the display unit 9502, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, it switches to display mode, and if it is text data, it switches to input mode.

[0431] In the input mode, a signal detected by an optical sensor of the display unit 9502 is detected and displayed. If there is no input by touch operation of the part 9502 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0432] The display portion 9502 can also function as an image sensor. By touching the palm or fingers to the sensor 9502 and capturing an image of the palm print, fingerprint, etc., personal authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0433] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination. [Example]

[0434] In this example, a layer having an energy gap of 1.0 μm or less is formed on the first oxide semiconductor layer. a second oxide semiconductor layer having a thickness smaller than that of the first oxide semiconductor layer, and a third oxide semiconductor layer is formed on the second oxide semiconductor layer. Samples (Sample 1A, Sample 1B, Sample 2A, and Sample 2B) were prepared. The cross-sectional structures of Samples 1A, 1B, 2A, and 2B were observed. The ionization potentials of specimens 1A and 2A were measured, and based on the results, the energy bands were In this specification, the value of the ionization potential is calculated based on the band gap and the potential. The band gap value is measured by ellipsometry on a single film of the material. The resulting value is used.

[0435] As a sample 1A, a first oxide semiconductor layer 1001 was formed on a quartz substrate 1000. a 5 nm thick In-Ga-Zn oxide film as the second oxide semiconductor layer 1002; a 5 nm thick In-Sn-Zn oxide film as the third oxide semiconductor layer 1003; The In-Ga-Zn oxide films were deposited by sputtering. Film formation was carried out at a substrate temperature of 300°C in an oxygen atmosphere (100% oxygen) using the target In-Ga was grown using an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. In addition, the In-Sn-Zn oxide film is formed by In:Sn:Zn An oxide target with an atomic ratio of 2:1:3 is used.

[0436] Sample 1B was prepared by performing heat treatment on a stack of oxide semiconductor films formed in the same manner as Sample 1A, to form a mixed region. The heat treatment was performed at a temperature of 650° C. in a nitrogen atmosphere. After that, it was further carried out at a temperature of 650°C in an oxygen atmosphere for 1 hour.

[0437] As sample 2A, a first oxide semiconductor layer 1001 was formed on a quartz substrate 1000. a 5 nm thick In-Ga-Zn oxide film as the second oxide semiconductor layer 1002; a 5-nm thick In-Zn oxide film as the third oxide semiconductor layer 1003; The Ga-Zn oxide films were deposited on the substrate. The film was formed at a substrate temperature of 300°C in an oxygen atmosphere (100% oxygen). Using an oxide target with an atomic ratio of n:Ga:Zn=1:1:1, In-Ga-Zn The In-Zn oxide film is formed with an atomic ratio of In:Zn=2:1. ] oxide target is used.

[0438] Sample 2B is a sample obtained by performing heat treatment on a stack of oxide semiconductor films formed in the same manner as Sample 2A, to form a mixed region. The heat treatment was performed at a temperature of 650° C. in a nitrogen atmosphere. After that, it was further carried out at a temperature of 650°C in an oxygen atmosphere for 1 hour.

[0439] For specimens 1A, 1B, 2A, and 2B, the end faces were cut out and high-resolution transmission The electron microscope (Hitachi High-Technologies "H9000-NAR": TEM) was used with an accelerating voltage of 3 The cross-sectional observations of Samples 1A, 1B, 2A, and 2B were performed at a voltage of 00 kV. 7(B) shows sample 1A, Fig. 17(C) shows sample 1B, Fig. 18(B) shows sample 2A, Fig. 18(C) shows sample 2A. The TEM image of sample 2B is shown in Fig. 17(A). Schematic diagrams of sample 1A and sample 2A are shown in Fig. 17(A) and Fig. 17(B). 17A and 18A, the oxide semiconductor layer The interface is shown by a dotted line, but this is a schematic illustration.

[0440] The TEM images of the sample 1A and the sample 1B shown in FIGS. 17(B) and 17(C) show that the first The oxide semiconductor layer 1001 is a first In-Ga-Zn oxide film having a thickness of 5 nm, a second In-Ga-Zn oxide film having a thickness of 5 nm, and a The oxide semiconductor layer 1002 is an In-Sn-Zn oxide film having a thickness of 5 nm, and the third oxide A second In-Ga-Zn oxide film having a thickness of 5 nm was deposited as a semiconductor layer 1003. The TEM image of Sample 1A in FIG. 17(B) shows the stacked oxide semiconductors. The interface between the layers can be seen. On the other hand, Sample 1B, which was subjected to heat treatment after forming the oxide semiconductor stack, As shown in FIG. 17(C), the TEM image of the oxide semiconductor layer shows that there is no clear interface between the oxide semiconductor layers. It is a mixed area.

[0441] The TEM images of the sample 2A and the sample 2B shown in FIGS. 18(B) and 18(C) show that the first The oxide semiconductor layer 1001 is a first In-Ga-Zn oxide film having a thickness of 5 nm, a second In-Ga-Zn oxide film having a thickness of 5 nm, and a The oxide semiconductor layer 1002 is an In-Zn oxide film having a thickness of 5 nm, and the third oxide semiconductor The layer 1003 is a second In-Ga-Zn oxide film having a thickness of 5 nm. The TEM image of Sample 2A in FIG. 18(B) shows that the oxide semiconductor layer is On the other hand, the TE of Sample 2B, which was subjected to heat treatment after forming the oxide semiconductor stack, In the M image, as shown in Figure 18(C), no clear interface was observed between the stacked oxide semiconductor layers. It is a mixed region.

[0442] As shown in FIGS. 17(B)(C) and 18(B)(C), Sample 1A, Sample 1B, Sample 2A and Sample 2B are the first In-Ga-Z oxide semiconductor layer 1001. The n-based oxide film, the In-Sn-Zn-based oxide film which is the second oxide semiconductor layer 1002, and the I The n-Zn-based oxide film and the second In-Ga-Z oxide semiconductor layer 1003 The n-type oxide film contains crystals and is a crystalline oxide semiconductor with c-axis orientation (CAAC- It can be seen that the first oxide semiconductor layer 1001 is an I (oscillation-doped oxide) film. The n-Ga-Zn oxide film also contains an amorphous structure.

[0443] In the stack of oxide semiconductor layers, the crystalline state of each oxide semiconductor layer is not particularly limited. The oxide semiconductor layer may have a crystalline structure or an amorphous structure. Alternatively, an oxide semiconductor layer having a crystalline structure and an oxide semiconductor layer having an amorphous structure may be mixed. You may do so.

[0444] In addition, Sample 1A was obtained by using a single crystal silicon substrate as the substrate and forming a laminate film under the same film forming conditions. and ultraviolet photoelectron spectroscopy (UPS) while sputtering from the surface of sample 2A. Ionosphere by raviolet Photoelectron Spectroscopy The results of measuring the ionization potential are shown in FIGS.

[0445] 19 and 21, the horizontal axis represents the sputtering time from the sample surface, and the vertical axis represents the ionization potential. -Zn-based oxide film sputtering rate, In-Ga-Zn-based oxide film and In-Zn-based oxide The sample boundaries are shown assuming that the sputtering rates of the films are equal.

[0446] As can be seen from Figure 19, the ions are generated by the In-Sn-Zn oxide film sandwiched between the In-Ga-Zn oxide films. It can be seen that the ionization potential decreases. Represents the energy difference to the valence band.

[0447] The conduction band is calculated by subtracting the band gap measured by ellipsometry from the ionization potential value. The energy was calculated and the band structure of this laminated film was created. The band gaps of the oxide film and the In-Sn-Zn oxide film are 3.2 eV and 2.8 eV, respectively. The results are shown in Figure 20. Figure 20 shows the energy band shown in Figure 4(C). As shown in the figure, a buried channel is formed.

[0448] As can be seen from Figure 21, the ionized ions are generated in the In-Zn oxide film sandwiched between the In-Ga-Zn oxide films. The ionization potential decreases from the vacuum level to the valence electron level. Represents the energy difference up to the band.

[0449] The conduction band is calculated by subtracting the band gap measured by ellipsometry from the ionization potential value. The energy was calculated and the band structure of this laminated film was created. The band gaps of the oxide film and the In-Zn oxide film are 3.2 eV and 2.6 eV, respectively. The result is shown in Figure 22. Figure 22 shows the energy band diagram shown in Figure 4(C). As can be seen, a buried channel is formed.

[0450] In this example, the first oxide semiconductor layer and the third oxide semiconductor layer are made of In—Ga— A Zn-based oxide film is used, and the intrinsic conductivity is smaller than that of the first oxide semiconductor layer and the third oxide semiconductor layer. a second oxide semiconductor having an ionization potential and a small energy gap; The laminate using an In-Sn-Zn oxide film or an In-Zn oxide film as the dielectric layer is shown in Fig. 20, and it can be expressed by the energy band diagram shown in Figure 22 or Figure 4(C). Materials for the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer The combination is not particularly limited, and may be any of the energy balances shown in FIG. 20, FIG. 22, or FIG. 4(C). To obtain a band diagram, the implementer should select the appropriate material taking into consideration the energy gap of the material to be used. You can choose and combine them. [Example]

[0451] In this embodiment, the transistors shown as the transistors 440a, 440b, and 430 in Embodiment 1 are a stack of oxide semiconductor layers including the first oxide semiconductor layer and the second oxide semiconductor layer; Transistors having the above structure (Example Transistors 1 to 4 and Comparative Example Transistors 1 to 4) The characteristics of the

[0452] The calculations in this example were performed using the simulation software TCAD (Technology Aided Design) manufactured by Synopsys. Computer-Aided Design (CDA) was used.

[0453] Example transistor 1, Example transistor 2, Comparative example transistor 1, and Comparative example transistor As the transistor 2, as shown in the transistors 440a and 440b in the first embodiment, A first oxide semiconductor is formed on a gate insulating film having a thickness of 100 nm provided on the gate electrode layer. an oxide semiconductor stack in which a dielectric layer and a second oxide semiconductor layer are stacked in this order; A bottom gate structure (channel) having a source electrode layer and a drain electrode layer provided thereon. The transistors used were etched.

[0454] Example transistor 3, Example transistor 4, Comparative example transistor 3, and Comparative example transistor The transistor 4 is a transistor having a gate voltage similar to that of the transistor 430 in the first embodiment. A source electrode layer and a drain electrode layer are formed on a 100 nm thick gate insulating film provided on the electrode layer. a first oxide semiconductor layer and a second oxide semiconductor layer on the source electrode layer and the drain electrode layer; a bottom-gate transistor having an oxide semiconductor stack in which conductor layers are stacked in order; was used.

[0455] In the example transistors 1 to 4 and the comparative example transistors 1 to 4, the channel The length (L) and width (W) of the channel are both 10 μm and the drain voltage (Vd) is 1 V. and calculated it.

[0456] Furthermore, the structure of the oxide semiconductor stack included in the example transistors 1 to 4 is The first oxide semiconductor layer and the second oxide semiconductor layer have different gaps. The conductive layer was a 5 nm thick In-Sn-Zn oxide film, and the second oxide semiconductor layer was a 5 nm thick In-Sn-Zn oxide film. Example transistor 1 and example transistor 2 each having an In-Ga-Zn oxide film with a thickness of 5 nm The first oxide semiconductor layer is a 5 nm thick In-Ga-Zn oxide film. The oxide semiconductor layer of Example 2 is an In-Sn-Zn oxide film having a thickness of 5 nm. The transistors were designated as transistor 2 and example transistor 4.

[0457] On the other hand, the oxide semiconductor stacks included in Comparative Transistors 1 to 4, which are comparative examples, have the following configurations: a first oxide semiconductor layer and a second oxide semiconductor layer having the same energy gap; The oxide semiconductor layer is an In-Ga-Zn oxide film with a thickness of 5 nm, and the second oxide semiconductor The layer has an In-Ga-Zn oxide film with a thickness of 5 nm (i.e., an oxide semiconductor film). Comparative Example Transistor 1 and Comparative Example Transistor 2 The first oxide semiconductor layer is a 5 nm thick In-Sn-Zn oxide film. The oxide semiconductor layer of 2 has an In-Sn-Zn oxide film with a thickness of 5 nm (i.e. Comparative Example Transistor 2 and Comparative Example Transistor 3 each having an oxide semiconductor layer formed of a single layer of ITGO film It was set to Stadium 4.

[0458] The In-Ga- included in the example transistors 1 to 4 and the comparative example transistors 1 to 4 Zn-based oxide film has a band gap of 3.15 eV and a carrier lifetime of 1 nsec. , bulk mobility 10 cm 2 / Vs, the electron affinity is calculated as 4.6 eV, and In-Sn -Zn-based oxide film has a band gap of 2.8 eV and a carrier lifetime of 1 nsec , bulk mobility 35 cm 2 / Vs, and the electron affinity was calculated as 4.6 eV.

[0459] Example transistor 1, example transistor 2, and comparative example transistor obtained by calculation 23(A) and 23(B) show the off-state current values ​​of the example transistor 1 and the comparative example transistor 2. Example transistor 3, Example transistor 4, Comparative example transistor 3, and Comparative example transistor 4 The values ​​of the current are shown in Figures 23(A) and 25(B), respectively. 23(A) or 25(A), the drain current is 1.0×10 -35 A to 1. 0×10 -25 23(A)(B) and 25 are graphs showing an enlarged view of the range A. In (A) and (B), the vertical axis represents the drain current (A) and the horizontal axis represents the gate voltage (V).

[0460] In addition, the calculated values ​​of Example Transistor 1, Example Transistor 2, and Comparative Example Transistor The field effect mobility of the example transistor 1 and the comparative example transistor 2 is shown in FIG. The electric field of the example transistor 3, the example transistor 4, the comparative example transistor 3, and the comparative example transistor 4 The field-effect mobility is shown in FIG. 26. In FIG. 24 and FIG. 26, the vertical axis represents the field-effect mobility. (cm 2 / Vs), and the horizontal axis indicates the gate voltage (V).

[0461] Example transistor 1, example transistor 2, and comparative example transistor are transistors with the same structure. In the transistor 1 and the comparative example transistor 2, as shown in FIGS. The field-effect mobility also differed as shown in FIG.

[0462] Similarly, Example Transistor 3, Example Transistor 4, and In the comparative example transistor 3 and the comparative example transistor 4, the As shown in FIG. 26, the off-state current values ​​were different, and the field-effect mobility also showed different values.

[0463] In particular, in this example, in the field-effect mobility shown in FIGS. 24 and 26, the oxide semiconductor stack The difference in the value was significant depending on the oxide semiconductor material used and the stacking order.

[0464] From the above results, it can be seen that the oxides used in transistors have the same structure but different band gaps. By stacking semiconductor layers, the electrical characteristics of the transistor (in this embodiment, It was shown that the field effect mobility and off-current characteristics can be varied in various ways.

[0465] Therefore, by using a stack of oxide semiconductor layers, the electrical characteristics of a transistor can be improved. This allows for good control, making it possible to impart desired electrical characteristics to the transistor. [Explanation of symbols]

[0466] 101 Oxide semiconductor layer 102 Oxide semiconductor layer 103 Oxide semiconductor layer 105 Mixed area 106 Element isolation insulating layer 108 Gate insulating film 110 gate electrode 111 Oxygen excess region 112 Oxygen excess region 113 Oxygen Excess Region 116 Channel formation region 120 Impurity region 121a Low resistance area 121b Low resistance region 121c Channel formation region 122a Low resistance area 122b Low resistance region 122c Channel formation region 124 Metal compound area 128 insulating film 130 insulating film 140 transistors 142a Drain electrode 142b Drain electrode 144 Oxide Semiconductor Stack 146 Gate insulating film 148 gate electrode layer 150 insulating film 152 insulating film 153 Electrode layer 156 Wiring 162 transistors 164 Capacitor 185 PCB 191 Oxide semiconductor film 192 Oxide semiconductor film 340 transistors 343 Transistor 380a transistor 380b transistor 380c transistor 383 Transistor 400 boards 401 Gate electrode layer 402 Gate insulating film 403 Oxide Semiconductor Stack 404a Source electrode layer 404b Drain electrode layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating Film 409 Insulating Film 410 Transistor 413 Transistor 416 Planarization insulating film 418 Transistor 420 transistors 421 Dopant 427 Insulating Film 430 transistors 431 Oxygen 433 Transistor 438 Transistor 440a transistor 440b transistor 440c transistor 440d transistor 443a Transistor 443b transistor 449 Transistor 465a Wiring layer 465b wiring layer 480 transistors 483 Transistor 493 Lamination 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 631 Insulating film 632 insulating film 633 Interlayer insulating film 634 Interlayer insulating film 640 transistors 641 Electrode layer 642 Electrode layer 643 Conductive Layer 645 Conductive Layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photo sensor reference signal line 1000 boards 1001 oxide semiconductor layer 1002 Oxide semiconductor layer 1003 Oxide semiconductor layer 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 insulating film 4021 Insulating film 4023 Insulating film 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 4033 Insulating film 4510 Bulkhead 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 9000 tables 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9100 Television equipment 9101 Housing 9103 Display section 9105 Stand 9107 Display section 9109 Operation key 9110 Remote control device 9201 Main Unit 9202 Housing 9203 Display section 9204 keyboard 9205 External connection port 9206 Pointing Device 9500 mobile phone 9501 Housing 9502 Display section 9503 Operation button 9504 External connection port 9505 Speaker 9506 Microphone 9507 Operation button

Claims

1. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; A capacitance element, a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having an opening; an oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a top surface of the second insulating layer, and a region in contact with a top surface of the first conductive layer in the opening, and having a function as one electrode of the capacitor and a function as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the second insulating layer and serving as the other of the source electrode and drain electrode of the second transistor; a fourth conductive layer having a region located under the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a third insulating layer having a region overlying the second conductive layer; a fifth conductive layer having a region overlapping with the second conductive layer with the third insulating layer interposed therebetween and having a function as the other electrode of the capacitor element; the opening has a region overlapping with the first conductive layer and does not have a region overlapping with the oxide semiconductor layer.

2. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; A capacitance element, a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having an opening; an oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a top surface of the second insulating layer, and a region in contact with a top surface of the first conductive layer in the opening, and having a function as one electrode of the capacitor and a function as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the second insulating layer and serving as the other of the source electrode and drain electrode of the second transistor; a fourth conductive layer having a region located under the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a third insulating layer having a region overlying the second conductive layer; a fifth conductive layer having a region overlapping with the second conductive layer with the third insulating layer interposed therebetween and having a function as the other electrode of the capacitor element; the opening has a region overlapping with the first conductive layer and does not have a region overlapping with the oxide semiconductor layer; the second conductive layer has a region overlapping with the fourth conductive layer with the oxide semiconductor layer interposed therebetween; the third conductive layer has a region overlapping with the fourth conductive layer with the oxide semiconductor layer interposed therebetween.

3. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; A capacitance element, a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having an opening; an oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a top surface of the second insulating layer, and a region in contact with a top surface of the first conductive layer in the opening, and having a function as one electrode of the capacitor and a function as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the second insulating layer and serving as the other of the source electrode and drain electrode of the second transistor; a fourth conductive layer having a region located under the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a third insulating layer having a region overlying the second conductive layer; a fifth conductive layer having a region overlapping with the second conductive layer with the third insulating layer interposed therebetween and functioning as the other electrode of the capacitor; a fourth insulating layer having a region in contact with an upper surface of the fifth conductive layer; the opening has a region overlapping with the first conductive layer and does not have a region overlapping with the oxide semiconductor layer; The fourth conductive layer comprises an organic material.

4. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; A capacitance element, a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having an opening; an oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a top surface of the second insulating layer, and a region in contact with a top surface of the first conductive layer in the opening, and having a function as one electrode of the capacitor and a function as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the second insulating layer and serving as the other of the source electrode and drain electrode of the second transistor; a fourth conductive layer having a region located under the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a third insulating layer having a region overlying the second conductive layer; a fifth conductive layer having a region overlapping with the second conductive layer with the third insulating layer interposed therebetween and functioning as the other electrode of the capacitor; a fourth insulating layer having a region in contact with an upper surface of the fifth conductive layer; the opening has a region overlapping with the first conductive layer and does not have a region overlapping with the oxide semiconductor layer; the fourth conductive layer comprises an organic material; the second conductive layer has a region overlapping with the fourth conductive layer with the oxide semiconductor layer interposed therebetween; the third conductive layer has a region overlapping with the fourth conductive layer with the oxide semiconductor layer interposed therebetween.

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