Method for manufacturing vertical type field-effect transistor structure, and corresponded vertical type field-effect transistor structure

Abstract

To provide a method for manufacturing a vertical type field-effect transistor structure, and the vertical type field-effect transistor structure.SOLUTION: A vertical type field-effect transistor structure comprises: a semiconductor main body (100) that includes first connection regions (12 and 14) of a first conductive type (n) and a second connection region (30); the first conductive type or a second conductive type (p) channel region (20) that is arranged to between the first and second connection regions; a trench (60') that is extended into the semiconductor main body, passes a channel region from the second connection region, reaches to each first connection region, and forms a fin of the channel region and the second connection region; a control electrode that is adjacent to the channel region arranged in the trench, and is insulated and arranged from the semiconductor main body; and a breakdown circuit path that is a break-down voltage between the first and second connection regions, includes at least one pn bonding part, and is conducted when it is reached to the breakdown voltage applied to between the first and second connection regions.SELECTED DRAWING: Figure1h

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a vertical field effect transistor structure and to a corresponding vertical field effect transistor structure. [Background technology]

[0002] In the application of wide bandgap semiconductors (eg, silicon carbide (SiC) or gallium nitride (GaN)) in power electronics, power MOSFETs with vertical channel areas (TMOSFETs) are typically used.

[0003] The TMOSFET concept involves an n+ source area and a p-channel area in a semiconductor material interrupted by a trench that extends to the n- drift area. Within the trench is a gate electrode, separated from the semiconductor material by a gate oxide, which serves to control the channel area.

[0004] By appropriate selection of geometry, epitaxial doping, channel doping, and screening doping, the on-resistance, threshold voltage, short circuit resistance, oxide loading, and breakdown voltage of such TMOSFETs can be optimized.

[0005] FIG. 3 shows a partial perspective view of a vertical field effect transistor structure according to the prior art DE 10224201 B4 as a starting point for the present invention. The semiconductor component shown in Fig. 3 realizes an n-type vertical trench MOSFET with a shielding structure arranged in the trench. This known structure can of course also be applied to p-type MOSFETs, with the necessary exchange of doping as explained below.

[0006] The semiconductor component comprises a semiconductor body 100 having an n-doped first connection region 12, 14 which is more heavily n-doped in a region on the back side of the semiconductor body 100 forming there an n+ drain region 12 of the MOSFET, followed by a more lightly n-doped n- drift region 14. Following the n- drift region 14, the semiconductor body 100 further comprises a p-channel region or body region 20 formed between the n- drift region 14 and a more heavily n-doped second n+ connection region 30 formed in a region on the front side. The second n+ connection region 30 forms the source region of the MOSFET.

[0007] Starting at the front side 101 of the semiconductor body 100, a number of trenches 60 (two of which are shown in FIG. 3) extend through the n+ source region 30, the p-body region 20, and into the n- drift region 14 of the semiconductor body 100.

[0008] Disposed within the sidewall regions of the trenches 60 are respective control electrodes 40 which are interconnected to form the gate electrodes of the MOSFET. The gate electrodes 40 are insulated from the semiconductor body 100 by a gate insulating layer 50 and extend vertically through the semiconductor body from the n+ source regions 30 along the p body regions 20 to the n- drift region 14, forming a conductive channel in the body region 20 along the sidewalls of the trenches between the n+ source regions 30 and the n- drift region 14 when a suitable driving potential is applied.

[0009] The semiconductor component includes a number of similar transistor structures, so-called cells, with respective n+ source regions 30, p-body regions 20 and gate electrodes 40, where in this example all the cells have in common an n- drift region 14 and an n+ drain region 12, where the n+ source regions 30 of all the cells are conductively connected to each other to form a common source region, and the gate electrodes 40 of all the cells are conductively connected to each other to form a common gate electrode.

[0010] The semiconductor component shown in FIG. 3 includes a shielding structure with an electrode 80 formed in the respective trench 60 and insulated from the respective gate electrode 40 by a further insulating layer 70. This electrode 80 extends vertically over the entire length of the trench and contacts the semiconductor body 100 at the bottom of the trench 60 in the region of the drift region 14. This contact region between the electrode 80 and the drift region 14 is provided with a p-doped region 90, which is contacted by the electrode 80 and completely covers the electrode in this region. The p-doped region 90 and the drift region 14 or the drain region 12 form a diode (whose circuit symbol is shown in FIG. 3) which, in the illustrated n-type MOSFET, is forward biased in the source-drain direction and reverse biased in the drain-source direction. The breakdown voltage of this diode in the drain-source direction is adjusted by the doping of the p-doped region 90. A JFET is formed in the p-doped region, which serves to limit the current through the channel area in the event of a short circuit.

[0011] The electrode 80 arranged in the trench 60 is short-circuited with the n+ source region 30. For this purpose, the electrode 80 is connected to the n+ source region 30 directly at the sidewall of the trench 60 in the upper region of the trench. Thereby, the electrode 80, which preferably consists of metal or polysilicon, in particular of n-doped or p-doped polysilicon, simultaneously serves as a connection contact for the n+ source region 30 and can be contacted above the trench 60 so as to be in direct contact with the n+ source region 30, whereby a contact connection above the semiconductor regions arranged between the trenches, the so-called mesa regions, can be dispensed with.

[0012] The semiconductor component further comprises a highly p-doped p+ body connection region 22 which, as is evident from the perspective view in Fig. 3, extends from the p body region 20 between the sections of the n+ source region 30 to the front surface of the semiconductor body 100 and contacts an electrode 80 in the upper region of the trench 60, which electrode 80 short-circuits the p body region 20 and the n+ source region 30 via the p+ body connection region 22, avoiding parasitic bipolar effects in a known manner. In this semiconductor component, it is possible to dispense with a separate contact for short-circuiting the n+ source region 30 and the p body region 20 in the semiconductor region formed between the trenches, the so-called mesa region.

[0013] A narrow p+ body connection region 22 is sufficient to connect the p body region 20 to the electrode 80 to achieve a short circuit, and therefore the space requirement for this in the mesa area is small. The body diode between the source 30 and the drain 14 caused by the short circuit between the n+ source region 30 and the p body region 20 is biased corresponding to the diode of the shield structure.

[0014] The threshold voltage of the shield structure is set to be smaller than the threshold voltage of the body diode. When a positive voltage is applied in the source-drain direction, most of the current flows through the forward biased diode of the shield structure, and therefore the cross-sectional area of ​​the p+ body connection region 22, where the p body region 20 and the n+ source region 30 are shorted, can be reduced and thus realized in a space-saving manner. This allows the dimensions of this silicon region between the trenches 60 to be reduced compared to conventional semiconductor components, which contributes to a reduction in the specific on-resistance of the semiconductor component.

[0015] The known semiconductor component functions like a conventional MOSFET (whose circuit symbol is shown in FIG. 3) when a positive drain-source voltage and a positive gate potential with respect to the source potential are applied. When the drain-source voltage in the cut-off state of the MOSFET exceeds the threshold voltage of the diode formed by the p-doped region 90 and the drift region 14, a reverse current flows from the drain terminal connected to the drain region 12 through the drift region 14, the p-doped region 90 and the electrode 80 to the source terminal connected to the electrode 80. This breakdown structure functions like a body diode when a voltage in the reverse direction, i.e. a positive voltage in the source-drain direction, is applied and takes over most of the current flowing therein, so that the connecting contact for the p-body region 20 can be made small and space-saving.

[0016] In the TMOSFET according to Figure 3, a short circuit can occur, for example, if the switch is turned on without applying a gate voltage: in this case, a high drain voltage is applied to the semiconductor component, and if appropriate measures are not taken, very high short circuit currents can flow, which can lead to the destruction of the component.

[0017] The limitation of the short circuit current can be achieved by the JFET formed by the p-doped region 90, the space charge region originating from the p-doped region 90 being close enough for pinch-off of the short circuit current to occur, and thus the p-doped region 90 acts as a p-shield region in the event of a short circuit. [Prior art documents] [Patent documents]

[0018] [Patent Document 1] German patent no. 10224201B4 Summary of the Invention [Problem to be solved by the invention]

[0019] The general optimization problem with TMOSFETs is that each power MOSFET must be designed to compromise between low on-resistance (i.e., high current at low drain voltage) and low short-circuit current (i.e., low current at high drain voltage). [Means for solving the problem]

[0020] The present invention provides a vertical field effect transistor structure as claimed in claim 1 and a method for manufacturing a vertical field effect transistor structure as claimed in claim 7. Preferred developments are the subject matter of the respective dependent claims. Advantages of the Invention The idea behind the present invention is to provide a p-shield implant in, for example, only every other trench in a vertical field effect transistor structure and still achieve a good compromise between low short circuit current and low on-resistance.

[0021] The p-body connection can be designed deeper than the p-body area and thus extends into the n-drift region. This results in a PN junction under the channel, which contributes to reducing the resistance at high drain voltages and thus further reducing the short circuit current. That is, at high drain voltages, a depletion zone is created in the n-drift region, which leads to an increase in the resistance of the component. Now, in the event of a short circuit, it is precisely this increase in resistance that helps to limit the short circuit current.

[0022] Since the short circuit current is further limited by this PN junction in addition to the JFET formed under the fin between the two p-shield implants, according to the invention, it is sufficient to inject, for example, only one trench in two, resulting in a p-shield area only under one trench in two. Gate electrodes in trenches without a p-shield area under the trench bottom are designed as non-bisected, since there is no p-shield area under the trench that needs to be contacted. Gate electrodes in trenches with a p-shield area under the trench bottom can be designed as bisected (especially when the p-body connection does not reach the p-shield area and does not contact it, as in FIG. 1c) or as unsplit electrodes (especially when the area is already contacted by a deep p-body connection, as in FIG. 2b).

[0023] The trenches are preferably widened by repeated oxidation and oxide etches, and the mesas between the trenches are narrowed into fins. According to a preferred development, the reverse current path extends into the trench, in which respective electrodes are arranged, the electrodes being conductively connected to the second connection area and electrically insulated with respect to the control electrode, and a first of the electrodes contacts a doped area of ​​the second conductivity type at the bottom of a first of the trenches.

[0024] According to a further preferred development, the body connection region of the second conductivity type is in electrical contact with the doped area of ​​the second conductivity type, and the reverse current path runs through the body connection region of the second conductivity type and through the doped area of ​​the second conductivity type, which has the advantage that complex processing of this connection in a trench for producing an electrode can be avoided.

[0025] According to a further preferred development, the first connection region has a lightly doped drift region and a heavily doped drain region of a first conductivity type, a doped region of a second conductivity type is arranged in the drift region, and a body connection region of the second conductivity type extends into the drift region.

[0026] According to a further preferred development, a diffusion area of ​​the first conductivity type is provided between the first connection region and the channel area, which contributes to a better current distribution. According to a further preferred development, the semiconductor body consists of silicon carbide or gallium nitride.

[0027] Further features and advantages of the invention will be explained below on the basis of embodiments with reference to the drawings. [Brief description of the drawings]

[0028] [Figure 1a] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a first embodiment of the present invention; [Figure 1b] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a first embodiment of the present invention; [Figure 1c] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a first embodiment of the present invention; [Figure 1d] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a first embodiment of the present invention; [Figure 1e] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a first embodiment of the present invention; [Figure 1f] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a first embodiment of the present invention; [Figure 1g]1A-1D are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a first embodiment of the present invention; [Figure 1h] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a first embodiment of the present invention; [Figure 2a] 5A-5C are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a second embodiment of the present invention. [Figure 2b] 5A-5C are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a second embodiment of the present invention. [Diagram 3] 1 is a partial perspective view of a vertical field effect transistor structure according to prior art DE 10224201 B4, which is the starting point of the present invention; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] In the drawings, like reference numbers indicate identical or functionally identical elements. 1a-h are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to one embodiment of the present invention.

[0030] FIG. 1a shows a semiconductor body 100 having a heavily n-doped region 12 (later n+ drain region) in the backside region, a lightly n-doped n-drift region 14 following the n+ drain region 12, a p-doped region 20 (later body region) following the n-drift region 14, and a heavily n-doped region (later n+ source region 30) following the body region 20 at the front side 101. Optionally, an n-diffusion region 14a can be provided between the n-drift region 14 and the body region 20, which contributes to a better current distribution during operation. The diffusion region 14a can be deeper in the n-drift region 14 if necessary, or can reach deeper into the n-drift region 14, in particular between the p-shield areas 90.

[0031] The process state according to Fig. 1a is achieved by preparing a semiconductor body 100 in the form of a semiconductor wafer, followed by epitaxy and implantation steps known per se. Using a hard mask M, trenches 60 are etched on the front side 101 by a trench etching process, then a scattering oxide 120 is deposited on the walls of the trenches 60. Optionally (not shown), another n-type implantation step can also be performed to generate n-diffusion regions in the n-drift regions 14.

[0032] According to FIG. 1b, a p-type implant I is then performed to form a p-doped area 90 (p-shield area) in the n-drift area 14 under the trench 60. No p-type implant is performed in other adjacent trenches. The p-type implant can be performed at periodic intervals. For example, a p-shield area can be implanted under every second, every third, or every fourth trench, with no p-type implant in the trenches located in between. Other patterns of p-shield areas are possible as well, for example two consecutive trenches with implanted p-shield areas followed by one trench without p-type implantation. It is also possible to perform a p-type implant only partially in the trench, while keeping the n-drift area 14 partially in the trench.

[0033] In contrast to the known structure according to FIG. 3, with p-type implantation I through corresponding openings in the hard mask M, the p-body regions 20 can also be contacted in three dimensions via p+ doped areas 22′, which are alternated with n+ source regions 30 along the n+p fin FI.

[0034] Furthermore, the p+ doped area 22' can be implanted much deeper than the p+ doped area 22 according to Figure 3. In particular, the p+ doped area 22' in this embodiment can extend into the n- drift region 14, as shown in dashed lines in Figure 1b and in perspective partial cross-section in Figure 1c.

[0035] The annealing step makes it possible to diffuse and activate the p-doped regions 90 and / or the p+ doped areas 22'. With further reference to FIG. 1d, the hard mask M and the scattering oxide 120 are removed.

[0036] Then, according to Fig. 1e, at least the trench 60 in which the implantation step I according to Fig. 1b has been performed is widened and the widened trench 60' is laterally defined by a narrowed n+ / p mesa region (also called n+ / p fin FI). This is done by repeated oxidation and oxide etching of the n+ / p mesa region. This step removes unwanted p-type implanted regions from the sidewalls of the n+ / p mesa region, which may result from the implantation step I according to Fig. 1b.

[0037] FIG. 1f shows the structure after deposition of a gate insulating layer 50 and a polysilicon layer 40 from which, according to FIG. 1g, the gate electrode 40 is produced on the sidewalls of the widened trench 60'. These gate electrodes 40 can be produced, for example, by the so-called polyspacer process. For this purpose, the polysilicon layer 40 is etched back, for example by an anisotropic etching method, in order to remove it at the bottom of the trenches 60' and from the front surface 101 of the semiconductor body 100 and also partially from the side walls of the upper region of the widened trenches 60'. Similarly, the gate insulating layer 50 is removed from the front surface 101.

[0038] Finally, an insulating layer 70, for example an oxide layer, is produced on the exposed regions of the gate electrode 40. For this purpose, the insulating layer 70 is deposited on the gate electrode 40 or the gate electrode 40 is subjected to an oxidation process. The insulating layer 70 is then removed from the front side 101 of the semiconductor body 100 and in the bottom region of the widened trench 60'.

[0039] The widened trench 60' is then filled with an electrode material, such as metal or polysilicon, to create an electrode 80, as shown in FIG. 1h, to achieve a vertical field effect transistor structure according to an embodiment of the present invention.

[0040] If the electrode consists of metal or n-doped silicon, advantageously, before making the electrode 80, the exposed front surface 101 of the semiconductor body 100 is coated with a silicide, at least in the region of the p-doped area, in order to obtain a good ohmic contact between the electrode 80 and the p-doped area 90 and to prevent the creation of a pn junction or a Schottky contact at this junction. The contact creation of the gate electrode 40 can be performed similarly to known trench transistors and is not shown here.

[0041] Here, the process sequence described above only focuses on the processes in the cell field. Outside the cell field, other processes such as edge termination and contact pad lead-out must also be considered. Furthermore, each step may include multiple sub-steps (not detailed).

[0042] 2a, b are schematic cross-sectional views illustrating a method for manufacturing a vertical field effect transistor structure and a corresponding vertical field effect transistor structure according to a second embodiment of the present invention.

[0043] As already described with reference to Fig. 1b, a p-type implant I was performed to form a p-doped region 90a (p-shield region) in the n-drift region 14 under the trench 60. The p-type implant was performed only under one trench, and not in the other adjacent trenches. The p-type implant I can be performed in a similar manner as described with reference to Fig. 1b.

[0044] FIG. 2a shows a completed vertical field effect transistor structure according to the second embodiment in a process state similar to that of FIG. 1f. Unlike FIG. 1f, according to FIG. 2a the p+ doped area 22'' is implanted deeper into the n- drift region 14. This brings the p+ doped area 22'' and the p doped region 90a into contact with each other and therefore electrically connected to each other. In this way, no electrical connection of the p doped region 90a (p shield area) via the electrode 80 is necessary. This is advantageous since it makes it possible to avoid the need for complex processing of this connection in the trench 60' to make the electrode 80.

[0045] Thus, the trench 60' according to FIG. 2a is filled only with the insulating layer I in order to obtain a flat front surface 101. It should be noted that further layers can also be applied for filling and planarization. In particular in the case of the area 22'' implanted deep in the n-drift region 14 and in contact with the p-doped region 90a, the bisection of the electrode 40 can be eliminated. In this case (not shown), the trench is completely filled with the electrode material and insulated at the surface by the insulating layer I.

[0046] FIG. 2b shows a similar process state to FIG. 1c in a perspective partial cross-sectional view to reveal that the p+ doped area 22'' and the p doped region 90a are in contact with each other. Although the invention has been described based on preferred exemplary embodiments, the invention is not limited thereto. In particular, the materials and topologies mentioned are merely exemplary and are not limited to the examples described. The geometries shown are also merely exemplary and can be arbitrarily modified as required.

[0047] Although in the embodiment described above the p+ doped areas and the p doped regions are formed in a common implantation step, it is also possible to use two separate implantation steps for this purpose. [Explanation of symbols]

[0048] 12, 14 First connecting section 14a Diffusion Area 20 Channel Area 22';22'' Body Connection Area 30 Second connecting area 40 Control electrode 60' Trench 90;90a Dope Area 80 electrodes 100 Semiconductor body FI fins

Claims

1. A semiconductor body (100) having a first connection area (12, 14) of a first conductivity type (n) and a second connection area (30), a channel section (20) of said first conductivity type (n) or of a second conductivity type (p) complementary to said first conductivity type, arranged between said first and second connection sections (12, 14; 30); a plurality of trenches (60') extending into said semiconductor body (100), said trenches (60') extending from said second connection area (30) through said channel area (20) to said first connection area (12, 14) to form fins (FI) of said channel area (20) and said second connection area (30); a control electrode (40) disposed within the trench (60'), the control electrode (40) being adjacent to the channel region (20) and being insulated from the semiconductor body (100); a reverse current path connected between the first and second connection sections (12, 14; 30) in parallel to the channel section (20), the reverse current path having at least one pn junction and configured to be conductive when a threshold voltage applied between the first and second connection sections (12, 14; 30) is reached; A vertical field effect transistor structure comprising: said semiconductor body (100) has in said first connection area (12, 14) below a first one of said trenches (60') a doped area (90; 90a) of said second conductivity type (p), and said first connection area (12, 14) below a second one of said trenches (60') does not have a doped area (90; 90a) of said second conductivity type (p), the fin (FI) has a body connection region (22'; 22'') of the second conductivity type (p) in electrical contact with the channel region (20) and the second connection region (30); the body connection region (22'; 22'') of the second conductivity type (p) extends into the drift region (14); Vertical field effect transistor structure.

2. 2. The vertical field effect transistor structure of claim 1, wherein the reverse current path extends into the trench (60') and wherein respective electrodes (80) are arranged in the trench (60'), the electrodes (80) are conductively connected to the second connection area (30) and electrically insulated with respect to the control electrode (40), and a first one of the electrodes (80) contacts the doped area (90; 90a) of the second conductivity type (p) at a bottom of the first one of the trenches (60').

3. 2. The vertical field effect transistor structure of claim 1, wherein the body connection region (22'') of the second conductivity type (p) is in electrical contact with the doped area (90a) of the second conductivity type (p), and the breakdown current path extends through the body connection region (22'') of the second conductivity type (p) and the doped area (90a) of the second conductivity type (p).

4. 4. The vertical field effect transistor structure of claim 1, 2 or 3, wherein the first connection area (12, 14) has a lightly doped drift region (14) and a heavily doped drain region (12) of the first conductivity type (n), the doped area (90; 90a) of the second conductivity type (p) is arranged in the drift region (14) and the body connection area (22'; 22'') of the second conductivity type (p) extends into the drift region (14).

5. 5. The vertical field effect transistor structure according to claim 1, wherein a diffusion area (14a) of the first conductivity type (n) is provided between the first connection region (12, 14) and the channel area (20).

6. The vertical field effect transistor structure of any one of claims 1 to 5, wherein the semiconductor body (100) is made of silicon carbide (SiC) or gallium nitride (GaN).

7. 1. A method for fabricating a vertical field effect transistor structure, comprising: Providing a semiconductor body (100) having a first connection area (12, 14) and a second connection area (30) of a first conductivity type (n) and a channel area (20) of either the first conductivity type (n) or a second conductivity type (p) complementary to the first conductivity type, arranged between the first and second connection areas (12, 14; 30), forming a plurality of trenches (60') extending into said semiconductor body (100), said trenches (60') extending from said second connection area (30) through said channel area (20) to said first connection area (12, 14) to form fins (FI) of said channel area (20) and said second connection area (30); forming a control electrode (40) disposed in said trench (60'), the control electrode (40) being disposed adjacent to said channel region (20) and insulated from said semiconductor body (100); forming a reverse current path between said first and second connection sections (12, 14; 30), connected in parallel to said channel section (20), said reverse current path having at least one pn junction and configured to become conductive when a threshold voltage applied between said first and second connection sections (12, 14; 30) is reached; forming a doped area (90; 90a) of the second conductivity type (p) in the first connection area (12, 14) below a first one of the trenches (60'), the first connection area (12, 14) below a second one of the trenches (60') not having a doped area (90; 90a) of the second conductivity type (p); forming in said fin (FI) a body connection region (22'; 22'') of said second conductivity type (p) in electrical contact with said channel region (20) and with said second connection region (30); Including, the body connection region (22'; 22'') of the second conductivity type (p) is formed to extend into the drift region (14); method.

8. 8. The method of claim 7, wherein the doped area (90; 90a) of the second conductivity type (p) and the body connection region (22'; 22'') of the second conductivity type (p) are formed in a common implantation step (I).

9. 9. The method according to claim 7 or 8, wherein the reverse current path extends into the trench (60') and wherein respective electrodes (80) are arranged in the trench (60'), the electrodes (80) being conductively connected to the second connection area (30) and electrically insulated with respect to the control electrode (40), and a first one of the electrodes (80) contacts the doped area (90; 90a) of the second conductivity type (p) at a bottom of the first one of the trenches (60').

10. 9. The method of claim 7 or 8, wherein the body connection region (22'') of the second conductivity type (p) is in electrical contact with the doped area (90a) of the second conductivity type (p) and the breakdown current path is formed to extend through the body connection region (22'') of the second conductivity type (p) and the doped area (90a) of the second conductivity type (p).

11. 11. The method according to claim 7, wherein the first connection area (12, 14) comprises a lightly doped drift region (14) and a heavily doped drain region (12) of the first conductivity type (n), the doped area (90; 90a) of the second conductivity type (p) is arranged in the drift region (14), and the body connection area (22'; 22'') of the second conductivity type (p) extends into the drift region (14).

12. 12. The method according to any one of claims 7 to 11, wherein a diffusion area (14a) of the first conductivity type (n) is provided between the first connection region (12, 14) and the channel area (20).

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