Semiconductor device

Abstract

To provide a semiconductor device having electrical characteristics such as high breakdown voltage, low reverse saturation current, and high on-current, especially to provide a power diode including a non-linear element and a rectifier.SOLUTION: A semiconductor device comprises: a first electrode; a gate insulating layer covering the first electrode; an oxide semiconductor layer that contacts the gate insulating layer and overlaps with the first electrode; a pair of second electrodes covering the end portions of the oxide semiconductor layer; an insulating layer covering the pair of second electrodes and the oxide semiconductor layer; and a third electrode that contacts the insulating layer and is provided between the pair of second electrodes. The pair of second electrodes contacts the end faces of the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technical field of the disclosed invention relates to a semiconductor device including an oxide semiconductor.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. In this specification, a transistor is included in the nonlinear element, The nonlinear element is a semiconductor device, and electro-optical devices, semiconductor circuits, and electronic devices each including the nonlinear element are All child devices are also included in the semiconductor device. [Background technology]

[0003] Display devices such as flat panel displays (e.g., liquid crystal displays and light-emitting displays) The transistors contained in the device are made of amorphous silicon or polycrystalline silicon on a glass substrate. Many of them are made of silicon semiconductors such as crystalline silicon.

[0004] Instead of silicon semiconductors, metal oxides that exhibit semiconducting properties are used in transistors. In this specification, metal oxides that exhibit semiconducting properties are referred to as oxide semiconductors. Let us call it a conductor.

[0005] Examples of oxide semiconductors include tungsten oxide, tin oxide, indium oxide, and zinc oxide. There are single-component metal oxides and homologous compounds such as In-Ga-Zn-based metal oxides. The metal oxide is then used for a pixel switching element in a display device. Techniques for applying transistors have already been disclosed in Patent Documents 1 and 2.

[0006] As a semiconductor device using silicon semiconductor, a field effect transistor using metal and oxide insulating film is used. Metal-Oxide Silicon Field-Effect Transistor ansistor:MOSFET), Junction Field Effect Transistor (Junction Field-Effect Transistor (JFET) and Schottky Barrier 2. Description of the Related Art There are semiconductor devices for high power applications, such as diodes.

[0007] Among them, silicon carbide (SiC), a silicon-based semiconductor material, has a low reverse saturation current. It is used in Schottky barrier diodes, which have excellent voltage resistance characteristics (see Patent Document 3). . [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2000-133819 A Summary of the Invention [Problem to be solved by the invention]

[0009] Semiconductor devices for high-power applications require high breakdown voltage, low reverse saturation current, and high on-current. Various electrical characteristics are required, but to actually manufacture a semiconductor device having these electrical characteristics, There are so many problems.

[0010] For example, it is difficult to obtain high-quality crystals from silicon carbide, and it is difficult to fabricate semiconductor devices using silicon carbide. For example, the process temperature is high when an impurity region is formed in silicon carbide. Ion implantation is used to form the GaN- ... Heat treatment at 1500°C or higher is required.

[0011] In addition, the inclusion of carbon makes it possible to create a high-quality insulating layer by thermal oxidation. In addition, silicon carbide is extremely stable chemically, so it is difficult to use it in conventional The problem is that wet etching is difficult.

[0012] Furthermore, semiconductor devices for high-power applications generate heat when a large current flows through them, so they require high heat dissipation. A structure that takes this into consideration is required.

[0013] In view of the above problems, the present invention provides a semiconductor device that has electrical properties such as high breakdown voltage, low reverse saturation current, and high on-current. One of the objects of the present invention is to provide a semiconductor device having nonlinear characteristics. It is an object of the present invention to provide a power diode and a rectifier which are formed in such a manner. [Means for solving the problem]

[0014] One aspect of the present invention is a semiconductor device comprising a first electrode, a gate insulating layer covering the first electrode, and a gate insulating layer overlapping the first electrode. an oxide semiconductor layer that is folded and in contact with a gate insulating layer; a second electrode; an insulating layer covering the pair of second electrodes and the oxide semiconductor layer; and a third electrode provided between the pair of second electrodes, the pair of second electrodes being made of an oxide. The semiconductor device is in contact with the end face of the semiconductor layer.

[0015] In this specification, the end face of the oxide semiconductor layer refers to the end face of the gate insulating film of the oxide semiconductor layer. The upper surface and the side surface are included when the surface on the edge layer side is the lower surface. That is, the pair of second electrodes The oxide semiconductor layer is in contact with the channel formation region and the region other than the region in contact with the gate insulating layer. Therefore, the pair of second electrodes serves as a heat sink, and the channel forming region serves as a heat sink. Heat generated when a current flows through the oxide semiconductor layer can be dissipated to the outside.

[0016] Another embodiment of the present invention is a semiconductor device comprising: a pair of second electrodes and an oxide semiconductor layer; In order to reduce the contact resistance with + The gate insulating layer and the oxide semiconductor layer are The semiconductor device is provided in contact with the pair of second electrodes.

[0017] In the above semiconductor device, since the depletion layer of the oxide semiconductor is very thick, By increasing the thickness of the layer, a high on-current can be obtained. In the semiconductor device according to the embodiment, the oxide semiconductor layer has a thickness of 0.1 μm or more and 50 μm or less. and preferably, the semiconductor device has a thickness of 0.5 μm or more and 20 μm or less.

[0018] The oxide semiconductor layer may be a crystalline oxide semiconductor layer. This technology suppresses changes in electrical characteristics caused by exposure to visible light or ultraviolet light, ensuring high reliability. Furthermore, the crystalline oxide semiconductor layer has a single crystal structure. It is neither an amorphous structure nor an amorphous structure, and is a crystal with c-axis orientation (C Axis The oxides contain crystalline carbide (CAAC). The conductive oxide semiconductor layer has a crystal grain boundary in a part thereof. In the semiconductor device, the oxide semiconductor layer is a crystalline oxide semiconductor layer. The semiconductor layer has an ab plane parallel to the surface and a c axis oriented perpendicular to the surface. It is a semiconductor device.

[0019] Another embodiment of the present invention is a semiconductor device in which the crystalline oxide semiconductor layer contains zinc and indium. The semiconductor device includes one or both of indium.

[0020] Furthermore, another embodiment of the present invention is a semiconductor device in which the first electrode is a gate electrode. The pair of second electrodes are a source electrode and a drain electrode, and the third electrode is a back gate electrode. It is a semiconductor device that functions as a pole.

[0021] The semiconductor device is a power diode in which a plurality of nonlinear elements are connected in series in the forward direction. That is, another aspect of the present invention is a gate insulating film having a first electrode and a gate insulator covering the first electrode. an oxide semiconductor layer overlapping the first electrode and in contact with the gate insulating layer; a pair of second electrodes in contact with the oxide semiconductor layer; and an insulating layer covering the pair of second electrodes and the oxide semiconductor layer. a third electrode in contact with the insulating layer and provided between the pair of second electrodes; The second electrodes are in contact with the end faces of the oxide semiconductor layer, and one of the pair of second electrodes is connected to the gate insulating layer via the gate insulating layer. The nonlinear elements are connected in series in the forward direction. It is a power diode.

[0022] The semiconductor device may also be a rectifier having two nonlinear elements having the above configuration. That is, another embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer overlapping with the first electrode and in contact with the gate insulating layer; a pair of second electrodes that are connected to the oxide semiconductor layer; an insulating layer that covers the pair of second electrodes and the oxide semiconductor layer; and a third electrode disposed between the pair of second electrodes and in contact with the first electrode. The first electrode is in contact with an end surface of the oxide semiconductor layer, and one of the pair of second electrodes is connected to the first electrode via the gate insulating layer. The electrode of the first nonlinear element is in contact with the electrode of the second nonlinear element. The node is connected to the low-potential side reference potential, and the cathode of the first nonlinear element is connected to the input and the second The anode of the first nonlinear element is connected to the anode of the second nonlinear element, and the cathode of the second nonlinear element is connected to the output. It is a rectifier.

[0023] Furthermore, as the semiconductor device, a rectifier consisting of four nonlinear elements having the above configuration is That is, another embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, and an oxide semiconductor layer overlapping with the first electrode and in contact with the gate insulating layer; a pair of second electrodes in contact with each other, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and an insulating a third electrode in contact with the layer and disposed between the pair of second electrodes, The electrode is in contact with an end surface of the oxide semiconductor layer, and one of the pair of second electrodes is connected to the first electrode via the gate insulating layer. The first nonlinear element has a first nonlinear element to a fourth nonlinear element in contact with the first electrode. The anode of the transistor is connected to a reference potential on the low potential side, the cathode of the transistor is connected to the first input, and the second The anode of the nonlinear element is connected to the first input section, the cathode is connected to the output section, and the third The anode of the nonlinear element is connected to the second input section, the cathode is connected to the output section, and the fourth The anode of the nonlinear element is connected to the reference potential on the low potential side, and the cathode is connected to the second input. The rectifier is connected to the Effect of the Invention

[0024] It has characteristics such as higher breakdown voltage and lower reverse saturation current than conventional devices, and can obtain a high on-current. It is also possible to provide a semiconductor device capable of suppressing deterioration due to heat generation. can. [Brief description of the drawings]

[0025] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating a nonlinear element according to one embodiment of the present invention. [Diagram 2] 1A to 1C are plan views illustrating a method for manufacturing a nonlinear element according to one embodiment of the present invention. [Diagram 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a nonlinear element according to one embodiment of the present invention. [Figure 4] 1A and 1B are a plan view and a cross-sectional view illustrating a nonlinear element according to one embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a nonlinear element according to one embodiment of the present invention. [Figure 6] 1 is a cross-sectional view illustrating a nonlinear element according to one embodiment of the present invention. [Figure 7] FIG. 1 is a diagram illustrating a two-dimensional crystal. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a nonlinear element according to one embodiment of the present invention. [Figure 9] 1 is a cross-sectional view illustrating a nonlinear element according to one embodiment of the present invention. [Figure 10] 1A and 1B are diagrams illustrating a power diode and a rectifier according to one embodiment of the present invention. [Figure 11] 1A and 1B are a plan view and a cross-sectional view illustrating a diode according to one embodiment of the present invention. [Figure 12] FIG. 2 is an example of a top view of a manufacturing apparatus for manufacturing one embodiment of the present invention. [Figure 13] 1 is a cross-sectional view illustrating the structure of a nonlinear element used in calculations. [Figure 14] FIG. 14 is a diagram showing the calculation results of the drain current in the nonlinear element shown in FIG. [Figure 15] FIG. 11 is a cross-sectional view for explaining the structure of a nonlinear element used in calculations as a comparative example. [Figure 16]FIG. 11 is a cross-sectional view for explaining the structure of a nonlinear element used in calculations as a comparative example. [Figure 17] FIG. 11 is a cross-sectional view for explaining the structure of a nonlinear element used in calculations as a comparative example. [Figure 18] FIG. 18 is a diagram showing calculation results of drain currents in the nonlinear elements of FIGS. 13 and 15 to 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and methods thereof may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications and details may be made to the present invention. The present disclosure should not be construed as being limited to the description of the following embodiment. In explaining the configuration of the invention using the drawings, the same reference numerals are used in different drawings. In addition, when referring to similar items, the same hatch pattern will be used and no particular symbol will be added. In addition, the size, layer thickness, and area of ​​each component shown in each drawing may be different from those shown in the drawings. In some cases, the figures are exaggerated for clarity. Therefore, the figures are not necessarily limited to the scale. It won't be done.

[0027] When expressing the stacking of layers (or electrodes) that make up a transistor, For convenience, the protruding lower layer ends may not be shown in the plan view of the transistor.

[0028] When describing that A and B are connected, it means that A and B are electrically connected. This includes the case where A and B are directly connected, and the case where A and B are directly connected. It is assumed that the object is an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0029] Voltage is the potential difference between two points, and potential is the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in a particle. Generally, the potential difference between a potential at a certain point and a reference potential (for example, ground potential) This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, potential may be read as voltage. In this specification, voltage may be read as potential.

[0030] The function of the "source" and "drain" is to change the direction of current flow during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. The terms may be used interchangeably.

[0031] On-state current is the current that flows between the source and drain electrodes when a transistor is in the on state. For example, in the case of an n-type transistor, the gate voltage is the drain current that flows when the transistor threshold voltage is higher than the The off-state current is the current that flows between the source and drain electrodes when the transistor is in the off state. For example, in the case of an n-type transistor, the gate voltage is This is the drain current that flows when the transistor's threshold voltage is lower than the threshold voltage. The ratio is the ratio of the on current to the off current.

[0032] In this specification, the threshold voltage of an n-channel transistor is positive. A transistor in which the In this paper, a transistor whose threshold voltage is negative is defined as a normally-off transistor. In addition, in the case of n-channel transistors, the threshold voltage value is negative. In this paper, we define a p-channel transistor as a normally-on transistor. A transistor whose threshold voltage has a positive value is defined as a normally-on transistor.

[0033] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a nonlinear element according to one embodiment of the present invention will be described. 1 to 3. Note that in this embodiment, a transistor is used as an example.

[0034] FIG. 1A is a plan view of a transistor 100, and FIG. FIG. 1C is a cross-sectional view of the transistor 100 taken along line A-B. In FIG. 1A, the base insulating layer 102 and the gate insulating layer 105 For convenience, the gate electrode and the insulating layer 111 are not shown. The wiring 104 includes a first electrode 103 that functions as a gate electrode, and an oxide semiconductor that functions as a channel forming region. A conductor layer 107 and a pair of second electrodes 109a functioning as a source electrode and a drain electrode. , 109b and a pair of second electrodes 109a, 109b. A third electrode which overlaps with the oxide semiconductor layer 107 with the insulating layer 111 interposed therebetween and serves as a backgate electrode. The wiring 114 including the pole 113 is shown. Here, the first electrode 103 is connected to the wiring 104. The pair of second electrodes 109a and 109b are connected to a wiring 110, and the third electrode 113 is connected to a wiring 114. The electrodes and wiring are formed separately and are electrically connected. The configuration may be as follows.

[0035] In this embodiment, the first electrode 103 serves as a gate electrode, and the pair of second electrodes 109a , 109b serves as a source electrode and a drain electrode, and the third electrode 113 serves as a back gate electrode. However, the function is not limited to this, and the first electrode 103, the pair of second electrodes 109a, 109b and the third electrode 113 are a gate electrode, a source electrode, a drain electrode, and a back gate electrode.

[0036] As shown in FIG. 1B, the transistor 100 has a gate electrode and a back gate electrode. The transistor is a dual-gate type transistor, and is formed on a substrate 101, a base insulating layer 102, a first electrode 103, a gate insulating layer 105, an oxide semiconductor layer 107, a pair of second electrodes 109a, 9b, an insulating layer 111, and a third electrode 113 are provided.

[0037] The first electrode 103 is provided in contact with the base insulating layer 102. The gate insulating layer 105 is The oxide semiconductor layer 107 is provided to cover the gate electrode 103. The pair of second electrodes 109a and 109b are provided so as to overlap with the first electrode 103. The insulating layer 111 is provided to cover an end portion of the oxide semiconductor layer 107. The third electrode 113 is provided so as to cover a part of the pair of second electrodes 109a and 109b. It is provided on and in contact with the insulating layer 111 and between the pair of second electrodes 109a, 109b.

[0038] The pair of second electrodes 109a and 109b cover the end portions of the oxide semiconductor layer 107. Since the pair of second electrodes 109a and 109b is provided, Therefore, in the region in contact with the oxide semiconductor layer 107, a pair of The electrode width of the second electrodes 109a and 109b is set to be equal to or smaller than the width of the channel formed in the oxide semiconductor layer 107. It becomes wider than it is wide (see Figure 1(A)).

[0039] Furthermore, as shown in FIG. 1C, the pair of second electrodes 109a and 109b are Since the pair of second electrodes 109a and 109b are in contact with the end surface of the heat sink 07, This allows heat generated when a high on-current flows through the oxide semiconductor layer 107 to be dissipated to the outside. As a result, deterioration of the transistor 100 due to heat generation can be suppressed. Cut.

[0040] In the transistor 100, the electrode width of the first electrode 103 is equal to or smaller than the width of the oxide semiconductor layer 10. The third electrode 113 is formed of an oxide semiconductor via an insulating layer 111. The third electrode 113 overlaps the semiconductor layer 107, and the electrode width of the third electrode 113 is at least equal to or greater than the channel length. .

[0041] Therefore, the oxide semiconductor layer that is not covered by the pair of second electrodes 109a and 109b The end of 107 is connected to the first electrode 103 and the second electrode 104 via the gate insulating layer 105 and the insulating layer 111. In other words, all the ends of the oxide semiconductor layer 107 are covered with the first electrode 113. 103 is covered with a pair of second electrodes 109 a , 109 b and a third electrode 113 .

[0042] Even when the gate insulating layer 105 and the insulating layer 111 are interposed, the end portion of the oxide semiconductor layer 107 Therefore, the transistor 100 can be made of an oxide semiconductor. The heat generated when a high on-current flows through the semiconductor layer 107 can be effectively dissipated to the outside. This makes it possible to suppress deterioration of the transistor 100 due to heat generation.

[0043] The substrate 101 is a non-alkali glass substrate produced by the fusion method or the float method. A heat-resistant plastic substrate that can withstand heat treatment can be used. A substrate with an insulating film on the surface of a metal substrate such as stainless steel, or a semiconductor substrate with an insulating film on the surface A thin substrate may also be used.

[0044] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. The above is recommended. For the glass substrate, for example, aluminosilicate glass, Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. By containing more barium oxide (BaO) than boron oxide, it is possible to obtain a more practical Heat-resistant glass can be obtained. For this reason, it is recommended to use a glass substrate containing more BaO than B2O3. is preferred.

[0045] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a substrate made of crystallized glass or the like may be used.

[0046] The insulating base layer 102 provided between the substrate 101 and the first electrode 103 is In addition to preventing the diffusion of impurity elements, Therefore, the substrate 101 is prevented from being etched. Although there is no limitation, the thickness of the insulating base layer is preferably 50 nm or more. The edge layer 102 may be made of silicon oxide, gallium oxide, aluminum oxide, silicon nitride, or nitroxide. oxide or nitride insulators such as silicon oxide, aluminum oxide nitride, or silicon nitride oxide; The substrate is used as a single layer or a laminated structure. Among them, aluminum nitride, nitride Aluminum oxide and silicon nitride are used for the base insulating layer 102 because they have high thermal conductivity. In addition, alkali metals such as Li and Na have the following properties: Since the oxide semiconductor layer 107 described later is an impurity, the content of the impurity must be reduced. When a glass substrate containing impurities such as alkali metals is used as the substrate 101, To prevent the intrusion of alkali metals, nitride insulators such as silicon nitride and aluminum nitride are used. It is preferable to form the

[0047] The first electrode 103 which becomes the gate electrode is made of molybdenum, titanium, tantalum, or tungsten. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or materials containing these as the main components The first electrode 103 can be formed using an alloy material having the above structure. For example, a single layer of an aluminum film containing silicon may be used. Layer structure, two-layer structure with titanium film laminated on aluminum film, titanium film on tungsten film A two-layer structure in which a titanium film is laminated, and an aluminum film is laminated on top of the titanium film. and a three-layer structure in which a titanium film is formed on top of the above.

[0048] The thickness of the first electrode 103 is not particularly limited, and may be any thickness of a conductive film made of the above-listed materials. This can be appropriately determined taking into consideration the electrical resistance and the time required for forming the conductive film.

[0049] The gate insulating layer 105 is required to have high quality since it is in contact with the oxide semiconductor layer 107. In other words, the oxide semiconductor layer 107 is made to be i-type or substantially i-type by removing impurities. (an oxide semiconductor layer in which the hydrogen concentration is reduced and oxygen is supplied) Therefore, it is extremely sensitive to the interface state and the interface charge, and the interface with the gate insulating layer 105 is Because it's important.

[0050] The gate insulating layer 105 can be formed of the oxide insulating materials listed above. The layer 105 preferably contains oxygen in a portion in contact with the oxide semiconductor layer 107. It is preferable that the gate insulating layer 105 contains oxygen in an amount exceeding the stoichiometric ratio. For example, Silicon oxide (SiO 2+α (where α>0) The gate insulating layer 105 may be formed of silicon oxide. By forming the gate insulating film, the gate insulating film can be formed in the heat treatment performed in the manufacturing process of the transistor 100. A part of the oxygen contained in the insulating layer 105 can be supplied to the oxide semiconductor layer 107. This can improve the electrical characteristics of the transistor 100.

[0051] Furthermore, the gate insulating layer 105 may have a single layer structure or a stacked layer structure. In addition, by increasing the thickness of the gate insulating layer 105, the gate leakage current can be reduced. For example, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y x>0, y>0), nitrogen-doped hafnium silicate (HfSiO x N y ( x>0, y>0), hafnium aluminate (HfAl x O y (x>0, y>0) The gate leakage current can be reduced by using high-k materials such as The thickness of the edge layer is preferably 50 nm or more and 500 nm or less.

[0052] The oxide semiconductor layer 107 is made of a quaternary metal oxide, In-Sn-Ga-Zn-based metal oxide. Oxides and ternary metal oxides such as In-Ga-Zn metal oxides and In-Sn-Zn Metal oxides, In-Al-Zn metal oxides, Sn-Ga-Zn metal oxides, Al-G a-Zn metal oxide, Sn-Al-Zn metal oxide, In-Hf-Zn metal oxide , In-La-Zn metal oxide, In-Ce-Zn metal oxide, In-Pr-Zn Metal oxides, In-Nd-Zn metal oxides, In-Sm-Zn metal oxides, In-E U-Zn metal oxide, In-Gd-Zn metal oxide, In-Tb-Zn metal oxide , In-Dy-Zn metal oxide, In-Ho-Zn metal oxide, In-Er-Zn Metal oxides, In-Tm-Zn metal oxides, In-Yb-Zn metal oxides, In-L In-Zn metal oxides, which are binary metal oxides, and Sn-Zn metal oxides, Al-Zn metal oxides, Zn-Mg metal oxides, Sn-Mg metal acids oxides, In-Mg-based metal oxides, In-Ga-based metal oxides, indium, tin or zinc The crystalline oxide can be formed by using a single-element metal oxide including the following. Considering the fabrication of an oxide semiconductor, the oxide semiconductor layer 107 serving as a channel region is formed of the above-mentioned zinc. A metal oxide containing lead or a metal oxide containing zinc and indium is preferred. Here, for example, the In-Ga-Zn metal oxide is a metal oxide containing indium (In), gallium ( It means an oxide containing Ga (Ga) and zinc (Zn), and the composition ratio is not particularly limited. In addition, elements other than In, Ga, and Zn may be contained.

[0053] Furthermore, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 107 and oxygen is sufficiently contained. Specifically, the hydrogen concentration of the oxide semiconductor layer 107 is preferably Degrees are 5 x 10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 The following applies. In addition, oxide semiconductor The hydrogen concentration in the layer 107 was measured by secondary ion mass spectrometry (SIMS). This value is measured by mass spectroscopy. The layer 107 is supplied with a sufficient amount of oxygen, and oxygen vacancies in the energy gap are eliminated. Therefore, the oxide semiconductor layer 107 can reduce the defect levels caused by donors such as hydrogen. The carrier density due to 10 cm -3 More than 1×10 13 cm -3 The following is true: In this manner, the oxide semiconductor layer 107 is provided with an i-type (intrinsic) or substantially i-type oxide. By using a nitride semiconductor, a transistor 100 having excellent off-current characteristics can be obtained. For example, the off-current at room temperature (25°C) (unit channel width (1 μm) per ampere) is 100zA (1zA (zeptoampere) is 1×10 -21 A) The following are preferred: Or less than 10zA.

[0054] In addition, it is preferable to reduce the content of alkali metals such as Li and Na. The concentration of the alkali metal element in the semiconductor layer 107 is 2×10 16 cm -3 Hereinafter, preferably , 1×10 15 cm -3 Furthermore, alkaline earth metals are also impurities. Therefore, it is preferable to reduce the content. The reasons are as follows. It is insensitive to pure substances, and there is no problem even if a considerable amount of metal impurities are contained in the film. You can also use inexpensive soda-lime glass that contains a large amount of alkali metals such as thorium (Na). It has been pointed out that the properties of amorphous oxide semiconductors and their devices are Current status of development," Solid State Physics, September 2009, Vol. 44, pp. 621-633. However, this is not an appropriate criticism. Alkali metals are elements that make up oxide semiconductors. Alkaline earth metals are not elements that make up oxide semiconductors. In particular, Na, which is an alkali metal, becomes an impurity when it is in contact with an oxide semiconductor layer. When the insulating film is an oxide, Na diffuses into the insulating film. + In addition, Na is oxidized In the oxide semiconductor layer, the bond between the metal and oxygen constituting the oxide semiconductor is broken, or As a result, for example, the threshold voltage shifts in the negative direction. This allows the drain current to flow even when no voltage is applied to the gate electrode (Vg=0). This leads to degradation of electrical characteristics, such as a normally-on state and a decrease in field-effect mobility. The electrical characteristics also vary due to the impurities. The variation in the electrical characteristics becomes noticeable when the hydrogen concentration in the oxide semiconductor layer is sufficiently low. do.

[0055] In-Ga-Zn metal oxides have sufficiently high resistance when no electric field is present and sufficiently small off-current. In addition, the field-effect mobility is high. It is suitable as a semiconductor material for use in transistors.

[0056] Unlike the transistor 100, which uses silicon semiconductor for the channel formation region, The depletion layer formed by using an oxide semiconductor is thicker. Therefore, the channel region is The thickness of the oxide semiconductor also increases because it is formed in the depth direction of the oxide semiconductor. This allows many carriers to flow, resulting in a high on-current. can.

[0057] In addition, the drain withstand voltage of the transistor 100 depends on the thickness of the oxide semiconductor layer 107. Therefore, in order to increase the drain breakdown voltage, the oxide semiconductor layer 107 is preferably thick. The thickness may be selected according to the desired drain breakdown voltage.

[0058] Therefore, the thickness of the oxide semiconductor layer 107 determines the electrical characteristics of the on-state current and the drain withstand voltage. Considering this, the thickness is set to 0.1 μm or more and 50 μm or less, preferably 0.5 μm or more and 20 μm or less. It is good to do so.

[0059] Here, the drain withstand voltage of a transistor including an oxide semiconductor will be described.

[0060] When the electric field in the semiconductor reaches a certain threshold, impact ionization occurs, creating a high electric field in the depletion layer. The more accelerated carriers collide with the crystal lattice, generating electron-hole pairs. When the electric field is high, the electron-hole pairs generated by impact ionization are further accelerated by the electric field. The avalanche breakdown occurs when the current increases exponentially due to repeated impact ionization. Impact ionization occurs when carriers (electrons, holes) reach a kinetic energy greater than the band gap of a semiconductor. The impact ionization coefficient, which indicates how easily impact ionization occurs, and the balance There is a correlation between the band gap and the impact ionization. The larger the band gap, the smaller the impact ionization. The direction is known.

[0061] The band gap of oxide semiconductors is about 3.15 eV, which is the same as that of silicon. Since this is larger than the approximately 1.12 eV of the junction, avalanche breakdown is unlikely to occur. Therefore, transistors using oxide semiconductors have a high drain withstand voltage and can withstand high electric fields. Even if the on-state current is increased, an exponential increase in the on-state current is unlikely to occur.

[0062] Next, hot carrier degradation of a transistor including an oxide semiconductor will be described.

[0063] Hot carrier degradation occurs when electrons accelerated to high speeds reach the gate near the drain in the channel. They are injected into the insulating film and become fixed charges, or they form trap levels at the gate insulating film interface. This can cause degradation of transistor characteristics such as threshold voltage fluctuation and gate leakage. The cause of hot carrier degradation is channel hot electron injection (CH E injection) and drain avalanche hot carrier injection (DAHC injection).

[0064] Since silicon semiconductors have a narrow band gap, avalanche breakdown occurs, causing an avalanche of electrons. This increases the number of electrons accelerated to a high enough speed to overcome the barrier to the gate insulating film. However, since the oxide semiconductor described in this embodiment has a wide band gap, Avalanche breakdown is less likely to occur, and resistance to hot carrier degradation is higher than that of silicon semiconductors. From the above, it can be said that a transistor including an oxide semiconductor has a high drain withstand voltage. Insulated-Gate Field-Effect Transistor IGFET), junction field effect transistor and This is suitable for semiconductor devices for high power applications, such as Schottky barrier diodes.

[0065] The pair of second electrodes 109a and 109b are made of the materials listed in the description of the first electrode 103. The thickness and structure of the electrode can be appropriately determined based on the description of the first electrode 103. Note that the pair of second electrodes 109a and 109b are formed on the oxide semiconductor layer 10. 7 to function as a heat sink that dissipates heat generated when an on-current flows through It is preferable that the heat transfer member 11 is made of a metal material or an alloy material that easily transfers heat.

[0066] The insulating layer 111 can be formed of the oxide insulators listed in the description of the gate insulating layer 105. Since the insulating layer 111 is also in contact with the oxide semiconductor layer 107, It is preferable that the oxygen is contained in the portion where the oxygen is contained, and in particular, the amount of oxygen contained exceeds the stoichiometric ratio. Silicon (SiO 2+α (where α>0)) is preferably used. By forming the silicon oxide 111, the transistor 100 can be manufactured without any problems. During the heat treatment, part of oxygen contained in the insulating layer 111 is supplied to the oxide semiconductor layer 107. This can improve the electrical characteristics of the transistor 100. The high-k material described for the gate insulating layer 105 may be used for the insulating layer 111. The insulating layer 111 may have a single-layer structure or a multilayer structure. By increasing the thickness, it is possible to reduce the gate leakage current on the back gate side. The thickness of the insulating layer 111 is preferably 50 nm or more and 500 nm or less.

[0067] The third electrode 113 serving as the back gate electrode is made of the materials listed in the description of the first electrode 103. The thickness and structure of the third electrode 113 can be the same as those of the first electrode Please select the appropriate one based on the explanation in 103.

[0068] From the viewpoint of reliability, a transistor including an oxide semiconductor has excellent reliability when illuminated with visible light and ultraviolet light. When radiation, heat, or an electric field is applied, the electrical properties change. Normally, a drain current flows even when no voltage is applied to the gate electrode (Vg=0). In the case of an n-channel transistor, where electrons are the majority carriers, the drain The electrons in the current flow through the region where the depletion layer is formed. In the region where electrons flow, a pair of second electrodes 109a and 109b and an insulating layer 111 are provided. The oxide semiconductor layer 107 includes a region adjacent to the upper surface of the oxide semiconductor layer 107. The insulating layer 111 in contact with the oxide semiconductor layer 107 (particularly, the lower surface of the insulating layer 111 in contact with the oxide semiconductor layer 107) It is believed that holes are induced in the junction (region adjacent to the junction) and the junction becomes normally on over time. Therefore, the transistor described in this embodiment has a dual-layer structure including a third electrode 113. Since it is a gate type, a voltage can be applied to the third electrode 113 at will, and the threshold The voltage (Vth) can be controlled, and normally-on can be suppressed.

[0069] In addition, since the transistor described in this embodiment is a dual-gate transistor, In the case where the oxide semiconductor layer 107 is formed thick, a voltage can be applied to the electrode 113. Therefore, a channel can be formed efficiently and a high on-current can be obtained.

[0070] Here, the shape of the third electrode 113 will be described with reference to FIG.

[0071] The third electrode 113 shown in FIG. 2A has the same shape as the third electrode 113 shown in FIG. The third electrode 113 is parallel to the first electrode 103 and has an insulating layer 111 interposed therebetween. In this case, the third electrode 113 overlaps with the pair of second electrodes 109a and 109b. The voltage applied to the first electrode 102 and the voltage applied to the second electrode 103 can be controlled arbitrarily. It is possible.

[0072] The third electrode 113 shown in FIG. 2B is parallel to the first electrode 103. In this configuration, the third electrode 109a and the second electrode 109b do not overlap each other. The voltage applied to the electrode 113 and the voltage applied to the first electrode 103 are each arbitrarily controlled. It is possible to do so.

[0073] Furthermore, the third electrode 113 shown in FIG. 2C can be connected to the first electrode 103. That is, in the opening 150 formed in the gate insulating layer 105 and the insulating layer 111, The first electrode 103 and the third electrode 113 are connected to each other. The voltage applied to the pole 113 and the voltage applied to the first electrode 103 are equal.

[0074] As shown in FIG. 2D, the third electrode 113 is not connected to the first electrode 103. A floating configuration may also be used.

[0075] Furthermore, in the configuration shown in FIG. 2(C) and FIG. 2(D), the third electrode 113 is an insulating layer. It may be configured to overlap with the pair of second electrodes 109a, 109b via 111.

[0076] In the transistor 100, although not shown in FIG. 1, an insulating layer 111 and a third electrode A protective insulating layer may be provided on the electrode 113 .

[0077] Next, a method for manufacturing the transistor 100 will be described with reference to FIGS.

[0078] An insulating base layer 102 is formed on a substrate 101. By carrying out this process, the non-uniformity of the glass substrate is reduced. This can prevent impurities from being mixed into the transistor being manufactured.

[0079] The base insulating layer 102 can be formed by a sputtering method, a CVD method, a coating method, or the like. In this embodiment, silicon oxide is produced by sputtering using a silicon target. After the base insulating layer 102 is formed, moisture and The substrate 101 may be subjected to a heat treatment to remove hydrogen.

[0080] Next, the first electrode 103 is formed on the base insulating layer 102. The step of forming the first electrode also serves as a step of forming the wiring 104 (see FIG. 1(A)). 103 is a conductive film formed on the substrate 101 by sputtering, vacuum deposition, or CVD. A resist mask is formed over the conductive film by a first photolithography process. The conductive film can be etched using a photomask. By forming a resist mask using printing and inkjet methods without using a lithography process, The number of steps for forming the first electrode 103 can be reduced. The tapered end improves the coverage of the gate insulating layer 105 to be formed later. It is preferable to form a tapered shape by etching while receding the resist mask. It is possible.

[0081] In this embodiment, a conductive film (for example, a tungsten film) having a thickness of 150 nm is formed by sputtering. The resist mask formed in the first photolithography process is used to form the first insulating film. The first electrode 103 is formed by etching. However, the etching process using a resist mask also includes a step of removing the resist mask. It is assumed that this is included.

[0082] Next, a gate insulating layer 105 is formed to cover the first electrode 103. Since the insulating film 104 is in contact with the oxide semiconductor layer 107 to be formed later, it is required to have high quality. By contacting the gate insulating layer 105, the interface between the oxide semiconductor layer 107 and the gate insulating layer 105 The level is reduced and the interface characteristics are improved, resulting in a completed transistor 10. This is because it is possible to improve the electrical characteristics of 0.

[0083] The gate insulating layer 105 can be formed by the methods listed in the description of the base insulating layer 102. In this embodiment, the gate insulating layer 105 contains oxygen in an amount exceeding the stoichiometric ratio. Silicon oxide (SiO 2+α(where α>0)) is formed. Note that the acid The thickness of the silicon oxide is 200 nm.

[0084] When the silicon oxide is formed by the sputtering method, a silicon target is used. A quartz target or a quartz target is used, and oxygen or A mixed gas of argon and hydrogen is used. At this time, hydrogen, water, hydroxyl groups or It is preferable to form the gate insulating layer 105 while removing hydrides or the like. To remove residual hydrogen, water, hydroxyl radicals, or hydrides, an adsorption type vacuum pump is used. As the adsorption type vacuum pump, for example, a cryopump or an ion pump is used. It is preferable to use a pump, a titanium sublimation pump, etc. Alternatively, a turbo pump with a cold trap may be used. In the evacuated processing chamber, hydrogen, water, hydroxyl radicals, hydrides, etc. are exhausted, so the processing When the gate insulating layer 105 is formed in the chamber, hydrogen, water, and hydroxyl groups contained in the gate insulating layer 105 Alternatively, the concentration of hydrides can be reduced.

[0085] The sputtering gas used in forming the gate insulating layer 105 is hydrogen, water, or water. High purity, with impurities such as acid groups or hydrides removed to concentrations of ppm or ppb. It is preferable to use a high-temperature gas.

[0086] In this embodiment, the substrate 101 is transferred to a processing chamber, and hydrogen, water, a hydroxyl group, a hydride, or the like is added to the processing chamber. A sputtering gas containing high-purity oxygen from which oxygen has been removed is introduced, and a silicon target is used. The silicon oxide is formed as the gate insulating layer 105 on the substrate 101. A gate insulating layer 105 may be formed while 101 is being heated.

[0087] In addition, when the gate insulating layer 105 is formed in a laminated structure, for example, the above-mentioned silicon oxide and a substrate Silicon nitride is formed between the silicon target and the plate 101. Using a sputtering method, hydrogen, water, hydroxyl groups, hydrides, etc. are removed from the high-purity nitrogen. In addition, the silicon oxide film is formed by using a ring gas. It is preferable to form the silicon nitride film while removing hydrogen, water, hydroxyl groups, hydrides, etc. I wish.

[0088] When silicon nitride and silicon oxide are laminated as the gate insulating layer 105, It is now possible to form silicon nitride and silicon oxide using a common silicon target. In this case, a sputtering gas containing nitrogen is first introduced into the processing chamber. Silicon nitride was formed using a silicon target containing oxygen. The silicon oxide was then grown using the same silicon target. This allows silicon nitride and silicon oxide to be formed successively without exposure to the atmosphere. Therefore, it is necessary to prevent hydrogen, water, hydroxyl groups, hydrides, etc. from being adsorbed on the silicon nitride surface. It is possible.

[0089] In addition, before the gate insulating layer 105 is formed, the inner wall of the processing chamber, the target surface, and the target Preheating to remove hydrogen, water, hydroxyl groups, or hydrides remaining in the material. After the preheating process is completed, the substrate 101 or the processing chamber is cooled. After that, the gate insulating layer 105 is formed without being exposed to the air. It is advisable to use oils and fats instead of water.

[0090] In addition, when the gate insulating layer 105 is formed by a CVD method, for example, a microwave (for example, a frequency By forming the material using high density plasma CVD at 2.45GHz, it has a dense and high dielectric strength. In addition, the high-density plasma CVD can form a high-quality gate insulating layer. The gate insulating layer can be formed with a constant thickness, and therefore has excellent step coverage. The thickness of the gate insulating layer obtained by plasma CVD can be precisely controlled.

[0091] Next, an oxide semiconductor The oxide semiconductor film 106 is formed on the gate insulating layer 105 by sputtering. method, molecular beam epitaxy method, atomic layer deposition method, pulsed laser deposition method, coating method, or printing method etc.

[0092] In this embodiment, the oxide semiconductor film 106 is formed by a sputtering method. The semiconductor film 106 is formed by holding the substrate in a processing chamber that is kept in a reduced pressure state and allowing the substrate to remain in the processing chamber. Sputtering gas from which hydrogen, water, hydroxyl groups, hydrides, etc. have been removed while removing moisture. The oxide semiconductor film 106 is formed on the gate insulating layer 105 using a metal oxide as a target. To remove hydrogen, water, hydroxyl radicals, hydrides, etc. remaining in the processing chamber, This can be done in the same manner as in forming the gate insulating layer 105. Impurities such as hydrides (and more preferably compounds containing carbon atoms) are exhausted from the processing chamber. Therefore, the concentration of the impurities in the oxide semiconductor film 106 can be reduced. The oxide semiconductor film 106 may be formed while the substrate 101 is heated.

[0093] The oxide semiconductor film 106 is formed by a sputtering method using a target of at least A metal oxide target containing zinc or a gold oxide target containing at least zinc and containing indium In this embodiment, an In-Ga-Zn based metal oxide target can be used. An oxide target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) was used. The oxide semiconductor film 106 is formed to a thickness of 500 nm using a metal oxide target. Another example is a composition of In2O3:Ga2O3:ZnO=1:1:1 [molar ratio]. A target having a composition ratio of In:Ga:Zn=1:1:0.5 [atomic ratio] A target having a composition ratio of In:Ga:Zn=1:1:1 [atomic ratio] In addition, in the listed metal oxide targets, SiO2 is 2% by weight or more. The metal oxide target may contain 10% by weight or less. The metal oxide tertiary oxide having a high filling rate is preferably 95% or more and 99.9% or less. The oxide semiconductor film formed using the get becomes a dense film.

[0094] The oxide semiconductor film 106 is grown under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or The oxide semiconductor film 106 is formed in an atmosphere of a rare gas (typically, argon) and oxygen. The sputtering gas used in the formation of the SiO2 layer contains impurities such as hydrogen, water, hydroxyl groups, and hydrides. It is preferable to use a high-purity gas in which the concentration has been reduced to about ppm or ppb.

[0095] An example of the formation conditions is a distance between the substrate 101 and the target of 170 mm, a substrate temperature of 25 The temperature was 0°C, the pressure was 0.4 Pa, and the direct current (DC) power supply was 0.5 kW.

[0096] In order to prevent hydrogen from being contained in the oxide semiconductor film 106 as much as possible, Then, the substrate 101 that has been through the steps of forming the gate insulating layer 105 is preheated. It is preferable to desorb and exhaust the adsorbed impurities such as hydrogen, water, hydroxyl groups, and hydrides. It is preferable to use a cryopump to evacuate the gas during preheating. The heat treatment may be omitted. Also, this pre-heating is performed on the substrate before the first electrode 103 is formed. Alternatively, the oxide semiconductor layer 107 may be formed on the substrate 101. You may go to.

[0097] Note that before the oxide semiconductor film 106 is formed by a sputtering method, argon gas is The reverse sputtering is performed by introducing the ions into the gate insulating layer 105 to generate plasma. By removing the dust and the oxide film, the boundary between the gate insulating layer 105 and the oxide semiconductor film 106 is This is preferable because it can reduce the resistance on the surface. A voltage is applied to the substrate using an RF power source to form plasma near the substrate and modify the surface. In addition, nitrogen, helium, etc. may be used instead of the argon atmosphere. The heating may be performed in an argon atmosphere to which oxygen, hydrogen, nitrous oxide, etc. have been added. The treatment may be carried out in an atmosphere containing chlorine, carbon tetrafluoride, or the like.

[0098] The structure obtained through the steps up to this point is shown in FIG.

[0099] Next, the oxide is removed using a resist mask formed by a second photolithography process. The semiconductor film 106 is etched to form a first island-shaped oxide semiconductor layer.

[0100] A process for forming the first island-shaped oxide semiconductor layer will be described. The conductor layer is etched using a resist mask formed in a second photolithography process. The second photolithography process is a process of forming a first photolithography The process is similar to that of the

[0101] The oxide semiconductor film 106 can be etched by either dry etching or wet etching. Furthermore, these methods may be used in combination. The cleaning solution used was a mixture of phosphoric acid, acetic acid, and nitric acid, and ammonia hydrogen peroxide (31% by weight hydrogen peroxide). Water: 28% by weight ammonia water: water = 5:2:2) can be used. O07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0102] In addition, the etching solution after wet etching is washed away together with the etched material. The waste liquid of the etching solution containing the removed material is purified, and the material contained therein is The waste liquid after etching may be reused. Materials such as indium contained in the waste liquid may be recovered and reused. By reusing materials, resources can be used more effectively and costs can be reduced.

[0103] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (C Cl4) etc.) are preferred.

[0104] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur fluoride (S F6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HB r), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing , etc. can be used.

[0105] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) The inductively coupled plasma etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0106] Next, the obtained first island-shaped oxide semiconductor layer is subjected to a first heat treatment. A semiconductor layer 126 is formed.

[0107] The temperature of the first heat treatment is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and 750° C. or lower. The substrate is introduced into an electric furnace, which is one type of heat treatment device, and The first island-shaped oxide semiconductor layer is heated under an inert gas atmosphere such as nitrogen or a rare gas. Heat treatment at 50℃ for 1 hour. After that, keep it away from air. This prevents hydrogen, water, a hydroxyl group, hydride, or the like from reentering the oxide semiconductor layer 126. As a result, the oxide semiconductor layer 126 in which the hydrogen concentration is reduced can be obtained. At least one of dehydration and dehydrogenation of the first island-shaped oxide semiconductor layer is performed by the heat treatment. This can be done.

[0108] In addition to the dehydration and dehydrogenation, the first heat treatment also causes oxygen to be added to the gate insulating layer 105. In the case where the oxide semiconductor layer contains oxygen, part of the oxygen diffuses to the interface with the first island-shaped oxide semiconductor layer or in the vicinity thereof. As a result of this treatment, the oxide semiconductor layer 126 in which oxygen vacancies are reduced is obtained. can be done.

[0109] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain hydrogen, water, hydroxyl groups, hydrides, etc. The purity of the nitrogen or rare gases such as helium, neon, and argon introduced into the device is 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (i.e. impurity concentration It is preferable to set the content of the EDTA to 1 ppm or less, and preferably 0.1 ppm or less.

[0110] The heat treatment device used in the first heat treatment is not particularly limited, and may be a heat treatment device that can be used for a heat source such as a resistance heating element. The apparatus may include a device for heating the object to be treated by thermal conduction or thermal radiation. For example, Furnaces, GRTA (Gas Rapid Thermal Anneal) equipment, LRTA RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used for halogen-free lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure The radiation of light (electromagnetic waves) emitted from lamps such as sodium lamps and high-pressure mercury lamps can cause This is a device that heats the object to be treated. The GRTA device is a device that uses high-temperature gas to perform heat treatment. It is located.

[0111] The first heat treatment is performed before the first island-shaped oxide semiconductor layer is formed, that is, before the oxide The semiconductor film 106 may be heated. In that case, the substrate is removed from the heating device after the first heat treatment. The resultant is then taken out and subjected to a second photolithography step and an etching step.

[0112] The structure obtained through the steps up to this point is shown in FIG.

[0113] Next, a pair of second electrodes 109 are formed over the gate insulating layer 105 and the oxide semiconductor layer 126. A conductive film to be processed into 109a and 109b is then formed. The conductive film is then subjected to a third photolithography. The pair of second electrodes 109 are formed by etching using a resist mask formed by a photolithography process. The pair of second electrodes 109a and 109b are formed in the same manner as the first electrodes 109a and 109b. The method for forming the electrode 103 may be the same as that for forming the electrode 103. In this embodiment, titanium is used for sputtering. A conductive film having a thickness of 150 nm is formed by a deposition method. The step of forming 09b also serves as a step of forming the wiring 110 (see FIG. 1A).

[0114] The structure obtained through the steps up to this point is shown in FIG.

[0115] Next, a conductive film was formed in contact with the pair of second electrodes 109a and 109b and part of the oxide semiconductor layer 126. The insulating layer 111 is formed by the same method as the gate insulating layer 105. In this embodiment, the insulating layer 111 is formed by oxidizing the insulating layer 111 by a sputtering method. The insulating layer 111 is formed of silicon. The thickness of the insulating layer 111 is set to 200 nm. The second heat treatment is performed at a different heating temperature from the first heat treatment. Part of the oxygen contained in the layer 105 and the insulating layer 111 is supplied to the oxide semiconductor layer 126. The second heat treatment is performed at a higher heating temperature, and the photoirradiation or The amount of change in threshold voltage caused by the application of BT stress is small. However, if the heating temperature is higher than 320° C., the on-state characteristics will be deteriorated. The treatment conditions are in an inert atmosphere, an oxygen atmosphere, or a mixed atmosphere of oxygen and nitrogen, at 200°C or higher. The heating temperature is set to 400°C, preferably 250°C to 320°C. The second heat treatment is performed for 1 minute or more and 24 hours or less. It may be performed after forming the insulating layer 3. In addition, it is possible to prevent the intrusion of moisture and alkali metals. Therefore, silicon nitride may be formed on the insulating layer 111. Since it is an impurity, the content of 2 is preferably small. ×10 16 cm -3 Less than 1×10 15 cm -3 The following is the case. Furthermore, Since potassium earth metals are also impurities, it is preferable to reduce their content. After forming the third electrode 113, silicon nitride may be formed as a protective insulating layer. In this case, an opening is provided in the protective insulating layer, and the first electrode 103 and the pair of second electrodes 109a , 109b and a conductive film electrically connected to the third electrode 113, etc. Do as appropriate.

[0116] Next, a thin film is formed in contact with the insulating layer 111 and overlaps with a channel formation region of the oxide semiconductor layer 107. In this manner, a third electrode 113 is formed. A conductive film is formed on the insulating layer 111, and then, The conductive film is etched using a resist mask formed by a fourth photolithography process. The third electrode 113 is formed by the same method as that for the first electrode 10. In this embodiment, the sputtering method is the same as that of the third embodiment. A conductive film having a thickness of 150 nm is formed by a deposition method. This process also serves as a process for forming the wiring 114 (see FIG. 1(A)).

[0117] The structure obtained through the steps up to this point is shown in FIG.

[0118] As a result, it is possible to obtain a nonlinear element having a high breakdown voltage, a low reverse saturation current, and a high on-state current. It should be noted that this embodiment may be appropriately combined with the configurations described in other embodiments. It is possible to combine these methods.

[0119] (Embodiment 2) In this embodiment, a nonlinear element having a configuration partially different from that of the nonlinear element shown in the first embodiment is used. Note that in this embodiment, a transistor will also be taken as an example.

[0120] FIG. 4A is a plan view of the transistor 200, and FIG. FIG. 4C is a cross-sectional view of the transistor 200 between GH. Note that the transistor 200 is a modified example of the transistor 100. In FIG. 4, the same reference numerals are used for the same parts as in FIG. 1, and the details of the same reference numerals are omitted. do.

[0121] As shown in FIG. 4B, the transistor 200 is a dual-gate transistor. On the plate 101, a base insulating layer 102, a first electrode 103, a gate insulating layer 105, an oxide semiconductor Body layer 107, n +layers 117a, 117b, a pair of second electrodes 109a, 109b, an insulating layer 111, a third electrode 113 is provided.

[0122] The first electrode 103 is provided in contact with the base insulating layer 102. The gate insulating layer 105 is The oxide semiconductor layer 107 is provided to cover the gate electrode 103. The n+ layers 117a and 117b are provided so as to overlap with the first electrode 103. The pair of second electrodes 109a are provided to cover end portions of the oxide semiconductor layer 105 and the oxide semiconductor layer 107. , 109b is n + The oxide semiconductor layer 107 is provided on the layers 117a and 117b and covers the end portions of the oxide semiconductor layer 107. The insulating layer 111 covers a part of the oxide semiconductor layer 107, the pair of second electrodes 109a, The third electrode 113 is provided on the insulating layer 111 and in contact with the pair of third electrodes 109b. It is provided between the two electrodes 109a and 109b.

[0123] Between the oxide semiconductor layer 107 and the pair of second electrodes 109a and 109b, + layer 117a 117b, the oxide semiconductor layer 107 and the pair of second electrodes 109a , 109b can be reduced in contact resistance, thereby making it possible to obtain a high on-current. Also, n + By forming the layers 117a and 117b, the parasitic resistance is reduced and the B The change in on-current before and after negative gate stress in the T test (Ion degradation) ) can be suppressed.

[0124] Furthermore, FIG. 1C illustrates only one of the pair of second electrodes 109a and 109b. But, n + The layers 117a and 117b are formed by depositing the pair of second electrodes 109a and 109b as a mask. In order to perform the etching process, the ends of the pair of second electrodes 109a and 109b protrude. Therefore, the channel length of the transistor 200 is n + layer 117a, The distance between the pair of second electrodes 109a and 109b is determined by the distance between the pair of second electrodes 109a and 109b. + The n-type oxide semiconductor layer 107 faces the end face of the n-type oxide semiconductor layer 107 through the n-type oxide semiconductor layer 117a and the n-type oxide semiconductor layer 107. + layer The regions 117a and 117b are not formed to be extremely thick, but are formed in the oxide semiconductor layer 107. Since the heat transfer is not blocked, it functions as a heat sink, similar to the first embodiment. The heat generated when a high on-current flows through the oxide semiconductor layer 107 can be dissipated to the outside. As a result, deterioration of the transistor 200 due to heat generation can be suppressed.

[0125] The steps of manufacturing the transistor 200 will be described below. The process is n + The steps of manufacturing the transistor 100 are the same as those of forming the layers 117a and 117b. Therefore, the description will be given with reference to Figures 3(A), 3(B) and 5.

[0126] According to the manufacturing process shown in the first embodiment (through the structure shown in FIG. 3(A)), the structure shown in FIG. Achieve success.

[0127] Next, an In-Zn based metal oxide layer is formed on the gate insulating layer 105 and the oxide semiconductor layer 107. In-Sn metal oxides, single-component metal oxides containing indium or tin, + The film 115 that will become the layers 117a and 117b is formed to a thickness of 1 nm or more and 200 nm or less. The method for forming the oxide semiconductor layer 115 may be similar to the method for forming the oxide semiconductor layer 107. + The above-mentioned materials may contain SiO2 as the layer. In this embodiment, the I An n-Sn-based metal oxide film is formed to a thickness of 100 nm.

[0128] Next, n + A pair of second electrodes 109a, 109b are formed on the film 115 to be the layer. The conductive film 108 is processed to form a pair of second Electrodes 109a and 109b are formed. In addition, a pair of second electrodes 109a and 109b are formed. This step also serves as a step of forming the wiring 110 (see FIG. 4(A)).

[0129] Next, the film 115 is processed using the pair of second electrodes 109a and 109b as a mask to form n + By this processing, layers 117a and 117b are formed. + The layers 117a and 117b are a pair of The second electrodes 109a and 109b are formed so that their ends protrude from the electrodes (see FIG. 5(B)). Therefore, the channel length of transistor 200 is n + Between the layers 117a and 117b On the other hand, the channel length of the transistor 100 described in the first embodiment is determined by a pair of It is determined by the distance between the second electrodes 109a and 109b. + Layer 117a, 1 The taper angle of the end of 17b (n + The angle that the side surfaces of the layers 117a and 117b make with the plane of the substrate 101 ) should be less than 30 degrees.

[0130] The subsequent steps are the same as those in Embodiment 1. An insulating layer 111 is formed to cover the two electrodes 109a and 109b. A third electrode 1 is formed on the oxide semiconductor layer 107 so as to overlap with the channel formation region of the oxide semiconductor layer 107. The details of each step are the same as those in the first embodiment.

[0131] As a result, it is possible to obtain a nonlinear element having a high breakdown voltage, a low reverse saturation current, and a high on-state current. It should be noted that this embodiment may be appropriately combined with the configurations described in other embodiments. It is possible to combine these methods.

[0132] (Embodiment 3) In this embodiment, a nonlinear element having a configuration partially different from that of the nonlinear element shown in the first embodiment is used. Note that in this embodiment, a transistor will also be taken as an example.

[0133] The transistor 300 described in this embodiment is the same as the transistor 100 described in Embodiment 1. The oxide semiconductor layer 107 is a crystalline oxide semiconductor layer 107a. The transistor in which the crystalline oxide semiconductor stack 120 is replaced with the crystalline oxide semiconductor layer 107b. In other words, the planar structure of the transistor 300 is the same as that of the transistor 100. Therefore, a plan view of the transistor 300 can be seen in FIG. FIG. 6B is a cross-sectional view of the transistor 300 taken along line AB. The transistor 300 is a cross-sectional view taken along the line C-D of the transistor 100. 6, the same reference numerals are used for the same parts as in FIG. 1, and the same reference numerals are used for the same parts as in FIG. Details will be omitted.

[0134] As shown in FIG. 6A, the transistor 300 is a dual-gate transistor. On the plate 101, a base insulating layer 102, a first electrode 103, a gate insulating layer 105, a crystalline oxide A stack of compound semiconductor layers 120, a pair of second electrodes 109a and 109b, an insulating layer 111, a third electrode 113 is provided.

[0135] The first electrode 103 is provided in contact with the base insulating layer 102. The gate insulating layer 105 is The crystalline oxide semiconductor stack 120 is provided to cover the gate insulating layer 105. The pair of second electrodes 109a, 10 The insulating layer 9b is provided to cover an end portion of the crystalline oxide semiconductor stack 120. A second electrode 109a and a second electrode 109b are provided so as to cover a part of the oxide semiconductor stack 120 and the pair of second electrodes 109a and 109b. The third electrode 113 is in contact with the insulating layer 111 and is connected to the pair of second electrodes 109a, 109b. It is located between 9b.

[0136] The pair of second electrodes 109 a and 109 b are disposed at the ends of the crystalline oxide semiconductor stack 120. Since the pair of second electrodes 109a and 109b are provided to cover the crystalline oxide Therefore, at least the crystalline oxide semiconductor stack 120 is in contact with the end surface of the crystalline oxide semiconductor stack 120. In the region in contact with 120, the electrode width of the pair of second electrodes 109a and 109b is The width of the channel is wider than the width of the channel formed in the oxide semiconductor stack 120 (see FIG. 1A).

[0137] Furthermore, FIG. 6B illustrates only one of the pair of second electrodes 109a and 109b. However, the pair of second electrodes 109a and 109b are in contact with the end faces of the crystalline oxide semiconductor stack 120. Therefore, the pair of second electrodes 109a, 109b are the same as in the other embodiments. When a high on-current flows through the crystalline oxide semiconductor stack 120, the on-current becomes a drain sink. The heat can be dissipated to the outside. As a result, the deterioration of the transistor 300 due to heat is reduced. can be suppressed.

[0138] Here, the crystalline oxide semiconductor stack 120 will be described. 20 is a first crystalline oxide semiconductor layer 107a and a second crystalline oxide semiconductor layer 107b. It is a laminated structure.

[0139] The first crystalline oxide semiconductor layer 107a has a c-axis orientation. The first crystalline oxide semiconductor layer 107b also has a c-axis orientation. The crystalline oxide semiconductor layer 107a and the second crystalline oxide semiconductor layer 107b do not have a single crystal structure but have an amorphous structure. The structure is not unique, and it is a crystal with c-axis orientation (C Axis Aligned Crystal al; also called CAAC).

[0140] CAAC-containing oxides are those whose crystals are c-axis oriented and are aligned from the ab plane, surface, or interface direction. The metal atoms are arranged in layers along the c-axis. Or, metal atoms and oxygen atoms are arranged in layers, and on the ab plane (or on the surface or interface) This refers to an oxide that contains crystals with different a- and b-axes (rotated around the c-axis).

[0141] In a broad sense, oxides containing CAAC are non-single crystals that have a crystal structure perpendicular to the ab plane. When viewed from the outside, the atomic arrangement is triangular or hexagonal, or equilateral triangular or equilateral hexagonal, and When viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in layers, or the metal atoms and oxygen atoms are arranged in layers. This term refers to oxides that contain phases arranged in a lattice pattern.

[0142] CAAC also contains crystallized regions (crystalline regions), but one crystalline region and another crystalline region The boundary between the first crystalline oxide semiconductor layer 107a and the second crystalline oxide semiconductor layer 107b may not be clearly distinguishable. The second crystalline oxide semiconductor layer 107b partially has crystal grain boundaries.

[0143] In addition, when the CAAC contains oxygen, a part of the oxygen may be replaced with nitrogen. In addition, the c-axes of the individual crystal regions that compose the CAAC are aligned in a certain direction (e.g., the direction of the crystals that support the CAAC). Even if the alignment is perpendicular to the substrate surface, the CAAC surface, the film surface, or the interface, Alternatively, the normal of the ab plane of each crystal region constituting the CAAC may be in a certain direction (e.g., The direction may be perpendicular to the substrate surface, surface, film surface, interface, etc.

[0144] CAAC may be a conductor or a semiconductor depending on its composition. CAAC may be either a transparent or insulating material. The transparent or opaque material may be used.

[0145] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface, substrate surface, or interface. When observed from the direction, a triangular or hexagonal atomic arrangement is confirmed, and the cross section of the film has metal atoms. Examples include crystals in which layered arrangements of electrons or metal atoms and oxygen atoms (or nitrogen atoms) are observed. It is possible.

[0146] The first crystalline oxide semiconductor layer 107a and the second crystalline oxide semiconductor layer 107b are A metal oxide containing at least zinc, or a metal oxide containing at least zinc and indium. For example, among the metal oxides listed in the first embodiment, a quaternary metal oxide is preferably used. In-Sn-Ga-Zn-based metal oxides, which are ternary metal oxides, and In-Ga -Zn-based metal oxides, In-Sn-Zn-based metal oxides, In-Al-Zn-based metal oxides, Sn-Ga-Zn metal oxide, Al-Ga-Zn metal oxide, Sn-Al-Zn metal oxide Metal oxides, binary metal oxides such as In-Zn metal oxides and Sn-Zn metal oxides It can be formed using Al-Zn-based metal oxides or single-component metal oxides containing Zn. can.

[0147] The first crystalline oxide semiconductor layer 107a is formed by a sputtering method. The substrate temperature during the deposition process is set to 200° C. or higher and 400° C. or lower. It can be obtained by heat treatment (400°C or higher and 750°C or lower).

[0148] Here, an example of the crystal structure of CAAC will be described. However, the first heat treatment causes crystallization from the surface of the film, and the film moves from the surface to the inside. The crystal grows and a c-axis oriented crystal is obtained. The first heat treatment causes zinc and oxygen to adhere to the film surface. A graphene-type two-dimensional crystal of zinc and oxygen that is concentrated on the surface and has a hexagonal upper surface. One or more layers of crystals (a schematic plan view is shown in FIG. 7(A)) are formed on the outermost surface, and this is In FIG. 7(A), the white circles represent zinc atoms and the black circles represent oxide atoms. When the temperature of the heat treatment is increased, the bonds form from the surface to the inside, and then from the inside to the bottom. The crystal growth progresses. Figure 7(B) shows an example of a two-dimensional crystal that has grown and been layered. A schematic showing a stack of six layers of a two-dimensional crystal.

[0149] When oxygen is contained in the gate insulating layer 105, a part of the oxygen is oxidized by the first heat treatment. The first crystalline oxide semiconductor layer 107a is diffused to the interface with the first crystalline oxide semiconductor layer 107a or in the vicinity thereof. Therefore, the gate insulating layer 105 is preferably made of a material having a low oxygen content. (in a bulk), or at the interface between the first crystalline oxide semiconductor layer 107a and the gate insulating layer 105; It is preferred that the amount of oxygen contained in the mixture is at least greater than the stoichiometric ratio.

[0150] The second crystalline oxide semiconductor layer 107b is formed by a sputtering method. The substrate temperature during the formation is set to 200° C. or higher and 400° C. or lower. By setting the temperature to be higher than or equal to 400° C., a crystalline oxide semiconductor layer 107a is formed on the surface of the first crystalline oxide semiconductor layer 107a. The precursors are aligned in the oxide semiconductor layer formed in contact with the oxide semiconductor layer, which gives the oxide semiconductor layer order. After the formation, a second heat treatment (400° C. to 750° C.) is performed. The second heat treatment is preferably performed in a nitrogen atmosphere, an oxygen atmosphere, or a mixed atmosphere of nitrogen and oxygen. By performing the treatment under an atmosphere, the densification of the second crystalline oxide semiconductor layer 107b and the oxygen deficiency can be reduced. By the second heat treatment, the first crystalline oxide semiconductor layer 10 The crystal growth proceeds from the bottom to the inside of the film thickness direction, that is, from the nucleus 7a, to form a second crystalline oxide semiconductor. A conductor layer 107b is formed.

[0151] Similar to the transistor 100, the transistor 300 also has a crystalline oxide semiconductor stack. The thicker the layer 120, the larger the current can be ensured between the source electrode and the drain electrode.

[0152] Furthermore, the drain breakdown voltage of the transistor 300 depends on the thickness of the crystalline oxide semiconductor stack 120. Therefore, in order to increase the drain breakdown voltage, a thicker layer is preferable. The thickness should be selected to suit the pressure.

[0153] Therefore, the thickness of the crystalline oxide semiconductor stack 120 is determined in consideration of the amount of on-state current and the drain breakdown voltage. The thickness is preferably 0.1 μm or more and 50 μm or less, more preferably 0.5 μm or more and 20 μm or less. good.

[0154] The transistor 300 in which the crystalline oxide semiconductor stack 120 is used as a channel formation region is In the direction along the interface, ordering is increased. In the case where carriers flow along the interface of the crystalline oxide semiconductor stack 120, that is, When carriers flow approximately parallel to the ab plane, the crystalline oxide semiconductor The conductor stack 120 is not an obstacle. Therefore, even if light irradiation or BT stress is applied, Therefore, the deterioration of the electrical characteristics of the transistor 300 is suppressed.

[0155] Note that the second crystalline oxide semiconductor layer 107b is formed on the first crystalline oxide semiconductor layer 107a. However, the present invention is not limited to a two-layer structure in which the second crystalline oxide semiconductor layer 107b is formed, and the third crystalline oxide semiconductor layer 107c is formed after the formation of the second crystalline oxide semiconductor layer 107b. The process of forming a crystalline oxide semiconductor layer and the process of heat treatment are repeated to form a crystalline oxide semiconductor layer. A laminated structure of more than one layer may also be used.

[0156] The steps of manufacturing the transistor 300 are described below. The process includes the steps of manufacturing the transistor 100 except for the step of manufacturing the crystalline oxide semiconductor stack 120. Therefore, the following description will be given with reference to FIG.

[0157] Following the manufacturing steps shown in the first embodiment, the gate insulating layer 105 is formed. ) to obtain the configuration shown in

[0158] Next, a first oxide semiconductor film is formed over the gate insulating layer 105. The thickness of the conductive film is set to be 100 nm or more than that of the second oxide semiconductor film to be the second crystalline oxide semiconductor layer 107b. Make it thinner.

[0159] In this embodiment, an In-Ga-Zn metal oxide target (In2O3:Ga2O 3:ZnO=1:1:2 [molar ratio]) was used, and the distance between the substrate and the target was set at 1 70mm, substrate temperature 250℃, pressure 0.4Pa, direct current (DC) power supply 0.5kW, oxygen only , a first oxide semiconductor having a thickness of 100 nm was grown under an atmosphere of argon alone or argon and oxygen. A film is formed.

[0160] Next, the atmosphere in the chamber in which the substrate is placed is changed to nitrogen or dry air, and a first heat treatment is performed. The temperature of the first heat treatment is set to 400° C. or more and 750° C. or less. The heating time of the treatment is from 1 minute to 24 hours. The details of the first heat treatment are described in the first embodiment. Since this has already been explained, it will be omitted here.

[0161] Next, a second crystalline oxide semiconductor film having a thickness larger than that of the first crystalline oxide semiconductor film is formed on the first crystalline oxide semiconductor film. A second oxide semiconductor film is formed.

[0162] In this embodiment, an In-Ga-Zn metal oxide target (In2O3:Ga2O 3:ZnO=1:1:2 [molar ratio]) was used, and the distance between the substrate and the target was set at 1 70mm, substrate temperature 400℃, pressure 0.4Pa, direct current (DC) power supply 0.5kW, oxygen only , a second oxide semiconductor having a thickness of 400 nm was grown under an atmosphere of argon alone or argon and oxygen. A film is formed.

[0163] Next, the atmosphere in the chamber in which the substrate is placed is changed to nitrogen or dry air, and a second heat treatment is performed. The temperature of the second heat treatment is set to 400° C. or more and 750° C. or less. The heating time of the treatment is from 1 minute to 24 hours. A first crystalline oxide semiconductor film is formed (see FIG. 8C). The details of the heat treatment in the second embodiment are the same as those described in the first embodiment. The interface between the crystalline oxide semiconductor film and the second crystalline oxide semiconductor film is indicated by a dotted line, and the oxide semiconductor stack is described. However, there is no clear interface, and the above is merely for the sake of easy understanding. As shown in the figure.

[0164] When the first and second heat treatments are performed at a temperature higher than 750° C., the glass substrate Due to the shrinkage, cracks (cracks extending in the thickness direction) are formed in the oxide semiconductor film. Therefore, the temperature of the first heat treatment and the second heat treatment and the sputtering method are The substrate temperature when the oxide semiconductor film is formed is set to 750° C. or lower, preferably 450° C. or lower. By this, a highly reliable transistor can be manufactured over a large-area glass substrate.

[0165] In addition, the steps from the formation of the gate insulating layer 105 to the second heat treatment are performed without exposure to the air. For example, the manufacturing apparatus shown in the top view of FIG. The manufacturing equipment shown in Figure 12 is a single-wafer multi-chamber facility with three sputtering The apparatus includes three devices 10a, 10b, and 10c, and a cassette port 14 for accommodating substrates to be processed. The substrate supply chamber 11, the load lock chambers 12a and 12b, the transfer chamber 13, the substrate heating chamber 15, etc. The substrate supply chamber 11 and the transport chamber 13 include a heater for transporting the substrate to be processed. The transfer robots are arranged in the sputtering apparatuses 10a, 10b, and 10c. The transfer chamber 13 and the substrate heating chamber 15 are provided with an atmosphere containing almost no hydrogen or moisture (inert It is preferable to control the temperature under a low temperature (e.g., low pressure, low dry air, etc.) atmosphere. The dew point is -40°C or less, preferably -50°C or less, in a dry nitrogen atmosphere. An example of the procedure of the manufacturing process using the manufacturing apparatus 12 is as follows: first, a substrate to be processed is fed from the substrate supply chamber 11. The substrate is transported through the load lock chamber 12a and the transport chamber 13 to the substrate heating chamber 15, where the substrate is heated. In the heat chamber 15, the moisture adhering to the substrate to be processed is removed by vacuum baking or the like, and then the substrate is transferred to the transfer chamber 1. The substrate is transferred to the sputtering device 10c via the sputtering device 10c. The gate insulating layer 105 is formed in the transfer chamber 13 without being exposed to the air. The substrate to be processed is moved to the sputtering device 10a, and a first oxidation is performed in the sputtering device 10a. Then, the substrate is transferred to the substrate heating chamber 1 through the transfer chamber 13 without being exposed to the air. The substrate is then transferred to the chamber 5 and the first heat treatment is performed. The substrate is transferred to the sputtering device 10b via the transfer chamber 13. A second oxide semiconductor film is formed in the transfer chamber 10b without being exposed to the air. The substrate is then moved to the substrate heating chamber 15 via the heating chamber 3, and the second heating process is performed. By using the manufacturing equipment shown in Figure 12, the transistor manufacturing process can be completed without exposure to air. In addition, the sputtering device of the manufacturing equipment shown in FIG. By changing the target, a manufacturing process without exposure to air can be realized. The substrate on which the gate insulating layer 105 is formed is placed in the cassette port 14, and the first oxide semiconductor The first crystalline oxide was formed by performing the process from the formation of the solid film to the second heat treatment without exposure to air. After forming the crystalline oxide semiconductor film and the second crystalline oxide semiconductor film, A pair of second electrodes 109a and 109b are formed using a metal target in the wafer forming apparatus 10c. A conductive film for forming a conductive layer can be formed over the second crystalline oxide semiconductor film.

[0166] Next, a crystalline oxide semiconductor film consisting of the first crystalline oxide semiconductor film and the second crystalline oxide semiconductor film is formed. The stack of oxide semiconductor layers is processed to form a first crystalline oxide semiconductor layer 107a and a second crystalline oxide semiconductor layer 107b. The crystalline oxide semiconductor layer 107b is stacked on the oxide semiconductor layer 107b to form a crystalline oxide semiconductor stack 120 (FIG. 8(D)). reference).

[0167] The crystalline oxide semiconductor stack is processed by forming a mask having a desired shape on the crystalline oxide semiconductor stack. After the mask is formed, the crystalline oxide semiconductor stack is etched using the mask. The mark can be formed using methods such as photolithography. The mask may be formed using a method such as a lithography method.

[0168] Note that the etching of the stacked crystalline oxide semiconductor layers may be performed by either dry etching or wet etching. Dry etching and wetting may also be used. Of course, these may be used in combination. The details of the wet etching are the same as those described in the first embodiment.

[0169] The subsequent steps are the same as those in the first embodiment, and a pair of second electrodes 109a and 109b are formed. A part of the crystalline oxide semiconductor stack 120 and the pair of second electrodes 109a and 109b are formed. In addition, a crystalline oxide semiconductor layer is formed in contact with the insulating layer. The third electrode 113 is formed so as to overlap the channel forming region of the laminated layer 120 (FIG. 6 The details of each step are the same as those described in the first embodiment. The process of forming the electrodes 109a and 109b also includes the process of forming the wiring 110 (see FIG. 1(A)). The step of forming the third electrode 113 is performed after the step of forming the wiring 114 (see FIG. 1A). He also serves as a consultant.

[0170] As a result, it is possible to obtain a nonlinear element having a high breakdown voltage, a low reverse saturation current, and a high on-state current. It should be noted that this embodiment may be appropriately combined with the configurations described in other embodiments. It is possible to combine these methods.

[0171] (Embodiment 4) In this embodiment, a nonlinear element having a configuration partially different from that of the nonlinear element shown in the above embodiment is used. Note that in this embodiment, a transistor will also be taken as an example.

[0172] The transistor 400 described in this embodiment is the same as the transistor 200 described in Embodiment 2. The oxide semiconductor layer 107 is a crystalline oxide semiconductor layer 107a. The transistor in which the crystalline oxide semiconductor stack 120 is replaced with the crystalline oxide semiconductor layer 107b. In other words, the planar structure of the transistor 400 is the same as that of the transistor 200. Therefore, a plan view of the transistor 400 can be seen in FIG. FIG. 9B is a cross-sectional view of the transistor 400 taken along a line E-F (see FIG. 4A). 4A is a cross-sectional view of the transistor 400 taken along the line G-H (see FIG. 4A). 9, the same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description is omitted.

[0173] As shown in FIG. 9B, the transistor 400 is a dual-gate transistor. On the plate 101, a base insulating layer 102, a first electrode 103, a gate insulating layer 105, a crystalline oxide Semiconductor stack 120, n + Layers 117a, 117b, a pair of second electrodes 109a, 109b , an insulating layer 111 and a third electrode 113 are provided.

[0174] The first electrode 103 is provided in contact with the base insulating layer 102. The gate insulating layer 105 is The crystalline oxide semiconductor stack 120 is provided to cover the gate insulating layer 105. The first electrode 103 is disposed in contact with the first electrode 104 and overlaps the first electrode 103. + Layers 117a and 117b are The second insulating layer 105 and the second insulating layer 120 are provided to cover end portions of the second insulating layer 105 and the crystalline oxide semiconductor stack 120. The second electrodes 109a and 109b are disposed at the end and the n + layer 117a The insulating layer 111 is provided to cover the end portions of the crystalline oxide semiconductor stack 120. The third electrode 113 is provided so as to cover a part of the pair of second electrodes 109a and 109b. It is provided on and in contact with the insulating layer 111 and between the pair of second electrodes 109a, 109b.

[0175] Between the crystalline oxide semiconductor stack 120 and the pair of second electrodes 109a and 109b, n + layer By forming the crystalline oxide semiconductor stack 120 and the pair of second insulating films 117a and 117a, Since the contact resistance between the electrodes 109a and 109b can be reduced, a high on-current can be obtained. Also, n + By forming the layers 117a and 117b, the parasitic resistance Furthermore, the change in on-current before and after applying negative gate stress in the BT test This can suppress the amount of ion degradation.

[0176] Furthermore, FIG. 1C illustrates only one of the pair of second electrodes 109a and 109b. But, n + The layers 117a and 117b are formed by depositing the pair of second electrodes 109a and 109b as a mask. In order to perform the etching process, the ends of the pair of second electrodes 109a and 109b protrude. The channel length of transistor 400 is then n + The spacing between layers 117a and 117b The pair of second electrodes 109a and 109b is determined by n + Layer 117a, 11 7b faces the crystalline oxide semiconductor stack 120. + layers 117a, 117 The thickness of b is not extremely large, and the thickness of the crystalline oxide semiconductor stack 120 is small. Since the transmission is not blocked, it acts as a heat sink in the same way as in the other embodiments. To dissipate heat generated when a high on-current flows through the oxide semiconductor stack 120 to the outside. As a result, deterioration of the transistor 400 due to heat generation can be suppressed.

[0177] The crystalline oxide semiconductor stack 120 includes a first crystalline oxide semiconductor layer 107a and a second crystalline oxide semiconductor layer 107b. The first crystalline oxide semiconductor layer 107a and the second crystalline oxide semiconductor layer 107b are stacked together. The details of the second crystalline oxide semiconductor layer 107b are the same as those described in Embodiment 3. In the transistor 400 described in this embodiment, the first crystalline oxide semiconductor layer 107a, and the second crystalline oxide semiconductor layer 107b is at least partially crystallized and has a c-axis orientation. The crystalline oxide semiconductor stack 120 has a thickness of 100 nm in the direction along the interface with the gate insulating layer. Therefore, when carriers flow along the interface, the flow The crystalline oxide semiconductor stack 120 does not impede this. Even if a BT stress is applied, the degradation of the electrical characteristics of the transistor 400 is suppressed.

[0178] The steps of manufacturing the transistor 400 are described below. The process includes a process for manufacturing the transistor 200 other than the process for manufacturing the crystalline oxide semiconductor stack 120. Therefore, the description will be given with reference to Figs.

[0179] According to the manufacturing steps described in the first and third embodiments, a crystalline oxide semiconductor stack 1 20 are formed to obtain the structure shown in FIG. 8(D).

[0180] Next, an In—Zn based Metal oxides, In-Sn metal oxides, and single-component metal oxides containing indium or tin Using the fee, n + The film 115 that will become the layers 117a and 117b is formed to a thickness of 1 nm to 200 nm. The method for forming the film 115 is the same as that described in the second embodiment. + Layers and In this embodiment, the above-mentioned materials may contain SiO2. A Sn-based metal oxide is formed to a thickness of 100 nm.

[0181] Next, n +A pair of second electrodes 109a, 109b are formed on the film 115 to be the layer. A conductive film for forming the pair of second electrodes 1 is formed by processing the conductive film (see FIG. 5(A)). In addition, the step of forming a pair of second electrodes 109a and 109b is performed. This process also serves as a process for forming the wiring 110 (see FIG. 4(A)).

[0182] Next, the film 115 is processed using the pair of second electrodes 109a, 109b as a mask, n + By this processing, layers 117a and 117b are formed. + The layers 117a and 117b are a pair. The ends of the second electrodes 109a and 109b are formed so as to protrude from the electrodes (FIG. 5(B)). Therefore, the channel length of transistor 400 is n + Spacing between layers 117a and 117b The channel length of the transistor 300 described in Embodiment 3 is determined by It is determined by the distance between the pair of second electrodes 109a and 109b. + layer 117a, The taper angle of the end of 117b (n + The side surfaces of the layers 117a and 117b are in the plane of the substrate 101. The angle should be less than 30 degrees.

[0183] The subsequent steps are the same as those in the second embodiment. An insulating layer 111 is formed to cover the pair of second electrodes 109a and 109b. 1 and overlapping with a channel formation region of the crystalline oxide semiconductor stack 120. The third electrode 113 is formed (see FIG. 9(A)). The process also includes a process for forming the wiring 114 (see FIG. 4(A)). Same as state 2.

[0184] As a result, it is possible to obtain a nonlinear element having a high breakdown voltage, a low reverse saturation current, and a high on-state current. It should be noted that this embodiment may be appropriately combined with the configurations described in other embodiments. It is possible to combine these methods.

[0185] (Embodiment 5) In this embodiment, the calculation results of the on-current of the nonlinear element will be described. The calculation is performed on a simplified nonlinear element structure. The device used is the Sentaurus device manufactured by the company.

[0186] First, we explain the results of calculating the change in drain current with respect to the change in gate voltage. do.

[0187] FIG. 13A shows the transistor 200 described in the second embodiment. FIG. 4(A) is a simplified cross-sectional view of the cross-sectional structure in the direction of the arrow (cross-sectional structure between EF in FIG. 4(A)). 1). Figure 13(B) is a simplified diagram of the cross-sectional structure between G and H in Figure 4(A). FIG. 13C shows a vertical line between EF in the channel formation region of the transistor 200. 13 is a simplified diagram of a cross-sectional structure in a vertical direction. The same reference numerals as in FIG. 4 are used for the components.

[0188] The parameters reflected in the calculation results of the on-current in the structure shown in Figure 13 are as follows: It is. 1. Channel length L1: 10 μm 2. Length L2 of the pair of second electrodes 109a, 109b: 5 μm 3. Thickness T of the oxide semiconductor layer 107 os :10μm 4. Thickness T of the gate insulating layer 105G and the thickness T of the insulating layer 111 BG :0.2μm 5.Channel width W1: 100μm 6. Width W2 of the pair of second electrodes 109a, 109b: 5 μm 7. Work function φM of tungsten used in the first electrode 103: 4.9 eV 8. Work function φM of titanium used in the pair of second electrodes 109a and 109b: 4.0 eV 9. Work function φM of molybdenum used in the third electrode 113: 4.8 eV 10. Band gap E of In-Ga-Zn metal oxide used in oxide semiconductor layer 107 g: 3.15eV, electron affinity χ: 4.3eV, dielectric constant: 15, electron mobility: 10cm 2 / Vs 11. Dielectric constant of silicon oxynitride used in gate insulating layer 105: 4.1 12. Dielectric constant of silicon oxide used in insulating layer 111: 3.8

[0189] The first electrode 103, the pair of second electrodes 109a and 109b, the third electrode 113, and Bin + The layers 117a and 117b are assumed to have the same potential in the calculations, regardless of their respective thicknesses. Therefore, these thicknesses are not reflected in the calculation results.

[0190] Figure 14 shows the results when the drain voltage was set to 15 V and the gate voltage was changed from 0 V to 20 V. As can be seen from FIG. 14, the drain current (Id) of the oxide semiconductor The end of the layer 107 is n + Layers 117a, 117b and a pair of second electrodes 109a, 109b A nonlinear element having a structure covered with the insulating film can obtain a high on-current.

[0191] Next, the change in drain current with respect to the change in drain voltage in structure 1 was calculated. The comparative examples are Structures 2 to 4 shown below.

[0192] Structure 2 is a transistor 200 having a pair of second electrodes 109a, 109b, n + The layers 117a and 117b and the third electrode 113 are not in contact with the side surfaces of the oxide semiconductor layer 107. Structure 2 (see FIG. 15) is the same as FIG. 13(A). FIG. 15(B) is a simplified diagram similar to FIG. 13(B). FIG. 15(C) is a simplified diagram similar to FIG. 13(C).

[0193] The structure 3 includes a pair of second electrodes 109a, 109b, n + The layers 117a and 117b are oxidized The third electrode 113 is in contact with the side surface of the oxide semiconductor layer 107. In Structure 3, FIG. 16(A) shows the same structure as FIG. 13(A). FIG. 16(B) is a simplified diagram similar to FIG. 13(B). Fig. 16(C) is a simplified diagram similar to Fig. 13(C).

[0194] The structure 4 includes a pair of second electrodes 109a, 109b, n + The layers 117a and 117b are oxidized The third electrode 113 is not in contact with the side surface of the oxide semiconductor layer 107. In Structure 4, FIG. 17(A) shows the same structure as FIG. 13(A). FIG. 17(B) is a simplified diagram similar to FIG. 13(B). FIG. 17(C) is a simplified diagram similar to FIG. 13(C).

[0195] In Structures 2 to 4, the parameters reflected in the calculation results are the parameters in Structure 1. The meter is the same as the meter. In addition, the first electrode 103, the pair of second electrodes 109a, 109b , the third electrode 113 and n + Layers 117a and 117b are at the same potential regardless of their respective thicknesses. Since the calculation is made assuming these thicknesses, these thicknesses are not reflected in the calculation results.

[0196] The calculation results of the on-current in the structures 1 to 4 are shown in FIG. When the drain voltage (Vd) is changed from 0V to 20V with the drain voltage (Vg) set to 10V. The results are shown in Table 1, where the drain current (Id) corresponding to each drain voltage is calculated.

[0197] As shown in FIG. 18, the drain current of the structure 1 is higher than that of the structures 2 to 4. That is, as in the structure 1, a pair of second electrodes 109a , 109b, n + The layers 117a and 117b and the third electrode 113 are By using a structure in which the oxide semiconductor layer 107, which is a channel formation region, is in contact with the side surface of the oxide semiconductor layer 107, It can inject carriers well, obtain a high on-current, and is suitable for large current applications. It is suitable for nonlinear elements.

[0198] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0199] (Embodiment 6) In this embodiment, a power diode and a rectifier using a nonlinear element according to one embodiment of the present invention will be described. An example of the flow converter will be described with reference to Figs.

[0200] FIG. 10A-1 illustrates a structural example of a power diode according to one embodiment of the present invention. The power diode shown in 0(A-1) is a series connection of multiple diodes. .

[0201] FIG. 10(B-1) illustrates a structural example of a rectifier according to one embodiment of the present invention. The rectifier shown in Figure 1 is a half-wave rectifier made up of two diodes. The anode of the diode is connected to a reference potential (preferably ground potential) on the low potential side, and the first diode The cathode of the diode is connected to the input and the anode of the second diode. The cathode is connected to the output.

[0202] FIG. 10(C-1) illustrates a structural example of a rectifier according to one embodiment of the present invention. The rectifier shown in FIG. 1 is a full-wave rectifier made up of four diodes. The first diodes are arranged clockwise from the top left diode. The anode of the first diode and the anode of the fourth diode are The anode is connected to a reference potential (preferably ground potential) on the low potential side. The cathode of the first diode and the anode of the second diode are connected to the “first input portion.” The anode of the third diode and the cathode of the fourth diode are connected to the "second input section." The cathode of the second diode and the cathode of the third diode are connected to the "output section." is connected to

[0203] The diodes used in the power diode, half-wave rectifier and full-wave rectifier are the same as those in the previous embodiment. A pair of second electrodes 1 functioning as source electrodes or drain electrodes of the nonlinear element described in One of the electrodes 09a and 109b is electrically connected to the first electrode 103 which functions as a gate electrode. A nonlinear element connected in series (diode-connected) can be used (see FIG. 11). In this case, when the nonlinear element described in the above embodiment is an n-type nonlinear element, a diode The connected electrode is the anode, and the electrode not diode-connected is the cathode.

[0204] FIG. 11(A) is a plan view of a diode-connected nonlinear element. FIG. 11(B) is a plan view of a diode-connected nonlinear element. 11(B) is a cross-sectional view taken along line IJ in FIG. The wiring 110 including the first electrode 103 is connected to the wiring 110 including the first electrode 109a and the wiring 110 including the first electrode 103 through the opening 150. It is electrically connected to the wire 104. In this embodiment, the Although the transistor 100 has been described, the transistors described in the second to fourth embodiments may be used. A transistor can also be diode-connected in the same manner.

[0205] The power diode in Figure 10(A-1) uses a diode-connected transistor. The half-wave rectifier shown in FIG. 10(B-1) can be configured as shown in FIG. The structure shown in FIG. 10(B-2) can be achieved by using a diode-connected transistor. The full-wave rectifier shown in Fig. 10(C-1) uses diode-connected transistors. It can have the configuration shown in (C-2).

[0206] In FIG. 10(A-2), the transistor that constitutes the power diode is a dual gate. Since the semiconductor device is of the gate type, a third electrode 113 (including a wiring 114) is provided (see FIG. 11). Each of the third electrodes 113 to which the control signals G1 to G5 are applied is diode-connected. The threshold voltage of each of the transistors is controlled by the control circuit shown in FIG. 10(B-2) and FIG. 10(C-3). Similarly, in the case of -2), each transistor is provided with a third electrode 113. Therefore, each diode-connected transistor is turned on or off by the control signals G1 to G4. For example, as described in the previous embodiment, the voltage can be controlled from the viewpoint of reliability. In the field of transistors using oxide semiconductors, when exposed to visible light or ultraviolet light, heat, or an electric field, This causes the electrical characteristics to change. An example of this is normally-on. When the current source and full-wave rectifier are constructed with n-type transistors, the n-type transistors When turned on, half-wave and full-wave rectifiers can pass current even when reverse bias is applied. Therefore, a half-wave rectifier and A third electrode 113 that functions as a back gate electrode of a transistor that constitutes a full-wave rectifier By applying a negative potential to the A good rectification effect can be obtained.

[0207] In this embodiment, the third transistor constituting the power diode and the rectifier The electrodes 113 are arranged to transmit control signals to the individual transistors in a one-to-one relationship. However, the individual third electrodes 113 are electrically connected together to form a power diode and a rectifier. The same control signal may be sent to each transistor constituting the device. In the present invention, a transistor constituting a power diode and a rectifier has an oxide semiconductor layer. In order to clarify that it is a transistor that uses It is written as "S".

[0208] In addition, the transistors constituting the power diode and rectifier described in this embodiment are Since an oxide semiconductor can be used, the power diode and the The rectifier has excellent drain withstand voltage and is capable of obtaining a high drain current.

[0209] As a result, the device has characteristics such as high breakdown voltage and low reverse saturation current, and can achieve a high on-state current. It is possible to obtain a semiconductor device having a nonlinear element that can be used for the present embodiment. The present invention can be implemented in appropriate combination with the configurations described in the above embodiment. [Explanation of symbols]

[0210] 10a Sputtering equipment 10b Sputtering equipment 10c Sputtering equipment 11 Substrate supply room 12a Load lock chamber 12b Load lock chamber 13 Transport Room 14 Cassette port 15 Substrate heating chamber 100 transistors 101 Substrate 102 Undercoat insulation layer 103 First electrode 104 Wiring 105 Gate Insulation Layer 106 Oxide semiconductor film 107 Oxide semiconductor layer 107a Crystalline oxide semiconductor layer 107b Crystalline oxide semiconductor layer 108 Conductive Film 109a second electrode 109b second electrode 110 Wiring 111 Insulating layer 113 Third Electrode 114 Wiring 115 Membrane 117a n + layer 117b n + layer 118 Conductive Film 126 Oxide Semiconductor Layer 150 Opening 200 Transistors 300 Transistors 400 Transistors

Claims

1. A first electrode having a region located above a substrate; a first insulating layer having a region overlying the first electrode; an oxide semiconductor layer having a region overlapping with the first electrode with the first insulating layer interposed therebetween and including a channel formation region of a transistor; a first layer having a region located above the oxide semiconductor layer; a source electrode having a region overlying the first layer; a second layer having a region located above the oxide semiconductor layer; a drain electrode having a region overlying the second layer; a second insulating layer having a region located above the source electrode and a region located above the drain electrode; a second electrode having a region located above the second insulating layer; the first layer has a region in contact with the oxide semiconductor layer, the second layer has a region in contact with the oxide semiconductor layer, the first layer comprises In and Zn; the second layer comprises In and Zn; the source electrode has a region in contact with the first layer, the drain electrode has a region in contact with the second layer, a first region arranged to extend in a channel width direction of the transistor and function as a gate electrode of the transistor, and a second region arranged to extend in a channel length direction of the transistor and function as a gate wiring, in a planar view of the semiconductor device.

2. A first electrode having a region located above a substrate; a first insulating layer having a region overlying the first electrode; an oxide semiconductor layer having a region overlapping with the first electrode with the first insulating layer interposed therebetween and including a channel formation region of a transistor; a first layer having a region located above the oxide semiconductor layer; a source electrode having a region overlying the first layer; a second layer having a region located above the oxide semiconductor layer; a drain electrode having a region overlying the second layer; a second insulating layer having a region located above the source electrode and a region located above the drain electrode; a second electrode having a region located above the second insulating layer; the first layer has a region in contact with the oxide semiconductor layer, the second layer has a region in contact with the oxide semiconductor layer, the first layer comprises In and Zn; the second layer comprises In and Zn; the source electrode has a region in contact with the first layer, the drain electrode has a region in contact with the second layer, When viewed in a cross section in a channel length direction, an angle between an upper surface of the substrate and a side surface of the first layer is 30 degrees or less; When viewed in a cross section in a channel length direction, an angle between an upper surface of the substrate and a side surface of the second layer is 30 degrees or less; a first region arranged to extend in a channel width direction of the transistor and function as a gate electrode of the transistor, and a second region arranged to extend in a channel length direction of the transistor and function as a gate wiring, in a planar view of the semiconductor device.

3. A first electrode having a region located above a substrate; a first insulating layer having a region overlying the first electrode; an oxide semiconductor layer having a region overlapping with the first electrode with the first insulating layer interposed therebetween and including a channel formation region of a transistor; a first layer having a region located above the oxide semiconductor layer; a source electrode having a region overlying the first layer; a second layer having a region located above the oxide semiconductor layer; a drain electrode having a region overlying the second layer; a second insulating layer having a region located above the source electrode and a region located above the drain electrode; a second electrode having a region located above the second insulating layer; the first layer has a region in contact with the oxide semiconductor layer, the second layer has a region in contact with the oxide semiconductor layer, the first layer comprises In and Zn; the second layer comprises In and Zn; the source electrode has a region in contact with the first layer, the drain electrode has a region in contact with the second layer, the first layer has a region extending from an end of the source electrode; the second layer has a region extending from an end of the drain electrode; a first region arranged to extend in a channel width direction of the transistor and function as a gate electrode of the transistor, and a second region arranged to extend in a channel length direction of the transistor and function as a gate wiring, in a planar view of the semiconductor device.

4. A first electrode having a region located above a substrate; a first insulating layer having a region overlying the first electrode; an oxide semiconductor layer having a region overlapping with the first electrode with the first insulating layer interposed therebetween and including a channel formation region of a transistor; a first layer having a region located above the oxide semiconductor layer; a source electrode having a region overlying the first layer; a second layer having a region located above the oxide semiconductor layer; a drain electrode having a region overlying the second layer; a second insulating layer having a region located above the source electrode and a region located above the drain electrode; a second electrode having a region located above the second insulating layer; the first layer has a region in contact with the oxide semiconductor layer, the second layer has a region in contact with the oxide semiconductor layer, the first layer comprises In and Zn; the second layer comprises In and Zn; the source electrode has a region in contact with the first layer, the drain electrode has a region in contact with the second layer, When viewed in a cross section in a channel length direction, an angle between an upper surface of the substrate and a side surface of the first layer is 30 degrees or less; When viewed in a cross section in a channel length direction, an angle between an upper surface of the substrate and a side surface of the second layer is 30 degrees or less; the first layer has a region extending from an end of the source electrode; the second layer has a region extending from an end of the drain electrode; a first region arranged to extend in a channel width direction of the transistor and function as a gate electrode of the transistor, and a second region arranged to extend in a channel length direction of the transistor and function as a gate wiring, in a planar view of the semiconductor device.

5. A first electrode having a region located above a substrate; a first insulating layer having a region overlying the first electrode; an oxide semiconductor layer having a region overlapping with the first electrode with the first insulating layer interposed therebetween and including a channel formation region of a transistor; a first layer having a region located above the oxide semiconductor layer; a source electrode having a region overlying the first layer; a second layer having a region located above the oxide semiconductor layer; a drain electrode having a region overlying the second layer; a second insulating layer having a region located above the source electrode and a region located above the drain electrode; a second electrode having a region located above the second insulating layer; the first layer has a region in contact with the oxide semiconductor layer, the second layer has a region in contact with the oxide semiconductor layer, the first layer comprises In and Zn; the second layer comprises In and Zn; the source electrode has a region in contact with the first layer, the drain electrode has a region in contact with the second layer, the first layer and the second layer each have a composition different from that of the oxide semiconductor layer, a first region arranged to extend in a channel width direction of the transistor and function as a gate electrode of the transistor, and a second region arranged to extend in a channel length direction of the transistor and function as a gate wiring, in a planar view of the semiconductor device.

6. A first electrode having a region located above a substrate; a first insulating layer having a region overlying the first electrode; an oxide semiconductor layer having a region overlapping with the first electrode with the first insulating layer interposed therebetween and including a channel formation region of a transistor; a first layer having a region located above the oxide semiconductor layer; a source electrode having a region overlying the first layer; a second layer having a region located above the oxide semiconductor layer; a drain electrode having a region overlying the second layer; a second insulating layer having a region located above the source electrode and a region located above the drain electrode; a second electrode having a region located above the second insulating layer; the first layer has a region in contact with the oxide semiconductor layer, the second layer has a region in contact with the oxide semiconductor layer, the first layer comprises In and Zn; the second layer comprises In and Zn; the source electrode has a region in contact with the first layer, the drain electrode has a region in contact with the second layer, the first layer and the second layer each have a composition different from that of the oxide semiconductor layer, When viewed in a cross section in a channel length direction, an angle between an upper surface of the substrate and a side surface of the first layer is 30 degrees or less; When viewed in a cross section in a channel length direction, an angle between an upper surface of the substrate and a side surface of the second layer is 30 degrees or less; a first region arranged to extend in a channel width direction of the transistor and function as a gate electrode of the transistor, and a second region arranged to extend in a channel length direction of the transistor and function as a gate wiring, in a planar view of the semiconductor device.

7. A first electrode having a region located above a substrate; a first insulating layer having a region overlying the first electrode; an oxide semiconductor layer having a region overlapping with the first electrode with the first insulating layer interposed therebetween and including a channel formation region of a transistor; a first layer having a region located above the oxide semiconductor layer; a source electrode having a region overlying the first layer; a second layer having a region located above the oxide semiconductor layer; a drain electrode having a region overlying the second layer; a second insulating layer having a region located above the source electrode and a region located above the drain electrode; a second electrode having a region located above the second insulating layer; the first layer has a region in contact with the oxide semiconductor layer, the second layer has a region in contact with the oxide semiconductor layer, the first layer comprises In and Zn; the second layer comprises In and Zn; the source electrode has a region in contact with the first layer, the drain electrode has a region in contact with the second layer, the first layer and the second layer each have a composition different from that of the oxide semiconductor layer, the first layer has a region extending from an end of the source electrode; the second layer has a region extending from an end of the drain electrode; a first region arranged to extend in a channel width direction of the transistor and function as a gate electrode of the transistor, and a second region arranged to extend in a channel length direction of the transistor and function as a gate wiring, in a planar view of the semiconductor device.

8. A first electrode having a region located above a substrate; a first insulating layer having a region overlying the first electrode; an oxide semiconductor layer having a region overlapping with the first electrode with the first insulating layer interposed therebetween and including a channel formation region of a transistor; a first layer having a region located above the oxide semiconductor layer; a source electrode having a region overlying the first layer; a second layer having a region located above the oxide semiconductor layer; a drain electrode having a region overlying the second layer; a second insulating layer having a region located above the source electrode and a region located above the drain electrode; a second electrode having a region located above the second insulating layer; the first layer has a region in contact with the oxide semiconductor layer, the second layer has a region in contact with the oxide semiconductor layer, the first layer comprises In and Zn; the second layer comprises In and Zn; the source electrode has a region in contact with the first layer, the drain electrode has a region in contact with the second layer, the first layer and the second layer each have a composition different from that of the oxide semiconductor layer, When viewed in a cross section in a channel length direction, an angle between an upper surface of the substrate and a side surface of the first layer is 30 degrees or less; When viewed in a cross section in a channel length direction, an angle between an upper surface of the substrate and a side surface of the second layer is 30 degrees or less; the first layer has a region extending from an end of the source electrode; the second layer has a region extending from an end of the drain electrode; a first region arranged to extend in a channel width direction of the transistor and function as a gate electrode of the transistor, and a second region arranged to extend in a channel length direction of the transistor and function as a gate wiring, in a planar view of the semiconductor device.

9. In any one of claims 1 to 8, the first insulating layer comprises silicon oxide; The second insulating layer comprises silicon oxide.

10. In any one of claims 1 to 9, The semiconductor device, wherein the oxide semiconductor layer contains In.

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