Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes: a p-channel type transistor that is provided on a silicon substrate; and an n-channel type transistor. One of a source and a drain of the p-channel type transistor is electrically connected to a first power supply wire, and one of the source and the drain of the n-channel type transistor is electrically connected to a second power supply wire. The other one of the source and the drain of the p-channel type transistor is connected to the other one of the source and the drain of the n-channel type transistor. The p-channel type transistor includes: a first gate electrode; and a first back gate electrode that is provided so as to face the first gate electrode while nipping a first channel formation region. The first back gate electrode is constructed by using a region into which an impurity element for applying conductivity is selectively introduced in the silicon substrate. The n-channel type transistor is provided to an upper portion of a layer having the p-channel type transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Metal oxides have been attracting attention as semiconductors that can be applied to transistors. In-Ga-Zn oxide, also known as "IGZO" or "Iguzo", is a representative multi-component metal oxide. In research on IGZO, a c-axis aligned crystalline (CAAC) structure and a nanocrystalline (nc) structure, which are neither single crystal nor amorphous, were discovered (e.g., Non-Patent Document 1).

[0004] It has been reported that a transistor having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as an "oxide semiconductor transistor" or an "OS transistor") has an extremely small off-state current (for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4).

[0005] The manufacturing process of an OS transistor can be incorporated into a CMOS process with a transistor having silicon in its channel formation region (Si transistor), and the OS transistor can be stacked on the Si transistor. For example, Patent Document 1 discloses a configuration in which multiple layers of a memory cell array having OS transistors are stacked on a substrate on which Si transistors are provided.

[0006] In logic circuits fabricated by CMOS processes, it is preferable for low-voltage operation that the variation in characteristics such as the threshold voltage of p-channel transistors and n-channel transistors is small. Patent Document 2 discloses a configuration called a transistor in which a well region under a buried insulating layer directly under a thin silicon film is used as a back gate in a fully-depleted SOI (FD-SOI: Fully-Depleted Silicon On Insulator). This transistor is said to have the advantages of reducing the variation in characteristics such as threshold voltage and current and having excellent short channel characteristics because it hardly contains impurity elements that impart conductivity to the channel formation region. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] US Patent Application Publication No. 2012 / 0063208 [Patent Document 2] JP 2015-103555 A [Non-patent literature]

[0008] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-Patent Document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-Patent Document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-Patent Document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0009] When fabricating a complementary logic circuit using transistors on an FD-SOI substrate, a backgate for controlling the threshold voltage is an effective way to achieve low-voltage operation. However, the circuit area increases because of the increased number of electrodes for controlling the backgate potential. In addition, the fabrication process becomes complicated because it is necessary to fabricate p-channel and n-channel transistors separately.

[0010] The current that flows through a Si transistor when it is turned on (on-state current) is much larger than the on-state current of an OS transistor. Therefore, when designing a logic circuit by fabricating an OS transistor on a Si transistor, the size of the OS transistor needs to be larger than the size of the Si transistor when designing a logic circuit such as an inverter circuit, which results in an imbalance in the transistor sizes.

[0011] In addition, the electrical characteristics of Si transistors and OS transistors with respect to temperature are different. For example, the on-current of Si transistors decreases at high temperatures and increases at low temperatures, whereas the on-current of OS transistors increases at high temperatures and decreases at low temperatures. Therefore, when designing logic circuits by fabricating OS transistors on Si transistors, it is difficult to ensure stable operation with respect to temperature changes.

[0012] An object of one embodiment of the present invention is to provide a miniaturized semiconductor device that is excellent in reducing a circuit area.Another object of one embodiment of the present invention is to provide a semiconductor device that is excellent in stable operation against temperature changes.Another object of one embodiment of the present invention is to provide a semiconductor device that is excellent in reducing power consumption.Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure.

[0013] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but only needs to solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0014] One embodiment of the present invention is a semiconductor device including a p-channel transistor and an n-channel transistor provided on a silicon substrate, in which one of a source or a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source or a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source or the drain of the p-channel transistor is connected to the other of the source or the drain of the n-channel transistor, the p-channel transistor has a first gate electrode and a first backgate electrode provided facing the first gate electrode with a first channel formation region therebetween, the first backgate electrode is formed using a region in the silicon substrate into which an impurity element that imparts conductivity is selectively introduced, and the n-channel transistor is provided above a layer having the p-channel transistor.

[0015] In one embodiment of the present invention, the semiconductor device is preferably such that the n-channel transistor has a second channel formation region, and the second channel formation region has a metal oxide.

[0016] In one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

[0017] In one embodiment of the present invention, the semiconductor device is preferably such that the n-channel transistor has a second backgate electrode, and a potential applied to the first backgate electrode is lower than a potential applied to the second backgate electrode.

[0018] One embodiment of the present invention is a semiconductor device including a p-channel transistor and an n-channel transistor provided on a silicon substrate, in which one of a source or a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source or a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source or the drain of the p-channel transistor is connected to the other of the source or the drain of the n-channel transistor, the p-channel transistor has a first gate electrode and a first backgate electrode provided facing the first gate electrode with a first channel formation region therebetween, the first backgate electrode is formed using a region in the silicon substrate into which an impurity element that imparts conductivity is selectively introduced, the n-channel transistor has a second gate electrode and a second backgate electrode provided facing the second gate electrode with a second channel formation region therebetween, and the n-channel transistor is provided above a layer having the p-channel transistor.

[0019] In one embodiment of the present invention, the second channel formation region preferably has a metal oxide.

[0020] In one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

[0021] In one embodiment of the present invention, the semiconductor device is preferably one in which a potential applied to the first backgate electrode is lower than a potential applied to the second backgate electrode.

[0022] Other aspects of the present invention will be described in the following embodiment and in the drawings. Effect of the Invention

[0023] According to one embodiment of the present invention, a miniaturized semiconductor device excellent in reducing a circuit area can be provided. According to another embodiment of the present invention, a semiconductor device excellent in stable operation against temperature changes can be provided. According to another embodiment of the present invention, a semiconductor device excellent in reducing power consumption can be provided. Alternatively, a semiconductor device having a novel structure can be provided.

[0024] The description of multiple effects does not preclude the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all of the exemplified effects. In addition, problems, effects, and novel features other than those described above regarding one embodiment of the present invention will become apparent from the description and drawings in this specification. [Brief description of the drawings]

[0025] [Figure 1] 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. [Diagram 2] 2A and 2B are diagrams illustrating a configuration example of a semiconductor device. [Diagram 3] 3A and 3B are diagrams illustrating a configuration example of a semiconductor device. [Figure 4] 4A and 4B are diagrams illustrating a configuration example of a semiconductor device. [Diagram 5] FIG. 5 is a diagram illustrating a configuration example of a semiconductor device. [Figure 6] 6A and 6B are diagrams illustrating a configuration example of a semiconductor device. [Figure 7] 7A and 7B are diagrams illustrating a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating a configuration example of a semiconductor device. [Figure 9] 9A to 9C are diagrams illustrating a configuration example of a semiconductor device. [Figure 10] 10A to 10C are diagrams illustrating a configuration example of a semiconductor device. [Figure 11] 11A and 11B are diagrams illustrating a configuration example of a semiconductor device. [Figure 12] 12A and 12B are diagrams illustrating a configuration example of a semiconductor device. [Figure 13] 13A and 13B are diagrams illustrating a configuration example of a semiconductor device. [Figure 14] FIG. 14 is a diagram illustrating a configuration example of a semiconductor device. [Figure 15] FIG. 15 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 16] FIG. 16 is a diagram for explaining a configuration example of an integrated circuit. [Figure 17] 17A and 17B are diagrams for explaining a configuration example of an integrated circuit. [Figure 18] 18A and 18B are diagrams for explaining an application example of an integrated circuit. [Figure 19] 19A and 19B are diagrams for explaining an application example of an integrated circuit. [Figure 20] 20A, 20B and 20C are diagrams for explaining an application example of an integrated circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the embodiment and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0027] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0028] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0029] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0030] Furthermore, when the same reference symbol is used for multiple elements, particularly when it is necessary to distinguish between them, identification symbols such as “_1”, “_2”, "[n]”, "[m,n]”, etc. may be added to the reference symbol. For example, the second wiring GL is written as wiring GL[2].

[0031] (Embodiment 1) The structure and the like of a semiconductor device according to one embodiment of the present invention will be described.

[0032] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, logic circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0033] FIG. 1A is a diagram illustrating a semiconductor device 100 according to one embodiment of the present invention.

[0034] 1A includes a logic unit 101 that performs logical operations. The logic unit 101 includes at least a p-channel transistor 103 and an n-channel transistor 104. In the logic unit 101, the logical operations performed are uniquely determined by the numbers of the p-channel transistors 103 and the n-channel transistors 104 and the connection configuration thereof. The logical operations performed in the logic unit 101 can obtain one output value for multiple input values.

[0035] The input value means a logical value represented by the potential Vin of an input signal input to the semiconductor device 100. The output value means a logical value represented by the potential Vout of an output signal output from the semiconductor device 100.

[0036] The p-channel transistor 103 and the n-channel transistor 104 are connected in series between a power supply line to which a high-level potential VDD is applied and a power supply line to which a low-level potential VSS is applied. The state in which the transistors are connected in series means, for example, a state in which only one of the source or drain of a transistor is connected to only one of the source or drain of another transistor.

[0037] 1A, one of the source or drain of the p-channel transistor 103 is connected to a power supply line to which a potential VDD is applied. One of the source or drain of the n-channel transistor 104 is connected to a power supply line to which a potential VSS is applied. The other of the source or drain of the p-channel transistor 103 is connected to the other of the source or drain of the n-channel transistor 104. The potential of a node to which the other of the source or drain of the p-channel transistor 103 and the other of the source or drain of the n-channel transistor 104 are connected is output as a potential Vout of an output signal.

[0038] In one embodiment of the present invention, the transistor constituting the logic portion 101 includes a backgate electrode for controlling a threshold voltage in addition to a gate electrode.

[0039] The p-channel transistor 103 has a gate electrode and a back gate electrode. The n-channel transistor 104 has a gate electrode and a back gate electrode. The threshold voltage of each transistor is controlled by the potential of the back gate electrode, more specifically, the potential difference between the source and the back gate electrode.

[0040] The semiconductor layer of the p-channel transistor 103 is silicon. That is, the p-channel transistor 103 is a Si transistor. The p-channel transistor 103 is a transistor formed using an SOI (Silicon On Insulator) substrate having an insulating layer (also called a BOX (Burried oxide) layer) formed by buried oxidation in a silicon substrate and a thin film of single crystal silicon on the insulating layer. Note that, although an example of an SOI substrate manufactured by a SIMOX (Separated by Implanted Oxygen) method will be described in this specification, an SOI substrate manufactured by a Smart Cut method may also be used.

[0041] A region (well region) to which an impurity element that imparts conductivity is added can be provided on the silicon substrate in the region where the p-channel transistor 103 is provided. The well region can function as a back gate electrode by independently changing the potential of the well region. This allows the threshold voltage of the Si transistor to be controlled. In particular, by applying a positive potential to the well region, the threshold voltage of the Si transistor can be increased and the off-current can be reduced. Therefore, by applying a positive potential to the well region, the drain current when the potential applied to the gate electrode of the Si transistor is 0 V can be reduced. In addition, since it is not necessary to add an impurity element to the channel formation region for the purpose of controlling the threshold voltage, the variation in the threshold voltage can be reduced and the power supply voltage can be lowered.

[0042] A semiconductor layer included in the n-channel transistor 104 is an oxide semiconductor (metal oxide). That is, the n-channel transistor 104 is an OS transistor.

[0043] Since the band gap of metal oxide is 2.5 eV or more, OS transistors have extremely small off-state current. For example, the off-state current per 1 μm of channel width is 1×10 at room temperature (25°C) with a source-drain voltage of 3.5 V. -20 Less than A, 1×10 -22 Less than A or 1×10 -24 That is, the on / off current ratio of the drain current can be set to 20 to 150 orders of magnitude.

[0044] High-density integrated semiconductor devices may generate heat due to the operation of the circuits. This heat increases the temperature of the transistor, which may change the characteristics of the transistor, causing a change in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so that the field-effect mobility is less likely to change due to temperature changes and the operating frequency is less likely to decrease. Furthermore, OS transistors tend to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage, even when the temperature rises. Therefore, the use of OS transistors allows stable operation in high temperature environments.

[0045] In the semiconductor device 100, the n-channel transistor 104 formed of an OS transistor can be stacked on the p-channel transistor 103, which is a Si transistor, so that the n-channel transistor and the p-channel transistor can be arranged without increasing the circuit area. In one embodiment of the present invention, the p-channel transistor, which is a Si transistor, is provided on a well region that functions as a back gate, so that the on-current can be reduced by controlling the threshold voltage. Therefore, compared with the Si transistor, the OS transistor does not need to be designed to have a large channel length (L) or a channel width (W) to match the on-current of the Si transistor. As a result, the transistor size in the semiconductor device can be reduced.

[0046] The p-channel transistor 103 has a gate electrode to which a potential Vin1 of an input signal is applied. The n-channel transistor 104 has a gate electrode to which a potential Vin2 of an input signal is applied. Note that the potentials Vin1 and Vin2 of the two input signals may be the same or may have a predetermined potential difference. However, the logical value indicated by the potential Vin1 and the logical value indicated by the potential Vin2 are the same.

[0047] The operation of the semiconductor device 100 will be described below by taking as an example a case where the potentials Vin1 and Vin2 are the same.

[0048] 1A, the p-channel transistor 103 performs switching in accordance with a gate voltage Vgs corresponding to the potential difference between the gate electrode and the source electrode. The gate voltage Vgs of the p-channel transistor 103 is the potential difference between the potential Vin1 of the input signal applied to the gate electrode and the potential VDD. Therefore, if the threshold voltage of the p-channel transistor 103 is Vthp and Vthp<0, the p-channel transistor 103 is turned on when Vin1-VDD≦-|Vthp| and turned off when Vin1-VDD>-|Vthp|.

[0049] The n-channel transistor 104 also switches in accordance with a gate voltage Vgs corresponding to the potential difference between the gate electrode and the source electrode. The gate voltage Vgs of the n-channel transistor 104 is the potential difference between the potential Vin2 of the input signal applied to the gate electrode and the potential VSS. Assuming that the threshold voltage of the n-channel transistor 104 is Vthn and Vthn>0, the n-channel transistor 104 is turned on when Vin2-VSS≧|Vthn| and turned off when Vin2-VSS<|Vthn|.

[0050] In order to keep the through current between the power supply lines low, it is desirable to operate the p-channel transistor 103 and the n-channel transistor 104 so that when one is on, the other is off. That is, the values ​​of the threshold voltages Vthp and Vthn are controlled so as to prevent both the p-channel transistor 103 and the n-channel transistor 104 from being on at the same time.

[0051] If Vin1=Vin2=Vin, the range of potential Vin where both the p-channel transistor 103 and the n-channel transistor 104 are turned on is VSS+|Vthn|≦Vin≦VDD-|Vthp|. Therefore, in order to keep the through current low, it is desirable to increase the absolute value of the threshold voltage Vthp and increase the absolute value of the threshold voltage Vthn, thereby narrowing the range of potential Vin.

[0052] The absolute value of the threshold voltage Vthp tends to increase as the potential Vctl_1 applied to the back gate electrode increases. Conversely, the absolute value of the threshold voltage Vthp tends to decrease as the potential Vctl_1 applied to the back gate electrode decreases. Therefore, in one embodiment of the present invention, the potential Vctl_1 is made higher than the potential VSS to increase the absolute value of the threshold voltage Vthp, thereby suppressing the through current.

[0053] Moreover, the absolute value of the threshold voltage Vthn tends to increase as the potential Vctl_2 applied to the back gate electrode decreases. Conversely, the absolute value of the threshold voltage Vthn tends to decrease as the potential Vctl_2 applied to the back gate electrode increases. Therefore, in one embodiment of the present invention, the potential Vctl_2 is set lower than the potential VSS to increase the absolute value of the threshold voltage Vthn, thereby suppressing the through current.

[0054] If the absolute value of the threshold voltage Vthp is further increased, it is possible to prevent both the p-channel transistor 103 and the n-channel transistor 104 from being turned on regardless of the value of the potential Vin, and therefore the through current can be further suppressed. However, if the absolute value of the threshold voltage Vthp is too large, a period in which both the p-channel transistor 103 and the n-channel transistor 104 are turned off appears depending on the value of the potential Vin. In the period in which both the p-channel transistor 103 and the n-channel transistor 104 are turned off, the potential Vout of the output signal becomes unstable. In order to prevent this unstable state, it is desirable to control the value of the threshold voltage Vthp so that VDD-|Vthp| does not fall below VSS+|Vthn|.

[0055] In the case of the n-channel transistor 104, the absolute value of the threshold voltage Vthn tends to decrease as the potential applied to the backgate electrode increases. Conversely, the absolute value of the threshold voltage Vthn tends to increase as the potential applied to the backgate electrode decreases. Therefore, in the case of the n-channel transistor 104, the shoot-through current is suppressed by making the potential of the backgate electrode lower than the potential VSS and increasing the absolute value of the threshold voltage Vthn.

[0056] Then, similarly to the case of the threshold voltage Vthp, if the absolute value of the threshold voltage Vthn is too large, a period appears in which both the p-channel transistor 103 and the n-channel transistor 104 are turned off depending on the value of the potential Vin. Therefore, in order to prevent the potential Vout of the output signal from becoming unstable, it is desirable to control the value of the threshold voltage Vthn so that VSS+|Vthn| does not exceed VDD-|Vthp|.

[0057] Next, a description will be given of structures of the p-channel transistor 103 and the n-channel transistor 104 used in the semiconductor device 100. An example of a cross-sectional structure of the p-channel transistor 103 and the n-channel transistor 104 is shown in FIG.

[0058] 1B, a p-channel transistor 103 and an n-channel transistor 104 that constitute a logic unit 101 are formed on a silicon substrate 300. Note that for details of each component, the description of the second embodiment described later can be used.

[0059] An insulating layer 302 and a well region 306 are formed on the silicon substrate 300. The insulating layer 302 functions as an element isolation layer. The well region 306 functions as a back gate electrode. On the well region 306, impurity regions 310A and 310B, which are semiconductor layers, and a channel formation region 310C are provided via an insulating layer 308, which is a BOX layer. Also, on the well region 306, an impurity region 312 and a conductive layer 322C for applying a potential Vctl_1 to the well region 306 are formed. On the channel formation region 310C, an insulating layer 314, a conductive layer 316, and a conductive layer 322D are formed. The conductive layer 316 and the conductive layer 322D function as a gate electrode to which a potential Vin1 is applied. The insulating layer 314 functions as a gate insulating film. On the impurity regions 310A and 310B, an insulating layer 318, a conductive layer 322A, and a conductive layer 322B are formed. The insulating layer 318 functions as a sidewall insulating layer. An insulating layer 324 functioning as an interlayer insulating film and a conductive layer 326 functioning as an electrode for applying a potential Vctl_1 to the p-channel transistor 103 and the well region are formed on the p-channel transistor 103. An insulating layer 328, a conductive layer 330, an insulating layer 332, and a conductive layer 334 are formed on the insulating layer 324 and the conductive layer 326.

[0060] An insulating layer 336 and a conductive layer 338 are formed on the insulating layer 332 and the conductive layer 334. The conductive layer 338 functions as a back gate electrode of an n-channel transistor to which a potential Vctl_2 is applied. An insulating layer 340 is formed on the insulating layer 336 and the conductive layer 338. A semiconductor layer 342, which is an oxide semiconductor, is formed on the insulating layer 340. Conductive layers 344A and 344B, an insulating layer 350, and a conductive layer 352 are formed on the semiconductor layer 342. The conductive layer 344A and the conductive layer 344B function as a source electrode or a drain electrode of the n-channel transistor 104. The insulating layer 350 functions as a gate insulating film of the n-channel transistor 104. The conductive layer 352 functions as a gate electrode of the n-channel transistor 104. An insulating layer 346, an insulating layer 348, an insulating layer 354, and an insulating layer 356 are formed on the n-channel transistor 104. A conductive layer 358 is formed on the insulating layer 336, the insulating layer 340, the insulating layer 346, the insulating layer 348, the insulating layer 354, and the insulating layer 356. The conductive layer 358 functions as an electrode for applying a potential VDD or a potential VSS, or an electrode for extracting a potential Vout. An insulating layer 360 and a conductive layer 362 are formed on the insulating layer 356 and the conductive layer 358.

[0061] In the semiconductor device according to one embodiment of the present invention, the threshold voltages of the p-channel transistor 103 and the n-channel transistor 104 constituting a complementary logic circuit can be individually controlled by the potential applied to the back gate electrode, so that when the potential of the gate electrodes of the p-channel transistor 103 and the n-channel transistor 104 is switched between a high level and a low level, one of the transistors can be turned off, or the period during which both transistors are turned on can be shortened. Thus, it is possible to reduce a through current flowing through the channel formation regions of the p-channel transistor 103 and the n-channel transistor 104. Furthermore, in the semiconductor device according to one embodiment of the present invention, by using an OS transistor as the n-channel transistor 104, it is possible to significantly reduce an off current flowing when both the p-channel transistor 103 and the n-channel transistor 104 are off.

[0062] Therefore, in the semiconductor device according to one embodiment of the present invention, the shoot-through current can be reduced, and thus power consumption can be reduced. Alternatively, in the semiconductor device according to one embodiment of the present invention, the shoot-through current can be reduced, and thus heat generation can be suppressed, and thus reliability of the semiconductor device can be improved.

[0063] FIG. 2A is a block diagram for explaining the potentials Vctl_1 and Vctl_2 applied to the semiconductor device 100. As shown in FIG.

[0064] 2A, transistor region 105 represents a region having a p-channel transistor 103. In Fig. 2A, transistor region 106 represents a region having an n-channel transistor 104. The semiconductor device 100 may have a configuration including a plurality of transistor regions 105 and a plurality of transistor regions 106.

[0065] 2A, the control unit 108 outputs potentials Vctl_1 and Vctl_2 to be applied to the p-channel transistor 103 and the n-channel transistor 104. The control unit 108 can individually control the potentials Vctl_1 and Vctl_2 in accordance with the control of the calculation unit 110 to control the threshold voltages of the p-channel transistor 103 and the n-channel transistor 104. When there are multiple transistor regions 105 and multiple transistor regions 106, a configuration may be adopted in which multiple potentials equivalent to the potentials Vctl_1 and Vctl_2 are output.

[0066] 2A, the calculation unit 110 outputs a signal for controlling the control unit 108 in response to data from an external sensor, such as a temperature sensor. The control unit 108 then outputs potentials Vctl_1 and Vctl_2 in response to the temperature. The temperature sensor can acquire data by monitoring the temperature of the surface of the semiconductor device 100, for example.

[0067] 2A, by separately generating and outputting potentials Vctl_1 and Vctl_2 for controlling the threshold voltages of the p-channel transistor 103 and the n-channel transistor 104, it is possible to perform control according to the difference in electrical characteristics caused by temperature between the p-channel transistor 103 and the n-channel transistor 104, that is, the Si transistor and the OS transistor. Therefore, the semiconductor device 100 can be controlled to operate with excellent reliability.

[0068] Fig. 2B is a schematic diagram showing a state in which the transistor region 105 and the transistor region 106 of the semiconductor device 100 described in Fig. 2A are in different layers as shown in Fig. 1B. As shown in Fig. 2B, the transistor region 105 has a p-channel transistor 103 having a channel formation region 310C made of single crystal silicon. The transistor region 106 has an n-channel transistor 104 having a semiconductor layer 342 made of an oxide semiconductor.

[0069] 2B, the n-channel transistor and the p-channel transistor are formed in different layers, which makes it easier to control the potential of the backgate electrode compared to the case where a complementary logic circuit is formed only with Si transistors. In addition, in one embodiment of the present invention, since the transistor region 105 is formed of a p-channel transistor, the manufacturing process can be simplified compared to the case where an n-channel transistor and a p-channel transistor are formed as Si transistors and a well region functioning as a backgate electrode is further provided.

[0070] Fig. 3A is a diagram for explaining a modified example of the logic portion 101 in Fig. 1A. The logic portion 101A shown in Fig. 3A has an n-channel transistor 104 without a backgate electrode.

[0071] 3B is a diagram for explaining a modification of the logic portion 101 in FIG. 1A. The logic portion 101B shown in FIG. 3B includes a transistor 111 and a capacitor 112 connected to a backgate electrode of a p-channel transistor 103. The transistor 111 is an OS transistor, and by turning off the transistor 111 by a control signal SW, a node N BG The potential of the p-channel transistor 103 can be held by the transistor 111 having an extremely low off-state current. With the above structure, the potential of the backgate electrode can be held and the threshold voltage of the p-channel transistor 103 can be set to a desired value without constantly supplying a potential to the backgate electrode.

[0072] FIG. 4A is a diagram illustrating a semiconductor device 100 including a logic unit 101C that functions as an inverter circuit, as an example of a configuration of a logic circuit applicable to FIG. 1A.

[0073] 4A, a gate electrode of the p-channel transistor 103 is connected to a wiring that applies a potential Vin. A gate electrode of the n-channel transistor 104 is connected to a wiring that applies a potential Vin. A backgate electrode of the p-channel transistor 103 is connected to a wiring that applies a potential Vctl_1. A backgate electrode of the n-channel transistor 104 is connected to a wiring that applies a potential Vctl_2.

[0074] 4A, one of the source or drain of the p-channel transistor 103 is connected to a power supply line to which a potential VDD is applied. One of the source or drain of the n-channel transistor 104 is connected to a power supply line to which a potential VSS is applied. The other of the source or drain of the p-channel transistor 103 is connected to the other of the source or drain of the n-channel transistor 104. The potential of a node to which the other of the source or drain of the p-channel transistor 103 and the other of the source or drain of the n-channel transistor 104 are connected is output as the potential Vout of the output signal.

[0075] FIG. 4B shows an ideal timing chart of the inverter circuit shown in FIG. 4A. FIG. 4B also shows the magnitude of the potentials Vctl_1 and Vctl_2 relative to the potentials VDD and VSS. The potential out is a potential obtained by inverting the logic of the potential Vin. In order to keep the through current between the power supply lines low, the values ​​of the threshold voltages Vthp and Vthn are controlled to prevent both the p-channel transistor 103 and the n-channel transistor 104 from being turned on. Specifically, by making the potential Vctl_1 higher than the potential VDD and making the potential Vctl_2 lower than the potential VSS, the absolute value of the threshold voltage Vthn is reduced, and the through current can be kept low.

[0076] 5 shows an example of a timing chart of the potential Vin from when the potential Vin completely transitions from a low level to a high level until when the potential Vin transitions from a high level to a low level. In addition, FIG 5 also shows an example of a time change of the through current Isc flowing through the p-channel transistor 103 and the n-channel transistor 104. Note that the time axis of the timing chart of the potential Vin and the time change of the through current Isc are the same.

[0077] 5, the potential Vin changes from a low-level potential VSS to a high-level potential VDD over a predetermined time period, and also changes from a high-level potential VDD to a low-level potential VSS over a predetermined time period.

[0078] 5, in a period t during which the potential Vin is within the range of VSS+|Vthn|≦Vin≦VDD-|Vthp|, the p-channel transistor 103 and the n-channel transistor 104 are both turned on. In FIG. 5, the absolute value of the threshold voltage Vthp is large, and the absolute value of the threshold voltage Vthn is large, so that the period t during which the potential Vin is within the range of VSS+|Vthn|≦Vin≦VDD-|Vthp| can be shortened. In other words, the period t during which both the p-channel transistor 103 and the n-channel transistor 104 are on can be made extremely short.

[0079] FIG. 6A is a diagram for explaining a semiconductor device 200 including a logic unit 201 that functions as a NAND circuit, as an example of a configuration of a logic circuit applicable to FIG. 1A.

[0080] A semiconductor device 200 shown in Fig. 6A has a logic unit 201 that performs logical operations. The logic unit 201 has a p-channel transistor 204, a p-channel transistor 205, an n-channel transistor 206, and an n-channel transistor 207. In Fig. 6A, each transistor has a backgate electrode for controlling a threshold voltage in addition to a normal gate electrode.

[0081] A potential Vctl_1 is applied to the backgate electrodes of the p-channel transistor 204 and the p-channel transistor 205. A potential Vctl_2 is applied to the backgate electrodes of the n-channel transistor 206 and the n-channel transistor 207.

[0082] Fig. 6B shows an example of an ideal timing chart of the potentials VinA and VinB of the input signals and the potential Vout of the output signal in the semiconductor device 200 shown in Fig. 6A. Fig. 6B also shows the magnitude of the potentials Vctl_1 and Vctl_2 relative to the potentials VDD and VSS.

[0083] 6B shows that the potentials VinA and VinB change instantaneously. However, in reality, it takes some time for the potentials VinA and VinB to completely change from a low level to a high level, or from a high level to a low level. During this potential change period, a through current is likely to flow.

[0084] In one embodiment of the present invention, assuming that the threshold voltage of the p-channel transistor 204 is VthpA and the threshold voltage of the n-channel transistor 206 is VthnA, the potential Vctl_1 is increased, the potential Vctl_2 is decreased, and the absolute value of the threshold voltage VthpA is increased, thereby shortening the period during which the potential VinA is within the range of VSS+|VthnA|≦VinA≦VDD−|VthpA|. In other words, the period during which both the p-channel transistor 204 and the n-channel transistor 206 are on can be shortened. Thus, the through current generated during the above period can be reduced.

[0085] Therefore, in the semiconductor device according to one embodiment of the present invention, the shoot-through current can be reduced, and thus power consumption can be reduced. Alternatively, in the semiconductor device according to one embodiment of the present invention, the shoot-through current can be reduced, and thus heat generation can be suppressed, and thus reliability of the semiconductor device can be improved.

[0086] FIG. 7A is a diagram for explaining a semiconductor device 210 including a logic unit 201 that functions as a NOR circuit, as an example of a configuration of a logic circuit applicable to FIG. 1A.

[0087] The semiconductor device 200 shown in Fig. 7A has a logic unit 211 that performs logical operations. The logic unit 211 has a p-channel transistor 214, a p-channel transistor 215, an n-channel transistor 216, and an n-channel transistor 217. In Fig. 7A, each transistor has a backgate electrode for controlling a threshold voltage in addition to a normal gate electrode.

[0088] A potential Vctl_1 is applied to the backgate electrodes of the p-channel transistor 214 and the p-channel transistor 215. A potential Vctl_2 is applied to the backgate electrodes of the n-channel transistor 216 and the n-channel transistor 217.

[0089] Fig. 7B shows an example of an ideal timing chart of the potentials VinA and VinB of the input signals and the potential Vout of the output signal in the semiconductor device 210 shown in Fig. 7A. Fig. 7B also shows the magnitude of the potentials Vctl_1 and Vctl_2 relative to the potentials VDD and VSS.

[0090] 7B shows that the potentials VinA and VinB change instantaneously. However, in reality, it takes some time for the potentials VinA and VinB to completely change from a low level to a high level, or from a high level to a low level. During this potential change period, a through current is likely to flow.

[0091] In one embodiment of the present invention, assuming that the threshold voltage of the p-channel transistor 214 is VthpA and the threshold voltage of the n-channel transistor 216 is VthnA, the potential Vctl_1 is increased, the potential Vctl_2 is decreased, and the absolute value of the threshold voltage VthpA is increased, thereby making it possible to shorten the period during which the potential VinA is within the range of VSS+|VthnA|≦VinA≦VDD−|VthpA|. In other words, the period during which both the p-channel transistor 214 and the n-channel transistor 216 are on can be shortened. Thus, the through current generated during the above period can be reduced.

[0092] Therefore, in the semiconductor device according to one embodiment of the present invention, the shoot-through current can be reduced, and thus power consumption can be reduced. Alternatively, in the semiconductor device according to one embodiment of the present invention, the shoot-through current can be reduced, and thus heat generation can be suppressed, and thus reliability of the semiconductor device can be improved.

[0093] FIG. 8 is a diagram illustrating a semiconductor device 220 that functions as a static RAM (SRAM) using logic units 201A and 201B that function as the inverter circuits shown in FIG. 4A.

[0094] The semiconductor device 220 shown in FIG. 8 includes a logic portion 201A, a logic portion 201B, a transistor 221, and a transistor 222. The logic portion 201A and the logic portion 201B each have the same configuration as the logic portion 101C shown in FIG. 4A. The transistor 221 and the transistor 222 function as switching elements whose conduction state is controlled by controlling the word line WL. The transistor 221 controls the conduction state between the bit line BL and the logic portion 201A. The transistor 222 controls the conduction state between the inverted bit line BLB and the input terminal of the logic portion 201B.

[0095] 8 illustrates a configuration in which the transistors 221 and 222 are n-channel transistors and a potential Vctl_3 that is different from the potential Vctl_2 is applied to the backgate electrodes. With this configuration, the off-state current of the transistors 221 and 222 can be reduced.

[0096] In the semiconductor device according to one embodiment of the present invention, the shoot-through current can be reduced, and thus the power consumption can be reduced. Alternatively, in the semiconductor device according to one embodiment of the present invention, the shoot-through current can be reduced, and thus the heat generation can be suppressed, and thus the reliability of the semiconductor device can be improved.

[0097] (Embodiment 2) In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described, which includes a p-channel Si transistor provided in an SOI substrate and an n-channel OS transistor provided over a layer including the Si transistor.

[0098] An SOI substrate having a silicon substrate 300, an insulating layer 301 formed on the silicon substrate 300, and a semiconductor layer 303 formed on the insulating layer 301 is prepared (FIG. 9A). The silicon substrate 300 is preferably a substrate made of p-type or n-type single crystal silicon. The insulating layer 301 is, for example, a silicon oxide layer having a film thickness of 10 nm to 50 nm. The insulating layer 301 is an insulating layer formed by buried oxidation. The semiconductor layer 303 is single crystal silicon provided by a SIMOX method, a smart cut method, or the like.

[0099] Next, in order to perform element isolation, openings are formed in the insulating layer 301 and the semiconductor layer 303 so as to reach the inside of the silicon substrate 300, and the openings are then filled with a single-layer or multi-layer insulating layer 302 made of silicon oxide and silicon nitride (FIG. 9B). The insulating layer in areas other than the opened areas is selectively removed by a CMP (Chemical Mechanical Polishing) method or the like, thereby forming island-shaped insulating layer 302, semiconductor layer 310, and insulating layer 308 as shown in FIG. 9B.

[0100] Next, a part of the semiconductor layer 310 and the insulating layer 308 is removed (region 305 in FIG. 9C) to expose a part of the silicon substrate 300. Then, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the silicon substrate to form an n-type well region 306 (FIG. 9C). The well region 306 may be formed before removing the semiconductor layer 310 and the insulating layer 308 in region 305. The well region 306 functions as a backgate electrode of the p-channel transistor 103.

[0101] Next, an insulating layer 314 is formed on the semiconductor layer 310. A conductive layer 316 is formed on the insulating layer 314 (FIG. 10A). The insulating layer 314 functions as a gate insulating film. The insulating layer 314 is, for example, a silicon oxide layer having a thickness of 1 nm to 10 nm. The conductive layer 316 functions as a gate electrode of the p-channel transistor 103. The conductive layer 316 is, for example, polycrystalline silicon having a thickness of 40 nm to 200 nm.

[0102] Next, an impurity that imparts p-type conductivity, such as boron (B), is introduced into the semiconductor layer 310 to form impurity region 310A and impurity region 310B (FIG. 10B). The semiconductor layer directly below insulating layer 314 and conductive layer 316 is not doped with impurities and serves as channel formation region 310C. Impurities are also introduced into the silicon substrate exposed in region 305 in FIG. 9C to form impurity region 312 (FIG. 10B).

[0103] Next, an insulating layer 318 is formed on the side surfaces of the insulating layer 314 and the conductive layer 316. The insulating layer 318 can be formed by forming an insulating film to be the insulating layer 318 and then performing anisotropic dry etching on the insulating film. The insulating layer 318 functions as a sidewall insulating layer (sidewall spacer). The insulating layer 318 can be formed of silicon oxide, silicon nitride, or a stack of silicon oxide and silicon nitride. Then, conductive layers 322A to 322D are selectively formed on the upper surfaces of the conductive layer 316, the impurity region 310A, the impurity region 310B, and the impurity region 312 (FIG. 10C). The conductive layers 322A to 322D are, for example, metal silicide layers such as cobalt silicide, nickel silicide, or nickel platinum silicide. Through the above steps, a p-channel transistor 103 can be formed in a fully-depleted silicon-on-insulator (FD-SOI), which is a type of fully-depleted silicon-on-insulator (SOI), and which has a well region that functions as a back gate electrode.

[0104] Next, an insulating layer 324, which is an interlayer insulating film, is formed, a plurality of openings are provided in the insulating layer 324, and a conductive layer 326, which functions as a plug electrode, is formed in the openings. Then, an insulating layer 328, which is an interlayer insulating film, is formed on the insulating layer 324 with the conductive layer 326 buried in. After a wiring groove is provided in the insulating layer 328, a conductive layer 330, which functions as a wiring, is formed in the wiring groove (FIG. 11A).

[0105] Next, an insulating layer 332, which is an interlayer insulating film, is formed, a plurality of openings are provided in the insulating layer 332, and a conductive layer 334, which functions as a plug electrode or wiring, is formed in the openings. The layer having the interlayer insulating film or wiring may be configured by stacking a plurality of layers. In addition, an insulating layer 336, which is an interlayer insulating film, is formed on the insulating layer 332 and the conductive layer 334. After providing a wiring groove in the insulating layer 336, a conductive layer 338, which functions as a back gate of an n-channel transistor, is formed in the wiring groove (FIG. 11B).

[0106] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used for the insulating layers 324, 328, 332, and 336.

[0107] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0108] The insulating layer 332 is preferably formed using a film having a barrier property that prevents hydrogen or impurities from diffusing from the silicon substrate 300 or the p-channel transistor 103 or the like to a region where the n-channel transistor 104 is provided.

[0109] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the n-channel transistor 104, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the p-channel transistor 103 and the n-channel transistor 104. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0110] As the material of the conductive layer 326, the conductive layer 330, the conductive layer 334, and the conductive layer 338, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to form the conductive layer using a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0111] Next, an insulating layer 340 is formed on the insulating layer 336 and the conductive layer 338. After a semiconductor layer 342 and a conductive layer 344 are formed in an island shape on the insulating layer 340, an insulating layer 346 and an insulating layer 348 are formed (FIG. 12A).

[0112] The insulating layer 340 is preferably made of an insulator containing more oxygen than the amount of oxygen that satisfies the stoichiometric composition. Such oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating may be referred to as "excess oxygen." In other words, the insulating layer 340 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the semiconductor layer 342, oxygen vacancies (V O In addition, when hydrogen enters the oxygen vacancy in the semiconductor layer 342, the defect (hereinafter, V O H.) may function as a donor and generate an electron that serves as a carrier. Some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate an electron that serves as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, the V in the semiconductor layer 342 OIt is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0113] Specifically, it is preferable to use an oxide material from which part of the oxygen is released by heating as an insulator having an excess oxygen region. al D The amount of oxygen released was 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more than 3.0×10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0114] In addition, the insulator having the excess oxygen region may be brought into contact with the semiconductor layer 342 and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the semiconductor layer 342 can be removed. For example, a reaction occurs in the semiconductor layer 342 that breaks the bond of VoH, in other words, "V O The reaction "H → Vo + H" occurs, and dehydrogenation can be achieved. Some of the hydrogen generated at this time combines with oxygen to form H 2As O, hydrogen may be removed from the semiconductor layer 342 or from an insulator near the semiconductor layer 342. Also, some of the hydrogen may be gettered into the conductive layer 344.

[0115] Moreover, the microwave treatment is preferably carried out using, for example, an apparatus having a power source for generating high density plasma, or an apparatus having a power source for applying RF to the substrate side. For example, high density oxygen radicals can be generated by using a gas containing oxygen and high density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high density plasma can be efficiently introduced into the semiconductor layer 342 or an insulator in the vicinity of the semiconductor layer 342. The microwave treatment may be carried out under a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. For example, oxygen and argon are used as gases to be introduced into the apparatus for carrying out the microwave treatment, with the oxygen flow ratio (O 2 / (O 2 +Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0116] The semiconductor layer 342 can be a semiconductor device with excellent reliability by having a structure in which two or more oxide layers having different atomic ratios of metal atoms are stacked. The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an atomic layer deposition (ALD) method.

[0117] Metal oxides applicable to OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is one or more selected from Ti, Ga, Y, Zr, La, Ce, Nd, Sn, and Hf). In particular, metal oxides using Ga as M are preferably used for OS transistors because they can be made into transistors with excellent electrical characteristics such as field-effect mobility by adjusting the ratio of elements. In addition, the oxide containing indium and zinc may contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0118] In order to improve the reliability and electrical characteristics of an OS transistor, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystalline part, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for cloud-aligned composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0119] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0120] CAC-OS has the function of flowing electrons (or holes) that act as carriers, and the function of not flowing electrons that act as carriers. By separating the function of flowing electrons from the function of not flowing electrons, it is possible to maximize both functions. In other words, by using CAC-OS in the channel formation region of an OS transistor, it is possible to achieve both a high on-current and an extremely low off-current.

[0121] Metal oxides have a large band gap, electrons are less likely to be excited, and the effective mass of holes is large, so that OS transistors are less likely to experience avalanche breakdown and the like compared to general Si transistors. Therefore, for example, hot carrier degradation caused by avalanche breakdown can be suppressed. Suppressing hot carrier degradation allows OS transistors to be driven at a high drain voltage.

[0122] As the conductive layer 344, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen and oxygen.

[0123] Although the conductive layer 344 has a single-layer structure, it may have a stacked structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0124] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated with an aluminum film or copper film on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated with an aluminum film or copper film on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0125] The insulating layer 348 is provided to cover the conductive layer 344 and the semiconductor layer 342 and suppresses oxidation of the conductive layer 344 .

[0126] The insulating layer 348 can be made of a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. The insulating layer 348 can also be made of silicon nitride oxide, silicon nitride, or the like.

[0127] In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), for the insulating layer 348. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film, and is therefore preferable because it is less likely to crystallize in a heat treatment in a later process.

[0128] Next, parts of the conductive layer 344, the insulating layer 346, and the insulating layer 348 are removed to form an opening to expose a part of the semiconductor layer 342. The conductive layer 344 on the semiconductor layer 342 is separated by the formation of the opening, and a conductive layer 344A and a conductive layer 344B that function as a source electrode and a drain electrode are formed. Then, an insulating layer 350 and a conductive layer 352 are formed in the opening.

[0129] The insulating layer 350 functions as a gate insulating film. Like the insulating layer 340, the insulating layer 350 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0130] Furthermore, in order to efficiently supply excess oxygen contained in the insulating layer 350 to the semiconductor layer 342, a metal oxide may be provided between the insulating layer 350 and the conductive layer 352. By providing the metal oxide, the diffusion of excess oxygen from the insulating layer 350 to the conductive layer 352 can be suppressed. In other words, a decrease in the amount of excess oxygen supplied to the semiconductor layer 342 can be suppressed.

[0131] The insulating layer 350 may have a laminated structure. As transistors become finer and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by making the insulator that functions as the gate insulating film a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0132] The conductive layer 352 functioning as a gate electrode may have a single-layer structure or a stacked structure of two or more layers.

[0133] The conductive layer 352 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductive layer 352 also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductive layer 352 may have a layered structure, and may have a layered structure with a conductive material having a function of suppressing diffusion of impurities, such as tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0134] Like the insulating layer 340, the insulating layer 348 preferably has a reduced concentration of impurities such as water or hydrogen.

[0135] Through the above steps, an n-channel transistor 104 can be formed (FIG. 12B).

[0136] Next, insulating layers 354 and 356 are formed over the n-channel transistor 104 and the insulating layer 348 (FIG. 13A).

[0137] A substance having a barrier property against oxygen and hydrogen is preferably used for the insulating layer 354. For example, the insulating layer 354 can be formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0138] Parasitic capacitance occurring between wirings can be reduced by using a material with a relatively low dielectric constant for the insulating layer 356. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulating layer 356.

[0139] Next, insulating layer 336, insulating layer 340, insulating layer 346, insulating layer 348, insulating layer 354, and insulating layer 356 are partially removed to form an opening so that conductive layer 334, conductive layer 344A, and conductive layer 344 are partially exposed. A conductive layer 358 functioning as a plug electrode is formed in the opening. Then, insulating layer 360, which is an interlayer insulating film, is formed on insulating layer 356 with conductive layer 358 embedded therein. A wiring groove is provided in insulating layer 360, and then conductive layer 362 functioning as wiring is formed in the wiring groove (FIG. 13B).

[0140] The conductive layer 358 can be provided using a material similar to that of the conductive layer 326. The conductive layer 362 can be provided using a material similar to that of the conductive layer 330. The conductive layer 362 is a wiring that applies a potential VDD, a potential VSS, or the like, or is electrically connected to the wiring.

[0141] As described above, one embodiment of the present invention can provide a semiconductor device that is miniaturized by stacking a Si transistor that is a p-channel transistor and an OS transistor that is an n-channel transistor. Alternatively, one embodiment of the present invention can provide a semiconductor device with low power consumption by including a backgate electrode for controlling the threshold voltage of both the n-channel transistor and the p-channel transistor. Alternatively, one embodiment of the present invention can provide a semiconductor device with a novel structure.

[0142] (Embodiment 3)

[0143] In this embodiment, a configuration including a CPU and an accelerator will be described as an application example of the semiconductor device 100 described in the above embodiment.

[0144] Fig. 14 is a diagram for explaining a semiconductor device 100P including a CPU and an accelerator. In the semiconductor device 100P in Fig. 14, a CPU 510, an accelerator 520, and a bus 530 are illustrated as an example. The CPU 510 has a CPU core 511 and a backup circuit 512. The accelerator 520 has an arithmetic processing unit 521 and a memory unit 522. The arithmetic processing unit 521 has an arithmetic circuit 523. The memory unit 522 has a memory circuit 524. The memory unit 522 may be called a device memory or a shared memory.

[0145] CPU 510 has a function of performing general-purpose processing such as executing an operating system, controlling data, and executing various calculations and programs. CPU 510 has CPU core 511. CPU core 511 corresponds to one or more CPU cores. CPU 510 also has backup circuit 512 that can hold data in CPU core 511 even if the supply of power supply voltage is stopped. The supply of power supply voltage can be controlled by electrically disconnecting it from the power supply domain (power domain) using a power switch or the like. The power supply voltage is sometimes called a drive voltage. A memory having an OS transistor is suitable as backup circuit 512.

[0146] The backup circuit 512, which is made up of OS transistors, can be stacked with the CPU core 511, which can be made up of transistors having silicon in their channel formation regions (Si transistors). Since the area of ​​the backup circuit 512 is smaller than the area of ​​the CPU core 511, the backup circuit 512 can be arranged on the CPU core without increasing the circuit area. The backup circuit 512 has a function of retaining data in a register of the CPU core 511. The backup circuit 512 is also called a data retention circuit.

[0147] The accelerator 520 has a function of executing a program (also called a kernel or a kernel program) called from the host program. The accelerator 520 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0148] The memory unit 522 has a function of storing data to be processed by the accelerator 520. Specifically, it can store weight data used in parallel processing of product-sum operations of a neural network. The memory circuit 524 of the memory unit 522 has a function of holding binary data, that is, 1-bit data. Note that the data is not limited to binary data, and ternary or more value data is also possible.

[0149] The memory circuit 524 is preferably a memory having an OS transistor (hereinafter also referred to as an OS memory). The OS memory has a function of holding a charge according to a voltage value by making the OS transistor non-conductive. The accelerator 520 can hold data even when the supply of power supply voltage is stopped by having the memory circuit 524, which is an OS memory. This enables power gating of the accelerator 520, and allows a significant reduction in power consumption.

[0150] The memory circuit 524 formed of OS transistors can be stacked with the arithmetic circuit 523 which can be formed of Si transistors. Therefore, the arrangement can be achieved without increasing the circuit area.

[0151] The memory circuit 524 preferably has a circuit configuration of NOSRAM. "NOSRAM (registered trademark)" is an abbreviation of "Nonvolatile Oxide Semiconductor RAM". NOSRAM refers to a memory in which the memory cell is a two-transistor type (2T) or three-transistor type (3T) gain cell, and the access transistor is an OS transistor. The current that flows between the source and drain in the off state, that is, the leakage current, is extremely small. NOSRAM can be used as a nonvolatile memory by retaining a charge according to data in the memory circuit using the characteristic of extremely small leakage current. In particular, NOSRAM can read the retained data without destroying it (nondestructive read), so it is suitable for parallel processing of product-sum operations of neural networks, which repeats a large amount of data read operations only.

[0152] The arithmetic processing unit 521 has a function of performing arithmetic processing using digital values. Digital values ​​are not easily affected by noise. Therefore, the accelerator 520 is suitable for performing arithmetic processing that requires highly accurate arithmetic results. The arithmetic processing unit 521 is preferably configured with Si transistors. With this configuration, it can be stacked with OS transistors. 。

[0153] The arithmetic circuit 523 has a function of performing any one of processes such as integer arithmetic, single-precision floating-point arithmetic, double-precision floating-point arithmetic, etc. The arithmetic circuit 523 has a function of repeatedly executing the same process such as a multiply-add operation.

[0154] The arithmetic circuit 523 is configured to provide one arithmetic circuit 523 for each bit line of the memory circuit 524, that is, for each column (column-parallel calculation). This configuration allows parallel arithmetic processing of data for one row (maximum all bit lines) of the memory circuit 524. Compared with the multiply-and-accumulate operation using the CPU 510, the column-parallel calculation is not limited by the data bus size (32 bits, etc.) between the CPU and the memory, so that the degree of parallelism of the calculation can be significantly increased, and the calculation efficiency of a large amount of calculation processing such as learning (deep learning) of deep neural networks, which is an AI technology, and scientific and technological calculations that perform floating-point calculations can be improved. In addition, since the calculation of the data output from the memory circuit 524 can be completed and read out, the power generated by memory access (data transfer between the CPU and memory and calculations by the CPU) can be reduced, and the increase in heat generation and power consumption can be suppressed. Furthermore, by shortening the physical distance between one arithmetic circuit 523 and the memory circuit 524, for example by stacking the circuits, the wiring distance can be shortened, thereby reducing the parasitic capacitance generated in the signal line, and thus reducing power consumption.

[0155] The bus 530 electrically connects the CPU 510 and the accelerator 520. That is, the CPU 510 and the accelerator 520 can transmit data via the bus 530.

[0156] Next, an example of the operation when part of the calculations of a program executed by the CPU 510 is executed by the accelerator 520 will be described.

[0157] FIG. 15 is a diagram for explaining an example of an operation when part of the calculations of a program executed by a CPU is executed by an accelerator.

[0158] The host program is executed by the CPU (step S1).

[0159] When the CPU confirms an instruction to reserve a data area required for performing a calculation using the accelerator in the memory section (step S2), the CPU reserves the data area in the memory section (step S3).

[0160] Next, the CPU transmits input data from the main memory to the memory unit (step S4). The memory unit receives the input data and stores the input data in the area secured in step S3 (step S5).

[0161] When the CPU confirms an instruction to start the kernel program (step S6), the accelerator starts calculation by executing the kernel program (step S7).

[0162] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state in which it performs calculations to a PG state (step S8). The PG state refers to a state in which the supply of power supply voltage to the CPU is stopped. In this case, the CPU is switched from the PG state to a state in which it performs calculations immediately before the accelerator finishes executing the kernel program (step S9). By keeping the CPU in the PG state during the period from step S8 to step S9, it is possible to suppress power consumption and heat generation in the semiconductor device as a whole.

[0163] When the accelerator finishes the execution of the kernel program, the output data is stored in the memory unit (step S10).

[0164] After the execution of the kernel program is completed, if the CPU confirms an instruction to transmit output data stored in the memory unit to the main memory (step S11), the output data is transmitted to the main memory and stored in the main memory (step S12).

[0165] When the CPU confirms an instruction to release the data area secured on the memory unit (step S13), the area secured on the memory unit is released (step S14).

[0166] By repeating the above operations from step S1 to step S14, it is possible to suppress the power consumption and heat generation of the CPU and accelerator, while allowing the accelerator to execute part of the calculations executed by the CPU.

[0167] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0168] (Embodiment 4) In this embodiment, the configuration of an integrated circuit including the configuration of the semiconductor device 100 described in the above embodiment will be described with reference to FIGS.

[0169] FIG. 16 is an example of a block diagram for explaining an example of the configuration of an integrated circuit including the configuration of the semiconductor device 100. As shown in FIG.

[0170] The integrated circuit 390 shown in FIG. 16 has a CPU 410, an accelerator 420, an on-chip memory 431, a DMAC (Direct Memory Access Controller) 441, a power supply circuit 460, a power management unit (PMU) 442, a security circuit 447, a memory controller 443, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) controller 444, a USB (Universal Serial Bus) interface circuit 445, a display interface circuit 446, a bridge circuit 450, an interrupt control circuit 451, an interface circuit 452, a battery control circuit 453, and an ADC (Analog-to-digital converter) / DAC (Digital-to-analog converter) interface circuit 454.

[0171] The CPU 410 includes, for example, a CPU core 411, an instruction cache 412, a data cache 413, and a bus interface circuit 414. The accelerator 420 includes a memory circuit 421, an arithmetic circuit 422, and a drive circuit 423.

[0172] The CPU core 411 has multiple CPU cores. The instruction cache 412 may have a circuit configuration that temporarily stores instructions to be executed by the CPU core 411. The data cache 413 may have a circuit configuration that temporarily stores data to be processed by the CPU core 411 or data obtained by the processing. The bus interface circuit 414 may have a circuit configuration that can transmit and receive signals such as data and addresses to and from a bus that connects the CPU 410 to other circuits in the integrated circuit 390.

[0173] The memory circuit 421 may have a circuit configuration that stores data to be processed by the accelerator 420. The arithmetic circuit 422 may have a circuit configuration that performs arithmetic processing of the data held in the memory circuit 421. The drive circuit 423 may have a circuit configuration for controlling each circuit in the accelerator 420.

[0174] The high-speed bus 440A is a bus for transmitting and receiving various signals at high speed between the CPU 410, the accelerator 420, the on-chip memory 431, the DMAC 441, the power management unit 442, the security circuit 447, the memory controller 443, the DDR SDRAM controller 444, the USB interface circuit 445, and the display interface circuit 446. As an example, an AMBA (Advanced Microcontroller Bus Architecture)-AHB (Advanced High-performance Bus) can be used as the bus.

[0175] The on-chip memory 431 has a circuit configuration for storing data or programs to be input / output to / from circuits included in the integrated circuit 390, such as the CPU 410 or the accelerator 420.

[0176] The DMAC 441 is a direct memory access controller. By including the DMAC 441, peripheral devices other than the CPU 410 can access the on-chip memory 431 without going through the CPU 410.

[0177] The power management unit 442 has a circuit configuration for controlling power gating of circuits such as a CPU core included in the integrated circuit 390.

[0178] The security circuit 447 has a circuit configuration for enhancing the confidentiality of signals, such as by encrypting signals before transmitting and receiving signals between the integrated circuit 390 and an external circuit.

[0179] The memory controller 443 has circuitry for writing and reading programs for execution by the CPU 410 or accelerator 420 from a program memory external to the integrated circuit 390 .

[0180] The DDR SDRAM controller 444 has circuitry for writing data to and reading data from a main memory, such as a DRAM, external to the integrated circuit 390 .

[0181] The USB interface circuit 445 has a circuit configuration for transmitting and receiving data to and from a circuit external to the integrated circuit 390 via a USB terminal.

[0182] Display interface circuitry 446 includes circuitry for transmitting data to and receiving data from a display device external to integrated circuit 390 .

[0183] The power supply circuit 460 is a circuit for generating a voltage used in the integrated circuit 390. For example, it is a circuit for generating a negative voltage to be applied to the back gate of an OS transistor in order to stabilize the electrical characteristics.

[0184] The low-speed bus 440B is a bus for transmitting and receiving various signals at low speed between the interrupt control circuit 451, the interface circuit 452, the battery control circuit 453, and the ADC / DAC interface circuit 454. As an example, an AMBA-APB (Advanced Peripheral Bus) can be used as the bus. Various signals are transmitted and received between the high-speed bus 440A and the low-speed bus 440B via a bridge circuit 450.

[0185] The interrupt control circuit 451 has a circuit configuration for performing interrupt processing in response to a request received from a peripheral device.

[0186] The interface circuit 452 has a circuit configuration for operating interfaces such as a universal asynchronous receiver / transmitter (UART), an inter-integrated circuit (I2C), or a serial peripheral interface (SPI).

[0187] The battery control circuit 453 has circuitry for transmitting and receiving data relating to charging and discharging of a battery external to the integrated circuit 390 .

[0188] The ADC / DAC interface circuit 454 has a circuit configuration for transmitting and receiving data to and from a device that outputs an analog signal, such as a MEMS (Micro Electro Mechanical Systems) device, located outside the integrated circuit 390 .

[0189] 17A and 17B are diagrams showing an example of the layout of circuit blocks when implemented as an SoC. As in the integrated circuit 390 shown in FIG. 17A, each configuration shown in the block diagram of FIG. 16 can be arranged in separate regions on a chip.

[0190] 16 can be configured with a memory circuit configured with OS transistors, such as NOSRAM. That is, the on-chip memory 431 and the memory circuit 421 have the same circuit configuration. Therefore, when fabricated into an SoC, the on-chip memory 431 and the memory circuit 421 can be integrated and arranged in the same area, as in the integrated circuit 390E illustrated in FIG. 17B.

[0191] According to the above-described embodiment of the present invention, a novel semiconductor device and electronic device can be provided. According to another embodiment of the present invention, a semiconductor device and electronic device with low power consumption can be provided. According to another embodiment of the present invention, a semiconductor device and electronic device in which heat generation can be suppressed can be provided.

[0192] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0193] (Embodiment 5) In this embodiment mode, an electronic device, a mobile object, and a computing system to which the integrated circuit 390 described in the above embodiment mode can be applied will be described with reference to FIGS.

[0194] Fig. 18A shows an external view of an automobile as an example of a moving body. Fig. 18B shows a simplified diagram of data exchange within the automobile. The automobile 590 has a plurality of cameras 591 and the like. The automobile 590 also includes various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar.

[0195] In an automobile 590, the above-mentioned integrated circuit 390 can be used for a camera 591, etc. In the automobile 590, a plurality of images obtained by a camera 591 in a plurality of imaging directions 592 are processed by the integrated circuit 390 described in the above embodiment, and the plurality of images are collectively analyzed by a host controller 594, etc. via a bus 593, etc., so that the automobile 590 can determine the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and perform automatic driving. The automobile 590 can also be used in a system that performs road guidance, hazard prediction, etc.

[0196] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0197] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, a moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc., and a computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0198] Fig. 19A is an external view showing an example of a portable electronic device. Fig. 19B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, and the like.

[0199] In portable electronic device 595, the integrated circuit 390 can be provided on printed circuit board 596. Portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by speaker 597, camera 598, microphone 599, etc., using integrated circuit 390 described in the above embodiment. Also, the portable electronic device can be used in a system that performs voice guidance, image search, etc.

[0200] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0201] A portable game machine 1100 shown in FIG. 20A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, an operation key 1107, and the like. The housings 1101, 1102, and 1103 are removable. By attaching the connection unit 1105 provided in the housing 1101 to the housing 1108, a video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated to function as an operation unit. The integrated circuit 390 described in the above embodiment can be incorporated in a chip provided on a substrate of the housings 1102 and 1103.

[0202] 20B shows a stick-type electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated in the controller chip 1126 of the board 1124, etc.

[0203] 20C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the integrated circuit 390 shown in the previous embodiment can be incorporated into the control circuit 2110.

[0204] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0205] (Additional Notes Regarding the Description of the Present Specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0206] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments or examples to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0207] In addition, the content (or a part of the content) described in one embodiment can be applied to, combined with, or replaced by another content (or a part of the content) described in that embodiment, and / or the content (or a part of the content) described in one or more other embodiments.

[0208] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0209] In addition, a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and / or with a figure (or a part of it) described in one or more other embodiments to form even more figures.

[0210] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately according to the situation.

[0211] In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0212] In addition, the positional relationship of components shown in the drawings is relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" that indicate the positional relationship may be used for convenience. The positional relationship of components is not limited to the contents described in this specification, and can be rephrased appropriately depending on the situation.

[0213] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode, or first terminal) and "the other of the source or drain" (or second electrode, or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0214] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0215] In addition, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage is a potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may be changed depending on the reference potential.

[0216] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0217] In this specification, A and B are connected means that A and B are electrically connected. Here, A and B are electrically connected means a connection in which an electrical signal between A and B can be transmitted when an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) exists between A and B. Note that when A and B are electrically connected, this includes a case in which A and B are directly connected. Here, A and B are directly connected means a connection in which an electrical signal between A and B can be transmitted through wiring (or electrodes) between A and B without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

[0218] In this specification, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0219] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between the source and drain in a region where a channel is formed.

[0220] In this specification, the channel width refers to, for example, the length of the region where a semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap, or the length of the portion where a source and a drain face each other in a region in which a channel is formed.

[0221] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". [Explanation of symbols]

[0222] : 100: semiconductor device, 100P: semiconductor device, 101: logic section, 101A: logic section, 101B: logic section, 101C: logic section, 103: p-channel transistor, 104: n-channel transistor, 105: transistor region, 106: transistor region, 108: control section, 110: calculation section, 111: transistor, 112: capacitance element, 200: semiconductor device, 201: logic section, 201A: logic section, 201B: logic section, 204: p-channel transistor, 205: p-channel transistor, 206: n-channel transistor transistor, 207: n-channel transistor, 210: semiconductor device, 211: logic section, 214: p-channel transistor, 215: p-channel transistor, 216: n-channel transistor, 217: n-channel transistor, 220: semiconductor device, 221: transistor, 222: transistor, 300: silicon substrate, 301: insulating layer, 302: insulating layer, 303: semiconductor layer, 305: region, 306: well region, 308: insulating layer, 310: semiconductor layer, 310A: impurity region, 310B: impurity region, 310C: channel formation region, 312: impurity region, 314: insulating layer, 316: conductive layer, 318: insulating layer, 322A: conductive layer, 322B: conductive layer, 322C: conductive layer, 322D: conductive layer, 324: insulating layer, 326: conductive layer, 328: insulating layer, 330: conductive layer, 332: insulating layer, 334: conductive layer, 336: insulating layer, 338: conductive layer, 340: insulating layer, 342: semiconductor layer, 344: conductive layer, 344A: conductive layer, 344B: conductive layer, 346: insulating layer, 348: insulating layer, 350: insulating layer, 352: conductive layer, 354: insulating layer, 356: insulating layer, 358: conductive layer, 360: insulating layer, 362: conductive layer ,390: integrated circuit, 390E: integrated circuit, 410: CPU, 411: CPU core, 412: instruction cache, 413: data cache, 414: bus interface circuit, 420: accelerator, 421: memory circuit, 422: arithmetic circuit, 423: drive circuit, 431: on-chip memory, 440A: high-speed bus, 440B: low-speed bus, 441: DMAC, 442: power management unit, 443: memory controller, 444: SDRAM controller, 445: USB interface circuit, 446: display interface circuit,447: security circuit, 450: bridge circuit, 451: control circuit, 452: interface circuit, 453: battery control circuit, 454: ADC / DAC interface circuit, 460: power supply circuit, 510: CPU, 511: CPU core, 512: backup circuit, 515: backup circuit, 520: accelerator, 521: arithmetic processing unit, 522: memory unit, 523: arithmetic circuit, 524: memory circuit, 530: bus, 590: automobile, 591: camera, 592: imaging direction, 593: bus, 594: host controller, 595: portable electronic device, 59 6: printed wiring board, 597: speaker, 598: camera, 599: microphone, 1100: portable game machine, 1101: housing, 1102: housing, 1103: housing, 1104: display unit, 1105: connection unit, 1107: operation key, 1108: housing, 1109: housing, 1120: electronic device, 1121: housing, 1122: cap, 1123: USB connector, 1124: substrate, 1125: memory chip, 1126: controller chip, 1130: robot, 2101: sensor, 2106: sensor, 2110: control circuit, 3404: insulating layer, 3420: semiconductor layer,

Claims

[Claim 1] A p-channel transistor and an n-channel transistor are provided on a silicon substrate, One of the source and the drain of the p-channel transistor is electrically connected to a first power supply line; One of the source and the drain of the n-channel transistor is electrically connected to a second power supply line; the other of the source and the drain of the p-channel transistor is electrically connected to the other of the source and the drain of the n-channel transistor; the p-channel transistor has a first gate electrode and a first back gate electrode provided opposite to the first gate electrode with a first channel forming region therebetween; the first back gate electrode is formed using a region in the silicon substrate into which an impurity element that imparts electrical conductivity is selectively introduced, the n-channel transistor is provided above a layer having the p-channel transistor; the n-channel transistor has a second channel forming region; the second channel formation region includes a metal oxide; The metal oxide includes In, Ga, and Zn, the n-channel transistor has a second gate electrode and a second back gate electrode provided opposite to the second gate electrode with the second channel formation region interposed therebetween; a potential applied to the first back-gate electrode is lower than a potential applied to the second back-gate electrode.

Images