Semiconductor device

Abstract

To provide a transistor having high electron field-effect mobility; or provide a transistor having stable electrical characteristics; or provide a transistor having less current in an OFF state (non-conductive state); or provide a semiconductor device having the above-described transistor.SOLUTION: A semiconductor device comprises: a first electrode formed on a substrate; a first insulation layer formed adjacent to a lateral face of the first electrode; and a second insulation layer which covers the first insulation layer and is formed adjacent to at least part of a surface of the first electrode. The surface of the first electrode is formed by a conductive material where an impurity element is less likely to penetrate; and the second insulation layer is formed by an insulating material where an impurity element is less likely to penetrate. The semiconductor device further comprises an oxide semiconductor layer formed on the first electrode via third insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, Manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, In particular, one aspect of the present invention relates to a method for driving a semiconductor device, a semiconductor memory ... The present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices may include a semiconductor device. [Background technology]

[0003] Silicon used as a semiconductor in transistors is classified into amorphous silicon and polycrystalline silicon depending on the application. For example, it is used in transistors that make up large display devices. In this case, it is preferable to use amorphous silicon, for which a technique for forming it on a large-area substrate has been established. On the other hand, it is applied to transistors that constitute high-performance display devices that are integrated with driving circuits. In this case, if polycrystalline silicon is used, transistors with high field effect mobility can be fabricated. Polycrystalline silicon is preferably obtained by subjecting amorphous silicon to high-temperature heat treatment or laser light. A method for forming the same by processing is known.

[0004] In recent years, oxide semiconductors have been attracting attention. For example, A transistor including an amorphous oxide semiconductor has been disclosed (see Patent Document 1).

[0005] Since the oxide semiconductor can be formed by a sputtering method or the like, it can be used to form a large display device. The oxide semiconductor can be used for the channel formation region of a transistor. The transistors have high field effect mobility, making them ideal for high-performance integrated drive circuits. In addition, some of the production facilities for amorphous silicon transistors can be used Since it is possible to improve and reuse the system, it also has the advantage of reducing capital investment.

[0006] Meanwhile, a transistor including an oxide semiconductor has a large leakage current in a non-conducting state. For example, it is known that a transistor using an oxide semiconductor has low leakage current. A low-power consumption CPU that utilizes this characteristic has been disclosed (see Patent Document 2). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2006-165528 A [Patent Document 2] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to provide a transistor having high field effect mobility. It is an object of the present invention to provide a transistor having stable electrical characteristics. It is an object of the present invention to provide a transistor with a low current (current). Another object of the present invention is to provide a transistor having a low defect rate. Another object of the present invention is to provide a novel transistor. This is one of the challenges.

[0009] Another object of the present invention is to provide a semiconductor device that occupies a small area. Another object of the present invention is to provide a semiconductor device having high reliability. Another object of the present invention is to provide a novel semiconductor device. Let us assume that.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device comprising a first electrode, a first insulating layer, a second insulating layer, and a third insulating layer; an oxide semiconductor layer, the first insulating layer being adjacent to a side of the first electrode, and a second insulating layer covers the first insulating layer and contacts at least a portion of the surface of the first electrode, The second insulating layer overlaps with the oxide semiconductor layer with the third insulating layer interposed therebetween, and the second insulating layer is a layer through which an impurity element is transmitted. The surface of the first electrode is made of an insulating material that is difficult to penetrate by impurity elements, and the surface of the second electrode is made of a conductive material that is difficult to penetrate by impurity elements. The semiconductor device is characterized in that

[0012] Alternatively, one aspect of the present invention is a semiconductor device including a first gate electrode, a second gate electrode, and a first gate insulator. a gate insulating layer, a second gate insulating layer, an oxide semiconductor layer, a source electrode, a drain electrode, and a first The oxide semiconductor layer has a first insulating layer and a second insulating layer. The first gate insulating layer, the oxide semiconductor layer, and the second gate insulating layer are sandwiched between the first gate insulating layer, the oxide semiconductor layer, and the second gate insulating layer. The edge layer is sandwiched between the first gate electrode and the second gate electrode, and includes a source electrode and a drain electrode. The first insulating layer is in contact with the oxide semiconductor layer, and the first insulating layer is adjacent to a side surface of the second gate electrode. The insulating layer covers the first insulating layer and contacts at least a portion of a surface of the second gate electrode. The second insulating layer is made of an insulating material that is difficult for impurity elements to penetrate, and is disposed on the surface of the second gate electrode. The semiconductor device is characterized in that the surface is made of a conductive material that is difficult for impurity elements to penetrate.

[0013] The second insulating layer may be aluminum oxide, aluminum nitride, aluminum oxynitride, or aluminum nitride oxide. Aluminum oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide It is formed using titanium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. do.

[0014] The surface of the first electrode and the surface of the second gate electrode are made of indium tin oxide (hereinafter, “IT Indium-O alloys containing silicon, phosphorus, boron, nitrogen, and / or carbon. Indium gallium oxide containing silicon, phosphorus, boron, nitrogen, and / or carbon. The insulating layer is formed using a conductive material such as tantalum zinc oxide, tantalum nitride, or ruthenium. Effect of the Invention

[0015] It is possible to provide a semiconductor device with a small occupancy area. Alternatively, a semiconductor device with good reliability can be provided. Alternatively, a novel semiconductor device can be provided.

[0016] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0017] [Figure 1] 1A and 1B illustrate examples of a transistor and a capacitor according to one embodiment of the present invention. [Diagram 2] 1A to 1C illustrate an example of a manufacturing process of a transistor according to one embodiment of the present invention. [Diagram 3] 1A to 1C illustrate an example of a manufacturing process of a transistor according to one embodiment of the present invention. [Figure 4] 1A to 1C illustrate an example of a manufacturing process of a transistor according to one embodiment of the present invention. [Diagram 5] 1A to 1C illustrate an example of a manufacturing process of a transistor according to one embodiment of the present invention. [Figure 6] FIG. 2 is a diagram for explaining an energy band structure. [Figure 7] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 8] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 9] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 10] Electron diffraction pattern of CAAC-OS. [Figure 11] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 12]Schematic diagram explaining the film formation model of CAAC-OS and nc-OS. [Figure 13] A diagram explaining InGaZnO4 crystals and pellets. [Figure 14] Schematic diagram explaining a film formation model of CAAC-OS. [Figure 15] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 16] 1A to 1C are diagrams illustrating a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus. [Figure 17] An example of structural analysis using transmission electron diffraction measurements, and a planar TEM image. [Figure 18] 1A and 1B are a cross-sectional view and a circuit diagram illustrating an example of a semiconductor device. [Figure 19] FIG. 1 is a circuit diagram illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 20] FIG. 1 is a block diagram illustrating an example of a semiconductor device. [Figure 21] FIG. 1 is a circuit diagram illustrating an example of a memory device. [Figure 22] FIG. 1 is a block diagram of an RF tag according to an embodiment of the present invention. [Diagram 23] 1A to 1C are diagrams illustrating examples of use of an RF tag according to one embodiment of the present invention. [Figure 24] 1A and 1B are a block diagram and a circuit diagram illustrating one embodiment of a semiconductor device. [Diagram 25] FIG. 2 is a diagram illustrating a display module. [Figure 26] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 27] 1A to 1C are diagrams illustrating the cross-sectional structure and analysis results of a sample used in Example 1. [Figure 28] 1A to 1C are diagrams illustrating a cross-sectional structure and analysis results of a sample used in Example 2. [Figure 29] 1A to 1C illustrate an example of a manufacturing process of a transistor according to one embodiment of the present invention. [Diagram 30] 1A and 1B illustrate examples of a transistor and a capacitor according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. A repeated explanation will be omitted.

[0019] In addition, the position, size, range, etc. of each component shown in the drawings are for the purpose of facilitating understanding of the invention. Therefore, the actual location, size, range, etc. may not be shown. The invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. For example, In the actual manufacturing process, resist masks, etc., may be unintentionally damaged by etching or other processes. However, in order to make it easier to understand, these may be omitted.

[0020] In order to make the drawings easier to understand, especially in top views (also called "plan views"), Description of some components may be omitted.

[0021] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0022] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "the electrode on insulating layer A is directly in contact with the insulating layer A" is not limited to the above. If the expression is "electrode B", it is not necessary for electrode B to be formed directly on insulating layer A. The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0023] The source and drain functions may also be different in some cases, such as when transistors of different polarities are used, or when When the direction of the current changes during operation of the circuit, the two are interchangeable depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. It shall be so.

[0024] In addition, in this specification, "electrically connected" means "something that has some electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects. Therefore, even if it is expressed as "electrically connecting," in the actual circuit, In some cases, there are no physical connections and only wires running along the wiring.

[0025] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. In addition, "perpendicular" and "orthogonal" mean that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it includes the case where the angle is between 85° and 95°. "Straight" refers to two straight lines that form an angle of 60° or more and 120° or less.

[0026] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0027] In this specification, when an etching process is performed after a photolithography process, In this case, unless otherwise specified, the resist mask formed in the photolithography process is It shall be removed after the etching process is completed.

[0028] Also, a voltage is a voltage between a certain potential and a reference potential (for example, a ground potential or a source potential). Therefore, voltage can be replaced with electric potential. do.

[0029] Even if a material is described as a "semiconductor," if its electrical conductivity is sufficiently low, it may be considered an "insulator." In addition, the boundary between "semiconductor" and "insulator" is unclear, and Therefore, the term "semiconductor" as used herein may not be distinguishable from "insulator." Similarly, the term "insulator" used in this specification may be interpreted as "semiconductor." " This can sometimes be rephrased as ".

[0030] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it should be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear, and Therefore, the term "semiconductor" as used herein may not be distinguished from "conductor." Similarly, the term "conductor" used in this specification may be used interchangeably with "semiconductor." " This can sometimes be rephrased as ".

[0031] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with a concentration of less than 0.1 atomic percent are considered impurities. The density of state (DOS) of the body increases and the carrier mobility decreases. In some cases, the semiconductor may be an oxide semiconductor. In this case, the impurities that change the properties of the semiconductor are, for example, Group 1 elements, Group 2 elements, Elements of Group 14, Group 15, transition metals other than the main component, etc. (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of oxide semiconductors, for example, oxygen vacancies are formed due to the inclusion of impurities such as hydrogen. In addition, if the semiconductor is a silicon film, impurities that change the properties of the semiconductor may occur. Examples of the elements include oxygen, elements of Group 1 except hydrogen, elements of Group 2, elements of Group 13, elements of Group 15, Group elements, etc.

[0032] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The names are given for the purpose of illustrating the order or sequence of steps, stacking, etc. In addition, even if a term is not designated by an ordinal number in this specification, it is not considered to be a mismatch of constituent elements. To avoid confusion, ordinal numbers may be used in the claims.

[0033] Note that the "channel length" refers to, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). The source (source region or source electrode) in the region where the channel is formed The distance between the drain and the transistor (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value or the maximum value in the region where the channel is formed. , the minimum or average value.

[0034] Also, the "channel width" refers to, for example, the width of a semiconductor (or a semiconductor transistor when it is in the on state). The area where the gate electrode overlaps with the conductor (the part of the conductor where the current flows), or the channel is formed. The length of the part where the source and drain face each other in the region where the source and drain are connected. In a transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of a transistor may not be fixed to a single value. In this specification, the channel width is any one of the values ​​in the region where the channel is formed, This can be the maximum, minimum or average value.

[0035] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in a transistor with a fine, three-dimensional structure, The percentage of the channel region that is formed on the side of the semiconductor, compared to the percentage of the channel region that is formed In that case, the apparent channel width shown in the top view may be larger. In this case, the effective channel width where the channel is actually formed is larger than the width of the channel formed by the MOSFET.

[0036] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0037] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The width of the channel is called the surrounded channel width (SCW). In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when the term "channel width" is used, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. A value can be determined.

[0038] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the calculation may be performed using the enclosure channel width. In such a case, the value may be different from the case where the calculation is performed using the effective channel width.

[0039] (Embodiment 1) In this embodiment, a configuration example of the transistor 100 according to one aspect of the present invention will be described with reference to the drawings.

[0040] <A: Configuration Example of Transistor and Capacitor Element> FIG. 1(A) is a top view of the transistor 100 and the capacitor element 130. FIG. 1(B) is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 1(A). FIG. 1(C) is a cross-sectional view of the portion indicated by the dashed line B1 - B2 in FIG. 1(A).

[0041] The transistor 100 shown in FIG. 1 is formed on the substrate 101. The transistor 100 includes an electrode 102, an insulating layer 106, an insulating layer 107, an oxide semiconductor layer 108, an electrode 109, an electrode 119, an insulating layer 110, an electrode 111, and an insulating layer 112. Also, in FIGS. 1(A) and 1(B), the electrodes 103 and 104 are also shown.

[0042] More specifically, the electrodes 102, 103, and 104 are formed on the substrate 101, and an insulating layer 105 is formed between the respective electrodes. The electrode 102 has a structure in which the electrode 102b is laminated on the electrode 102a. The electrode 103 has a structure in which the electrode 103b is laminated on the electrode 103a. The electrode 104 has a structure in which the electrode 104b is laminated on the electrode 104a. The insulating layer 106 is formed on the insulating layer 105 in contact with a part of the electrode 102b, a part of the electrode 103b, and a part of the electrode 104b.

[0043] The insulating layer 107 is formed on a part of the electrode 102b, a part of the electrode 103b, and a part of the electrode 104b. The insulating layer 107 is formed on the insulating layer 106 in contact with a part of the insulating layer 107. The insulating layer 107 has a protrusion. An oxide semiconductor layer 108a and an oxide semiconductor layer 108b are formed on the electrode 10. The electrode 119 is formed in contact with the oxide semiconductor layer 108b. , and is electrically connected to the electrode 104 via an opening formed in the insulating layer 107 .

[0044] The oxide semiconductor layer 108c is formed by stacking the oxide semiconductor layer 108b, the electrode 109, and the electrode 101. In FIG. 1, the oxide semiconductor layer 108a and the oxide semiconductor layer 10 The oxide semiconductor layer 8b and the oxide semiconductor layer 108c are referred to as the oxide semiconductor layer 108.

[0045] In addition, an insulating layer 110 is formed on the oxide semiconductor layer 108c, and an electrode 11 is formed on the insulating layer 110. An insulating layer 112 is formed to cover the electrodes 109, 119, and 111. is formed.

[0046] The electrode 111 can function as a gate electrode. The insulating layer 110 can be a gate insulating layer. The electrode 109 can function as either a source electrode or a drain electrode. The electrode 119 can function as the other of the source electrode or the drain electrode. The electrode 102 can function as a back gate electrode. The transistor 100 is a transistor using an oxide semiconductor in a semiconductor layer in which a channel is formed. The transistor 100 can be considered a type of top-gate transistor. do.

[0047] Here, the back gate electrode will be explained. In general, the back gate electrode is a conductive layer. The gate electrode and the back gate electrode are disposed so as to sandwich a channel forming region of the semiconductor layer. Therefore, the back gate electrode can function similarly to the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or may be the GND potential or any other potential. Alternatively, the potential of the back gate electrode may be changed independently of the gate electrode. By changing the capacitance, the threshold voltage of the transistor can be changed.

[0048] The electrode 111 and the electrode 102 of the transistor 100 are both used as gate electrodes. Thus, both the insulating layer 110 and the insulating layer 107 function as gate insulators. Therefore, either the electrode 111 or the electrode 102 can function as an edge layer. When the first electrode is simply called the "gate electrode," the other is called the "back gate electrode." Either the electrode 11 or the electrode 102 is referred to as the "first gate electrode" and the other is referred to as the "second gate electrode." In addition, when the electrode 102 is used as the "gate electrode", In this regard, the transistor 100 can be considered as a type of bottom-gate transistor.

[0049] By providing the electrode 111 and the electrode 102 with the oxide semiconductor layer 108 interposed therebetween, By setting the electrode 111 and the electrode 102 to the same potential, a carrier is generated in the oxide semiconductor layer 108. Since the area in which the a flows becomes larger in the film thickness direction, the amount of carrier movement increases. As a result, the on-state current of the transistor 100 increases and the field effect mobility increases. .

[0050] Therefore, the transistor 100 is a transistor having a large on-current relative to its area. That is, the area of ​​the transistor 100 required for the required on-current is According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0051] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity It has an electrostatic shielding function against

[0052] In addition, the electrodes 111 and 102 each have a function of blocking an electric field from the outside. Therefore, the charges of the charged particles provided on the substrate 101 side or the electrode 111 side are transferred to the oxide semiconductor layer. 108. As a result, stress testing (e.g. applying a negative charge to the gate - GBT (Gate Bias-Temperature) stress test) deterioration is suppressed. At the same time, the fluctuation of the on-current rise voltage at different drain voltages is suppressed. This effect can be obtained when the electrode 111 and the electrode 102 are at the same potential or different potentials. This occurs in the case of electric potential.

[0053] The BT stress test is a type of accelerated test that measures the transistor damage caused by long-term use. The change in the characteristics of the BT (i.e., aging) can be evaluated in a short time. The amount of change in the threshold voltage of a transistor before and after a stress test is used to check reliability. The smaller the change in threshold voltage before and after the BT stress test, the Therefore, it can be said that this is a highly reliable transistor.

[0054] In addition, the electrode 111 and the electrode 102 are provided, and the electrode 111 and the electrode 102 are set to the same potential. This reduces the amount of variation in threshold voltage before and after the BT stress test. Therefore, the variation in electrical characteristics among the multiple transistors is also reduced at the same time.

[0055] Also, the transistor 100 having a back gate electrode has a positive charge applied to the gate + The variation in threshold voltage before and after the GBT stress test is small.

[0056] In addition, when light is incident from the back gate electrode side, the back gate electrode is made of a material having a light blocking property. By forming the semiconductor layer from a conductive film, light is prevented from entering the semiconductor layer from the back gate electrode side. This prevents the semiconductor layer from being photodegraded and the threshold voltage of the transistor is shifted. This can prevent deterioration of electrical characteristics such as the occurrence of

[0057] Next, we will explain the "threshold voltage." Here, the electrode 111 is used as the gate electrode. When a voltage is applied to the electrode 111, an electric field having a strength corresponding to the voltage is generated in the insulating layer 1. A voltage is applied to the oxide semiconductor layer 108 via the voltage regulator 10, and carriers are generated in the oxide semiconductor layer 108. When the channel is formed, the electrodes 109 and 119 are electrically connected to each other. A channel is formed in the oxide semiconductor layer 108. The voltage of electrode 111 at which the leakage begins is called the "threshold voltage."

[0058] For example, the transistor 100 is an n-channel transistor, and the electrode 109 is a source electrode. When the electrode 119 is used as a drain electrode, when the potential of the electrode 109 is set to 0 V, When a voltage equal to or higher than the threshold voltage is applied to the electrode 111, the oxide semiconductor layer 10 Carriers are supplied to the channel 8 to form a channel. The region where the channel is formed is called the "channel forming region." At this time, a positive voltage is applied to the electrode 119. When a voltage is applied, carriers flow from electrode 109 to electrode 119. In other words, A current flows from the electrode 119 to the electrode 109. When the transistor is in the on state, The current that flows between the source and drain electrodes of a transistor is called the "on-current." The current that flows between the source electrode and the drain electrode when the MOSFET is in the off state is called the "off current."

[0059] The insulating layers 106 and 112 are free of impurities such as hydrogen, water, alkali metals, and alkaline earth metals. It is preferable to form the insulating material by using an insulating material that is difficult for oxygen to permeate. By forming the insulating layer 106 and the insulating layer 112 using the above, the oxide semiconductor layer 10 In addition, the diffusion of impurities into the oxide semiconductor layer 108 can be suppressed. Therefore, it is possible to suppress the diffusion of the elements to the outside.

[0060] It is also preferable that the insulating layer 106 is not provided on at least a portion of the electrode 102. By not providing the insulating layer 106 on at least a part of the electrode 102, the electrode 102 and the oxide semiconductor The distance between the electrode 102 and the insulating layer 106 can be reduced by the thickness of the insulating layer 106. Therefore, the electric field strength acting on the oxide semiconductor layer 108 can be increased. , the function as a gate electrode or a back gate electrode can be improved.

[0061] The capacitance element 130 has an insulating layer 107 between the electrode 103 and the electrode 109 as a dielectric. In this embodiment, the insulating layer 106 on the electrode 103 is removed. However, the insulating layer 106 on the electrode 103 is not removed, and the stack of the insulating layer 106 and the insulating layer 107 is formed. The layer may be used as a dielectric.

[0062] In addition, it is preferable that the insulating layer 106 and the insulating layer 112 are in contact with each other on the outside of the transistor 100. In FIG. 1B, the regions where the insulating layer 106 and the insulating layer 112 are in contact with each other are located at both ends of FIG. With such a structure, impurities from the outside are prevented from entering the oxide semiconductor layer 108. In addition, the effect of suppressing the diffusion of the oxide semiconductor layer 108 can be further improved. The present invention can further enhance the effect of suppressing the diffusion of oxygen to the outside. According to this, a highly reliable semiconductor device can be provided.

[0063] [A-1: Substrate 101] There is no particular restriction on the material used for the substrate 101, but it should be at least able to withstand the subsequent heat treatment. For example, barium borosilicate glass or aluminum Glass substrates such as borosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used.

[0064] The substrate 101 may be a single crystal semiconductor substrate made of silicon, silicon carbide, or the like, or a polycrystalline A semiconductor substrate, a compound semiconductor substrate made of silicon germanium, etc. may also be used. In addition, semiconductors such as strained transistors and FIN type transistors on SOI substrates and semiconductor substrates Alternatively, a high electron mobility transistor ( HEMT:High Electron Mobility Transistor) Applicable gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride Alternatively, it is possible to use tin, indium phosphide, silicon germanium, etc. By using this, a transistor suitable for high speed operation can be obtained. That is, the substrate 101 is not limited to being a simple support substrate, but may be a substrate on which other devices such as transistors are formed. In this case, the gate electrode, source electrode, or At least one of the drain electrodes may be electrically connected to the other device. .

[0065] Note that a flexible substrate may be used as the substrate 101. In the case of using a flexible substrate, a transistor, a capacitor, and the like may be directly formed on the flexible substrate. Transistors, capacitors, etc. are manufactured on another manufacturing substrate, and then peeled off and transferred to a flexible substrate. In order to peel and transfer the substrate from the substrate to the flexible substrate, A peeling layer may be provided between the transistor, the capacitor, and the like.

[0066] [A-2: electrode 102a, electrode 103a, and electrode 104a] The conductive materials for forming the electrodes 102a, 103a, and 104a include , aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum , Tungsten, Hafnium (Hf), Vanadium (V), Niobium (Nb), Manganese, A metal element selected from magnesium, zirconium, beryllium, etc., The alloy may be a combination of the above-mentioned metal elements. In addition, there are many types of silicon that have high electrical conductivity, such as polycrystalline silicon that contains impurity elements such as phosphorus. A semiconductor having a high conductivity, or a silicide such as nickel silicide may be used. Not limited to this, various methods such as deposition, CVD, sputtering, spin coating, etc. The method can be used.

[0067] Generally, the CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD method, Thermal CVD (TCVD) Furthermore, depending on the source gas used, it can be classified into metal CVD (MCVD) and other methods. :Metal CVD) method, metal organic CVD (MOCVD) method These methods include chemical vapor deposition (CVD) methods.

[0068] Generally, the deposition method includes resistance heating deposition, electron beam deposition, MBE (Molecular Beam Evaporation), Beam Epitaxy) method, PLD (Pulsed Laser Deposit) ion) method, IAD:Ion beam Assisted Deposit tion method, ALD (ALD: Atomic Layer Deposition) method They can be classified as follows:

[0069] The plasma CVD method can produce high-quality films at relatively low temperatures. If a deposition method that does not use plasma is used, the surface on which the film is formed is less likely to be damaged. Furthermore, a film with fewer defects can be obtained.

[0070] In addition, the electrodes 102a, 103a, and 104a are made of indium tin oxide, oxide Tungsten-containing indium oxide, tungsten oxide-containing indium zinc oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Conductive materials containing oxygen such as zinc oxide, indium tin oxide doped with silicon, nitrides Nitrogen-containing conductive materials such as titanium and tantalum nitride can also be used. It is also possible to form a laminated structure by combining a material containing the metal element and a conductive material containing oxygen. In addition, the multilayer structure of the material containing the above-mentioned metal element and the conductive material containing nitrogen can be obtained. A layer structure may also be used. In addition, the above-mentioned materials containing metal elements and conductive materials containing oxygen may also be used. Alternatively, a laminated structure may be formed by combining a conductive material containing nitrogen and the like.

[0071] The electrodes 102a, 103a, and 104a may each have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum layer containing silicon, A two-layer structure in which a titanium layer is laminated on a titanium nitride layer; a two-layer structure in which a titanium layer is laminated on a titanium nitride layer; Two-layer structure with a tungsten layer laminated on a tantalum layer, and a tungsten layer laminated on a tantalum nitride layer. A two-layer structure with a titanium layer and an aluminum layer laminated on top of the titanium layer. There are also three-layer structures in which a titanium layer is formed on the aluminum. Layers of elements selected from tungsten, molybdenum, chromium, neodymium, and scandium, Alternatively, an alloy layer or a nitride layer in which a plurality of layers are combined may be used.

[0072] The thickness of the electrodes 102a, 103a, and 104a is 10 nm or more and 500 nm or less. The thickness may be set to 50 nm or more and preferably 300 nm or less.

[0073] [A-3: electrode 102b, electrode 103b, and electrode 104b] The electrodes 102b, 103b, and 104b are connected to each other. It is preferable to form the insulating layer using a conductive material that is difficult to transmit impurities such as lithium-earth metals and oxygen. Such conductive materials include indium tin oxide, silicon, phosphorus, boron, nitrogen, etc. and / or indium tin oxide containing carbon, silicon, phosphorus, boron, nitrogen, and Conductive oxide materials such as indium gallium zinc oxide and / or carbon-containing Other examples include conductive materials such as tantalum nitride and ruthenium. In addition, the electrodes 102b, 103b, and 104b may each have a single-layer structure or a two-layer structure or more. A laminated structure of the above may also be used.

[0074] The thickness of the electrodes 102b, 103b, and 104b is 10 nm or more and 500 nm or less. The thickness may be set to 50 nm or more and preferably 300 nm or less.

[0075] In addition, the electrodes 102a, 103a, and 104a are not provided, and the electrodes 102, 103, and electrode 104, with only electrodes 102b, 103b, and 104b. It may be configured.

[0076] [A-4: Insulating layer 105] The insulating layer 105 is made of aluminum nitride, aluminum oxide, aluminum nitride oxide, or aluminum oxynitride. aluminum oxide, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, Silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide The material selected from lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide The insulating layer 10 may be formed as a single layer or a laminate. In addition, the insulating layer 10 may be formed as an oxide material, a nitride material, or an oxide / nitride material. Alternatively, a mixture of a plurality of nitride materials and nitride oxide materials may be used.

[0077] In this specification, the term "nitride oxide" refers to a compound that contains more nitrogen than oxygen. In addition, oxynitrides refer to compounds that contain more oxygen than nitrogen. The content of is, for example, measured by Rutherford Backscattering (RBS) spectroscopy. Measurements can be made using techniques such as kScattering Spectrometry. .

[0078] When the insulating layer 105 is a laminate of multiple layers, for example, the first layer is a silicon nitride layer, and the second layer is a silicon nitride layer. The first layer may be a silicon oxide layer. In this case, the silicon oxide layer may be a silicon oxynitride layer. Also, the silicon nitride layer may be a silicon oxynitride layer.

[0079] The thickness of the insulating layer 105 is 10 nm or more and 500 nm or less, preferably 50 nm or more and 300 nm or less. m or less.

[0080] [A-5: Insulating layer 106] The insulating layer 106 is permeable to impurities such as hydrogen, water, alkali metals, alkaline earth metals, and oxygen. It is preferable to form the insulating layer using an insulating material that is resistant to oxidation. Aluminum nitride, aluminum oxide nitride, aluminum oxide nitride, aluminum oxide Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, Examples of insulating oxide materials include neodymium oxide, hafnium oxide, and tantalum oxide. Cut.

[0081] The thickness of the insulating layer 106 is 10 nm or more and 500 nm or less, preferably 50 nm or more and 300 nm or less. m or less.

[0082] [A-6: Insulating layer 107] The insulating layer 107 can be formed using the same material and method as the insulating layer 105. In order to prevent an increase in the hydrogen concentration in the oxide semiconductor, the hydrogen concentration in the insulating layer 107 is reduced. Specifically, the hydrogen concentration of the insulating layer 107 is preferably 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 The following is more preferred: 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 In addition, in order to prevent an increase in the nitrogen concentration in the oxide semiconductor, the insulating layer 107 Specifically, it is preferable to reduce the nitrogen concentration in the insulating layer 107 by reducing the nitrogen concentration in the SIM In S, 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 More preferably, 5×10 17 atoms / cm 3 The following applies.

[0083] In addition, the insulating layer 107 is an insulating layer containing more oxygen than the oxygen that satisfies the stoichiometric composition. It is preferable to form the insulating layer by using an oxygen-rich layer containing more oxygen than the stoichiometric composition. When the layer is heated, some of the oxygen is desorbed. The insulating layer containing the compound had a loss of oxygen of 1.0×10 1 8 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 That's all. The surface temperature of the film during the TDS analysis was 100°C or higher and 70°C or lower. A temperature range of 0° C. or lower, or 100° C. to 500° C. is preferred.

[0084] The thickness of the insulating layer 106 is 10 nm or more and 500 nm or less, preferably 50 nm or more and 300 nm or less. m or less.

[0085] [A-7: Oxide semiconductor layer 108] The oxide semiconductor layer 108 includes an oxide semiconductor layer 108a, an oxide semiconductor layer 108b, and an oxide semiconductor layer 108c. It has a structure in which conductor layers 108c are laminated.

[0086] The oxide semiconductor layer 108a, the oxide semiconductor layer 108b, and the oxide semiconductor layer 108c are It is formed of a material containing either indium or gallium, or both. Typically, I n-Ga oxide (oxide containing In and Ga), In-Zn oxide (oxide containing In and Zn) oxide) and In-M-Zn oxide (an oxide containing In, the element M, and Zn).

[0087] The element M is preferably aluminum, gallium, yttrium, tin or the like. Other elements that can be used for element M include boron, silicon, titanium, iron, and nickel. , Germanium, Yttrium, Zirconium, Molybdenum, Lanthanum, Cerium, Neo Examples include zinc, hafnium, tantalum, and tungsten. However, the element M is In some cases, a combination of multiple elements may be used. For example, the element M has a bond energy with oxygen of The element M has a function to increase the energy gap of the oxide, for example. The oxide semiconductor layer 108 is an oxide semiconductor containing the element M. It is preferable that the oxide semiconductor contains zinc. When the oxide contains zinc, for example, For example, the oxide becomes easier to crystallize.

[0088] However, the oxide semiconductor is not limited to an oxide containing indium. For example, zinc tin oxide and gallium tin oxide may be used.

[0089] The oxide semiconductor layer 108 is formed by a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like. Deposition method (MOCVD (Metal Organic Chemica) l Vapor Deposition) method, ALD (Atomic Layer Deposition) method, position method, thermal CVD method or PECVD (Plasma Enhanced Chemical Vapor Deposition (CVA) method, but not limited to MBE (Molecular Beam Epitaxy) or PLD (Pu It is recommended to use the LSLD method for film formation. The CVD, ALD, or thermal CVD methods do not use plasma, so oxide semiconductors can be This makes it difficult to damage the layer 108, and reduces the leakage current in the off-state of the transistor. This is preferable because it is possible to

[0090] For example, the oxide semiconductor layer 108 may be formed by thermal CVD of InGaZnO X (X>0) Film formed In the case of the film, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula for trimethylindium is In(CH 3 ) 3 Also, trimethyl The chemical formula for gallium is Ga(CH 3 ) 3 The chemical formula for dimethylzinc is Zn (CH 3 ) 2 In addition, the combination is not limited to these, and trimethylgallium may be used instead. Triethylgallium (chemical formula Ga(C) 2 H 5 ) 3 ) can also be used, Diethyl zinc (chemical formula Zn(C) 2 H 5 ) 2 ) can also be used.

[0091] For example, the oxide semiconductor layer 108 may be formed by an ALD method using InGaZnO X (X>0) Film formed In the case of membrane, In(CH 3 ) 3 Gas and O 3 The gases were repeatedly introduced to produce InO 2 Layer Then, Ga(CH 3 ) 3 Gas and O 3 Gases are introduced simultaneously to form a GaO layer, Then, Zn(CH 3 ) 2 and O 3 Gas is introduced at the same time to form a ZnO layer. The order of these layers is not limited to this example. 2 Layer and In ZnO 2 The layer is a mixed compound layer such as a GaInO layer, a ZnInO layer, and a GaZnO layer. Also, O 3 H bubbled with inert gas such as Ar instead of gas 2 O gas However, it is not possible to use3 It is preferable to use In(CH 3 ) 3 gas Instead, In(C 2 H 5 ) 3 Using gas and tris(acetylacetonato)indium Tris(acetylacetonato)indium is also good. 3 Also called Also, Ga(CH 3 ) 3 Instead of gas, Ga(C 2 H 5 ) 3 Gas and Tris (Acetyl Tris(acetylacetonato)gallium may also be used. , Ga(acac) 3 Also called In(CH 3 ) 3 Instead of gas, In(C 2 H 5 ) 3 Gas may also be used. 3 ) 2 Gas or zinc acetate may also be used. The gas types are not limited to these.

[0092] When the oxide semiconductor layer 108 is formed by a sputtering method, the following steps are required to reduce the number of particles: It is preferable to use a target containing indium. In addition, an oxide having a high atomic ratio of element M is used. When using a target, the conductivity of the target may be reduced. When a target is used, the conductivity of the target can be increased, and DC discharge and AC discharge can be used. This makes it easier to handle large-area substrates. can be increased.

[0093] When the oxide semiconductor layer 108 is formed by a sputtering method, the atomic ratio of the target is I n:M:Zn is 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1, 1 :1:2, 1:4:4, etc.

[0094] When the oxide semiconductor layer 108 is formed by a sputtering method, the atomic ratio of the target is different. In particular, zinc may form a film with a higher atomic ratio than that of the target. The atomic ratio of the film may become smaller. Specifically, the number of zinc atoms contained in the target The ratio may be between 40 atomic % and 90 atomic %.

[0095] The oxide semiconductor layer 108a and the oxide semiconductor layer 108c constitute the oxide semiconductor layer 108b. It is preferable that the metal element is made of a material containing one or more of the same metal elements. It is preferable that such a material is used. 8b, and the interfaces with the oxide semiconductor layer 108c and the oxide semiconductor layer 108b. This makes it difficult for interface states to occur at the interface. This makes it possible to improve the field effect mobility of the transistor. It is possible to reduce the variation in the threshold voltage of the transistor. It is therefore possible to realize a semiconductor device having the desired characteristics.

[0096] The thickness of the oxide semiconductor layer 108a and the oxide semiconductor layer 108c is 3 nm or more and 100 nm or less. The thickness of the oxide semiconductor layer 108b is preferably 3 nm or more and 50 nm or less. is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably The thickness is between 3 nm and 50 nm.

[0097] The oxide semiconductor layer 108b is an In-M-Zn oxide, and the oxide semiconductor layer 108a is When the oxide semiconductor layer 108c is also an In-M-Zn oxide, the oxide semiconductor layer 10 The oxide semiconductor layer 8a and the oxide semiconductor layer 108c are formed of In:M:Zn=x 1 :y 1 :z 1 [Atomic ratio], The oxide semiconductor layer 108b is made of In:M:Zn=x 2 :y 2 :z 2 [Atomic ratio], y 1 / x 1 y 2 / x 2 The oxide semiconductor layer 108a and the oxide semiconductor layer 108 c, and the oxide semiconductor layer 108b. 1 / x 1 y 2 / x 2 Yo The oxide semiconductor layer 108a, the oxide semiconductor layer 108c, and The oxide semiconductor layer 108b is preferably selected. 1 / x 1 y 2 / x 2 than The oxide semiconductor layer 108a, the oxide semiconductor layer 108c, and the oxide semiconductor layer 108b are each twice as large as the oxide semiconductor layer 108a. The conductive layer 108b is preferably selected. 1 / x 1 y 2 / x 2 More than three times larger than The oxide semiconductor layer 108a, the oxide semiconductor layer 108c, and the oxide semiconductor layer 108 At this time, in the oxide semiconductor layer 108b, y 1 x 1 If it is more than This is preferable because it can provide stable electrical characteristics to the transistor. 1 x 1 More than three times If the y 1 x 1 Less than three times It is preferable that the oxide semiconductor layer 108a and the oxide semiconductor layer 108c have the above-described structure. By this, the oxide semiconductor layer 108a and the oxide semiconductor layer 108c can be formed as oxide semiconductor layers. This layer can be made less susceptible to oxygen deficiency than the conductor layer 108b.

[0098] Note that the oxide semiconductor layer 108a and the oxide semiconductor layer 108c are made of In-M-Zn oxide. The atomic ratio of In and M when the sum of In and M is 100 atomic % is preferably Preferably, In is less than 50 atomic % and M is 50 atomic % or more, and more preferably In is less than 25 atomic % and M is 75 atomic % or more. The conductor layer 108b is an In-M-Zn oxide, and the sum of In and M is 100 atomic %, the atomic ratio of In and M is preferably 25 atomic % or more of In and 25 atomic % or more of M. 75 atomic %, more preferably In is 34 atomic % or more and M is 66 atomic % or more. tomic% or less.

[0099] For example, the oxide semiconductor layer 108a containing In or Ga and the oxide semiconductor layer 108b containing In or Ga The compound semiconductor layer 108c has a composition of In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, In-Ga formed using targets with atomic ratios of 1:6:4 or 1:9:6 - Using targets with an atomic ratio of Zn oxide, In:Ga=1:9, or 7:93 In addition, the oxide semiconductor layer 108b can be formed by forming an In—Ga oxide film on the oxide semiconductor layer 108c. For example, a target with an atomic ratio of In:Ga:Zn=1:1:1 or 3:1:2 is used. The In-Ga-Zn oxide formed by using a ZnO thin film can be used. The atomic ratios of the oxide semiconductor layer 108a, the oxide semiconductor layer 108b, and the oxide semiconductor layer 108c are Each of these includes a margin of error of ±20% from the atomic ratios listed above.

[0100] In order to give stable electrical characteristics to a transistor including the oxide semiconductor layer 108, The oxide semiconductor layer 108 is then highly purified and intrinsic by reducing impurities and oxygen vacancies in the oxide semiconductor layer 108. It is preferable that the semiconductor layer 108 be an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. In addition, at least a channel formation region in the oxide semiconductor layer 108 is intrinsic or substantially intrinsic. It is preferable that the semiconductor layer be regarded as such.

[0101] Note that an oxide semiconductor layer that can be regarded as substantially intrinsic is an oxide semiconductor layer having a carrier density of , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 × 10 13 / cm 3 The term "oxide semiconductor layer" refers to an oxide semiconductor layer having a thickness of less than 100 nm.

[0102] Here, the oxide semiconductor layer 108a, the oxide semiconductor layer 108b, and the oxide semiconductor layer 10 The function and effect of the oxide semiconductor layer 108 formed by stacking the layers 8 and 8c will be described with reference to FIG. The energy band structure diagram shown in FIG. 6 is a diagram of the C1-C2 region in FIG. The energy band structure of the area indicated by the dashed line is shown in FIG. 6. 1 shows the energy band structure of the channel formation region of 100.

[0103] In Figure 6, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 are The insulating layer 107, the oxide semiconductor layer 108a, the oxide semiconductor layer 108b, and the oxide semiconductor The energy of the conduction band minimum of the layer 108c and the insulating layer 110 is shown.

[0104] Here, the difference between the vacuum level and the conduction band minimum energy (also called "electron affinity") is The energy difference between the vacant level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap from the spectroscopic ellipsometer ( It can be measured using HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI) It can be measured using a VersaProbe.

[0105] The In-Ga target with an atomic ratio of In:Ga:Zn=1:3:2 was used. The energy gap of a-Zn oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In addition, the In- The energy gap of Ga-Zn oxide is about 3.4 eV and the electron affinity is about 4.5 eV. In addition, the In was formed using a target with an atomic ratio of In:Ga:Zn=1:3:6. The energy gap of Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV. In addition, the I was formed using a target with an atomic ratio of In:Ga:Zn=1:6:2. The energy gap of n-Ga-Zn oxide is about 3.9 eV, and the electron affinity is about 4.3 eV. In addition, the film was formed using a target with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4.4 e V. In addition, a target with an atomic ratio of In:Ga:Zn=1:6:10 was used. The energy gap of the In-Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4. The energy of the target is 5 eV. The atomic ratio of In:Ga:Zn is 1:1:1. The energy gap of the synthesized In-Ga-Zn oxide is about 3.2 eV, and the electron affinity is about 4 .7 eV. In addition, a target with an atomic ratio of In:Ga:Zn=3:1:2 was used. The energy gap of the formed In-Ga-Zn oxide is about 2.8 eV, and the electron affinity is about It is 5.0 eV.

[0106] Since the insulating layer 107 and the insulating layer 110 are insulators, Ec382 and Ec386 are Closer to the vacuum level (lower electron affinity) than 3a, Ec383b, and Ec383c .

[0107] Also, Ec383a is closer to the vacuum level than Ec383b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0108] Also, Ec383c is closer to the vacuum level than Ec383b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 It is preferably above 0.15 eV and below 2 eV, 1 eV, 0.5 eV or 0.4 eV and close to the vacuum level. Preferably, it is close to the vacuum level.

[0109] In the vicinity of the interface between the oxide semiconductor layer 108a and the oxide semiconductor layer 108b, and in the vicinity of the interface between the oxide semiconductor layer 108b and the oxide semiconductor layer 108c, a mixed region is formed, so that the energy at the lower end of the conduction band changes continuously. That is, at these interfaces, there are no or almost no levels.

[0110] Therefore, in the stacked structure having the energy band structure, electrons mainly move through the oxide semiconductor layer 1 08b. Therefore, even if there are levels at the interface between the oxide semiconductor layer 108a and the insulating layer 10 7, or at the interface between the oxide semiconductor layer 108c and the insulating layer 110, such levels hardly affect the movement of electrons. Also, there are no or almost no levels at the interface between the oxide semiconductor layer 108a and the oxide semiconductor layer 108b, and at the interface between the oxide semiconductor layer 108c and the oxide semiconductor layer 1 08b, so the movement of electrons is not inhibited in this region. Therefore, the transistor 10 having the stacked structure of the above oxide semiconductor can achieve high field-effect mobility. That is, high field-effect mobility can be achieved.

[0111] As shown in FIG. 6, near the interfaces between the oxide semiconductor layer 108a and the insulating layer 107, and between the oxide semiconductor layer 108c and the insulating layer 110, trap levels 390 caused by impurities and defects may be formed. However, since there are the oxide semiconductor layers 108a and 108c the oxide semiconductor layer 108b can be separated from the trap levels. That is, the oxide semiconductor layer 108b can be separated from the trap levels.

[0112] In particular, the transistor 100 illustrated in this embodiment has an oxide The top surface and side surfaces of the semiconductor layer 108b are in contact with the oxide semiconductor layer 108c. The bottom surface of the insulating film b is in contact with the oxide semiconductor layer 108a (see FIG. 1C). In this manner, the oxide semiconductor layer 108b is divided into the oxide semiconductor layer 108a and the oxide semiconductor layer 108c. By using a covering structure, the influence of the trap levels can be further reduced.

[0113] However, if the energy difference between Ec383a or Ec383c and Ec383b is small, In this case, electrons in the oxide semiconductor layer 108b exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating layer. This causes the threshold voltage of the transistor to shift in the positive direction.

[0114] Therefore, the energy difference between Ec383a and Ec383c and Ec383b is When each of these is set to 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage of the transistor is Since the voltage fluctuation is reduced and the electrical characteristics of the transistor can be improved, I wish.

[0115] The band gaps of the oxide semiconductor layers 108a and 108c are It is preferable that the band gap is wider than that of the nitride semiconductor layer 108b.

[0116] [Oxide semiconductors] An oxide semiconductor that can be used for the oxide semiconductor layer 108 will be described in detail below.

[0117] Applicable to the oxide semiconductor layer 108a, the oxide semiconductor layer 108b, and the oxide semiconductor layer 108c The oxide semiconductor is, for example, an oxide containing indium. This increases carrier mobility (electron mobility).

[0118] However, the oxide semiconductor is not limited to an oxide containing indium. For example, zinc tin oxide and gallium tin oxide may be used.

[0119] In addition, oxide semiconductors are made of oxides with a large energy gap. The energy gap is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more. It is set to 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0120] The effect of impurities in an oxide semiconductor will be described below. In order to stabilize the electrical characteristics of the oxide semiconductor, it is necessary to reduce the impurity concentration in the oxide semiconductor and to achieve a low carrier density. It is effective to increase the carrier density of oxide semiconductors by 1× 10 17 pieces / cm 3 Less than 1×10 15 pieces / cm 3 Less than or equal to 1 × 10 13 pieces / cm 3 In order to reduce the impurity concentration in the oxide semiconductor, the impurity concentration in the adjacent film is It is preferable to also reduce the intensity.

[0121] For example, silicon in an oxide semiconductor can become a carrier trap or a carrier generation source. Therefore, the silicon between the oxide semiconductor and the insulating layer 107 and the insulating layer 110 is The concentration of ions was measured by secondary ion mass spectrometry (SIMS). Spectrometry) is 1×1019 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 less than 2×10 18 atoms / c m 3 Less than.

[0122] The structure of an oxide semiconductor will be described below.

[0123] Oxide semiconductors are classified into, for example, non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Alternatively, oxide semiconductors can be divided into crystalline oxide semiconductors and amorphous oxide semiconductors, for example. Non-single-crystal oxide semiconductors are called CAAC-OS (C Axis Aligned C rystalline Oxide Semiconductor), polycrystalline oxide semiconductor In addition, crystalline oxide semiconductors and Examples of the oxide semiconductors include single-crystalline oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors. There are bodies, etc.

[0124] CAAC-OS First, let me explain about CAAC-OS.

[0125] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0126] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of CAAC-OS were obtained by using a high-resolution microscope. By observing the TEM image, multiple pellets can be confirmed. On the other hand, the high-resolution TEM image also clearly shows the boundaries between pellets, i.e., grain boundaries. Therefore, CAAC-OS cannot check the boundary between the It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0127] For example, as shown in FIG. 7(A), the cross section of the CAAC-OS is A high-resolution TEM image is observed. Here, spherical aberration correction is used. The TEM image is observed using the Spherical Aberration Corrector function. Hereinafter, the high-resolution TEM image using the correction function will be specifically referred to as the Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM images were obtained using, for example, an atomic resolution analyzer manufactured by JEOL Ltd. This can be done using a deposition electron microscope such as the JEM-ARM200F.

[0128] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 7(A) is shown in Figure 7(B). From (B), it can be seen that the metal atoms are arranged in layers in the pellet. Each layer of atoms is a concave surface of the CAAC-OS film-forming surface (also called a surface on which the film is to be formed) or a concave surface of the top surface. The shape reflects a convexity and is arranged parallel to the surface on which the CAAC-OS is formed or the upper surface.

[0129] In FIG. 7(B), CAAC-OS has a characteristic atomic arrangement. The atomic arrangement of the Pellet is shown by auxiliary lines. The size of each pellet is about 1 nm to 3 nm, and the size varies depending on the inclination of the pellets. It can be seen that the size of the gap that occurs is about 0.8 nm. They can also be called nanocrystals (nc).

[0130] Here, from the Cs-corrected high-resolution TEM image, the pellet 5 of CAAC-OS on the substrate 5120 was A schematic diagram of the arrangement of 100 would resemble a pile of bricks or blocks. (See Fig. 7(D)). The pellets in Fig. 7(C) are tilted. The portion corresponds to the region 5161 shown in FIG.

[0131] For example, as shown in FIG. 8(A), the CAAC-OS Observe the Cs-corrected high-resolution TEM image of the plane. The Cs-corrected high-resolution TEM images of area (1) and area (2) enlarged are shown in Fig. 8(B) and Fig. 8(C), respectively. and Fig. 8(D). From Fig. 8(B), Fig. 8(C) and Fig. 8(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0132] For example, X-ray diffraction (XRD) of CAAC-OS with InGaZnO4 crystals Using the out-of-plane method with a 3D ray diffraction (RF) device, When structural analysis was performed, a peak appeared at a diffraction angle (2θ) of about 31°, as shown in Figure 9(A). This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the CAAC-OS crystal has a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the CAAC-OS is formed or the upper surface. You can see that it is facing the right direction.

[0133] In addition, InGaZnO 4 The out-of-plane method of CAAC-OS with crystals In the structural analysis by NMR, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° may be due to the c-axis orientation in some CAAC-OS. This indicates that the CAAC-OS contains crystals that do not have a peak at 2θ of around 31°. It is preferable that the compound exhibits a peak at 2θ of about 36° and does not exhibit a peak at 2θ of about 36°.

[0134] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In GaZnO 4 In the case of CAAC-OS, the 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. 9(B). , InGaZnO 4 In the case of a single crystal oxide semiconductor, 2θ is fixed at around 56° and φ is When the ion beam was scanned, a peak was observed that was assigned to a crystal plane equivalent to the (110) plane, as shown in FIG. Therefore, the structure analysis using XRD shows that CAAC-OS has a-axis It can be seen that the orientation of the b axis is irregular.

[0135] Next, the In-Ga-Zn oxide CAAC-OS was subjected to a plasmon resonance in a direction parallel to the sample surface. Diffraction pattern when an electron beam with a lobe diameter of 300 nm is incident (selected area transmission electron diffraction The pattern is shown in FIG. 10(A). O 4 The spots due to the (009) plane of the crystal are confirmed. However, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed or the On the other hand, the same sample had a surface perpendicular to the sample surface. The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident from the direction is shown in Fig. 10(B ) is shown. From FIG. 10(B), a ring-shaped diffraction pattern is confirmed. Therefore, Diffraction analysis also revealed that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. It can be seen that the first ring in FIG. 10(B) is made of InGaZnO 4 Crystal This is thought to be due to the (010) and (100) planes. The second ring is thought to be due to the (110) plane.

[0136] In this way, the c-axis of each pellet (nanocrystal) is approximately perpendicular to the surface on which the pellet is formed or the top surface. Because of the direction, CAAC-OS is aligned with CANC (C-Axis Aligned The oxide semiconductor may also be referred to as an oxide semiconductor having nanocrystals.

[0137] CAAC-OS is an oxide semiconductor with a low concentration of impurities. The impurities are hydrogen, carbon, and silicon. Elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. The elements that bond with oxygen more strongly than the metal elements that make up the oxide semiconductor are The removal of oxygen from the oxide semiconductor disrupts the atomic arrangement of the oxide semiconductor, which is a factor in reducing the crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular radii). Since the radius of the oxide semiconductor is large, when the oxide semiconductor is contained in the oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed. Impurities contained in an oxide semiconductor can cause carrier transport and lead to a decrease in crystallinity. These may be sources of tripping or carrier generation.

[0138] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Oxygen deficiencies in the body act as carrier traps or capture hydrogen to reduce the amount of carriers. It can be a source of pollution.

[0139] In addition, transistors using CAAC-OS show changes in their electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0140] <<Microcrystalline oxide semiconductor>> Next, a microcrystalline oxide semiconductor will be described.

[0141] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often found. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline- In addition, nc-OS is a In high-resolution TEM images, the grain boundaries may not be clearly visible. It is possible that the pellets in AAC-OS have the same origin. Therefore, in the following, The crystalline part of c-OS is sometimes called a pellet.

[0142] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peaks are detected. Also, nc-OS is not detectable with a probe diameter larger than the pellet (e.g. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a diameter of 50 nm or more, A halo-like diffraction pattern is observed. On the other hand, pellet-like diffraction patterns are observed for nc-OS. The probe diameter is close to or smaller than the pellet (e.g., 1 nm to 30 nm). When electron diffraction using an electron beam (hereinafter also referred to as nanobeam electron diffraction) is performed, the spot In addition, when nanobeam electron diffraction was performed on the nc-OS, a circular (ripple) pattern was observed. In addition, when the nanobeam is applied to the nc-OS, a bright area may be observed. When electron diffraction is performed, multiple spots may be observed within the ring-shaped region.

[0143] In this way, the crystal orientation of each pellet (nanocrystal) is not regular. nc-OS has NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0144] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. Therefore, nc-OS is The defect level density is higher than that of AC-OS.

[0145] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0146] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0147] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0148] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. In contrast, when nanobeam electron diffraction is performed, no spots are observed, but a halo pattern is observed. can be.

[0149] There are various views on amorphous structures. For example, A structure that does not have a completely amorphous structure is called a completely amorphous structure. In addition, the distance between the nearest neighbors or the second nearest neighbors is called the A structure that has order but does not have long-range order is sometimes called an amorphous structure. According to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called an amorphous semiconductor. In addition, oxides with at least long-range order cannot be called solid oxide semiconductors. The semiconductor cannot be called an amorphous oxide semiconductor. For example, the CAAC-OS and nc-OS are It cannot be called a compound semiconductor.

[0150] Note that the oxide semiconductor has a structure that exhibits physical properties between the nc-OS and the amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor. (a-like OS:amorphous-like Oxide Semiconductor It is called a uctor.

[0151] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portion can be identified.

[0152] The following describes how the effect of electron irradiation differs depending on the structure of the oxide semiconductor.

[0153] a-like OS (sample A), nc-OS (sample B) and CAAC-OS (sample C) All samples are In-Ga-Zn oxide.

[0154] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0155] In addition, the size of the crystal part of each sample is measured. Figure 11 shows the crystal part of each sample (from 22 points). This is an example of investigating the change in the average size of the 45 locations. It can be seen that the crystal part grows larger according to the cumulative dose of electron irradiation. As shown in (1) in Fig. 11, the size of the particles was about 1.2 nm in the initial stage of TEM observation. The crystal part (also called the initial nucleus) that was initially exposed to a cumulative irradiation dose of 4.2 × 108 e - / nm 2 Smell On the other hand, the size of the nc-OS and C The AAC-OS had a cumulative electron dose of 4.2 × 10 8 e - / nm 2 To It was found that the size of the crystals did not change regardless of the cumulative dose of electron irradiation until the crystals were Specifically, as shown in (2) in Figure 11, the nc-OS was observed by TEM. Regardless of the time course, the size of the crystals is approximately 1.4 nm. As shown in (3) in Figure 11, the size of the crystalline part of the OS changes regardless of the TEM observation process. It can be seen that the thickness is about 2.1 nm.

[0156] In this way, a-like OS can be observed by irradiating it with a small amount of electrons, which is the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, good quality nc-OS and In the case of CAAC-OS, crystallization due to minute electron irradiation, which is comparable to that observed with a TEM, is hardly observed. You can see that it cannot be seen.

[0157] The size of the crystalline parts of the a-like OS and nc-OS was measured using high-resolution TEM. For example, InGaZnO 4 The crystal of In has a layered structure. There are two Ga-Zn-O layers between the InGaZnO 4 The unit cell of the crystal is It has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is determined by the lattice of the (009) plane. This is approximately the same as the interplanar spacing (also called the d value), and the value was determined to be 0.29 nm from crystal structure analysis. Therefore, we focused on the lattice fringes in high-resolution TEM images and investigated the In the area where the thickness is between 0.28 nm and 0.30 nm, each lattice fringe is InGaZ nO 4 This corresponds to the ab plane of the crystal.

[0158] In addition, the density of an oxide semiconductor may differ depending on the structure. For example, If the composition of is known, the density of the single crystal of the same composition can be compared to that of the said composition. The structure of the oxide semiconductor can be estimated. For example, the density of a single crystal is e The density of OS is 78.6% or more and less than 92.3%. For example, the density of a single crystal is In contrast, the density of the nc-OS and CAAC-OS was 92.3% or more and less than 100%. Note that an oxide semiconductor having a density of less than 78% of that of a single crystal can be formed by film formation. The body is difficult.

[0159] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor that satisfies the [numerical ratio], single crystal InGaZnO with a rhombohedral crystal structure 4 of Density is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1[ In the case of an oxide semiconductor that satisfies the atomic ratio, the density of the a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1:1 [ In the oxide semiconductor that satisfies the [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are is 5.9g / cm 3 More than 6.3g / cm 3It will be less than.

[0160] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. However, the density should be calculated using as few types of single crystals as possible. It is preferable to perform the calculation in combination.

[0161] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a compound semiconductor and a CAAC-OS.

[0162] Oxide semiconductors, which have low impurity concentrations and low defect state densities (few oxygen vacancies), have carrier Therefore, such an oxide semiconductor can be used as a high-purity intrinsic or The a-type oxide semiconductor is essentially a highly pure intrinsic oxide semiconductor. The impurity concentration is lower than that of OS-like and amorphous oxide semiconductors, and the density of defect states is lower. That is, a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor is likely to be obtained. In the case of a transistor using the CAAC-OS or nc-OS, the threshold voltage is negative. In addition, the high purity intrinsic or In reality, high-purity intrinsic oxide semiconductors have few carrier traps. Transistors using C-OS or nc-OS have small fluctuations in electrical characteristics and are highly reliable. The charge trapped in the carrier traps in the oxide semiconductor is It takes a long time for the charge to be released, and it can behave as if it were a fixed charge. Therefore, a transistor using an oxide semiconductor with a high impurity concentration and a high density of defect states has a low current density. The electrical characteristics may become unstable.

[0163] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0164] FIG. 12A shows how a CAAC-OS film is formed by a sputtering method. FIG.

[0165] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnet. The magnetic field of the magnet is used to increase the deposition speed. The sputtering method is called magnetron sputtering.

[0166] The target 5130 has a polycrystalline structure, with each grain including a cleavage plane.

[0167] As an example, the cleavage surface of a target 5130 having an In-Ga-Zn oxide is described. FIG. 13A shows InGaZnO contained in the target 5130. 4 The crystal structure of In FIG. 13(A), the c-axis is oriented upward, and the InGaZnO 4 This is the structure of the crystal when observed.

[0168] As shown in FIG. 13(A), the oxide in each of the two adjacent Ga-Zn-O layers is It can be seen that the atomic groups are arranged close to each other. And the oxygen atom has a negative charge. As a result, the two adjacent Ga-Zn-O layers repel each other. ZnO 4 The crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0169] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d ( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the deposition chamber is set to 0.02m or more and 0.5m or less. Most of the deposition gas (e.g., oxygen) is The chamber is filled with a gas mixture containing 5% or more by volume of nitrogen, argon, or oxygen. The pressure is controlled to be 0.1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, discharge begins and plasma is generated. It is noted that a high-density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 are generated. The ions 5101 are, for example, positive oxygen ions (O + ) and argon cations (A r + ) etc.

[0170] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually reach the target 5130. At this time, flat or pellet-shaped sputter particles are ejected from the cleavage surface. The pellets 5100a and 5100b are peeled off and knocked out. 5100a and pellet 5100b are structured by the impact of the collision of ion 5101. Distortion may occur.

[0171] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example equilateral, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, planar surface. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5 The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may have a shape that is made up of multiple triangles. In some cases, the shape may be two squares (for example, a diamond).

[0172] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferred over thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The diameter of the pellet 5100 is 1.2 nm or more and 2.5 nm or less. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the Ga-Zn-O layer 30, as shown in FIG. A pellet 5100 having three layers, an In-O layer, a Ga-Zn-O layer, and a Ga-Zn-O layer, is ejected. FIG. 13(C) shows the structure of the pellet 5100 when observed from a direction parallel to the c-axis. Therefore, the pellet 5100 is composed of two Ga-Zn-O layers (pans) and an In- It can also be called a nano-sized sandwich structure having a layer (filling) and a layer (filling).

[0173] The pellet 5100 receives an electrical charge as it passes through the plasma, causing the sides to become negative or positive. The pellet 5100 has oxygen atoms on the side, and the oxygen atoms are negatively charged. In this way, the sides can be charged with the same polarity, The repulsion between the particles occurs, allowing the particles to maintain their flat shape. However, in the case of In-Ga-Zn oxide, the oxygen atom bonded to the indium atom is negatively charged. Or, an acid bonded to an indium atom, a gallium atom, or a zinc atom may The elementary atoms may become negatively charged. Also, the pellet 5100 may become charged as it passes through the plasma. It grows by bonding with indium atoms, gallium atoms, zinc atoms, oxygen atoms, etc. The difference in size between (2) and (1) in Figure 11 above is due to the growth in the plasma. Here, when the substrate 5120 is at room temperature, the pellet 5100 is Since the film does not grow on the substrate, it becomes nc-OS (see Fig. 12(B)). The film can be formed at room temperature. Therefore, even if the substrate 5120 has a large area, the nc-OS can be formed. In order to grow the pellet 5100 in plasma, the sputtering method It is effective to increase the deposition power. By increasing the deposition power, the pellet 5100 The structure can be stabilized.

[0174] As shown in FIG. 12(A) and FIG. 12(B), for example, a pellet 5100 is It flies like a kite through the air and flutters up to the top of the substrate 5120. Pellet 51 Since the 00 is electrically charged, it approaches an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120. The magnetic field and the electric current act on the object, resulting in a force (Lorentz force). This is what Fleming This can be understood by the left-hand rule.

[0175] The pellet 5100 has a large mass compared to a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of a field and an electric current. In order to increase the size of the substrate 5120, the substrate 5120 is The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably It is preferable to provide an area where the resistance is 50 G or more. The magnetic field parallel to the top surface of the substrate 5120 is 1.5 times that of the magnetic field perpendicular to the top surface of the substrate 5120. fold or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more. It is a good idea to provide an area for this purpose.

[0176] At this time, the magnet and the substrate 5120 move or rotate relatively to each other. Thus, the orientation of the horizontal magnetic field on the top surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces in various directions and is moved in various directions. Can be moved.

[0177] Also, when the substrate 5120 is heated as shown in FIG. 12(A), the pellet 5100 The resistance due to friction between the substrate 5120 and the substrate 5120 is small. The pellet 5100 glides over the upper surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches the side of the pellet, the sides of the pellet 5100 are joined together. The oxygen atom on the side of 0 is removed. The removed oxygen atom causes the acid in CAAC-OS to be Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. or 170° C. or more and less than 400° C. That is, when the substrate 5120 has a large area, In this case, it is possible to form a CAAC-OS film.

[0178] In addition, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged and the The structural distortion caused by the collision of the pellet 5101 is relaxed. Pellet 5100 becomes almost a single crystal, so pellet 5 Even if the 100 are heated after bonding, the pellet 5100 itself hardly expands or contracts. This is not possible. Therefore, the gaps between the pellets 5100 may widen, causing defects such as grain boundaries. It does not form depressions or crevasses.

[0179] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The aggregates of Pellet 5100 (nano crystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between them. Even if CAAC-OS is deformed, such as shrinking, by heating or bending, the local stress Therefore, it is possible to reduce the stress or release the strain. The structure of nc-OS is suitable for biological devices. The arrangement is like something stacked in order.

[0180] When the target is sputtered with ions, not only pellets but also zinc oxide and other substances fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And, 0.1 nm to 10 nm, 0.2 nm to 5 nm, or 0.5 A zinc oxide layer 5102 having a thickness of 2 nm or more is formed. A schematic cross-sectional view is shown in FIG.

[0181] As shown in FIG. 14(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the pellet 5105b slides on the pellet 5105b. In another aspect of 5a, a plurality of particles 510 ejected from the target along with zinc oxide. The substrate 5120 is heated to crystallize the region 5105a1. The element 5103 may include oxygen, zinc, indium, gallium, and the like.

[0182] Then, as shown in FIG. 14(B), the region 5105a1 is assimilated with the pellet 5105a. The pellet 5105c is formed by cutting the pellet 5105a1 at its side. Place it so that it touches the other side of 05b.

[0183] Next, as shown in FIG. 14(C), a pellet 5105d is further formed on the pellet 5105a2. and pellet 5105b, and then pellet 5105a2 and pellet 51 It slides on the pellet 5105b. It also slides towards the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0184] As shown in FIG. 14(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is arranged so that its side surface is in contact with the pellet 5105a. Also, the other side of the pellet 5105d is arranged so as to contact the other side of the pellet 5105c. In the process, a plurality of particles 5103 that fly out of the target together with zinc oxide are deposited on the substrate 512. Heating at 0 causes crystallization, forming region 5105d1.

[0185] As described above, the piled up pellets are arranged so that they come into contact with each other, and the pellets are formed on the side surfaces. As a result of this growth, a CAAC-OS is formed on the substrate 5120. The individual pellets of C-OS are larger than those of nc-OS. The difference in size between (1) and (2) corresponds to the growth that occurred after deposition.

[0186] In addition, the gaps between the pellets 5100 become extremely small, so that one large pellet is formed. The large pellets may have a single crystal structure. The size is 10 nm to 200 nm, 15 nm to 100 nm, or In some cases, the thickness of the transistor channel may be between 20 nm and 50 nm. When the formation region is smaller than a large pellet, it has a single crystal structure as the channel formation region. In addition, the pellet size is increased, so that the transistor chip size can be increased. A region having a single crystal structure is used as the channel forming region, the source region, and the drain region. It may be possible.

[0187] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0188] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. Therefore, unlike epitaxial growth, if the surface on which the film is to be formed does not have a crystal structure, For example, the CAAC-OS film can be formed on the substrate 5120. Even if the structure of the upper surface (the surface to be formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form a film of C-OS.

[0189] In addition, the CAAC-OS can be used even if the upper surface of the substrate 5120 on which the formation is to be performed is uneven. For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed with the flat surface, which is parallel to the ab plane, facing down. When the pellet 5100 has a uniform thickness, the pellets 5100 are arranged side by side facing each other. A layer with high crystallinity is formed. The layers are then stacked in n layers (n is a natural number). Thus, CAAC-OS can be obtained.

[0190] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510. The structure is made up of n layers (n is a natural number) of layers with 0s arranged along the unevenness. Since the surface of the CAAC-OS is uneven, gaps may easily occur between the pellets. However, there are cases where intermolecular forces act between the pellets, and even if there are irregularities, the The gaps are arranged to be as small as possible. Therefore, even if there are irregularities, high crystallinity is maintained. It can be called CAAC-OS.

[0191] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if there is any, a uniform film can be formed.

[0192] Since the CAAC-OS film is formed by such a model, the sputtered particles have a thin film thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0193] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface with an amorphous structure. It is possible to obtain a CAAC-OS having the formula:

[0194] FIG. 15(A) is a high-resolution TEM image of the cross section of the CAAC-OS film. ) is a high-resolution TEM image of the cross section of FIG. 15(A) that is enlarged for easier understanding. The atomic arrangement is highlighted for ease of understanding.

[0195] FIG. 15(C) shows the area surrounded by a circle (diameter approximately 4n m) are local Fourier transform images. From Fig. 15(C), it is clear that the c-axis orientation is In addition, the orientation of the c-axis is different between the AO and O-A' sections, so different gradients are observed. In addition, the c-axis angles between the A and A are 14.3° and 16.6°. 26.4°, and so on. Similarly, O-A' Between these, the c-axis angle changes gradually and continuously from -18.3° to -17.6° to -15.9°. It is clear that the

[0196] The high-resolution TEM images of the cross section and the plan view show that the crystalline part of the CAAC-OS film It can be seen that the film has an orientation.

[0197] Most of the crystals in the CAAC-OS film are cubes with sides of less than 100 nm. Therefore, the crystal part in the CAAC-OS film has a side length of 10n This also includes cases where the size fits within a cube of less than 100 mm, less than 5 nm, or less than 3 nm. In addition, multiple crystals in the CAAC-OS film are connected to form a single large crystal region. For example, in a high-resolution TEM image of a plane, 2 End , 5 μm 2 More than or equal to 1000μm 2 In some cases, crystal regions having more than this amount may be observed.

[0198] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, it is clear that the orientation of the nuclei is consistent with that confirmed by the high-resolution TEM observation of the cross section mentioned above. Each layer of metal atoms arranged in layers is parallel to the ab plane of the crystal.

[0199] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0200] Furthermore, the distribution of c-axis oriented crystal parts in the CAAC-OS film does not need to be uniform. For example, the crystals in the CAAC-OS film grow from the top surface of the CAAC-OS film. When the crystal is formed by the above method, the region near the top surface has more c-axis oriented crystals than the region near the surface on which the crystal is formed. In addition, the CAAC-OS film containing impurities may have a high ratio of impurities. The doped region changes and regions with different proportions of c-axis oriented crystals are formed. This sometimes happens.

[0201] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, a microcrystalline oxide semiconductor, or a CAAC- Two or more of the OS may be included.

[0202] When an oxide semiconductor has multiple structures, the structure can be analyzed by using nanobeam electron diffraction. It may be possible.

[0203] FIG. 16C shows an electron gun chamber 1010, an optical system 1012 below the electron gun chamber 1010, and an optical A sample chamber 1014 below the system 1012, an optical system 1016 below the sample chamber 1014, and an optical system 1 10, an observation room 1020 under the observation room 1016, a camera 1018 installed in the observation room 1020, and The transmission electron diffraction measurement apparatus has a film chamber 1022 below the camera 1020. 018 is installed facing the inside of the observation room 1020. It's okay if not.

[0204] FIG. 16(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in FIG. 16(C). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 1010 The light is irradiated via an optical system 1012 onto a substance 1028 disposed in a sample chamber 1014 . The electrons that have passed through the material 1028 are guided through the optical system 1016 to the observation chamber 1020. The electrons are incident on the fluorescent screen 1032, which detects a pattern according to the intensity of the incident electrons. The appearance of the diffraction patterns allows the measurement of the transmission electron diffraction pattern.

[0205] The camera 1018 is installed facing the fluorescent screen 1032 and captures the pattern that appears on the fluorescent screen 1032. The center of the lens of the camera 1018 and the fluorescent screen 10 The angle between the line passing through the center of the fluorescent screen 1032 and the upper surface of the fluorescent screen 1032 is, for example, 15° to 80°. 30° or less, 30° to 75° or 45° to 70°. The smaller the angle, the better. However, the transmission electron diffraction pattern captured by the camera 1018 is significantly distorted. If the angle is known in advance, it is possible to correct distortions in the obtained transmission electron diffraction pattern. It is also possible to install the camera 1018 in the film chamber 1022. For example, the camera 1018 is placed in a film chamber 1022 facing the direction of incidence of the electrons 1024. In this case, the transmitted electrons with little distortion are guided from the rear surface of the fluorescent screen 1032. The diffraction pattern can be photographed.

[0206] A holder for fixing a sample material 1028 is installed in the sample chamber 1014. The holder is constructed to be transparent to electrons passing through the material 1028. For example, it may have a function of moving the substance 1028 in the X-axis, Y-axis, Z-axis, etc. The movement function of the ruler is, for example, 1 nm to 10 nm, 5 nm to 50 nm, 10 nm m or more and less than 100 nm, 50 nm or more and less than 500 nm, 100 nm or more and less than 1 μm, etc. These ranges are determined by the structure of the material 1028. An appropriate range can be set.

[0207] Next, the transmission electron diffraction pattern of the material is measured using the above-mentioned transmission electron diffraction measurement device. The method will be explained.

[0208] For example, as shown in FIG. 16(D), the irradiation position of the electron 1024, which is a nanobeam, in the material By changing the position (scanning), it is possible to observe how the structure of a material changes. In this case, if the substance 1028 is CAAC-OS, as shown in FIG. If the material 1028 is nc-OS, the diffraction pattern shown in FIG. A diffraction pattern like that shown in B) is observed.

[0209] By the way, even if substance 1028 is CAAC-OS, it may be partially nc-OS, etc. Therefore, the quality of CAAC-OS can be judged by the The ratio of the area where the diffraction pattern of CAAC-OS is observed in a certain range (CAAC ratio) For example, a good CAAC-OS can be expressed as: The CAAC ratio is 60% or more, preferably 80% or more, more preferably 90% or more. More preferably, the diffraction pattern is 95% or more. The area where this occurs is referred to as the non-CAAC rate.

[0210] As an example, CAAC-O immediately after formation (denoted as as-depo) and after heat treatment at 450°C The top surface of each sample having S was scanned to obtain a transmission electron diffraction pattern. In this study, the diffraction pattern was observed while scanning at a speed of 5 nm / sec for 60 sec. The CAAC conversion rate was calculated by converting the diffraction pattern into still images every 0.5 seconds. The electron beam used was a nanobeam with a probe diameter of 1 nm.

[0211] The CAAC ratio for each sample is shown in Figure 17. The CAAC ratio after heat treatment at 450°C is It can be seen that the CAAC conversion rate is high. In other words, the non-CAAC conversion rate is high by heat treatment at 450℃ or higher. It can be seen that the CAAC-OS conversion rate is lower (the CAAC conversion rate is higher). Most of the diffraction patterns were similar to those of nc-OS. By heat treatment, the regions with a structure similar to that of nc-OS are influenced by the structure of the neighboring regions. This suggests that it has become a CAAC in response to this.

[0212] By using such a measurement method, it is possible to analyze the structure of oxide semiconductors having multiple structures. There may be cases where this occurs.

[0213] In this embodiment, the oxide semiconductor layer 108 is used. One aspect of the present invention is not limited to this. In some cases or depending on the situation, an oxide semiconductor Instead of the semiconductor layer 108, a semiconductor film having another material may be used. For example, In the region, the source / drain region, the LDD region, and the like, instead of the oxide semiconductor layer 108, Semiconductor film containing one or more elements such as silicon, germanium, gallium, arsenic, etc. may also be used.

[0214] [A-8: Electrode 109, Electrode 119] The electrodes 109 and 119 are the electrodes 102a, 103a, and 104a, as well as and are formed of the same material and by the same method as electrodes 102b, 103b, and 104b. It is possible.

[0215] At least the portions of the electrode 109 and the electrode 119 in contact with the oxide semiconductor layer 108b It is preferable to use an oxygen-impermeable conductive material. By providing the oxide semiconductor layer 108 in contact with at least the oxide semiconductor layer 108b, This can make it difficult for oxygen contained in the electrode 109 and the electrode 119 to diffuse to the electrode 109 and the electrode 119 .

[0216] [A-9: Insulating layer 110] The insulating layer 110 can be formed using the same material and method as the insulating layer 105 .

[0217] The insulating layer 110 is, for example, a silicon nitride layer as a first layer and a silicon oxide layer as a second layer. A multi-layer film may be used. In this case, the silicon oxide layer may be a silicon oxynitride layer. The silicon nitride layer may be a silicon oxynitride layer. It is preferable to use a silicon oxide layer with a small ESR g value of 2.001. The spin density of the spins originating from the signal is 3×10 17 spins / cm 3 Hereinafter, preferably 5×10 16 spins / cm 3The silicon oxide layer is as follows: The silicon oxide layer preferably contains excess oxygen. The silicon nitride layer contains hydrogen and A silicon nitride layer that releases less hydrogen and ammonia is used. This can be measured by TDS analysis.

[0218] In order to prevent an increase in the hydrogen concentration in the oxide semiconductor, the hydrogen concentration in the insulating layer 110 is reduced. Specifically, the hydrogen concentration of the insulating layer 110 is preferably 2×1 0 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 More details below. Preferably 1 x 10 19 atoms / cm 3 Less than 5×10, more preferably 18 ato ms / cm 3 In order to prevent an increase in the nitrogen concentration in the oxide semiconductor, It is preferable to reduce the nitrogen concentration in the insulating layer 110. Specifically, the nitrogen concentration in the insulating layer 110 is In SIMS, 5×10 19 atoms / cm 3 Less than 5 x 10 18 at oms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 The following are more preferred Or 5×10 17 atoms / cm 3 The following applies.

[0219] In addition, the insulating layer 110 is an insulating layer containing more oxygen than the oxygen required for the stoichiometric composition. It is preferable to form the insulating layer by using an oxygen-rich layer containing more oxygen than the stoichiometric composition. The layer desorbs a part of oxygen upon heating. The insulating layer contains more oxygen than the oxygen that satisfies the stoichiometric composition. The insulating layer containing oxygen more than the oxygen that satisfies the stoichiometric composition has an oxygen desorption amount, in terms of oxygen atoms, of 1.0×10 1 8 atoms / cm 3 or more, preferably 3.0×10 20 atoms / cm 3 or more. It is an insulating layer. Note that, as the surface temperature of the film during the above TDS analysis, a range of 100°C or more and 70 0°C or less, or 100°C or more and 500°C or less is preferable. Also, in this specification and the like, oxygen more than the oxygen that satisfies the stoichiometric composition in the insulating layer is also referred to as "excess oxygen". Also, in this specification and the like, an insulating layer containing more oxygen than the oxygen that satisfies the stoichiometric composition is also referred to as an "insulating layer containing excess oxygen".

[0220] 〔A-10: Electrode 111〕 Electrode 111 can be formed by the same materials and methods as electrode 109 and electrode 119. The thickness of electrode 111 may be 10 nm or more and 500 nm or less, preferably 50 nm or more and 30 0 nm or less.

[0221] 〔A-11: Insulating layer 112〕 Insulating layer 112 can be formed by the same materials and methods as insulating layer 106. The thickness of insulating layer 112 may be 10 nm or more and 500 nm or less, preferably 50 nm or more and 300 nm or less as appropriate.

[0222] <B: Example of manufacturing method of transistor 100 and capacitor element 130> An example of the manufacturing method of transistor 100 will be described using the cross-sectional views shown in FIGS. 2 to 5.

[0223] 〔B-1: Formation of electrode 102, electrode 103, and electrode 104〕 First, electrodes 102a, 103a, and 104a are formed on a substrate 101. A conductive layer (not shown) for forming the electrodes 102b, 103b, and 104b. Each conductive layer is formed by sputtering, CV, etc. It can be formed by using the D method, deposition method, etc.

[0224] For example, when forming a tungsten film as a conductive layer, WF 6 Gas and B 2 H 6 Gas The initial tungsten film is then formed by repeatedly introducing WF 6 Gas and H 2 Gas At this time, tungsten is deposited. 2 H 6 Instead of gas, SiH 4 Using gas This is also fine.

[0225] In this embodiment, the electrodes 102a, 103a, and 104a are formed by As the conductive layer, a tungsten film having a thickness of 150 nm is formed by sputtering. , as a conductive layer for forming the electrodes 102b, 103b, and 104b, A 50 nm thick nitrogen-containing indium gallium zinc oxide film was formed by sputtering. do.

[0226] Next, a portion of each conductive layer is selectively etched using a resist mask to form electrodes. 102, electrode 103, and electrode 104 (other electrodes or wiring formed in the same layer as these) The resist mask is formed by photolithography, printing, inkjet printing, etc. The resist mask can be formed by the inkjet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0227] The etching of each conductive layer may be performed by either dry etching or wet etching. Note that the oxide semiconductor film is etched by a dry etching method. In this case, the capacitively coupled plasma (CCP) is used as the plasma source. Inductively Coupled Plasma (ICP) Coupled Plasma, Electron Cyclotron Resonance (ECR) n Cyclotron Resonance plasma, Helicon wave excited plasma (H WP: Helicon Wave Plasma, Microwave Excited Surface Wave Plasma (S WP: Surface Wave Plasma) can be used. In particular, I CP, ECR, HWP, and SWP can generate high density plasma. The etching performed by the dry etching method (hereinafter also referred to as "dry etching process") is In order to etch the processed shape, the etching conditions (voltage applied to the coil-shaped electrode) were The amount of power, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc. are appropriately adjusted. After etching of each conductive layer is completed, the resist mask is removed (see FIG. 2(A)).

[0228] [B-2: Formation of insulating layer 105] Subsequently, an insulating layer 105 is formed on the electrodes 102, 103, and 104. The layer 105 can be formed by using a sputtering method, a CVD method, an evaporation method, or the like. In particular, the ALD method, MOCVD method, and thermal CVD method do not use plasma, so damage is minimal. It is preferable.

[0229] For example, when a silicon oxide film is formed as the insulating layer 105 by using a thermal CVD method, The xachlorodisilane is adsorbed on the surface to be coated, the chlorine contained in the adsorbed matter is removed, and the oxidizing gas (O 2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0230] For example, when a hafnium oxide film is formed as the insulating layer 105 by using a thermal CVD method, A liquid containing a solvent and a hafnium precursor compound (a hafnium alkoxide solution, typically tetrahydrofuran) is The raw material gas is made by vaporizing tetrakisdimethylamidohafnium (TDMAH), and the oxidizer and And ozone (O 3 ) Two types of gases are used. The chemical formula for NH(CH) is Hf[N(CH 3 ) 2 ] 4 In addition, other material liquids include tetrakis (Ethylmethylamido)hafnium.

[0231] In this embodiment, the insulating layer 105 is a 250 nm thick oxide film formed by plasma CVD. Silicon nitride is formed (see FIG. 2(B)).

[0232] Next, in order to expose the surfaces of the electrodes 102b, 103b, and 104b, Mechanical polishing (CMP: Chemical Mechanical Polishing) process (See FIG. 2(C).) In addition, By carrying out this process, the unevenness of the sample surface is reduced, and the covering properties of the insulating layer and conductive layer that will be formed later are improved. can be increased.

[0233] Here, hydrogen, nitrogen, water in the electrodes 102, 103, 104, and the insulating layer 105 Heat treatment may be performed at a temperature of 300° C. or higher and 800° C. or higher. The treatment time is within 24 hours. Heat treatment for more than 24 hours is not preferred because it reduces productivity.

[0234] There is no particular limitation on the heating device used for the heat treatment. The apparatus may be equipped with a device for heating the object to be treated by heat radiation or heat treatment. For example, an electric furnace or LRTA (Lamp Rapid Thermal Anneal) equipment, GRTA (G Rapid Thermal Annealing (RTA) equipment The LRTA device is a halogen lamp. lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium The treated object is irradiated with light (electromagnetic waves) emitted from lamps such as mercury lamps and high-pressure mercury lamps. The GRTA device is a device that uses high-temperature gas to perform heat treatment. do.

[0235] In particular, when a semiconductor substrate having a semiconductor element provided thereon is used as the substrate 101, In this case, the hydrogen concentration in the substrate 101 can be reduced by performing a heat treatment. is preferred.

[0236] [B-3: Formation of insulating layer 106] Subsequently, an insulating layer 106 is formed on the electrodes 102, 103, 104, and the insulating layer 105. The insulating layer 106 is formed by using a sputtering method, a CVD method, a vapor deposition method, or the like. In particular, the ALD method, MOCVD method, and thermal CVD method do not use plasma. Therefore, it is preferable as it causes less damage.

[0237] For example, when aluminum oxide is formed as the insulating layer 106 by using a thermal CVD method, a raw material gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as TMA); H as an oxidizing agent 2 Two types of gases are used: O and 1. The chemical formula for trimethylaluminum is Al(CH 3 ) 3 In addition, other material liquids include tris(dimethylamido)aluminum. Aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl ethyl-3,5-heptanedionate).

[0238] In this embodiment, the insulating layer 106 is an oxidized aluminum film having a thickness of 50 nm formed by a sputtering method. Forms aluminum.

[0239] Next, a resist mask is used to overlap the electrodes 102, 103, and 104. A part of the insulating layer 106 is selectively etched to leave the electrodes 102b, 103b, and The insulating layer 106 can be etched by a dry etching method or a wet etching method. After etching of the insulating layer 106 is completed, The resist mask is removed (see FIG. 2(D)).

[0240] [B-4: Formation of insulating layer 107] Next, an insulating layer 107 is formed on the electrodes 102, 103, 104, and the insulating layer 106. The insulating layer 107 is formed by using a sputtering method, a CVD method, a vapor deposition method, or the like. In this embodiment, the insulating layer 107 is a 150 nm thick film formed by the CVD method. A silicon oxynitride containing more oxygen than satisfies the stoichiometric composition of m is formed.

[0241] The insulating layer containing excess oxygen can also be formed by performing a process of adding oxygen to the insulating layer. The process of adding oxygen includes heat treatment in an oxygen atmosphere, ion implantation equipment, ion doping equipment, etc. The process can be carried out using an ion doping apparatus or a plasma processing apparatus. As the doping device, an ion doping device having a mass separation function may be used. The gases used for this purpose are: 16 O 2 or 18 O 2 Oxygen gas, nitrous oxide gas, etc. Alternatively, ozone gas or the like can be used. In this specification, the process of adding oxygen is referred to as " This is also called "oxygen doping treatment."

[0242] In addition, CMP processing may be performed to reduce unevenness on the sample surface.

[0243] [B-5: Formation of oxide semiconductor layer 108a and oxide semiconductor layer 108b] Next, the oxide semiconductor layer 11 is formed on the insulating layer 107. 8a, and the oxide semiconductor layer 118b for forming the oxide semiconductor layer 108b ( See Figure 3(A).

[0244] In this embodiment, the oxide semiconductor layer 118a is formed by a sputtering method using In:G Using a target with an atomic ratio of a:Zn=1:3:4, a 20 nm thick In-Ga-Z In addition, the oxide semiconductor layer 118b is formed of In:Ga:Zn=1:1 A 20 nm thick In-Ga-Zn oxide film was formed using a target with an atomic ratio of 1:1. do.

[0245] Next, moisture or hydrogen contained in the oxide semiconductor layers 118a and 118b is removed by The impurities such as these are further reduced to form the oxide semiconductor layer 118a and the oxide semiconductor layer 118b. In order to highly purify the above-mentioned compound, it is preferable to carry out a heat treatment.

[0246] For example, the method may be carried out under a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or an ultra-dry atmosphere. Dry air (measured using a CRDS (cavity ring down laser spectroscopy) type dew point meter The moisture content when the air is cooled should be 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. The oxide semiconductor layer 118a and the oxide semiconductor layer 118b are heated in an atmosphere of air (preferably 10 ppb or less). The conductor layer 118b is subjected to a heat treatment. The oxidizing atmosphere is oxygen, ozone, or nitriding acid. An inert atmosphere is an atmosphere that contains 10 ppm or more of oxidizing gas such as oxygen. The above oxidizing gases are less than 10 ppm, and the atmosphere is filled with nitrogen or rare gases. Be careful.

[0247] In addition, by performing a heat treatment, the oxygen contained in the insulating layer 107 is removed at the same time as the impurities are released. The oxide semiconductor layer 11 is diffused into the oxide semiconductor layer 118a and the oxide semiconductor layer 118b. In this way, oxygen vacancies in the oxide semiconductor layer 8a and the oxide semiconductor layer 118b can be reduced. After heat treatment in a nitrogen atmosphere, oxidizing gas is added at a concentration of 10 ppm or more to replenish the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing 1% or more or 10% or more of oxygen. This may be performed at any time after the formation of the nitride semiconductor layer 118a and the oxide semiconductor layer 118b. For example, after the oxide semiconductor layer 108a and the oxide semiconductor layer 108b are formed, heat treatment is performed. You may go.

[0248] The heat treatment is carried out at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. The treatment time should be within 24 hours. Heat treatment for more than 24 hours will lead to a decrease in productivity. Therefore, it is not desirable.

[0249] Next, the oxide semiconductor layer 118a and the oxide semiconductor layer 118b are formed using a resist mask. The oxide semiconductor layer 108a and the oxide semiconductor layer 108b are selectively etched. At the same time, the exposed insulating layer 107 is slightly etched to form the insulating layer 107 in that region. At this time, the amount of etching of the insulating layer 107 is 20 times the thickness of the insulating layer 107. % or more and 80% or less, and more preferably 30% or more and 70% or less. An insulating layer 107 having a protrusion can be formed (see FIG. 3(B)).

[0250] The oxide semiconductor layer 118a, the oxide semiconductor layer 118b, and the insulating layer 107 are etched as follows: The etching method may be a dry etching method or a wet etching method, or both may be used. After the etching is completed, the resist mask is removed.

[0251] Next, a resist mask is used to form a film overlapping part of the electrode 104b and part of the insulating layer 106. The insulating layer 107 is selectively etched to remove a part of the electrode 104b and the insulating layer 106. A part of the insulating layer 107 is exposed (see FIG. 3(C)). The insulating layer 107 is etched by dry etching. The etching method may be a wet etching method or both. Remove the stain mask.

[0252] [B-6: Formation of electrodes 109 and 119] Next, the electrode 109 and the electrode 11 are formed on the oxide semiconductor layer 118b and the insulating layer 107. A conductive layer for forming the insulating film 9 is formed (not shown). In this embodiment, the conductive layer Then, a tungsten film having a thickness of 100 nm is formed by sputtering.

[0253] Next, a part of the conductive layer is selectively etched using a resist mask to form the electrode 109 and and electrodes 119 (including other electrodes or wiring formed in the same layer as these). The etching of the conductive layer may be performed by either dry etching or wet etching, or both may be used. After that, the resist mask is removed (see FIG. 4(A)).

[0254] In addition, when forming a transistor with an extremely short channel length L, electron beam exposure, EU Suitable for fine line processing such as V (Extreme Ultraviolet) exposure and immersion exposure. A resist mask is formed by the method and an etching process is performed to form the electrode 109. and the electrode 119. As the resist mask, a positive resist is used. By using this, the exposure area can be minimized and throughput can be improved. Using this method, it is possible to fabricate transistors with channel lengths of 30 nm or less. It is possible.

[0255] In addition, the electrodes 109 and 119 (other electrodes or wiring formed in the same layer as these) It is preferable that the end of the end portion of the casing (including the casing) is tapered. The angle θ is set to 80° or less, preferably 60° or less, and more preferably 45° or less.

[0256] In addition, the electrodes 109 and 119 (other electrodes or wiring formed in the same layer as these) By making the cross-sectional shape of the end of the layer (including the staircase) into a multi-step shape, the covering property of the layer to be coated on it is improved. In addition to the electrodes 109 and 119, the end portions of each layer can also be improved. By forming the cross-sectional shape into a forward tapered shape or a stepped shape, the layer formed to cover the end portion is The phenomenon of discontinuity at the edge (step discontinuity) can be prevented, and good covering properties can be achieved. .

[0257] [B-7: Formation of oxide semiconductor layer 108c] Next, an oxide semiconductor layer is formed on the electrode 109, the electrode 119, and the oxide semiconductor layer 108b. An oxide semiconductor layer for forming 108c is formed (not shown).

[0258] In this embodiment, the oxide semiconductor layer for forming the oxide semiconductor layer 108c is made of I Using a target with an atomic ratio of n:Ga:Zn=1:3:4, a 5 nm thick In-Ga -Forms Zn oxide.

[0259] Next, using a resist mask, an oxide semiconductor The oxide semiconductor layer 108c is formed by selectively etching part of the layer (see FIG. 4B). .).

[0260] The oxide semiconductor layer may be etched by either a dry etching method or a wet etching method. After etching is completed, the resist mask is removed.

[0261] [B-8: Formation of insulating layer 110 and electrode 111] Next, the insulating layer 120 is formed on the electrode 109, the electrode 119, and the oxide semiconductor layer 108c. The insulating layer 120 can be formed by using a sputtering method, a CVD method, a vapor deposition method, or the like. In this embodiment, the insulating layer 120 is a 20 nm thick film formed by plasma CVD. A silicon oxynitride is formed.

[0262] Next, the conductive layer 121 is formed over the insulating layer 120. In this embodiment, the conductive layer 121 is Then, a 30 nm thick titanium nitride layer and a 135 nm thick tungsten layer were sputtered on the substrate. The method is as shown in FIG. 4(C).

[0263] Next, a part of the insulating layer 120 and the conductive layer 121 are selectively etched using a resist mask. The insulating layer 110 and the electrode 111 (or other electrodes formed in the same layer) are The insulating layer 120 and the conductive layer 121 are etched by dry etching. The etching method may be a photoresist film or a wet etching method, or both may be used. Remove the mask (see FIG. 5(A)).

[0264] In this case, the insulating layer 120 does not necessarily have to be etched. The diagram is shown in Fig. 29. The plan view and cross-sectional view of the completed product are shown in Fig. 30.

[0265] The insulating layer 120 and the conductive layer 121 are etched simultaneously in a single etching process. Alternatively, after etching of the conductive layer 121 is completed, the etching method may be changed to The insulating layer 120 may be etched using the insulating layer 120 as a mask.

[0266] As shown in FIG. 1C, the transistor 100 has an insulating layer 107 having a protrusion. As a result, the oxide semiconductor layer 108b is electrically surrounded by the electric field of the electrode 111. This structure allows the semiconductor to be electrically surrounded by the electric field of the conductive film. This structure is called the surrounded channel (s-channel) structure. Therefore, a channel may be formed in the entire oxide semiconductor layer 108b (bulk). The s-channel structure allows the drain current of the transistor to be increased. In addition, the electric field of the electrode 111 can oxidize the semiconductor. It is possible to deplete the entire channel formation region formed in the organic semiconductor layer 108b. Therefore, in the s-channel structure, the off-state current of the transistor is further reduced. It is possible.

[0267] [B-9: Formation of insulating layer 112] Subsequently, the insulating layer 112 is formed to cover the electrodes 109, 119, and 111. The insulating layer 112 can be formed by using a sputtering method, a CVD method, a vapor deposition method, or the like. In this embodiment, the insulating layer 112 is a 50 nm thick film formed by sputtering. Aluminum oxide is formed (see FIG. 5(B)).

[0268] Through the above steps, the transistor 100 and the capacitor 130 can be manufactured.

[0269] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. Therefore, a semiconductor device with excellent performance can be realized.

[0270] In addition, the band gap of oxide semiconductors is 2 eV or more, so A transistor that uses an oxide semiconductor for its dielectric layer has a low leakage current when the transistor is in an off state. The off-state current (also called the off-state current) can be made extremely small. The off-state current per 1 μm width is 1×10 at room temperature. -20 Less than A, preferably 1×10 -22 A, more preferably less than 1×10 -24 It can be less than A. That is, The on / off ratio can be between 20 and 150 digits.

[0271] According to one embodiment of the present invention, a transistor with low power consumption can be realized. As a result, a semiconductor device with low power consumption can be realized.

[0272] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0273] (Embodiment 2) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is A semiconductor device (memory device) that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. An example of the device will be described with reference to the drawings.

[0274] FIG. 18A shows a cross-sectional view of the semiconductor device, and FIG. 18B shows a circuit diagram of the semiconductor device. show.

[0275] The semiconductor device shown in FIG. 18(A) and FIG. 18(B) is a transistor using a substrate 700 at the bottom. A transistor 100 having a transistor 750 and an oxide semiconductor therein, and a capacitor Note that in the circuit diagram, the transistor 100 is a transistor using an oxide semiconductor. To clearly indicate that it is a transistor, the notation "OS" is added.

[0276] The substrate 700 may be a single crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. Conductor substrates, compound semiconductor substrates made of silicon germanium, etc., and SOI (Silic A semiconductor substrate such as a silicon-on-insulator substrate can be used. The formed transistors are easy to operate at high speed.

[0277] In this embodiment, a p-type single crystal silicon substrate is used as the substrate 700. The transistor 750 is a transistor in which a channel is formed in the substrate 700. The transistor 750 includes a channel forming region 753, an LDD (Lightly Doped Drain) region and the n-type impurity region 754 which functions as an extension region, An n-type impurity region 755 functioning as a drain region, an insulating layer 752, and an electrode 751 The electrode 751 functions as a gate electrode. The insulating layer 752 functions as a gate insulating layer. The impurity concentration of the n-type impurity region 755 is lower than that of the n-type impurity region 754. A sidewall insulating layer 756 is provided on the side surface of the electrode 751. Using the insulating layer 756 as a mask, the n-type impurity region 754 and the n-type impurity region 755 are formed by self-etching. It can be formed using a self-aligned method.

[0278] In addition, the transistor 750 is isolated from other elements formed on the substrate 700 by an element isolation region 789. The transistor 750 is separated from the electrode 751. The electrode 751 and the sidewall insulating layer 756 are surrounded by the sidewall insulating layer 756. An insulating layer 790 and an insulating layer 791 are formed.

[0279] In addition, in FIG. 18A, an insulating layer 113 is formed over the transistor 100. The insulating layer 113 is formed using the same material and method as the insulating layer 105 shown in the first embodiment. In addition, an electrode 114 is formed on the insulating layer 113, and the insulating layer 113 and the insulating An opening is formed in layer 112 providing electrical contact with electrode 119 .

[0280] Moreover, an insulating layer 115 is formed on the insulating layer 113 and the electrode 114 as a planarizing insulating layer. The insulating layer 115 is made of polyimide, acrylic, benzocyclobutene, polyamide, etc. Organic materials having heat resistance, such as epoxy, can be used. Other materials include low-k materials, siloxane resins, PSG (phosphorus glass), and B It is possible to use PSG (polysilicon boron glass) and other materials. The insulating layer 115 may be formed by stacking a plurality of insulating films.

[0281] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0282] The method for forming the insulating layer 115 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, etc.), printing method The insulating layer 115 may be baked using a printing method such as screen printing or offset printing. By combining this with another heat treatment step, a semiconductor device can be manufactured efficiently.

[0283] The insulating layer 115 is formed using the same material and method as the insulating layer 105 shown in the first embodiment. After that, the insulating layer 115 may be subjected to a CMP process.

[0284] In addition, an electrode 116 is formed on the insulating layer 115, and the electrode 116 is disposed in an opening formed in the insulating layer 115. 114 is electrically connected thereto.

[0285] The electrode 751 is electrically connected to the electrode 103. One end of the n-type impurity region 755 is electrically connected to the wiring 3001. The other end of the electrode 55 is electrically connected to the wiring 3002 (not shown). 9 is electrically connected to the wiring 3003, and the electrode 109 is electrically connected to the wiring 3003 through the capacitor 130. 05, and the electrode 111 and the electrode 102 are electrically connected to the wiring 3004. (not shown).

[0286] Here, the material of the semiconductor layer in which the channel of the transistor 750 is formed and the material of the semiconductor layer in which the channel of the transistor 1 The semiconductor layer in which the channel of 00 is formed can be made of materials with different band gaps. For example, an oxide semiconductor is preferably used as the semiconductor layer in which the channel of the transistor 100 is formed. In the case where the transistor 750 is used, a semiconductor layer in which a channel of the transistor 750 is formed is formed using a material other than an oxide semiconductor. For example, a semiconductor material other than an oxide semiconductor, such as crystalline silicon, is preferably used. Transistors using other semiconductor materials are faster than transistors using oxide semiconductors. On the other hand, a transistor using an oxide semiconductor has low off-state current and is therefore easy to operate. Its characteristics allow it to retain charge for long periods of time.

[0287] For example, when crystalline silicon is used for the semiconductor layer in which the channel of a transistor is formed, This transistor can operate at a higher speed than a transistor that uses an oxide semiconductor in the semiconductor layer in which a channel is formed. Therefore, by using the transistor as a readout transistor, Therefore, information can be read out at high speed.

[0288] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that p-channel transistors can also be used. Unless otherwise stated, the materials used in the semiconductor device and the structure of the semiconductor device may not be used in the The specific configuration need not be limited to that shown here.

[0289] As shown in FIG. 18A, a transistor 750 is formed on a substrate. 100 and the capacitance element 130 can be formed, thereby increasing the integration degree of the semiconductor device. It is possible.

[0290] FIG. 18(B) is a circuit diagram of a semiconductor device corresponding to FIG. 18(A). The wiring 3001 is electrically connected to the source electrode of the transistor 750. 2 is electrically connected to the drain electrode of the transistor 750. is electrically connected to one of the source electrode and the drain electrode of the transistor 100, 3004 is electrically connected to the gate electrode of the transistor 100. the gate electrode of the transistor 750, the other of the source electrode or drain electrode of the transistor 100 , and one of the electrodes of the capacitor 130 is electrically connected to the node ND. The wiring 3005 is electrically connected to the other electrode of the capacitor 130 .

[0291] A transistor that uses an oxide semiconductor for the semiconductor layer in which a channel is formed has an extremely low off-state current. The transistor 100 can be made smaller by using a semiconductor layer in which a channel is formed. By using a transistor including an oxide semiconductor as a Therefore, the charge on the gate electrode of the transistor 750 can be retained for a long period of time. can be done.

[0292] In the semiconductor device shown in FIG. 18B, the charge of the gate electrode of the transistor 750 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows: .

[0293] The writing and holding of information will be described. First, the potential of the wiring 3004 is changed to This sets the transistor 100 to a potential at which the transistor 100 is turned on, thereby turning the transistor 100 on. The potential of the wiring 3003 is applied to the gate electrode of the transistor 750 and the capacitor 130. That is, a predetermined charge is applied to the gate electrode of the transistor 750. (Write). Here, the charges that give two different potential levels (hereafter, low-level charges) Then, the wiring 300 is supplied with either a high level charge or a low level charge. The potential of the transistor 100 is set to a potential at which the transistor 100 is turned off. By turning on the transistor 750, the charge applied to the gate electrode of the transistor 750 is held. (retain).

[0294] Since the off-state current of the transistor 100 is extremely small, the gate electrode of the transistor 750 The charge is retained for a long period of time.

[0295] Next, reading of information will be described. When a predetermined potential (constant potential) is applied to the wiring 3001, In this state, when an appropriate potential (read potential) is applied to the wiring 3005, the gate of the transistor 750 Depending on the amount of charge held in the gate electrode, the wiring 3002 assumes different potentials. If the transistor 750 is an n-channel type, a high level is applied to the gate electrode of the transistor 750. Apparent threshold V for a given Bell charge th_H is the transistor 750 Apparent threshold voltage V when a low-level charge is applied to the gate electrode th_L twist Here, the "apparent threshold voltage" is the voltage at which the transistor 750 is turned on. The potential of the wiring 3005 required to turn on the wiring 3005 is referred to as the potential of the wiring 3005. The potential of 05 is V th_H and V th_L The potential V between 0 By doing so, transistor 7 For example, in writing, the charge applied to the gate electrode of High When a level charge is applied, the potential of the wiring 3005 becomes V 0 (>V th_H ) If a low level charge is applied, transistor 750 is in the "on state." In this case, the potential of the wiring 3005 is V 0 ( <V th_L ), transistor 750 Therefore, by determining the potential of the wiring 3002, The information stored in the memory can be read out.

[0296] When memory cells are arranged in an array, only the information in a desired memory cell can be read. If the information is not read out, the state of the gate electrode is Regardless of the potential, transistor 750 is turned off, i.e., V th_H Less than A small potential may be applied to the wiring 3005. The potential at which transistor 750 is turned on, that is, V th_L Wire the higher potential 3 Just give it to 005.

[0297] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. This makes it possible to reduce the frequency of the power consumption significantly. In addition, even if there is no power supply (although it is preferable that the potential is fixed), Even if the memory is changed, the stored contents can be retained for a long period of time.

[0298] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0299] As described above, a semiconductor device that realizes miniaturization and high integration and has excellent electrical characteristics is developed. An apparatus can be provided.

[0300] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0301] (Embodiment 3) In this embodiment, an example of a semiconductor device including a transistor according to one embodiment of the present invention will be described. FIG. 19 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. Here is an example.

[0302] The semiconductor device shown in FIG. 19 includes a capacitor 660a, a capacitor 660b, and a transistor 6 61a, transistor 661b, transistor 662a, and transistor 662b. , an inverter 663a, an inverter 663b, a wiring BL, a wiring BLB, and a wiring WL , a wiring CL, and a wiring GL.

[0303] In the semiconductor device shown in FIG. 19, an inverter 663a and an inverter 663b are connected in a ring. The output of the inverter 663b is a memory cell that constitutes a flip-flop. The node from which the signal is output is designated as node VN1, and the output signal of inverter 663a is output. The node where the memory cells are arranged in a matrix is ​​called node VN2. A memory device (memory cell array) can be configured.

[0304] One of the source and drain of the transistor 662a is electrically connected to the wiring BL. The other of the drains is electrically connected to a node VN1, and the gate is electrically connected to a wiring WL. One of the source and drain of the transistor 662b is electrically connected to the node VN2. The other of the source and drain is electrically connected to the wiring BLB, and the gate is electrically connected to the wiring WL. do.

[0305] One of the source and drain of the transistor 661a is electrically connected to the node VN1. The other of the source and drain is electrically connected to one electrode of the capacitor 660a, and the gate is connected to the wiring G. L. Here, the other of the source and drain of the transistor 661a is electrically connected to the capacitor The node between one electrode of the capacitance element 660a and the node NVN1. One of the source and drain of 61b is electrically connected to the node VN2. The other electrode is electrically connected to one electrode of the capacitor 660b, and the gate is electrically connected to the wiring GL. Here, the other of the source and drain of the transistor 661b and the capacitance element 660b The node between one electrode of and is designated as node NVN2.

[0306] The other electrode of the capacitor 660a is electrically connected to the wiring CL. The electrode is electrically connected to the wiring CL.

[0307] The conductive and non-conductive states of the transistors 662a and 662b are selected by the arrangement. The transistor 661a and the transistor 661b can be controlled by applying a potential to the line WL. The selection of the conductive state or non-conductive state of the resistor 661b is controlled by the potential applied to the wiring GL. It is possible.

[0308] The writing, holding and reading of the memory cell shown in FIG. 19 will be described below.

[0309] When writing data, a potential corresponding to data 0 or data 1 is first applied to the wiring BL and the wiring BLB. is applied.

[0310] For example, if you want to write data 1, connect line BL to the high-level power supply potential (VDD) and line The line BLB is set to the ground potential. Next, the transistor 662a and the transistor 66 A potential (VH) equal to or higher than the potential obtained by adding VDD to the threshold voltage of 2b is applied.

[0311] Next, the potential of the wiring WL is set to a value less than the threshold voltage of the transistor 662a and the transistor 662b. By filling it with data, the data 1 written to the flip-flop is retained.

[0312] When reading, the lines BL and BLB are set to VDD in advance. Next, the line WL is set to By applying VH, the line BL remains at VDD, but the line BLB becomes a transistor. The line BL is discharged through the inverter 662a and the inverter 663a to the ground potential. The potential difference between the wiring BLB is amplified by a sense amplifier (not shown). Data 1 can be read out.

[0313] If you want to write data 0, set the line BL to ground potential and the line BLB to VDD. Then, VH is applied to the wiring WL. , the flip-flop is written by making the threshold voltage of the transistor 662b lower. When reading, data 0 is held. When reading, set the lines BL and BLB to VDD By applying VH to the wiring WL, the wiring BLB remains at VDD, but BL is discharged through transistor 662b and inverter 663b to become ground potential. The potential difference between the wiring BL and the wiring BLB is amplified by a sense amplifier. The data 0 can be read out.

[0314] Therefore, the semiconductor device shown in FIG. SRAM functions as a digital access memory (DMA). Since data is retained, no refresh operation is required. This reduces power consumption. In addition, since no capacitance element is used in the flip-flop, This is suitable for applications requiring high speed operation.

[0315] In addition, in the semiconductor device shown in FIG. 19, a voltage VN1 is supplied from the node VN1 to the node VN2 via the transistor 661a. Similarly, data can be written to the NVN1 through transistor 661b. It is possible to write data from node VN2 to node NVN2. The received data is transmitted to the transistor 661a or the transistor 661b by turning the transistor 661a or the transistor 661b off. For example, even if the supply of the power supply potential is stopped, the nodes VN1 and It may be possible to retain data for node VN2.

[0316] Unlike conventional SRAMs, in which data is lost immediately when the power supply voltage is stopped, The semiconductor device shown in FIG. 1 can retain data even after the supply of power supply potential is stopped. By stopping the supply of power supply potential, a semiconductor device with low power consumption can be realized. For example, by using the semiconductor device shown in FIG. 19 for the memory area of ​​a CPU, the power consumption of the CPU can be reduced. It is also possible to reduce power consumption.

[0317] The period during which data is held at the nodes NVN1 and NVN2 is the period during which the transistors 6 It can be seen that the change depends on the off-current of the transistor 661a and the transistor 661b. In order to extend the data retention period, the transistors 661a and 661b are A transistor with low off-state current may be used for 61b. This can be achieved by increasing the capacitance of the capacitor 660a and the capacitor 660b.

[0318] For example, the transistor 100 and the capacitor 130 described in the first embodiment may be If the capacitor 661a and the capacitor 660a are used, the node NVN1 can be depleted for a long period of time. Similarly, the transistor 100 and the capacitance element 130 can be If the transistor 661b and the capacitor 660b are used, the node NVN2 Therefore, the data can be held for a long period of time. For transistor 661b, see the description of transistor 100. In addition, the capacitance elements 660a and 660b are the same as those of the capacitance element 130. Please refer to the relevant description.

[0319] As described in the above embodiment, the transistor 100 and the capacitor 130 are The transistor 750 may be fabricated at least partially overlapping the transistor 750. A transistor 662a, a transistor 662b, and a transistor included in an inverter 663a The transistors included in the inverter 663b are the transistor 661a, the transistor The capacitor 661b is formed by at least partially overlapping the capacitor elements 660a and 660b. Therefore, the semiconductor device shown in FIG. In some cases, it may be possible to fabricate the transistor without significantly increasing the area. 62a, transistor 662b, the transistors and invertors included in inverter 663a The transistors included in the converter 663b are the same as those in the description of the transistor 750. Please refer to the following.

[0320] As described above, the semiconductor device according to one embodiment of the present invention has high performance relative to the area it occupies. It is also clear that the semiconductor device has high productivity.

[0321] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0322] (Embodiment 4) In this embodiment, an example of a semiconductor device including a transistor according to one embodiment of the present invention will be described. In this embodiment, a CPU is used as an example of a semiconductor device according to one embodiment of the present invention. The apparatus will be described.

[0323] FIG. 20 illustrates an example of a CPU including, at least in part, a transistor according to one embodiment of the present invention. FIG.

[0324] The CPU shown in FIG. 20 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, a SOI substrate, The ROM 1199 and the ROM interface 1189 are Of course, the CPU shown in FIG. 20 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 20 is regarded as one core, and a multi-core processor including multiple cores is used. Alternatively, the CPU may be configured to operate each core in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It may be a bit, etc.

[0325] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0326] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0327] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. Supplied to various circuits.

[0328] In the CPU shown in FIG. 20, a register 1196 is provided with a memory cell. The transistors shown in the above embodiment can be used as the memory cells of 1196. do.

[0329] In the CPU shown in FIG. 20, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, a power supply voltage is applied to the memory cells in the register 1196. If data retention is selected in the capacitive element, rewriting data to the capacitive element This allows the supply of the power supply voltage to the memory cells in the register 1196 to be stopped. .

[0330] FIG. 21 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 730 includes a circuit 701 in which stored data is volatilized when the power is cut off, and a circuit 702 in which stored data is volatilized when the power is cut off. A circuit 702 in which data is not volatile, a switch 703, a switch 704, and a logic element 706. The circuit 702 includes a capacitor 707 and a circuit 720 having a selection function. The memory element 708, a transistor 709, and a transistor 710. 730 may include other elements such as diodes, resistors, inductors, etc., as needed. It may also have.

[0331] Here, the memory device described in the above embodiment can be used for the circuit 702. When the supply of the power supply voltage to the memory element 730 is stopped, the gate of the transistor 709 in the circuit 702 The ground potential (0V) or a potential at which the transistor 709 is turned off is continuously input to the For example, the gate of the transistor 709 is grounded via a load such as a resistor. Let us assume that.

[0332] The switch 703 is configured using a transistor 713 of one conductivity type (for example, an n-channel type). The switch 704 is a transistor of the opposite conductivity type (e.g., p-channel type). Here, the first terminal of the switch 703 is a transistor 714. The second terminal of the switch 703 corresponds to one of the source and drain of the transistor 713. The switch 703 corresponds to the other of the source and drain of the transistor 713. A control signal RD input to the gate of the transistor controls conduction between the first and second terminals or The non-conducting state (i.e., the on or off state of the transistor 713) is selected. The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714. The second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714. The transistor 704 is connected to a first terminal of the transistor 714 in response to a control signal RD input to the gate of the transistor 714. and the second terminal (i.e., the on or off state of the transistor 714). The off state is selected.

[0333] One of the source and drain of the transistor 709 is connected to one of the pair of electrodes of the capacitor 708. On the other hand, the transistor 710 is electrically connected to the gate of the transistor 710. One of the source and drain of the transistor 710 is connected to a low power supply potential. The other is electrically connected to a wiring (for example, a GND line) that can be connected to the switch 703. It is electrically connected to the first terminal (one of the source and drain of the transistor 713). The second terminal of the switch 703 (the other of the source and drain of the transistor 713) is 704 (one of the source and drain of the transistor 714). The second terminal of the switch 704 (the other of the source and drain of the transistor 714) is The switch 703 is electrically connected to a wiring that can supply a power supply potential VDD. 2 terminal (the other of the source and drain of the transistor 713) and the first terminal of the switch 704 A terminal (either the source or drain of the transistor 714) and an input terminal of the logic element 706 The connection portion is electrically connected to one of a pair of electrodes of the capacitor 707. The other of the pair of electrodes of the capacitor 707 is a node M1. For example, a low power supply potential (GND, etc.) or a high power supply potential (V DD, etc.) can be input to the other of the pair of electrodes of the capacitor 707. The other side is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line). A constant potential is input to the other of the pair of electrodes of the capacitor 708. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 708 is supplied with a low power supply potential. The power supply is electrically connected to a wiring (for example, a GND line) that can supply power.

[0334] Note that the capacitors 707 and 708 are formed by actively reducing the parasitic capacitance of transistors and wirings. It is also possible to omit it by using it in a more practical way.

[0335] A control signal WE is input to the gate of the transistor 709. The switch 704 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state is selected between the first terminal and the second terminal of one switch. When the first terminal and the second terminal of the other switch are in a conductive state, the second terminal and the first terminal of the other switch are in a non-conductive state. .

[0336] The other of the source and drain of the transistor 709 is connected to a data input terminal of the circuit 701. In FIG. 21, a signal output from the circuit 701 is input to the transistor The second terminal of the switch 703 is connected to the other of the source and drain of the switch 709. The signal output from the other of the source and drain of the transistor 713 is 6, the logical value of which is inverted to become an inverted signal, and the inverted signal is input to the circuit 701 via the circuit 720. Be encouraged.

[0337] In FIG. 21, the second terminal of the switch 703 (the source and drain of the transistor 713) The signal output from the other input terminal is input to the circuit 701 via the logic element 706 and the circuit 720. The second terminal of the switch 703 (transistor The signal output from the other of the source and drain of the transistor 713 can be inverted in logical value. For example, the signal input from the input terminal may be input to the circuit 701. When there is a node that holds a signal with the logic value of the signal that has been inverted, the switch 703 The signal output from the second terminal (the other of the source and drain of the transistor 713) is The node can be input.

[0338] The transistor 709 in FIG. 21 is the same as the transistor 100 illustrated in the first embodiment. A control signal WE can be input to the gate electrode, and a back gate electrode A control signal WE2 can be input to the control signal WE2. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, the ground potential GND or the source potential of the transistor 709. The control signal WE2 is set to a potential smaller than the threshold potential of the transistor 709. This is a potential signal for controlling the value voltage, and further reduces Icut of the transistor 709. Note that the transistor 709 is a transistor without a back gate electrode. A resistor can also be used.

[0339] In addition, in FIG. 21, among the transistors used in the memory element 730, the transistor The transistors other than 709 are formed on a layer or a substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a silicon layer or a silicon transistor in which a channel is formed. The memory element 73 may be a transistor in which a channel is formed in a conductive substrate. All the transistors used in 0 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 730 may be a transistor other than the transistor 709. The panel may include a transistor formed of an oxide semiconductor layer, and the remaining transistors The transistor is a layer made of a semiconductor other than an oxide semiconductor or a substrate 1190 in which a channel is formed. It can also be a transistor.

[0340] For example, a flip-flop circuit can be used for the circuit 701 in FIG. In addition, the logic element 706 may be, for example, an inverter or a clocked inverter. can be done.

[0341] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 730, The data stored in the circuit 701 is transferred to the capacitor 708 in the circuit 702. It can be held in place.

[0342] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 709, the memory element 73 The signal held in the capacitor 708 is maintained for a long period of time even while the power supply voltage is not supplied to the capacitor 708. In this way, the memory element 730 can retain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to retain it.

[0343] In addition, by providing the switches 703 and 704, the precharge operation Since the circuit 701 is a memory element characterized by performing the above-mentioned operations, the circuit 701 can be restored to the original data after the power supply voltage is restarted. This can shorten the time it takes to re-hold the data.

[0344] In the circuit 702, the signal held by the capacitor 708 is 0 is input to the gate of the storage element 730. Therefore, after the supply of the power supply voltage to the storage element 730 is resumed, The signal held by the capacitor 708 is input to the transistor 710 in the on state (or The capacitance element 702 can be read out by converting the capacitance element 702 to a positive or negative state (OFF state). Even if the potential corresponding to the signal held in 08 fluctuates slightly, the original signal can be read out accurately. It is possible.

[0345] Such a memory element 730 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the device can quickly return to the state it was in before the power supply was stopped. Therefore, the entire processor, or one of the components of the processor, or Power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. It is possible to do so.

[0346] In this embodiment, the memory element 730 is used as a CPU. 0 is DSP (Digital Signal Processor), custom LSI , PLD (Programmable Logic Device) and other LSIs, RF ( It can also be applied to radio frequency (RF)

[0347] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0348] (Embodiment 5) In this embodiment, an example of a semiconductor device including a transistor according to one embodiment of the present invention will be described. In this embodiment, an RF tag will be described as an example of a semiconductor device according to one embodiment of the present invention. The body apparatus will be described.

[0349] The RF tag according to one embodiment of the present invention has a memory circuit therein, stores information in the memory circuit, and It is a device that transmits and receives information to and from the outside world using contact means, such as wireless communication. RF tags are used for individual authentication to identify items by reading their individual information. It is possible to use it in systems such as these. Sex is required.

[0350] The structure of an RF tag will be described with reference to FIG. 22. FIG. 22 is a block diagram showing an example of the structure of an RF tag. FIG.

[0351] As shown in FIG. 22, an RF tag 800 includes a communicator 801 (also called an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 804. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, a reverse current flows in the semiconductor of the transistor having a rectifying effect included in the demodulation circuit 807. For example, an oxide semiconductor capable of sufficiently suppressing the inverse This suppresses the deterioration of the rectification effect caused by the directional current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linear. The data transmission format is electromagnetic, with a pair of coils facing each other and communicating through mutual induction. Coupling method, electromagnetic induction method that communicates by induced electromagnetic fields, radio wave method that communicates using radio waves The RF tag 800 can be used for any of these methods.

[0352] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 is a rectifier for an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential. The limiter circuit may include a limiter circuit. When the internally generated voltage is large, the power above a certain level is controlled so as not to be input to the downstream circuit. This is a circuit for

[0353] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may include a reset signal generating circuit. The reset signal generating circuit uses the stable rise of the power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0354] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit that performs modulation based on the

[0355] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. This is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 also stores a unique number (ID) and outputs it according to the processing. This is a circuit for this purpose.

[0356] The above-mentioned circuits can be selected or omitted as appropriate.

[0357] Here, the semiconductor device described in the above embodiment can be used for the memory circuit 810. The storage device according to one aspect of the present invention can retain information even when the power supply is cut off. Furthermore, the memory device according to one embodiment of the present invention is suitable for an RF tag. The power (voltage) required to read data is lower than that required for conventional non-volatile memory. It is also possible to eliminate the difference in maximum communication distance between when data is read and when it is written. This can prevent malfunction or erroneous writing caused by a power shortage when writing data.

[0358] Further, the memory device according to one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF tag that is produced, only good products that are shipped will be assigned a unique number. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0359] An example of the use of an RF tag according to one embodiment of the present invention will be described below with reference to FIG. F-tags have a wide range of uses, including banknotes, coins, securities, bearer bonds, certificates, etc. (See Figure 23(A)) and packaging containers (Wrapping paper, bottles, etc.) See Figure 23(C).), recording media (DVDs, video tapes, etc., see Figure 23(B).), Vehicles (bicycles, etc., see Figure 23(D)), personal belongings (bags, glasses, etc.), food, plants , animals, the human body, clothing, daily necessities, medicines and medical products including drugs, or electronic devices (liquid crystal displays display devices, EL display devices, television devices, or mobile phones) or each item It can be used by attaching it to a tag (see Figure 23 (E) and Figure 23 (F)). can.

[0360] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of an object. For example, in a book, the sensor is embedded in the paper, and in a package made of organic resin, the sensor is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, and even after it is attached to an object, it does not change the design of the object. In addition, the security of banknotes, coins, securities, bearer bonds, or certificates is not lost. The RF tag 4000 according to one embodiment of the present invention can provide an authentication function to items, By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention relates to an embodiment of the present invention, which is applied to the body, personal belongings, food, clothing, daily necessities, electronic devices, etc. By attaching RF tags 4000, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RF tag 4000 according to one embodiment of the present invention can be attached. By attaching the tag, security against theft and the like can be improved.

[0361] As described above, the RF tag according to one embodiment of the present invention can be used for the above-mentioned applications. can.

[0362] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0363] (Embodiment 6) In this embodiment, an example of a semiconductor device according to one embodiment of the present invention will be described with reference to drawings. Note that in this embodiment, a display device is taken as an example of a semiconductor device which is one embodiment of the present invention. explain.

[0364] FIG. 24A shows an example of a display device. The display device shown in FIG. 24A has a pixel portion 401. The scanning line driver circuit 404 and the signal line driver circuit 406 are arranged in parallel or approximately in parallel. m scanning lines 407 whose potentials are controlled by a scanning line driving circuit 404; are arranged in parallel or approximately in parallel, and the potential is controlled by a signal line driver circuit 406. The pixel portion 401 has a plurality of signal lines 409 arranged in a matrix. The pixel 411 is a pixel having a pixel size of 411.

[0365] In addition, by using three pixels 411 as one pixel, color display is possible. For example, a pixel 411 that emits red light, a pixel 411 that emits green light, and a pixel 411 that emits blue light may be used. By operating the pixels 411 as one pixel, a color display can be achieved. The color of light emitted by the pixel 411 can be yellow, cyan, magenta, etc. in addition to red, green, and blue. This is also fine.

[0366] In addition, the four pixels 411 may be used as one pixel. For example, Alternatively, the pixels 4 may be configured to emit red, green, blue, and yellow light, respectively. By increasing the number of 11, it is possible to improve the reproducibility of intermediate tones in particular. In addition, the four pixels 411 are red, green, blue, and white. By providing the pixel 411 that emits white light, the brightness of the display area can be increased. Depending on the application of the display device, the two pixels 411 may be combined into one. It can also be used as a pixel.

[0367] In addition, the display device shown in FIG. 24A has a structure in which the scanning lines 407 are parallel or approximately parallel to each other. The capacitance line 415 is disposed along the signal line 409. The scanning line driving circuit 404 and the signal The line driver circuit 406 may be collectively referred to as a driver circuit portion.

[0368] Each scanning line 407 corresponds to any one of the pixels 411 arranged in m rows and n columns in the pixel section 401. Each signal line 409 is electrically connected to n pixels 411 arranged in one row. Among the pixels 411 arranged in m rows and n columns, m pixels 411 arranged in any one of the columns Each of m and n is an integer of 1 or more. Among the pixels 411 arranged in m rows and n columns, n pixels 411 arranged in any row The capacitance lines 415 are electrically connected to the signal lines 409. In the case where the pixels 411 are arranged in m rows and n columns, It is electrically connected to m pixels 411 arranged in a column.

[0369] 24B and 24C show the configuration of the pixel 411 of the display device shown in FIG. 24A. 4 shows a circuit configuration that can

[0370] The pixel 411 shown in FIG. 24B includes a liquid crystal element 432, a transistor 431_1, and a capacitor The transistor 431_1 is the transistor disclosed in the above embodiment. The transistor 100 can be used.

[0371] The potential of one of the pair of electrodes of the liquid crystal element 432 is set appropriately according to the specifications of the pixel 411. The alignment state of the liquid crystal element 432 is determined by the written data. A common potential (common potential) is applied to one of a pair of electrodes of the liquid crystal element 432 of each of the pixels 411. In addition, one of a pair of electrodes of the liquid crystal element 432 for each pixel 411 in each row may be provided with Different potentials may be applied.

[0372] For example, the display device including the liquid crystal element 432 can be driven in a TN mode, an STN mode, or the like. mode, VA mode, ASM (Axially Symmetric Aligned Mi cro-cell mode, OCB (Optically Compensated B irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode, MVA mode, PVA (Patterned Ver (Artificial Alignment) mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, the liquid crystal element and its driving method are not limited to these. A variety of different ones can be used.

[0373] In addition, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent The liquid crystal element may be constructed from these. The liquid crystal that exhibits the blue phase has a short response speed of 1 msec or less. In addition, since it is optically isotropic, alignment treatment is not required and viewing angle dependency is small.

[0374] In the pixel 411 in the mth row and the nth column, One of the electrodes is electrically connected to the signal line DL_n, and the other is a pair of electrodes of the liquid crystal element 432. The gate electrode of the transistor 431_1 is electrically connected to the other of the scan line G L_m. The transistor 431_1 is in an on state or an off state. By this, the write control circuit 100 has a function of controlling the writing of data of the data signal.

[0375] One of a pair of electrodes of the capacitor 433_1 is connected to a wiring to which a potential is supplied (hereinafter, a “capacitor line CL "), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 432. The potential value of the capacitance line CL is appropriately set according to the specifications of the pixel 411. The capacitor 433_1 functions as a storage capacitor for storing written data. do.

[0376] For example, in a display device having a pixel 411 shown in FIG. 24B, the scanning line driver circuit 404 The pixels 411 in each row are selected in sequence, and the transistors 431_1 are turned on to output data signals Write data.

[0377] The pixel 411 to which the data has been written is held by turning off the transistor 431_1. By performing this process for each row in sequence, an image can be displayed.

[0378] In addition, the pixel 411 shown in FIG. 24C includes a transistor 431_2 and a capacitor 433_ 2, a transistor 434, and a light-emitting element 435. The transistor 100 disclosed in the above embodiment can be used. The transistor 100 disclosed in the above embodiment can be used as the transistor 434. Cut.

[0379] One of the source electrode and the drain electrode of the transistor 431_2 is supplied with a data signal. Further, the transistor is electrically connected to a wiring (hereinafter, referred to as "signal line DL_n"). The gate electrode of the transistor 431_2 is connected to a line through which a gate signal is applied (hereinafter, the "scanning line GL_ m).

[0380] The transistor 431_2 is turned on or off to de-assert the data signal. It has the function of controlling the writing of data.

[0381] One of a pair of electrodes of the capacitor 433_2 is electrically connected to the node 436, and the other is Electrically connected to node 437.

[0382] The capacitor 433_2 functions as a storage capacitor for storing written data.

[0383] One of the source electrode and the drain electrode of the transistor 434 is connected to the potential supply line VL_a. In addition, the gate electrode of transistor 434 is electrically connected to node 436. is connected to.

[0384] One of the anode and the cathode of the light-emitting element 435 is electrically connected to the potential supply line VL_b. and the other is electrically connected to node 437.

[0385] The light-emitting element 435 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 435 is not limited to this. An inorganic EL element made of an inorganic material may also be used.

[0386] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0387] In a display device having the pixel 411 in FIG. 24C, the image of each row is generated by a scanning line driver circuit 404. The elements 411 are sequentially selected, the transistor 431_2 is turned on, and the data of the data signal is Write.

[0388] The pixel 411 to which the data has been written is held by turning off the transistor 431_2. Furthermore, the transistor 434 is turned on and off in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 435 is By performing this process row by row, an image can be displayed.

[0389] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0390] (Embodiment 7) In this embodiment, a display module to which a semiconductor device according to one embodiment of the present invention is applied will be described. This will be explained with reference to FIG.

[0391] The display module 8000 shown in FIG. 25 is made up of an upper cover 8001 and a lower cover 8002. In between, touch panel 8004 is connected to FPC8003, and touch panel 8005 is connected to FPC8005. Cell 8006, backlight unit 8007, frame 8009, printed circuit board 801 0 and a battery 8011. 011, the touch panel 8004 may not be provided.

[0392] The semiconductor device according to one embodiment of the present invention can be used for the cell 8006, for example.

[0393] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the cell 8005. The shape and dimensions can be changed as appropriate to fit the size of 06.

[0394] The touch panel 8004 is a resistive or capacitive touch panel. The cell 8006 can be used by overlapping it with the opposite substrate (sealing substrate). It is also possible to provide a panel function. It is also possible to provide an optical sensor to make it an optical touch panel. It is also possible to provide a touch sensor electrode in each pixel to create a capacitive touch panel. do.

[0395] The backlight unit 8007 includes a light source 8008. It may be provided at the end of the unit 8007 and may be configured to use a light diffusion plate.

[0396] The frame 8009 protects the cell 8006 and also operates the printed circuit board 8010. It may also have a function as an electromagnetic shield to block the electromagnetic waves generated. The plate 8009 may function as a heat sink.

[0397] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. In some cases, the battery 8011 may not be required.

[0398] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0399] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0400] (Embodiment 8) In this embodiment, an example of an electronic device using a semiconductor device according to one embodiment of the present invention will be described. Reveal.

[0401] Examples of electronic devices using a semiconductor device according to one embodiment of the present invention include display devices such as televisions and monitors. , lighting equipment, desktop or notebook personal computers, word processors The data is stored on recording media such as DVD (Digital Versatile Disc). Image reproducing devices that reproduce still or moving images, portable CD players, radios, tapes Recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets , transceivers, mobile phones, car phones, portable game machines, tablet terminals, pachinko machines Large game consoles such as mobile phones, calculators, personal digital assistants, electronic organizers, electronic books, electronic translators, voice input devices, etc. High-frequency processing equipment such as power equipment, video cameras, digital still cameras, electric shavers, and microwave ovens Heating equipment, electric rice cookers, electric washing machines, vacuum cleaners, water heaters, electric fans, hair dryers, air conditioners Air conditioning equipment such as conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, Futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for storing DNA, flashlights , tools such as chainsaws, smoke detectors, medical equipment such as dialysis machines, etc. Exit lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage These include industrial equipment such as power storage systems, power leveling and smart grid storage units. In addition, moving objects propelled by electric motors using electricity from storage batteries are also included in the category of electronic devices. The above-mentioned moving bodies include, for example, electric vehicles (EVs), vehicles with internal combustion engines and electric motors, and Hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), These tires and wheels are converted into tracks, and motorized vehicles including electric-assisted bicycles are also included. Bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters Examples include aircraft, rockets, satellites, space probes, interplanetary probes, and spacecraft. .

[0402] FIG. 26A shows an example of a portable game machine. The portable game machine has a housing 901, a housing 902, a display unit 903, Display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908, etc. The portable game machine shown in FIG. and a display unit 904, the number of display units that the portable game machine has is not limited to this. I can't.

[0403] FIG. 26B shows an example of a portable data terminal, which includes a first case 911, a second case 912, a first table The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit and the housing 912. At least one of the first display unit 913 and the second display unit 914 is provided with a function as a position input device. The function of the position input device may be the same as that of the display device. Alternatively, it can be used as a position input device. The function can also be achieved by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It can be added.

[0404] FIG. 26C shows an example of a notebook personal computer. The computer includes a housing 921, a display unit 92, and a 2, a keyboard 923, a pointing device 924, etc.

[0405] FIG. 26(D) is an example of an electric refrigerator-freezer, and includes a housing 931, a refrigerator door 932, and a freezer door 933. It has a door 933 etc.

[0406] FIG. 26E shows an example of a video camera, which includes a first housing 941, a second housing 942, and a display unit 9 43, an operation key 944, a lens 945, a connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. The switch may be configured to switch according to the angle between the body 942.

[0407] FIG. 26(F) shows an example of an automobile, which includes a body 951, wheels 952, a dashboard 953, Light 954 etc.

[0408] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. EXAMPLES

[0409] In this embodiment, tungsten and silicon doped indium tin oxide (hereinafter referred to as "ITO Si), indium gallium zinc oxide (hereinafter referred to as "IGZO") and nitrogen-doped indium gallium zinc oxide (hereinafter referred to as "IGZON" ) on which an insulating layer containing more oxygen than the oxygen required for the stoichiometric composition was formed. We will explain the results of preparing each of them and analyzing the amount of oxygen molecules released by heating using TDS. .

[0410] <Sample preparation> FIG. 27(A) shows a schematic diagram of the cross-sectional structure of the sample. The sample is a single crystal silicon substrate 2001. A thermal oxide film 2002 having a thickness of 100 nm is formed on the thermal oxide film 2002, and a barrier layer 201 is formed on the thermal oxide film 2002. 3, and oxygen having a stoichiometric composition is deposited on the barrier layer 2013 by a sputtering method. A silicon oxide layer 2004 having a thickness of 300 nm and containing more oxygen than the silicon oxide layer 2004 formed on the substrate was formed.

[0411] [Sample 2010] As the barrier layer 2013, tungsten with a thickness of 150 nm was formed by sputtering. The sample was named sample 2010.

[0412] [Sample 2020] A sample in which ITOSi with a thickness of 50 nm was formed by sputtering as a barrier layer 2013. This was designated as sample 2020.

[0413] [Sample 2030] The barrier layer 2013 was formed by sputtering with an atomic ratio of In:Ga:Zn=1:1:1. The sputtering gas was a mixture of oxygen and argon. The sample on which IGZO was formed with a thickness of 50 nm was designated as sample 2030.

[0414] [Sample 2040] The barrier layer 2013 was formed by sputtering with an atomic ratio of In:Ga:Zn=1:1:1. The sputtering gas was argon and the thickness of the IGZ was 50 nm. The sample in which O was formed was designated as sample 2040.

[0415] [Sample 2050] The barrier layer 2013 was formed by sputtering with an atomic ratio of In:Ga:Zn=1:1:1. A 50 nm thick IGZON was sputtered using a target of 100 nm and nitrogen as the sputtering gas. The formed sample was designated as sample 2050.

[0416] <TDS analysis results> For samples 2010 to 2050, TDS analysis (temperature-programmed desorption gas analysis) was performed. In Fig. 27(B), the analysis results of the emission amount of the gas with M / z = 32 (oxygen molecule) by TDS analysis are shown. In Fig. 27(B), the horizontal axis is the substrate temperature, and the vertical axis is the signal intensity proportional to the emission amount of the gas having a specific molecular weight. Note that the total amount of molecules emitted to the outside corresponds to the integrated value of the signal intensity. Therefore, the total amount of molecules contained in the oxide insulating film can be evaluated by the level of the peak intensity.

[0417] In Fig. 27(B), it can be seen that for samples 2020 to 2050, the emission amount of oxygen molecules is larger than that of sample 2010. From this, it can be inferred that in sample 2010, much of the oxygen contained in the silicon oxide layer 2004 diffused into the barrier layer 2013 formed of tungsten. On the other hand, since the barrier layer 2013 of samples 2020 to 2050 is less permeable to oxygen, the oxygen contained in the silicon oxide layer 2004 is released to the outside, and as a result, it can be inferred that a large amount of oxygen molecules was detected.

[0418] From this example, it can be seen that tungsten is a material that easily permeates oxygen. Also, it can be seen that ITOSi, IGZO, and IGZON are materials that are less permeable to oxygen. .

Example

[0419] In this example, using samples different from those in Example 1, more oxygen than the stoichiometric composition was contained in the oxygen formed on tungsten, ITOSi, IGZO, or IGZON. This section describes the results of a TDS analysis of the amount of oxygen molecules released from the insulating layer due to heating.

[0420] <Sample preparation> Using Figures 28(A) and 28(B), the cross-sectional structure of the sample and the fabrication method are described. First, a sample similar to that in Example 1 was prepared, and the oxygen content was increased more than the stoichiometric composition. A cap layer 2005 is formed on a 300 nm thick silicon oxide layer 2004 containing a large amount of oxygen. The cap layer 2005 is formed by sputtering In:Ga:Zn=1:1:1 The atomic ratio of the target was 1.0 and the sputtering gas was a mixture of oxygen and argon. The IGZO film was 50 nm thick and formed using a SiO2 thin film (see FIG. 28(A)).

[0421] Next, the sample was subjected to a heat treatment at 450° C. for 1 hour in a nitrogen atmosphere. The heat treatment was carried out at 450° C. for 1 hour in an oxygen atmosphere. 5 was removed to expose the silicon oxide layer 2004 (see FIG. 28(B)).

[0422] [Sample 2110] As the barrier layer 2013, tungsten with a thickness of 150 nm was formed by sputtering. The sample was named sample 2110.

[0423] [Sample 2120] As the barrier layer 2013, a 50 nm thick ITOSi was formed by sputtering. The sample was named Sample 2120.

[0424] [Sample 2130] The barrier layer 2013 was formed by sputtering with an atomic ratio of In:Ga:Zn=1:1:1. The sputtering gas was a mixture of oxygen and argon. A sample with 50 nm of IGZO formed was designated as Sample 2130.

[0425] 〔Sample 2140〕 As the barrier layer 2013, a target with an atomic ratio of In:Ga:Zn = 1:1:1 was used in sputtering, and argon was used as the sputtering gas to form IGZO with a thickness of 50 nm. The sample was designated as Sample 2140.

[0426] 〔Sample 2150〕 As the barrier layer 2013, a target with an atomic ratio of In:Ga:Zn = 1:1:1 was used in sputtering, and nitrogen was used as the sputtering gas to form IGZON with a thickness of 50 nm. The sample was designated as Sample 2150.

[0427] <TDS analysis results> TDS analysis (temperature-programmed desorption gas analysis) was performed on Samples 2110 to 2150. In Fig. 28(C), the analysis results of the release amount of the gas with M / z = 32 (oxygen molecule) by TDS analysis are shown. In Fig. 28(C), the horizontal axis is the substrate temperature, and the vertical axis is the signal intensity proportional to the release amount of the gas having a specific molecular weight.

[0428] In Fig. 28(C), it can be seen that almost no release of oxygen molecules can be confirmed in Sample 2110. Also, in Samples 2120 to 2150, the release of oxygen molecules was clearly confirmed. By attaching the cap layer 2005 and performing heat treatment, in Sample 2110, most of the oxygen more than that satisfying the stoichiometric composition contained in the silicon oxide layer 2004 is presumed to have diffused into the barrier layer 2013 formed of tungsten. Also, the barrier layer 2013 and the cap layer 2005 of Samples 212 0 to 2150 are less permeable to oxygen. ​ Therefore, oxygen in excess of the stoichiometric composition does not form silicon oxide even after heat treatment. It can be assumed that most of the material remained in layer 2004.

[0429] This example shows that tungsten is a material that easily transmits oxygen. TOSi, IGZO, and IGZON are materials that are difficult for oxygen to permeate. . [Explanation of symbols]

[0430] 100 transistors 101 Substrate 102 electrode 103 Electrode 104 Electrode 105 Insulating layer 106 Insulating Layer 107 Insulating layer 108 Oxide semiconductor layer 109 Electrode 110 Insulating layer 111 Electrode 112 Insulating layer 113 Insulating Layer 114 Electrode 115 Insulating Layer 116 Electrode 119 Electrode 120 Insulating layer 121 Conductive layer 130 Capacitive element 382 Ec 386 Ec 390 Trap Levels 401 Pixel section 404 Scanning line driver circuit 406 Signal Line Driver Circuit 407 scan lines 409 Signal Line 411 pixels 415 Capacitive Line 432 Liquid crystal element 434 Transistor 435 Light-emitting element 436 nodes 437 nodes 700 Substrates 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logic Elements 707 Capacitive element 708 Capacitive element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 730 Memory Element 750 Transistors 751 Electrode 752 Insulation layer 753 Channel formation region 754 n-type impurity region 755 n-type impurity region 756 Sidewall insulation layer 789 Element Isolation Area 790 Insulating layer 791 Insulation Layer 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1010 Electron gun room 1012 Optical system 1014 Sample Room 1016 Optical system 1018 Camera 1020 Observation Room 1022 Film Room 1024 electronic 1028 Substance 1032 Fluorescent screen 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 2001 Single crystal silicon substrate 2002 Thermal oxide film 2004 Silicon oxide layer 2005 Cap Layer 2010 Sample 2013 Barrier Layer 2020 Sample 2030 Sample 2040 Sample 2050 Sample 2110 Sample 2120 Sample 2130 Sample 2140 Sample 2150 Samples 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 4000 RF tags 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Cell 8007 Backlight unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery 102a electrode 102b electrode 103a electrode 103b electrode 104a electrode 104b electrode 108a Oxide semiconductor layer 108b Oxide semiconductor layer 108c Oxide semiconductor layer 118a Oxide semiconductor layer 118b Oxide semiconductor layer 383a Ec 383b Ec 383c Ec 431_1 Transistor 431_2 Transistor 433_1 Capacitive element 433_2 Capacitor element 660a Capacitive element 660b Capacitive element 661a Transistor 661b Transistor 662a Transistor 662b Transistor 663a Inverter 663b Inverter

Claims

1. a first conductive layer serving as a first gate electrode of a transistor; a second conductive layer having the same material as the first conductive layer; a third conductive layer having the same material as the first conductive layer; a first insulating layer having a region in contact with an upper surface of the first conductive layer, a region in contact with an upper surface of the second conductive layer, and a region in contact with an upper surface of the third conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the transistor; a second insulating layer having a region located above the oxide semiconductor layer; a fourth conductive layer having a region overlapping with the oxide semiconductor layer with the second insulating layer interposed therebetween and functioning as a second gate electrode of the transistor; and a fifth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region overlapping with the second conductive layer; a sixth conductive layer having a region in contact with an upper surface of the oxide semiconductor layer and a region in contact with an upper surface of the third conductive layer through an opening in the first insulating layer, the sixth conductive layer being made of the same material as the fifth conductive layer; a third insulating layer having a region in contact with an upper surface of the fifth conductive layer and a region in contact with an upper surface of the sixth conductive layer; the opening of the first insulating layer does not overlap with the oxide semiconductor layer; The fifth conductive layer has no region in contact with the second conductive layer.

2. a first conductive layer serving as a first gate electrode of a transistor; a second conductive layer having the same material as the first conductive layer; a third conductive layer having the same material as the first conductive layer; a first insulating layer having a region in contact with an upper surface of the first conductive layer, a region in contact with an upper surface of the second conductive layer, and a region in contact with an upper surface of the third conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the transistor; a second insulating layer having a region located above the oxide semiconductor layer; a fourth conductive layer having a region overlapping with the oxide semiconductor layer with the second insulating layer interposed therebetween and functioning as a second gate electrode of the transistor; and a fifth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region overlapping with the second conductive layer; a sixth conductive layer having a region in contact with an upper surface of the oxide semiconductor layer and a region in contact with an upper surface of the third conductive layer through an opening in the first insulating layer, the sixth conductive layer being made of the same material as the fifth conductive layer; a third insulating layer having a region in contact with an upper surface of the fifth conductive layer and a region in contact with an upper surface of the sixth conductive layer; the opening of the first insulating layer does not overlap with the oxide semiconductor layer; the fifth conductive layer does not have a region in contact with the second conductive layer, The second conductive layer functions as an electrode of a capacitor.

3. In claim 1 or 2, The fifth conductive layer and the sixth conductive layer have a stacked structure.

Images