Semiconductor device

Abstract

To provide a semiconductor device that can reduce forward voltage degradation and turn-on loss.SOLUTION: A vertical MOSFET includes: a first conductive type semiconductor substrate 2; a first conductive type first semiconductor layer 1; a second conductive type second semiconductor layer 16; a first conductive type first semiconductor region 17; a first trench 31 and a second trench 32; a gate electrode 20 provided inside the first trench 31 via a gate insulating film 19; and a Schottky electrode 29 provided inside the second trench 32. The first trench 31 is provided in a striped pattern in a plan view, and the second trench 32 surrounds the first trench 31.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with a trench structure have been fabricated (manufactured) in power semiconductor elements to reduce the on-resistance of the elements. In vertical MOSFETs, a trench structure in which the channel is formed perpendicular to the substrate surface can increase the cell density per unit area compared to a planar structure in which the channel is formed parallel to the substrate surface, and therefore the current density per unit area can be increased, which is advantageous in terms of cost.

[0003] Vertical MOSFETs incorporate a parasitic pn diode formed by a p-type base layer and an n-type drift layer as a body diode between the source and drain. This allows the free wheeling diode (FWD) used in inverters to be omitted, contributing to cost reduction and miniaturization. However, when a silicon carbide substrate is used as the semiconductor substrate, the parasitic pn diode has a higher built-in potential than when a silicon (Si) substrate is used, which increases the on-resistance of the parasitic pn diode and leads to increased loss. In addition, when the parasitic pn diode is turned on and current is passed, the bipolar operation of the parasitic pn diode causes the characteristics to change over time (aging degradation), resulting in forward degradation and increased turn-on loss.

[0004] To address this issue, a Schottky Barrier Diode (SBD) can be connected in parallel with the MOSFET so that current flows through the SBD during freewheeling and no current flows through the parasitic pn diode. However, this increases costs because the number of SBD chips required is roughly the same as that of MOSFETs.

[0005] For this reason, a technology has been proposed in which a contact trench is formed on the surface of the substrate that penetrates the p-type channel portion, an SBD is embedded in the inner wall of the trench, and the return current flows through the built-in SBD instead of a PiN diode (see, for example, Patent Document 1 below).

[0006] Fig. 24 is a top view showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. Fig. 25 is a cross-sectional view of the CC' portion of Fig. 24 showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. As shown in Fig. 24, a silicon carbide semiconductor device 150 with an SBD built in includes an active region 140 in which an element structure is formed and through which a current flows in an on-state, an edge region 142 surrounding the periphery of the active region 140 and maintaining a breakdown voltage, and a transition region 141 between the active region 140 and the edge region 142. The active region 140 is the region surrounded by a dashed line in Fig. 24.

[0007] 25, a semiconductor substrate made of silicon carbide (hereinafter referred to as silicon carbide substrate) is provided with a MOS gate having a general trench gate structure on its front surface (the surface on the side of a p-type base layer 116 described later). + n-type silicon carbide substrate + A silicon carbide substrate (102) is formed on the n - The n-type drift layer 101, the n-type region 115 which is a current diffusion region, and the p-type base layer 116 are formed by epitaxially growing silicon carbide layers in this order.

[0008] n + On a silicon carbide substrate 102 - The n-type drift layer 101 - The n-type layer is epitaxially grown. + The front surface (n - On the side of the drift layer 101, a p-type base layer 116 and an n-type + A MOS gate structure is provided, which is made up of a type source region 117, a trench gate 131, a gate insulating film 119, and a gate electrode 120. Reference numerals 118, 121, and 122 denote p ++a type contact region, an interlayer insulating film, and a source electrode.

[0009] In the n-type region 115, a first p + The n-type region 115 is provided with a first p-type region 103 so as to cover the entire bottom surface of the trench SBD 132. + A mold region 103 is selectively provided. + The type region 103 is - The edge region 142 is provided at a depth not reaching the first p drift layer 101. + The second p + A mold area 104 is provided.

[0010] Moreover, trench SBD 132 is a trench whose inner wall is covered with Schottky metal 129 connected to source electrode 122, and a Schottky is formed between the semiconductor region exposed on the inner wall and Schottky metal 129. In this manner, in Fig. 24, a parasitic Schottky diode (built-in SBD) is provided in parallel with the parasitic pn diode between the source and drain.

[0011] As shown in FIG. 24, in a conventional silicon carbide semiconductor device with an SBD built in, trench gate 131 is longer than trench SBD 132 to facilitate connection of trench gate 131 to a gate runner (not shown) provided in edge region 142.

[0012] A positive voltage is applied to the source electrode 122, and n + When a negative voltage is applied to a drain electrode (not shown) provided on the back surface of the silicon carbide substrate 102 (when the MOSFET is off), the p-type base layer 116 and the n-type - 24, by designing the parasitic Schottky diode to turn on before the parasitic pn diode turns on when the MOSFET is off, the bipolar operation of the parasitic pn diode can be suppressed and deterioration over time due to the bipolar operation can be prevented.

[0013] Also known is a configuration that includes multiple rings made of p-type layers formed by arranging an epitaxial film in a linear frame-shaped trench surrounding a cell portion, and a Schottky electrode is arranged to cover a portion of the inner circumference of each ring (for example, see Patent Document 2 below). [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Japanese Patent Application Publication No. 8-204179 [Patent Document 2] JP 2018-006630 A Summary of the Invention [Problem to be solved by the invention]

[0015] Here, Fig. 26 is a cross-sectional view of the A-A' portion of Fig. 24 showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. Fig. 27 is a cross-sectional view of the B-B' portion of Fig. 24 showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. As shown in Figs. 26 and 27, in the transition region 141, the first p + A second p + The p-type region 104 is provided on the surface of the p-type base layer 116. ++ Therefore, in the transition region 141, the trench SBD 132 is surrounded by a p-type region (the p-type base layer 116, the p ++ Type contact region 118, first p + The mold region 103 and the second p + The structure is surrounded by a mold region 104).

[0016] As a result, in the transition region 141, the trench SBD 132 does not function as a parasitic Schottky diode and cannot suppress the bipolar operation of the parasitic pn diode. When the parasitic pn diode is turned on and conducts current, the bipolar operation of the parasitic pn diode causes a hole current to flow along path D in Figures 26 and 27, and stacking faults are generated and expanded by the energy generated by recombination of the hole current and electron current.

[0017] Therefore, the transition region 141 has a problem that the characteristics change over time (deterioration due to aging) due to the bipolar operation of the parasitic pn diode, and this causes forward deterioration and increased turn-on loss, more than the inside of the active region 140.

[0018] SUMMARY OF THE PRESENT EMBODIMENT In order to solve the above-mentioned problems associated with the conventional technology, an object of the present invention is to provide a semiconductor device capable of reducing the degradation of the forward voltage and the loss at turn-on. [Means for solving the problem]

[0019] In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on a front surface of a semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on the opposite side of the first semiconductor layer to the semiconductor substrate. A first semiconductor region of a first conductivity type having a higher impurity concentration than the semiconductor substrate is selectively provided inside the second semiconductor layer. A second semiconductor region of a second conductivity type is provided inside the first semiconductor layer. A third semiconductor region of a second conductivity type having a bottom surface in contact with the second semiconductor region is provided in a surface layer of the first semiconductor layer. A first trench and a second trench are provided which penetrate the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. A gate electrode is provided inside the first trench via a gate insulating film. A Schottky electrode is provided inside the second trench. The first trench is provided in a stripe shape in a plan view, the second trench has a stripe-shaped portion parallel to the first trench in a plan view and an outer peripheral portion connecting the stripe-shaped portion and surrounding each end of the first trench, and the second trench surrounds each of the first trenches. The second trench has a second conductive type region below the first trench and below the second trench, and surrounds the first trench, and has a Schottky junction on each of both side surfaces of the second trench.

[0020] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, a junction termination structure for improving breakdown voltage is provided in an edge region that surrounds an active region through which current flows in an on-state and maintains a breakdown voltage, the distance between an end of the first trench and the outer periphery of the second trench is equal to or greater than the distance between the first trench and the second trench, and the end of the first trench is provided on the active region side of the junction termination structure.

[0021] In addition, in the semiconductor device according to the present invention, the second trench is formed as a heterojunction with polysilicon.

[0022] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, a portion of the second trench is provided at a position opposite in the depth direction to a gate contact region that connects the gate electrode and a gate runner.

[0023] In addition, in the semiconductor device according to the present invention, the first trench and the second trench have the same depth.

[0024] In addition, in the semiconductor device according to the present invention, in the above-mentioned invention, the second conductivity type regions below the first trench and the second trench have the same depth.

[0025] According to the above-mentioned invention, the trench gate (first trench) is surrounded by the trench SBD (second trench). As a result, the portion of the trench gate that comes into contact with the source electrode is inside the region surrounded by the trench SBD. Therefore, outside the region surrounded by the trench SBD, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with an SBD built in, the parasitic pn diode does not operate in a bipolar manner, and forward degradation and an increase in turn-on loss can be suppressed. Effect of the Invention

[0026] The semiconductor device according to the present invention has the effect of reducing the degradation of the forward voltage and the loss at the time of turn-on. [Brief description of the drawings]

[0027] [Figure 1] 1 is a top view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Diagram 2] 2 is a cross-sectional view taken along line AA' of FIG. 1 showing a structure of a silicon carbide semiconductor device according to an embodiment. [Diagram 3] 2 is a cross-sectional view taken along the line BB' of FIG. 1, showing a structure of a silicon carbide semiconductor device according to an embodiment. [Figure 4] 2 is a cross-sectional view taken along the line CC' of FIG. 1 showing a structure of a silicon carbide semiconductor device according to an embodiment. [Diagram 5] 2 is a cross-sectional view taken along line DD' of FIG. 1 showing a structure of a silicon carbide semiconductor device according to an embodiment. [Figure 6] 1 is a top view showing an external appearance of a silicon carbide semiconductor device according to an embodiment; [Figure 7] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 1). [Figure 8] 5A to 5C are cross-sectional views (part 2) illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 9] 6A to 6C are cross-sectional views (part 3) illustrating a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 10] 4 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 4). FIG. [Figure 11] 5 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 5). FIG. [Figure 12] FIG. 1 is a top view (part 1) showing a state during manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 13] 13 is a cross-sectional view (part 1) taken along the line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 14] FIG. 2 is a second top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 15] 13 is a cross-sectional view (part 2) taken along the line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 16] FIG. 3 is a third top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 17] 13 is a cross-sectional view (part 3) taken along the line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 18]FIG. 4 is a top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment (part 4). [Figure 19] 13 is a fourth cross-sectional view taken along the line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 20] FIG. 5 is a fifth top view showing a state during manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 21] 13 is a fifth cross-sectional view of the silicon carbide semiconductor device according to the embodiment taken along the line AA' of FIG. 12 during manufacture. FIG. [Figure 22] FIG. 6 is a top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment (part 6). [Diagram 23] 13 is a cross-sectional view (part 6) taken along the line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 24] FIG. 1 is a top view showing the structure of a conventional silicon carbide semiconductor device with an embedded SBD. [Diagram 25] 25 is a cross-sectional view taken along the line CC' of FIG. 24, showing the structure of a conventional silicon carbide semiconductor device with an embedded SBD. [Figure 26] FIG. 25 is a cross-sectional view taken along line AA' of FIG. 24 showing the structure of a conventional silicon carbide semiconductor device with an embedded SBD. [Figure 27] FIG. 25 is a cross-sectional view taken along the line BB' of FIG. 24, showing the structure of a conventional silicon carbide semiconductor device with an embedded SBD. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] A preferred embodiment of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the layer or region has a higher impurity concentration and a lower impurity concentration than the layer or region not prefixed with n or p. In the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index.

[0029] (Embodiment) The semiconductor device according to the present invention is configured using a semiconductor having a wider band gap than silicon (hereinafter, referred to as a wide band gap semiconductor). Here, the structure of a semiconductor device (silicon carbide semiconductor device) using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described as an example. FIG. 1 is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view of an A-A' portion of FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view of a B-B' portion of FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view of a C-C' portion of FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. Here, FIG. 5 is a cross-sectional view of a D-D' portion of FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 4 is a C-C' cross-sectional view of a transition region 41, and FIG. 5 is a D-D' cross-sectional view of an active region in which an element structure is formed and a main current flows in the thickness direction of a substrate when in an on-state.

[0030] As shown in Fig. 1, a silicon carbide semiconductor device 50 with an SBD is composed of an active region 40 in which an element structure is formed and a main current flows in the thickness direction of the substrate when the device is in an on-state, an edge region 42 that surrounds the periphery of the active region 40 and maintains a breakdown voltage, and a transition region 41 between the active region 40 and the edge region 42. The active region 40 is a region surrounded by a dashed line in Fig. 1. The transition region 41 is a region in which a side surface of a trench gate 31 described later is covered with a p-type region and does not function as a MOS, as shown in Fig. 4. The silicon carbide semiconductor device according to the embodiment shown in Figs. 1 to 4 is a silicon carbide semiconductor device 50 with an SBD, which is provided with a MOS gate on the front surface (surface on the side of a p-type base layer 16 described later) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide.

[0031] The silicon carbide substrate is a n-type silicon carbide substrate. + A silicon carbide substrate (a semiconductor substrate of a first conductivity type) 2 is formed on the n - The n-type drift layer (first semiconductor layer of a first conductivity type) 1 and the p-type base layer (second semiconductor layer of a second conductivity type) 16 are epitaxially grown in sequence. In the active region 40, the MOS gate is formed by epitaxially growing the p-type base layer 16 and the n-type + The n-type source region (first semiconductor region of the first conductivity type) 17, the gate insulating film 19, and the gate electrode 20 are configured as follows. - An n-type region 15 may be provided in the surface layer on the source side (the side of a source electrode 22 described later) of the drift layer 1 so as to be in contact with the p-type base layer 16. The n-type region 15 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type region 15 is provided uniformly in a direction parallel to the front surface of the substrate (front surface of the silicon carbide substrate), for example.

[0032] n-type region 15 (n-type region 15 not provided) - The inside of the first drift layer 1 (hereinafter referred to as (1)) is + A first conductive type region (a second semiconductor region of a second conductive type, a second conductive type region) 3 is selectively provided. +The n-type region 3 is provided so as to be in contact with the bottom surface of a trench gate (first trench) 31 (to be described later) and the bottom surface of a trench SBD (second trench) 32 (to be described later). + A second p type region (a third semiconductor region of a second conductivity type) 4 is selectively provided. + The mold region 4 has a bottom surface of the first p + It is provided so as to be in contact with the mold region 3 .

[0033] When the n-type region 15 is provided, the first p + The p-type region 3 is connected to the n-type region 15 from a position deeper on the drain side than the interface between the p-type base layer 16 and the n-type region 15. - The first p + By providing the mold region 3, the first p + A pn junction between the first p-type region 3 and the n-type region 15(1) can be formed. + Type 3 and 2p + The p-type region 4 has a higher impurity concentration than the p-type base layer 16 .

[0034] In addition, the p-type base layer 16 includes n + The n-type source region 17 is selectively provided. + type source region 17 and p ++ A p-type contact region (a fifth semiconductor region of the second conductivity type) (not shown) may be selectively provided. ++ The depth of the contact region is, for example, n + It may be the same depth as the n-type source region 17, + It may be deeper than the source region 17 .

[0035] The trench gate 31 is formed on the front surface of the substrate. +The gate electrode 20 is electrically connected to a gate electrode pad (not shown). The interlayer insulating film 21 is provided on the front surface of the substrate so as to cover the gate electrode 20 embedded in the trench gate 31. The interlayer insulating film 21 is opened at a joint region 41, and the gate electrode 20 is connected to a gate runner 27 at the opening via a gate contact region 26 of the polysilicon layer.

[0036] The trench SBD32 is formed from the front surface of the substrate + The trench SBD 32 penetrates the p-type source region 17 and the p-type base layer 16 to reach the n-type region 15(1). The inside of the trench SBD 32 is covered along the sidewall of the trench SBD 32 with a Schottky metal 29 that connects to the source electrode 22, and a Schottky junction is formed between the semiconductor region exposed on the inner wall and the Schottky metal 29. An oxide film, for example, silicon dioxide (SiO 2 ) may be provided.

[0037] As shown in FIG. 1, in the embodiment, the trench gate 31 is surrounded by the trench SBD 32. As shown in FIG. 6 described later, surrounding means that in order to reach the edge region 42 from any point of the trench gate 31 in a plan view, it is necessary to cross the trench SBD 32. For example, the trench gate 31 is provided in a stripe shape in a plan view, and the trench SBD 32 is provided in parallel with the trench gate 31 and has a stripe-shaped portion P1 that is longer than the trench gate 31 and an outer peripheral portion P2 that connects the stripe-shaped portions. As a result, the portion of the trench gate 31 that contacts the source electrode 22 is inside the region surrounded by the trench SBD 32. Therefore, outside the region surrounded by the trench SBD 32, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with an SBD built in, the parasitic pn diode does not operate in a bipolar manner, and forward degradation and an increase in turn-on loss can be suppressed.

[0038] As shown in FIG. 4, in the transition region 41, the sidewall of the trench SBD 32 is + In other words, in a conventional silicon carbide semiconductor device with an SBD built in, the p-type region (first and second p-type regions) surrounding the trench SBD 132 is not in contact with the p-type region 4. + By opening a part of n-type regions 103, 104), trench SBD 32 of the embodiment has its sidewall in contact with n-type region 15(1). This allows trench SBD 32 to function as a parasitic Schottky diode even in transition region 41. Therefore, when a negative bias is applied to the drain side of a silicon carbide semiconductor device incorporating an SBD, the parasitic Schottky diode can be operated in transition region 41 as well, thereby suppressing the bipolar operation of the parasitic pn diode and suppressing forward degradation and an increase in turn-on loss.

[0039] 6 is a top view showing the appearance of the silicon carbide semiconductor device according to the embodiment. As shown in FIG. +The active region 40 is surrounded by an edge region 42 that maintains a breakdown voltage and is provided in a stripe shape in the direction in which the crystal orientation of the silicon carbide substrate 1 is <11-20>. A JTE region 43 is provided as a junction termination extension (JTE) structure in an edge region 42 that surrounds the active region 40 and maintains a breakdown voltage in order to improve the breakdown voltage of the entire high-voltage semiconductor device by relaxing or dispersing an electric field. Outside the JTE region 43, a n-type junction termination extension (JTE) region 43 is provided that functions as a channel stopper. + A mold semiconductor region (not shown) is provided.

[0040] In the embodiment, the distance W1 between the end T of the trench gate 31 and the outer periphery portion P2 of the trench SBD 32 is preferably equal to or greater than the interval W2 between the trench gate 31 and the trench SBD 32. This is because if the distance W1 is short, the resistance in the current path of the trench SBD 32 may decrease, resulting in a decrease in the withstand voltage. Furthermore, the end T of the trench gate 31 is preferably provided inside (on the active region 40 side) the JTE region 43. For this reason, the outer periphery portion P2 of the trench SBD 32 is provided at a position facing the gate contact region 26 in the depth direction.

[0041] The source electrode 22 is connected to the n-type + The p-type source region 17 is in contact with the p-type source region 17 and is electrically insulated from the gate electrode 20 by an interlayer insulating film 21. ++ When a type contact region is provided, the source electrode 22 is a p ++ The source electrode 22 also contacts the type contact region. A barrier metal for preventing diffusion of metal atoms from the source electrode 22 to the gate electrode 20 side may be provided between the source electrode 22 and the interlayer insulating film 21. A source electrode pad (not shown) is provided on the source electrode 22. + n-type drain region + A drain electrode (not shown) is provided on the back surface of the silicon carbide substrate 1.

[0042] (Method of Manufacturing a Semiconductor Device According to an Embodiment) Next, a method for manufacturing a semiconductor device according to an embodiment will be described. Figs. 7 to 11 are cross-sectional views showing a state during the manufacturing of a silicon carbide semiconductor device according to an embodiment. Figs. 12, 14, 16, 18, 20, and 22 are top views showing a state during the manufacturing of a silicon carbide semiconductor device according to an embodiment. Also, Figs. 13, 15, 17, 19, 21, and 23 are cross-sectional views of the A-A' portion of Fig. 12 showing a state during the manufacturing of a silicon carbide semiconductor device according to an embodiment.

[0043] First, n + n-type drain region + A silicon carbide substrate 2 is prepared. Next, + The front surface of the silicon carbide substrate 2 is - The n-type drift layer 1 is epitaxially grown. - The epitaxial growth conditions for forming the n-type drift layer 1 are as follows: - The impurity concentration of the drift layer 1 is 3×10 15 / cm 3 The state up to this point is shown in FIG.

[0044] Next, n - A lower n-type region 15a (if the n-type region 15 is not formed, the n-type drift layer 1) is formed on the - The n-type layer (hereinafter abbreviated as n-type layer) having the same impurity concentration as that of the n-type drift layer 1 is epitaxially grown. For example, the epitaxial growth conditions for forming the lower n-type region 15a are set as follows: the impurity concentration of the lower n-type region 15a is 1×10 17 / cm 3 The lower n-type region 15a is a part of the n-type region 15. Next, a first p-type impurity is formed on the surface layer of the lower n-type region 15a (n-type layer) by photolithography and ion implantation of p-type impurities. + The mold region 3 is selectively formed. For example, the first p + The dose of ions implanted to form the mold region 3 is set to 5×10 18 / cm 3 The state up to this point is shown in FIG.

[0045] Next, the lower n-type region 15a (n-type layer), the first p + An upper n-type region 15b (n-type layer) is epitaxially grown on the n-type region 3. For example, the epitaxial growth conditions for forming the upper n-type region 15b may be set to have an impurity concentration similar to that of the lower n-type region 15a. The upper n-type region 15b is a part of the n-type region 15, and the lower n-type region 15a and the upper n-type region 15b together form the n-type region 15. Next, a second p-type impurity is formed in the surface layer of the upper n-type region 15b (n-type layer) by photolithography and ion implantation of p-type impurities. + The mold region 4 is selectively formed. For example, the second p + The dose of ions implanted to form the type region 4 is set to a value corresponding to the first p + The thickness of the first p + Type region 3 and 2p + The region including the mold region 4 is called the first and second p + The second p + When the mold region 4 is formed, the sidewall of the trench SBD 32 is formed in the transition region 41 so as to be the second p + It is formed so as not to come into contact with the mold region 4. The state up to this point is shown in FIG.

[0046] Next, the upper n-type region 15b and the second p + A p-type base layer 16 is epitaxially grown on the doped region 4. For example, the epitaxial growth conditions for forming the p-type base layer 16 are set as follows: the impurity concentration of the p-type base layer 16 is 4×10 17 / cm 3 The setting may be made so as to be about the same.

[0047] Next, photolithography and ion implantation of n-type impurities are performed to form n-type impurities in the surface layer of the p-type base layer 16. + The n-type source region 17 is selectively formed. For example, + The dose of ions implanted to form the source region 17 is set to 3×10 20 / cm 3The setting may be made so as to be about the same.

[0048] Next, by photolithography and ion implantation of p-type impurities, n + The p ++ A type contact region may be selectively formed. For example, ++ The dose of ions implanted to form the contact region is set to 3×10 20 / cm 3 It may be set to about n + Type source region 17 and p ++ The order of forming the first and second contact regions may be reversed. Next, the JTE region 43 is formed in the edge region 42 by photolithography and ion implantation of p-type impurities. After all ion implantation is completed, activation annealing is performed. The state up to this point is shown in FIG.

[0049] Next, by photolithography and etching, + A trench gate 31 is formed through the p-type source region 17 and the p-type base layer 16 to reach the n-type region 15(1). The bottom of the trench gate 31 is a first p + The p-type region 3 may extend between the p-type base layer 16 and the first p + The trench gate 31 may be located within the n-type region 15(1) between the n-type regions 3. Next, the mask used to form the trench gate 31 is removed. An oxide film is used as a mask when forming the trench. After the trench etching, isotropic etching may be performed to remove damage to the trench gate 31, and hydrogen annealing may be performed to round the corners of the bottom of the trench gate 31 and the opening of the trench gate 31. Only one of isotropic etching and hydrogen annealing may be performed. Hydrogen annealing may be performed after isotropic etching.

[0050] Next, by photolithography and etching, +A trench SBD32 is formed so as to penetrate the p-type source region 17 and the p-type base layer 16 and reach the n-type region 15(1). The bottom of the trench SBD32 is a first p + The p-type region 3 may extend between the p-type base layer 16 and the first p + The trench SBD 32 may be located within the n-type region 15(1) between the n-type regions 3. Next, the mask used to form the trench SBD 32 is removed. At this time, the distance W1 between the end T of the trench gate 31 and the outer periphery portion P2 of the trench SBD 32 is equal to or greater than the interval W2 between the trench gate 31 and the trench SBD 32, and the end of the trench gate 31 is formed closer to the active region 40 than the JTE region 42. The state up to this point is shown in FIG. 11.

[0051] Next, a gate insulating film 19 is formed along the front surface of the silicon carbide substrate and the inner wall of the trench gate 31. Next, a metal film is formed along the inner wall of the trench SBD 32 using, for example, titanium (Ti). Next, a nitrogen (N 2 ) atmosphere to form a Schottky junction between the metal film and the semiconductor region on the inner wall of the trench SBD 32.

[0052] Next, polysilicon is deposited and etched so as to fill trench gate 31 and trench SBD 32, thereby leaving polysilicon that will become gate electrode 20 inside trench gate 31 and polysilicon inside trench SBD 32. At this time, etching may be performed by etching back so that the polysilicon is left inside the substrate surface. In this way, by filling trench SBD 32 with polysilicon, trench SBD 32 is formed by a heterojunction between a metal film and polysilicon. A top view of the state up to this point is shown in FIG. 12, and a cross section A-A' of FIG. 12 is shown in FIG. 13.

[0053] Next, an interlayer insulating film 21 is formed on the entire front surface of the silicon carbide substrate so as to cover the gate electrode 20. The interlayer insulating film 21 is formed of, for example, NSG (Non-doped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), HTO (High Temperature Oxide), or a combination thereof. Next, the interlayer insulating film 21 and the gate insulating film 19 are patterned to form contact holes, and n + The source region 17 is exposed. ++ When a contact region is formed, n + type source region 17 and p ++ The mold contact region is exposed. The trench gate 31 opens the interlayer insulating film 21 only in the transition region 41. A top view of the state up to this point is shown in FIG. 14, and a cross section of the state taken along the line A-A' in FIG. 12 is shown in FIG.

[0054] Next, a barrier metal is formed and patterned so as to cover the interlayer insulating film 21. + type source region 17 and p ++ The n-type contact area is then exposed again. + A source electrode 22 is formed so as to be in contact with the polysilicon embedded in the type source region 17 and the trench SBD 32. The source electrode 22 may be formed so as to cover the barrier metal, or may be left only in the contact hole.

[0055] Next, polysilicon (Poly-Si) is deposited over the entire front surface of the silicon carbide substrate. A top view of the state up to this point is shown in FIG. 16, and a cross section taken along line A-A' in FIG. 12 in this state is shown in FIG. 17. Next, the polysilicon is patterned by etching, and is left only in the gate runner direction, thereby forming gate contact region 26. A top view of the state up to this point is shown in FIG. 18, and a cross section taken along line A-A' in FIG. 12 in this state is shown in FIG. 19. In this way, by dividing the deposition of polysilicon into two steps, one for filling trench SBD 32 and the other for forming gate contact region 26, it is possible to form a wide gate contact region 26 in the upper part of trench SBD 32.

[0056] Next, an interlayer insulating film 21 is formed on the entire front surface of the silicon carbide substrate. The interlayer insulating film 21 is formed of, for example, NSG, PSG, HTO, or a combination of these. A top view of the state up to this point is shown in FIG. 20, and a cross section of this state taken along line A-A' in FIG. 12 is shown in FIG. 21. Next, the interlayer insulating film 21 is patterned to form a contact hole, and the gate contact region 26 is exposed.

[0057] Next, a source electrode pad 28 and a gate runner 27 are formed so as to fill the contact hole. A part of the metal layer deposited to form the source electrode pad 28 may be used as a gate electrode pad. A top view of the state up to this point is shown in FIG. 22, and a cross section of the state shown in FIG. 12 along A-A' is shown in FIG. 23. + On the back surface of the silicon carbide substrate 2, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed on the contact portion of the drain electrode by sputter deposition or the like. This metal film may be a laminate of a combination of Ni films and Ti films. Then, annealing such as rapid thermal annealing (RTA) is performed so that the metal film is silicided to form an ohmic contact. Then, a thick film such as a laminate film in which a Ti film, a Ni film, and a gold (Au) are laminated in this order is formed by electron beam (EB) deposition or the like to form the drain electrode.

[0058] In the above-mentioned epitaxial growth and ion implantation, for example, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc., which are n-type impurities (n-type dopants) for silicon carbide, may be used. For example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc., which are p-type impurities for silicon carbide, may be used. In this manner, the MOSFET shown in FIGS. 1 to 4 is completed.

[0059] As described above, according to the embodiment, the trench gate is surrounded by the trench SBD. As a result, the portion of the trench gate that contacts the source electrode is inside the region surrounded by the trench SBD. Therefore, outside the region surrounded by the trench SBD, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with an SBD built in, the parasitic pn diode does not operate in a bipolar manner, and forward degradation and an increase in turn-on loss can be suppressed.

[0060] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-mentioned embodiments, for example, the dimensions and impurity concentration of each part are set in various ways according to the required specifications. In addition, in each of the above-mentioned embodiments, a MOSFET is used as an example, but the present invention is not limited to this and can be widely applied to various silicon carbide semiconductor devices that conduct and cut off current by being gate-driven and controlled based on a predetermined gate threshold voltage. Examples of silicon carbide semiconductor devices that are gate-driven and controlled include IGBTs (Insulated Gate Bipolar Transistors). In each of the above-mentioned embodiments, a case where silicon carbide is used as a wide band gap semiconductor is described as an example, but the present invention can also be applied to wide band gap semiconductors other than silicon carbide, such as gallium nitride (GaN). In each of the above-mentioned embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0061] INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for silicon carbide semiconductor devices with a trench gate structure. [Explanation of symbols]

[0062] 1, 101 n - Mold drift layer 2, 102 n + Silicon carbide substrate 3, 103 1st p. + type area 4, 104 2nd p. + type area 5, 105 p. + type area 15, 115 n-type region 15a Lower n-type region 15b Upper n-type region 16, 116 p-type base layer 17, 117 n + Type Source Area 18, 118 p. ++ Mold Contact Area 19, 119 Gate insulating film 20, 120 Gate electrode 21, 121 Interlayer insulating film 22, 122 Source electrode 25 Interlayer insulating film 26 Gate Contact Area 27 Gate Runner 28 Source electrode pad 29, 129 Schottky metal 31, 131 Trench Gate 32, 132 Trench SBD 40, 140 active area 41, 141 Transverse region 42, 142 Edge area 43 JTE area Silicon carbide semiconductor device with built-in 50, 150 SBD

Claims

1. a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate; a second semiconductor layer of a second conductivity type provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided within the second semiconductor layer and having a higher impurity concentration than the semiconductor substrate; a first trench and a second trench passing through the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer; a gate electrode provided inside the first trench via a gate insulating film; a Schottky electrode provided inside the second trench; Equipped with The first trench is provided in a stripe shape in a plan view, the second trench has a stripe-shaped portion parallel to the first trench in a plan view, and an outer circumferential portion connecting the stripe-shaped portions and surrounding each end of the first trench; the second trenches surround each of the first trenches; a second conductivity type region is provided below the first trench and below the second trench, The second trench surrounding the first trench has a Schottky junction on each of both side surfaces of the second trench.

2. An edge region surrounding an active region through which a current flows in an on-state and maintaining a breakdown voltage is provided with a junction termination structure for improving the breakdown voltage; 2. The semiconductor device according to claim 1, wherein a distance between an end of the first trench and the outer periphery of the second trench is equal to or greater than a distance between the first trench and the second trench, and the end of the first trench is located closer to the active region than the junction termination structure.

3. 3. The semiconductor device according to claim 1, wherein the second trench is formed as a heterojunction with polysilicon.

4. 4. The semiconductor device according to claim 1, wherein a portion of the second trench is provided at a position facing in a depth direction a gate contact region that connects the gate electrode and a gate runner.

5. 5. The semiconductor device according to claim 1, wherein the first trench and the second trench have the same depth.

6. 6. The semiconductor device according to claim 1, wherein the second conductivity type regions below the first trench and the second trench have the same depth.

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