Imaging element and imaging device

Abstract

SOLUTION: An imaging element includes a first substrate on which a first pixel block having pixels and a second pixel block adjacent to the first pixel block are arranged, and a second substrate in which a first circuit block that converts a signal output from the pixel of the first pixel block into a digital signal and a second circuit block that converts a signal output from the pixel of the second pixel block into a digital signal are arranged, and that is laminated on the first substrate. A distance between the first circuit block and the second circuit block is different from a distance between the first pixel block and the second pixel block.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an imaging device and an imaging apparatus.

Background Art

[0002] An imaging device including an AD conversion unit is known (for example, Patent Document 1). Conventionally, noise caused by heat generated in the AD conversion unit has been a problem. Patent Document 1: JP-A-2013-51674

Summary of the Invention

[0003] In a first aspect of the present invention, there is provided an imaging device including a first pixel block having pixels, a first substrate on which the first pixel block and a second pixel block adjacent to the first pixel block are arranged, a first circuit block that converts a signal output from the pixels of the first pixel block into a digital signal, and a second circuit block that converts a signal output from the pixels of the second pixel block into a digital signal, and a second substrate laminated on the first substrate, wherein a distance between the first circuit block and the second circuit block is different from a distance between the first pixel block and the second pixel block.

[0004] In a second aspect of the present invention, there is provided an imaging device including a first pixel block having pixels, a first substrate on which the first pixel block and a second pixel block are arranged, a first circuit block that converts a signal output from the pixels of the first pixel block into a digital signal, and a second circuit block that converts a signal output from the pixels of the second pixel block into a digital signal, and a second substrate laminated on the first substrate, wherein the first pixel block and the second pixel block are adjacent to each other, and the first circuit block and the second circuit block are not adjacent to each other.

[0005] In a third aspect of the present invention, there is provided an imaging device including a first substrate on which a plurality of pixel blocks each having pixels are two-dimensionally arranged, and a second substrate laminated on the first substrate and having a plurality of circuit blocks each configured to convert a signal output from at least any one of the corresponding plurality of pixel blocks into a digital signal, wherein the arrangement relationship of the plurality of pixel blocks is different from the arrangement relationship of the plurality of circuit blocks corresponding to each of the plurality of pixel blocks.

[0006] In a second aspect of the present invention, there is provided an imaging apparatus including the above-described imaging device.

[0007] Note that the above summary of the invention does not enumerate all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

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Mode for Carrying Out the Invention

[0009] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0010] In this specification, the X-axis and the Y-axis are orthogonal to each other, and the Z-axis is orthogonal to the XY plane. The XYZ axes form a right-handed system. The direction parallel to the Z-axis may be referred to as the stacking direction of the imaging element 400. In this specification, the terms "upper" and "lower" are not limited to the up and down directions in the direction of gravity. These terms only refer to the relative directions in the Z-axis direction. Note that in this specification, the arrangement in the X-axis direction will be described as "row", and the arrangement in the Y-axis direction will be described as "column", but the matrix direction is not limited to this. Also, the Z-axis direction is the optical axis direction in which light from the subject is incident.

[0011] FIG. 1 is a diagram showing an overview of an imaging element 400 according to the present embodiment. The imaging element 400 images a subject. The imaging element 400 generates image data of the imaged subject. The imaging element 400 includes a first substrate 100 and a second substrate 200. As shown in FIG. 1, the first substrate 100 is laminated on the second substrate 200.

[0012] The first substrate 100 has a pixel portion 110. The pixel portion 110 outputs a pixel signal based on the incident light. Note that the first substrate 100 may be called a pixel chip.

[0013] The second substrate 200 has a processing circuit portion 210 and a peripheral circuit portion 230. Note that the second substrate 200 may be called a signal processing chip.

[0014] The processing circuit unit 210 receives the pixel signals output from the first substrate 100. The processing circuit unit 210 processes the input pixel signals. For example, the processing circuit unit 210 performs a process of converting an analog signal into a digital signal. Specifically, the processing circuit unit 210 performs a process of converting the input pixel signals into digital signals. The processing circuit unit 210 may perform other signal processing. Examples of other signal processing include noise removal processing such as analog or digital CDS (Correlated Double Sampling).

[0015] In this example, the processing circuit unit 210 is disposed on the second substrate 200 at a position facing the pixel unit 110. That is, the processing circuit unit 210 is arranged so as to at least partially overlap the pixel unit 110 in the optical axis direction. The processing circuit unit 210 may output a control signal for controlling the driving of the pixel unit 110 to the pixel unit 110.

[0016] The peripheral circuit unit 230 controls the driving of the processing circuit unit 210. The peripheral circuit unit 230 is disposed on the second substrate 200 around the processing circuit unit 210. Also, the peripheral circuit unit 230 may be electrically connected to the first substrate 100 and control the driving of the pixel unit 110.

[0017] In addition to the first substrate 100 and the second substrate 200, the imaging device 400 may have a third substrate laminated on the second substrate 200. For example, the third substrate is a memory chip, and performs image processing according to the signal output from the second substrate 200. Also, the structure of the imaging device 400 may be a back-illuminated type or a front-illuminated type. Hereinafter, an example of the back-illuminated type will be described.

[0018] FIG. 2 shows an example of a specific configuration of the pixel unit 110. In this example, an enlarged view of the pixel unit 110 and the pixel block 120 provided in the pixel unit 110 is shown.

[0019] The pixel section 110 has a plurality of pixel blocks 120 arranged two-dimensionally side by side along the row direction and the column direction. The pixel section 110 in this example has M×N pixel blocks 120 (M and N are natural numbers). In this example, the case where M is equal to N is illustrated, but M and N may be different.

[0020] The pixel block 120 has at least one pixel 112. The pixel block 120 in this example has m×n pixels 112 (m and n are natural numbers). For example, the pixel block 120 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this. In this example, the case where m is equal to n is illustrated, but m may be different from n. The pixel block 120 has a plurality of pixels 112 connected to a common control line in the row direction. For example, each pixel 112 of the pixel block 120 is connected to a common control line so as to be set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.

[0021] On the other hand, between the plurality of pixel blocks 120, they may be set to different exposure times. That is, although each pixel 112 of the pixel block 120 has the same exposure time, it may be set to a different exposure time in other pixel blocks 120. For example, when the pixels 112 of the pixel block 120 are connected by a common control line in the row direction, the pixels 112 of other pixel blocks 120 are commonly connected by different control lines.

[0022] In the present embodiment, one pixel block 120 is arranged for one processing block 220. The connection relationship between the pixel block 120 and the processing block 220 will be described later.

[0023] The pixel 112 has a photoelectric conversion function of converting light into electric charge. The pixel 112 accumulates the photoelectrically converted electric charge. m pixels 112 are arranged side by side along the column direction and are connected to a common signal line 122. And m pixels 112 are arranged in n columns in the row direction in the pixel block 120.

[0024] In other words, the pixel block 120 is a collection of a plurality of pixels 112 connected by a common control line. Also, it can be said that the pixel block 120 is the minimum unit of the circuits of a plurality of pixels 112 for which the same exposure time is set.

[0025] FIG. 3 shows an example of the circuit configuration of the pixel 112. The pixel 112 includes a photoelectric conversion unit 104, a transfer unit 123, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 has an amplification unit 128 and a selection unit 129. In this example, the transfer unit 123, the reset unit 126, the amplification unit 128, and the selection unit 129 will be described as N-channel type FETs, but the type of transistor is not limited to this.

[0026] The photoelectric conversion unit 104 has a photoelectric conversion function of converting light into charges. The photoelectric conversion unit 104 accumulates the photoelectrically converted charges. The photoelectric conversion unit 104 is, for example, a photodiode.

[0027] The transfer unit 123 transfers the charges accumulated in the photoelectric conversion unit 104 to the accumulation unit 125. The transfer unit 123 is an example of a transfer gate that transfers the charges of the photoelectric conversion unit 104. In other words, with the transfer unit 123 as the gate, the photoelectric conversion unit 104 as the source, and the accumulation unit 125 as the drain, these constitute a so-called transfer transistor. The gate terminal of the transfer unit 123 is connected to a local transfer control line for each pixel block 120, and a control signal φTX1 is input.

[0028] The accumulation unit 125 has charges transferred from the photoelectric conversion unit 104 by the transfer unit 123. The accumulation unit 125 is an example of a floating diffusion (FD).

[0029] The reset unit 126 discharges the charges of the accumulation unit 125 to a power supply wiring to which a predetermined power supply voltage VDD is supplied. The gate terminal of the reset unit 126 is connected to a global reset control line spanning a plurality of pixel blocks 120, and a reset control signal φRST is input.

[0030] The pixel output unit 127 outputs a signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 includes an amplification unit 128 and a selection unit 129. The gate terminal of the amplification unit 128 is connected to the storage unit 125, the drain terminal is connected to a power supply wiring to which the power supply voltage VDD is supplied, and the source terminal is connected to the drain terminal of the selection unit 129.

[0031] The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the pixel 112 and the signal line 122 are electrically connected by the selection unit 129, a pixel signal is output from the pixel 112 to the signal line 122. The gate terminal of the selection unit 129 is connected to a global selection control line spanning a plurality of pixel blocks 120 for inputting a selection control signal φSEL. The source terminal of the selection unit 129 is connected to the load current source 121.

[0032] The load current source 121 supplies current to the signal line 122. The load current source 121 may be provided on the first substrate 100 or on the second substrate 200.

[0033] Hereinafter, any one of the charge accumulated in the photoelectric conversion unit 104, the charge transferred to the storage unit 125, and the signal based on the potential of the storage unit 125, or a general term for these may be referred to as a pixel signal.

[0034] In addition, the pixel 112 includes at least one photoelectric conversion unit 104 and a pixel output unit 127 as a readout unit that reads an image signal from the at least one photoelectric conversion unit 104 to the signal line 122. It can be said that the pixel 112 is the minimum unit of a circuit that outputs a pixel signal constituting an image to the signal line 122.

[0035] FIG. 4 shows an example of a more specific configuration of the processing circuit unit 210. In this example, an enlarged view of the processing circuit unit 210 and the processing block 220 provided in the processing circuit unit 210 is shown.

[0036] The processing circuit unit 210 has processing blocks 220 arranged side by side along the row direction and the column direction. The processing circuit unit 210 in this example has M×N processing blocks 220.

[0037] In this embodiment, the processing block 220 and the pixel block 120 are arranged at overlapping positions when viewed from the optical axis direction, but the processing block 220 and the pixel block 120 arranged at overlapping positions are not necessarily connected. In this case, the areas of the processing block 220 and the pixel block 120 may be substantially the same including the margin between adjacent blocks.

[0038] The processing block 220 controls the driving of the electrically connected pixel block 120. The fact that the processing block 220 and the pixel block 120 are electrically connected may be referred to as corresponding. For example, the processing block 220 controls the exposure time of the corresponding pixel block 120. Further, the processing block 220 has a processing circuit such as an AD converter and processes the signal output from the corresponding pixel block 120. In one example, the processing block 220 converts the analog pixel signal output from the corresponding pixel block 120 into a digital signal. The processing block 220 in this example includes an exposure control unit 10, a pixel driving unit 20, a junction unit 30, a signal conversion unit 40, and a signal output unit 50.

[0039] The exposure control unit 10 controls the exposure of a plurality of pixels 112. The exposure control unit 10 generates a signal for controlling the exposure time of the pixel 112. In one example, the exposure control unit 10 adjusts at least one of the start timing or the end timing of the exposure to control the exposure time for each pixel block 120.

[0040] The pixel driving unit 20 is electrically connected to a plurality of pixels 112. The pixel driving unit 20 selects and drives an arbitrary pixel 112 from the plurality of pixels 112 based on the signal from the exposure control unit 10. Since the imaging device 400 can set the exposure time for each pixel block 120 according to the intensity of the incident light, the dynamic range can be expanded.

[0041] The joint portion 30 joins the first substrate 100 and the second substrate 200. The joint portion 30 inputs the pixel signal input from the first substrate 100 to the signal conversion unit 40. The joint portion 30 is provided corresponding to n pixels 112 arranged in the row direction, and inputs the pixel signal to the signal conversion unit 40 for each column.

[0042] The signal conversion unit 40 digitally converts the analog signal output from the pixel unit 110. The signal conversion unit 40 in this example converts the analog pixel signal into a digital signal. The signal conversion unit 40 sequentially digitally converts the analog signals from m pixels 112 arranged in the column direction. The signal conversion unit 40 has n AD converters 42 arranged in the row direction. Each of the AD converters 42 digitally converts the analog signals from the pixels 112 in the corresponding column of the corresponding pixel block 120 in parallel. This can also be said to be a so-called column ADC method for one pixel block 120.

[0043] The signal output unit 50 receives the digital signal from the signal conversion unit 40. In one example, the signal output unit 50 temporarily stores the digital signal. The signal output unit 50 may have a latch circuit for storing the digital signal.

[0044] Note that instead of providing one processing block 220 for one pixel block 120, one processing block 220 may be provided for N pixel blocks 120 (N is a natural number of 2 or more). The N pixel blocks 120 corresponding to one processing block may be referred to as a pixel block group. For example, two pixel blocks 120 arranged side by side along the column direction may be regarded as one pixel block group, and one processing block 220 may be provided. In this case, the processing block 220 may control the exposure time for each pixel block 120.

[0045] Incidentally, it can be said that the processing block 220 is electrically connected to at least one pixel block 120 and is the minimum unit of a circuit that processes the pixel signals of the at least one pixel block 120. Also, it can be said that the processing circuit unit 210 is composed of a group of processing blocks 220.

[0046] FIG. 5 schematically shows the connection relationship between the pixel block 120 and the processing block 220. In FIG. 5, for simplicity of explanation, 4×4 blocks in the pixel unit 110 and the processing circuit unit 210 are shown, and each block is represented as "1-1", "1-2", etc. using the order in the XY directions.

[0047] In the example shown in FIG. 5, the columns in the X direction where X is "1", that is, the pixel blocks "1-1", "1-2", "1-3", and "1-4" are respectively connected by connection wirings 250 to the processing blocks "1-1", "1-2", "1-3", and "1-4" that overlap in the Z direction, which is the stacking direction. Note that there are n connection wirings 250, which is the number of columns of the pixel block 120, but only one is shown representatively in the figure. The connection wiring 250 extends substantially in the Z direction across the interface 102 between the pixel unit 110 and the processing circuit unit 210.

[0048] On the other hand, the columns in the X direction where X is "2", that is, the pixel blocks "2-1", "2-2", "2-3", and "2-4" are not connected to the processing blocks "2-1", "2-2", "2-3", and "2-4" that overlap in the Z direction, which is the stacking direction. Instead, the pixel block "2-1" is connected to the processing block "2-3" that does not overlap in the Z direction. Also, the pixel block "2-2" is connected to the processing block "2-4" that does not overlap in the Z direction, the pixel block "2-3" is connected to the processing block "2-1" that does not overlap in the Z direction, and the pixel block "2-4" is connected to the processing block "2-2" that does not overlap in the Z direction.

[0049] The pixel block "2-1" and the processing block "2-3" are electrically connected by a connection wiring 252 that extends substantially in the Z direction across the interface 102 between the pixel section 110 and the processing circuit section 210, and a connection wiring 253 that is connected to the connection wiring 252 and extends in the XY plane of the processing circuit section 210. Other pixel blocks and processing blocks in the column where the X direction is "2" are also electrically connected by the connection wirings 252 and 253 in the same manner.

[0050] Similar to the connection wiring 250, the connection wirings 252 and 253 are typically shown as one. Also, the connection wiring 253 extending in the XY plane may be provided on the pixel section 110 side, or may be provided on both the pixel section 110 and the processing circuit section 210.

[0051] The connection relationship between the pixel block and the processing block in the column where the X direction is "3" is the same as that in the column where the X direction is "1". Further, the connection relationship between the pixel block and the processing block in the column where the X direction is "4" is the same as that in the column where the X direction is "2". In other words, across the entire pixel section 110 and processing circuit section 210, taking the connection relationship between the pixel block and the processing block in the X direction "1" and the connection relationship between the pixel block and the processing block in the X direction "2" as one unit, that connection relationship is repeatedly applied in the XY direction. Note that a part of the repetition may have a different connection relationship.

[0052] The connection relationship between the pixel block and the processing block shown in FIG. 5 is such that, for example, although the pixel blocks "1-1" and "2-1" are adjacent in the X direction, the processing blocks "1-1" and "2-3" connected to them are not adjacent in the X direction. Therefore, it can be said that the connection relationship in FIG. 5 is an example where the arrangement relationship of a plurality of pixel blocks and the arrangement relationship of a plurality of circuit blocks corresponding to each of the plurality of pixel blocks are different.

[0053] Also, in Fig. 5, focusing on any one of the pixel blocks connected overlappingly in the Z direction with the processing block, any one of the pixel blocks adjacent to the said pixel block is connected to a processing block that does not overlap in the Z direction. For example, focusing on the pixel block "1-1" connected overlappingly in the Z direction with the processing block, among the pixel blocks adjacent to the pixel block "1-1", the pixel block "2-1" is connected to the processing block "2-3" that does not overlap in the Z direction.

[0054] Fig. 6 is a schematic diagram showing the relationship between the brightness of the subject and heat generation. Fig. 6 shows the connection relationship of Fig. 5 in the XY plane.

[0055] For example, assume that light from a bright subject is incident across the pixel blocks "1-1", "1-2", "2-1" and "2-2". Incidentally, the subject often spans across adjacent pixel blocks like this.

[0056] For example, as a method for expanding the dynamic range, when using a method of reading out pixel signals by changing the exposure time or the number of pixel signal outputs for each pixel block, for the pixel block where light from a bright subject is incident, in order to prevent the pixels of the said pixel block from saturating, the pixel signal may be read out to the processing block more frequently than other pixel blocks. In this case, in the processing block where frequent reading is performed, correspondingly, processing such as AD conversion is performed more frequently, resulting in increased heat generation.

[0057] According to the embodiment of FIG. 6, the processing blocks “1-1”, “1-2”, “2-3” and “2-4” are connected to the pixel blocks “1-1”, “1-2”, “2-1” and “2-2”. Therefore, the processing blocks “1-1”, “1-2”, “2-3” and “2-4” generate a large amount of heat. Here, the processing blocks “1-1” and “1-2” are not adjacent to the processing blocks “2-3” and “2-4” in either the X or Y direction. Thus, the regions with large heat generation are dispersed as a whole. As a result, it is possible to suppress the noise of the pixel signal caused by the heat being transmitted to the pixel block side due to the concentration of the regions with large heat generation.

[0058] FIG. 7 schematically shows another connection relationship between the pixel block 120 and the processing block 220. In FIG. 7, the same components as those in FIG. 5 are denoted by the same reference numerals and the description thereof is omitted. Also, FIG. 7 is simplified in the same manner as FIG. 5.

[0059] In the example shown in FIG. 7, the pixel block “1-1” is connected to the processing block “1-1” overlapping in the Z direction which is the stacking direction, and the processing block “1-3” not overlapping in the Z direction. In this case, some of the pixels 112 of the pixel block “1-1” are connected to the processing block “1-1” by the connection wiring 255 and the connection wiring 256 connected thereto and mainly extending in the Z direction. On the other hand, some other pixels 112 of the pixel block “1-1” are connected to the processing block “1-3” by the connection wiring 255 and the connection wiring 257 connected thereto and extending in the XY direction as well.

[0060] Here, corresponding to the fact that the processing block 220 is of the column ADC type, it is preferable that the above-mentioned some of the pixels 112 and some other pixels 112 are for each column. Also, from the viewpoint of dispersing heat generation, it is preferable that some of the number of pixels and some other number of pixels are the same or substantially the same. For example, the pixels 112 in the odd columns of the pixel block “1-1” may be connected to the processing block “1-1”, and the pixels 112 in the even columns of the pixel block “1-1” may be connected to the processing block “1-3”.

[0061] In this case, in the figure, n connection wirings 255, n / 2 connection wirings 256, and n / 2 connection wirings 257 are each represented by one line. Note that it is the same as the case of FIG. 5 that all or part of the connection wiring 257 may be arranged on the side of the pixel portion 110.

[0062] Similarly, the pixel block "1-2" is connected to the processing block "1-2" overlapping in the Z direction which is the stacking direction, and the processing block "1-4" not overlapping in the Z direction. Further, the pixel block "1-3" is connected to the processing block "1-3" overlapping in the Z direction which is the stacking direction, and the pixel block "1-1" not overlapping in the Z direction. Also, the pixel block "1-4" is connected to the processing block "1-4" overlapping in the Z direction which is the stacking direction, and the pixel block "1-2" not overlapping in the Z direction.

[0063] In the example shown in FIG. 7, when focusing on one processing block, the processing block is connected to two pixel blocks. For example, the processing block "1-1" is connected to the pixel blocks "1-1" and "1-3". In this case, a part of the plurality of AD converters 42 of the processing block "1-1" is connected to one pixel block "1-1", and another part of the plurality of AD converters 42 is connected to the other pixel block "1-3". Thereby, parallel processing similar to the case where the pixel block and the processing block are connected one-to-one can be performed.

[0064] In FIG. 7, over the entire pixel portion 110 and the processing circuit portion 210, with the connection relationship between the pixel blocks and the processing blocks in the Y direction from "1" to "4" as one unit, the connection relationship is repeatedly applied in the XY direction. Note that a part of the repetition may have a different connection relationship.

[0065] The connection relationship between the pixel block and the processing block shown in FIG. 7 is, for example, that although the pixel block "1-1" overlaps with the processing block "1-1" but does not overlap with the processing block "1-3", it is connected to both of them. Therefore, it can be said that the connection relationship in FIG. 7 is also an example where the arrangement relationship of a plurality of pixel blocks and the arrangement relationship of a plurality of circuit blocks corresponding to each of the plurality of pixel blocks are different.

[0066] In the example of FIG. 7, for example, it is assumed that light from a bright subject is incident across the pixel blocks "1-1", "1-2", "2-1" and "2-2". In this case, since the pixel block "1-1" is connected to two processing blocks "1-1" and "1-3", heat generation is dispersed to these two processing blocks. Furthermore, since these two processing blocks are not adjacent to each other, the regions with large heat generation are further dispersed.

[0067] Also, when looking at the four pixel blocks "1-1", "1-2", "2-1" and "2-2" as a whole, the eight processing blocks "1-1", "1-2", "1-3", "1-4", "2-1", "2-2", "2-3" and "2-4" are connected to them, and the processing frequency in each processing block is half of the readout frequency of one pixel block. Therefore, the regions with large heat generation are dispersed as a whole. As a result, it is possible to suppress the noise of the pixel signal caused by heat being transmitted to the pixel block side due to the concentration of the regions with large heat generation.

[0068] FIG. 8 schematically shows another connection relationship between the pixel block 120 and the processing block 222. In FIG. 8, the same components as those in FIGS. 5 to 7 are denoted by the same reference numerals and the description thereof is omitted. Also, FIG. 8 is simplified in the same manner as FIG. 5.

[0069] In the example of FIG. 8, as a whole of the pixel section 110 and the processing circuit section 212, two pixel blocks are connected to one processing block as one pixel block group. For example, two pixel blocks "1-1" and "1-2" are connected by a connection wiring 250 to one processing block "1-1,2". In this case, each of the processing blocks 222 has 2n AD converters 42.

[0070] Furthermore, the pixel blocks "1-1" and "1-2" are connected to an overlapping processing block "1-1,2" in the Z direction, and the pixel blocks "1-3" and "1-4" are also connected to an overlapping processing block "1-3,4" in the Z direction. On the other hand, the pixel blocks "2-1" and "2-2" are connected by connection wirings 252 and 253 to a non-overlapping processing block "2-3,4" in the Z direction, and the pixel blocks "2-3" and "2-4" are also connected to a non-overlapping processing block "2-1,2" in the Z direction.

[0071] In FIG. 8, over the whole of the pixel section 110 and the processing circuit section 210, taking the connection relationship between the pixel blocks, i.e., the pixel block group where the X direction ranges from "1" to "4" and the Y direction ranges from "1" to "2", and the processing blocks as one unit, the connection relationship is repeatedly applied in the XY direction. Note that a part of the repetition may have a different connection relationship.

[0072] The connection relationship between the pixel blocks and the processing blocks shown in FIG. 8 is such that, for example, the pixel block "1-1" overlaps with the processing block "1-1,2", but the pixel block "2-1" does not overlap with the processing block "2-3,4". Therefore, it can be said that the connection relationship in FIG. 8 is also an example where the arrangement relationship of a plurality of pixel blocks and the arrangement relationship of a plurality of circuit blocks corresponding to each of the plurality of pixel blocks are different.

[0073] In the example of FIG. 8, for example, it is assumed that light from a bright subject is incident across pixel blocks "1-1", "1-2", "2-1", and "2-2". In this case, due to the above connection relationship, the processing blocks with increased processing frequency are processing blocks "1-1,2" and "2-3,4". Since these two processing blocks are not adjacent to each other, the regions with high heat generation are dispersed. As a result, it is possible to suppress the noise of the pixel signal caused by heat being transmitted to the pixel block side due to the concentration of the regions with high heat generation.

[0074] FIG. 9 schematically shows another connection relationship between pixel block 120 and processing block 222. In FIG. 9, the same components as those in FIGS. 5 to 8 are denoted by the same reference numerals, and the description thereof is omitted. Also, FIG. 8 is simplified in the same manner as FIG. 5.

[0075] In the example of FIG. 9, as a whole of pixel section 110 and processing circuit section 212, two pixel blocks are connected to two processing blocks as one pixel block group. For example, two pixel blocks "1-1" and "1-2" are connected by connection wirings 255, 256, and 257 to two processing blocks "1-1,2" and "1-3,4".

[0076] In this case, each of processing blocks 222 has 2n AD converters 42. Further, some pixels 112 of two pixel blocks "1-1" and "1-2" are connected to one processing block "1-1,2", and some other pixels 112 are connected to the other processing block "1-3,4". For example, the pixels 112 in the odd-numbered columns of both two pixel blocks "1-1" and "1-2" may be connected to one processing block "1-1,2", and the pixels 112 in the even-numbered columns of both pixel blocks "1-1" and "1-2" may be connected to the other processing block "1-3,4".

[0077] In FIG. 9, over the entire pixel section 110 and processing circuit section 210, with the connection relationship between the pixel blocks and processing blocks in the X direction from "1" to "4" as one unit, the connection relationship is repeatedly applied in the XY directions. Note that a part of the repetition may have a different connection relationship.

[0078] The connection relationship between the pixel blocks and processing blocks shown in FIG. 9 is such that, for example, pixel block "1-1" overlaps with processing block "1-1,2" but does not overlap with processing block "1-3,4". Therefore, it can be said that the connection relationship in FIG. 9 is an example where the arrangement relationship of a plurality of pixel blocks and the arrangement relationship of a plurality of circuit blocks corresponding to each of the plurality of pixel blocks are different.

[0079] In the example of FIG. 9, for example, it is assumed that light from a bright subject is incident across pixel blocks "1-1", "1-2", "2-1", and "2-2". In this case, due to the above connection relationship, heat generation is dispersed to four processing blocks having a two-fold area. Further, the processing frequency in the four processing blocks is half of the read frequency of one pixel block group. Thus, regions with large heat generation are dispersed as a whole. Thereby, it is possible to suppress noise in the pixel signal caused by heat being transmitted to the pixel block side due to the concentration of regions with large heat generation.

[0080] FIG. 10 schematically shows the connection relationship between pixel block 120 and processing block 220. In FIG. 10, the same components as those in FIG. 6 are denoted by the same reference numerals and the description thereof is omitted.

[0081] In FIG. 10, pixel block "1-1" is electrically connected to processing block "1-1". Pixel block "2-1" is electrically connected to processing block "2-3".

[0082] Here, the distance L1 between the pixel block "1-1" and the pixel block "2-1" is different from the distance L2 between the corresponding processing block "1-1" and the processing block "2-3". Specifically, the distance L1 is shorter than the distance L2. Here, the distance may be the distance between representative positions in each block. For example, the representative position may be the geometric center of gravity (also called the center) of each block. Also, when each block is rectangular, it may be any one of the corners.

[0083] Note that for the sake of explanation, the connection relationships of the pixel blocks "1-1" and "2-1" and the processing blocks "1-1" and "2-3" in FIG. 10 are the same as those in FIG. 6. However, the connection relationship is not limited to being the same as that in FIG. 6. In this embodiment, it is sufficient that the distance between a certain pixel block of interest and another pixel block is connected so as to be different from the distance between the corresponding two processing blocks.

[0084] Also, in the above distance relationship, the pixel block of interest and another pixel block do not have to be adjacent to each other. Further, if there is at least one pair of a pixel block and a processing block in which the distance between a certain pixel block of interest and another pixel block is different from the distance between the corresponding two processing blocks, a pair in which the distance between the other two pixel blocks is the same as the distance between the corresponding processing blocks may be included.

[0085] Note that in any of the above embodiments, a discharge portion may be provided in the pixel 112. The discharge portion discharges the charge accumulated in the photoelectric conversion portion 104 to a power supply wiring to which the power supply voltage VDD is supplied. As yet another example, the transfer portion 123 may be omitted. In that case, the accumulation portion 125 no longer has the function as a floating diffusion. Also, the accumulation portion 125 and the pixel output portion 127 may be shared with other pixels. Also, the pixel 112 may be composed of a plurality of photoelectric conversion portions 104 and transfer portions 123.

[0086] Furthermore, in any of the above embodiments, the exposure control unit 10 and the pixel driving unit 20 may not be provided in the processing block 220, and reading may be mainly performed for each processing block 220 and conversion may be performed by the signal conversion unit 40. In this case, the exposure time of the pixels 112 is controlled not for each pixel block 120 but for the entire pixel unit 110.

[0087] FIG. 11 is a block diagram showing a configuration example of an imaging device 500 according to an embodiment. The imaging device 500 includes an image sensor 400, a system control unit 501, a driving unit 502, a photometric unit 503, a work memory 504, a recording unit 505, a display unit 506, a driving unit 514, and a photographing lens 520.

[0088] The photographing lens 520 guides a subject light beam incident along the optical axis OA to the image sensor 400. The photographing lens 520 is composed of a plurality of optical lens groups and forms an image of a subject light beam from a scene near its focal plane. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. Note that in FIG. 11, the photographing lens 520 is represented by a virtual single lens disposed near the pupil.

[0089] The driving unit 514 drives the photographing lens 520. In one example, the driving unit 514 moves the optical lens groups of the photographing lens 520 to change the focusing position. Further, the driving unit 514 may drive the iris diaphragm in the photographing lens 520 to control the amount of subject light beam incident on the image sensor 400.

[0090] The driving unit 502 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 400 according to an instruction from the system control unit 501. The operation unit 508 receives an instruction from an imaging person via a release button or the like.

[0091] The imaging element 400 delivers the pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 generates image data subjected to various image processes using the work memory 504 as a workspace. For example, when generating image data in the JPEG file format, after generating a color video signal from the signal obtained in the Bayer array, a compression process is executed. The generated image data is recorded in the recording unit 505 and is also converted into a display signal and displayed on the display unit 506 for a preset period of time.

[0092] The photometry unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor of about 1 million pixels. The arithmetic unit 512 of the system control unit 501 calculates the luminance for each region of the scene in response to the output of the photometry unit 503.

[0093] The arithmetic unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The photometry unit 503 may be combined with the imaging element 400. Note that the arithmetic unit 512 also executes various operations for operating the imaging device 500. The drive unit 502 may be partially or entirely mounted on the imaging element 400. A part of the system control unit 501 may be mounted on the imaging element 400.

[0094] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0095] In the claims, the specification, and the drawings, the execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown is not explicitly indicated as "earlier" or "preceding" etc. in particular, and it should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flows in the claims, the specification, and the drawings, even if "first," "next," etc. are used for convenience in the description, it does not mean that it is essential to be implemented in this order.

Explanation of Reference Numerals

[0096] 10 Exposure control unit, 20 Pixel drive unit, 30 Junction part, 40 Signal conversion unit, 42 AD converter, 50 Signal output unit, 100 First substrate, 102 Interface surface, 104 Photoelectric conversion unit, 110 Pixel part, 112 Pixel, 120 Pixel block, 121 Load current source, 122 Signal line, 123 Transfer part, 125 Accumulation part, 126 Reset part, 127 Pixel output part, 128 Amplification part, 129 Selection part, 200 Second substrate, 210, 212 Processing circuit part, 220, 222 Processing block, 250, 252, 253, 255, 256, 257 Connection wiring, 400 Imaging element, 500 Imaging device, 501 System control unit, 502 Drive unit, 503 Photometry unit, 504 Work memory, 505 Recording unit, 506 Display unit, 508 Operation unit, 511 Image processing unit, 512 Arithmetic unit, 514 Drive unit, 520 Photographing lens

Claims

[Claim 1] a first substrate on which pixel blocks are arranged in the row and column directions, the pixel blocks including a first photoelectric conversion unit that converts light into electric charges and a second photoelectric conversion unit that converts light into electric charges and is arranged in the row direction alongside the first photoelectric conversion unit; a second substrate, which is a substrate stacked on the first substrate, and in which processing blocks each including a plurality of conversion units for converting an analog signal into a digital signal are arranged side by side in the row direction and the column direction; Equipped with the processing block includes a first processing block arranged at a position overlapping a first pixel block among the pixel blocks in a stacking direction in which the first substrate and the second substrate are stacked, the first processing block includes a first conversion unit that converts a signal based on charges converted by the first photoelectric conversion unit of a second pixel block that is disposed at a position different from the first pixel block among the pixel blocks into a digital signal, and a second conversion unit that converts a signal based on charges converted by the second photoelectric conversion unit of the second pixel block into a digital signal; Image sensor.

Images