Semiconductor device
Patent Information
- Application Number
- JP2023196771
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-11-20
- Publication Date
- 2025-10-22
AI Technical Summary
Conventional semiconductor devices with temperature detection units become complex and require temperature correction, which can complicate the design and increase costs.
A semiconductor device is designed without a temperature detection unit, where the main element and sense element have a well layer in the sense cell region, allowing the detection of main current based on the detection result of a detection unit connected to the sense element, without being affected by temperature.
This design reduces the influence of temperature on current detection, eliminating the need for temperature correction and simplifying the device configuration, while maintaining accurate current detection.
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device.
Background Art
[0002] Conventionally, a semiconductor device having a main cell region in which a main element is formed and a sense cell region in which a sense element is formed has been proposed (see, for example, Patent Document 1). Specifically, the main element and the sense element in this semiconductor device are configured by forming IGBT (abbreviation for Insulated Gate Bipolar Transistor) elements having the same configuration, such as a gate structure and an emitter region. Further, the main element and the sense element (that is, the main cell region and the sense cell region) are formed so as to have a predetermined area ratio. Furthermore, this semiconductor device includes a temperature detection unit that detects the temperature of the semiconductor substrate on which the main element and the sense element are formed.
[0003] In such a semiconductor device, the current flowing through the main element is detected as follows. That is, a detection resistor is connected in series to the sense element in the semiconductor device. When detecting the current flowing through the main element, a control unit that performs a predetermined process detects the voltage across the detection resistor as a detection voltage, and detects the current flowing through the main element based on this detection voltage.
[0004] More specifically, when the main element and the sense element have the same configuration, the current flowing through the main element and the current flowing through the sense element depend on the area ratio between the main element and the sense element. For this reason, the main current flowing through the main element is derived from the sense current (that is, the detection voltage) flowing through the sense element and the area ratio between the main element and the sense element. At this time, the control unit detects the current flowing through the main element while performing correction using the temperature detected by the temperature detection unit.
Prior Art Documents
Patent Documents
[0005] Patent Document 1 Japanese Patent Application Laid-Open No. 2006-271098 Summary of the Invention Problems to be Solved by the Invention
[0006] However, in a configuration including a temperature detection unit, the configuration may become complicated. And the present inventors are considering a semiconductor device that can reduce the influence of temperature without including a temperature detection unit and without performing temperature correction.
[0007] An object of the present disclosure is to provide a semiconductor device that can reduce the influence of temperature without performing temperature correction. Means for Solving the Problems
[0008] According to one aspect of the present disclosure, there is provided a semiconductor device having a main cell region (Rm) in which a main element (Me) is formed and a sense cell region (Rs) in which a sense element (Se) is formed. A detection unit (R) is connected to the sense element, and a main current flowing through the main element is detected based on a detection result of the detection unit. The main element and the sense element have a semiconductor substrate (10) including a drift layer (11) of a first conductivity type. The main element includes a base layer (12) of a second conductivity type formed on the drift layer, an emitter region (16) of the first conductivity type formed on the surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a gate insulating film (14) disposed on the surface of the base layer disposed between the emitter region and the drift layer, a gate electrode layer (15) disposed on the gate insulating film, and a collector layer (19) formed on the opposite side of the base layer with the drift layer interposed therebetween. The sense element has a well layer (17) of the second conductivity type formed on the drift layer, an emitter electrode (E) electrically connected to the emitter region and the base layer, a collector electrode (C) electrically connected to the collector layer, and a sense electrode (S) electrically connected to the well layer. When a predetermined voltage is applied to the gate electrode layer, a first carrier is supplied from the emitter electrode to the drift layer and a second carrier is supplied from the collector electrode to the drift layer, and a part of the second carrier supplied to the drift layer flows into the well layer.
[0009] According to this, in the sense cell region, a well layer is formed on the drift layer, and when the main cell region is in an on state, a part of the second carrier flows into the well layer. In this case, the detection result of the detection unit connected to the sense element is based on the second carrier, and this detection result is not affected by temperature. Therefore, according to this semiconductor device, when detecting the main current based on the detection result of the detection unit connected to the sense element, the main current can be detected in a state where the influence of temperature is reduced without performing temperature correction.
[0010] Note that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.
Brief Description of the Drawings
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Embodiments for Carrying Out the Invention
[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are identical or equivalent to each other will be described with the same reference numerals.
[0013] (First Embodiment) The first embodiment will be described with reference to the drawings. Note that the semiconductor device of this embodiment is preferably applied, for example, as a device mounted on a vehicle such as an automobile and for driving various in-vehicle electronic devices.
[0014] As shown in FIG. 1, the semiconductor device of this embodiment has a main cell region Rm in which a main element Me is formed and a sense cell region Rs in which a sense element Se is formed. Note that the main cell region Rm and the sense cell region Rs are formed to have a predetermined area ratio (for example, several thousand:1).
[0015] The semiconductor device is configured using a semiconductor substrate 10, and the semiconductor substrate 10 has an N - -type drift layer 11. In the main cell region Rm, a P-type base layer 12 having a relatively low impurity concentration is disposed on the drift layer 11. In this embodiment, the base layer 12 has an outer edge base layer 12a on the sense cell region Rs side and an inner edge base layer 12b located on the inner edge side rather than the outer edge base layer 12a. The outer edge base layer 12a is deeper than the inner edge base layer 12b so as to suppress the occurrence of electric field concentration at the end on the outer edge side in the main cell region Rm. Hereinafter, in the semiconductor substrate 10, the surface on the base layer 12 side will be described as one surface 10a of the semiconductor substrate 10, and the surface located on the side opposite to the one surface 10a will be described as the other surface 10b.
[0016] In the semiconductor substrate 10, in the main cell region Rm, a plurality of trenches 13 are formed so as to penetrate the base layer 12 from one surface 10a side and reach the drift layer 11. And the base layer 12 in the main cell region Rm is separated into a plurality of parts by these trenches 13. Note that the plurality of trenches 13 have one direction (that is, the depth direction in the drawing in FIG. 1) in the plane direction of one surface 10a of the semiconductor substrate 10 as the longitudinal direction, and each trench 13 is extended so as to be in a stripe shape at equal intervals. And a portion of the base layer 12 located on the sense cell region Rs side from the trench 13 disposed at the end in the intersection direction intersecting with one direction is the outer edge base layer 12a. Note that the intersection direction can also be referred to as the arrangement direction of the trenches 13.
[0017] Inside each trench 13, it is filled with a gate insulating film 14 formed so as to cover the wall surface of each trench 13 and a gate electrode layer 15 formed of polysilicon or the like on this gate insulating film 14. Thereby, a trench gate structure is configured. Note that, in the present embodiment, a portion of the wall surface of the trench 13 that exposes the base layer 12 corresponds to the surface of the base layer 12 disposed between the emitter region 16 and the drift layer 11.
[0018] In the main cell region Rm, an N + -type emitter region 16 is formed in the surface layer portion of the base layer 12. Specifically, the emitter region 16 is formed with a higher impurity concentration than the drift layer 11 and is formed along the longitudinal direction of the trench 13. Although not particularly shown in FIG. 1, a P + -type contact region having a higher impurity concentration than the base layer 12 may be formed in a portion of the surface layer portion of the base layer 12 located on the side opposite to the trench 13 with the emitter region 16 interposed therebetween.
[0019] In the sense cell region Rs, a P-type well layer 17 is formed on the drift layer 11. In this embodiment, the well layer 17 is formed at a distance d from the base layer 12. Therefore, in this embodiment, the drift layer 11 is disposed between the well layer 17 and the base layer 12. In other words, in the semiconductor device of this embodiment, an intermediate region Rt in which the base layer 12 and the well layer 17 are not formed is disposed between the main cell region Rm and the sense cell region Rs.
[0020] Note that the well layer 17 of this embodiment has the same impurity concentration as the outer edge base layer 12a in the main cell region Rm and is formed at the same depth as the outer edge base layer 12a. Therefore, the well layer 17 is formed in the same process as the process of forming the outer edge base layer 12a.
[0021] In the main cell region Rm, the base layer 12 and the emitter region 16 are connected to the emitter electrode E, and the gate electrode layer 15 is connected to the gate electrode G. In the sense cell region Rs, the well layer 17 is connected to the sense electrode S.
[0022] In the main cell region Rm and the sense cell region Rs, an N-type field stop layer (hereinafter simply referred to as the FS layer) 18 is formed on the side opposite to the base layer 12 side of the drift layer 11 (that is, on the other surface 10b side of the semiconductor substrate 10). This FS layer 18 is not necessarily required, but is provided to improve the breakdown voltage and steady-state loss performance by preventing the spread of the depletion layer and to control the injection amount of holes injected from the other surface 10b side of the semiconductor substrate 10.
[0023] A p-type collector layer 19 is formed on the side opposite to the drift layer 11 with the FS layer 18 interposed therebetween. The collector layer 19 is connected to the collector electrode C.
[0024] The above is the configuration of the semiconductor device in this embodiment. Note that in this embodiment, N-type, N - type, N +The type corresponds to the first conductivity type, and the P type and P+ type correspond to the second conductivity type. In such a semiconductor device, as described above, the semiconductor substrate 10 is configured to include a collector layer 19, an FS layer 18, a drift layer 11, a base layer 12, an emitter region 16, and the like. Further, although the details are omitted above, a termination structure such as a guard ring is formed so as to surround the main cell region Rm and the sense cell region Rs.
[0025] Next, while explaining the operation of such a semiconductor device and the main current (i.e., collector current IC) flowing through the main cell region Rm, a more detailed configuration will be described.
[0026] In the semiconductor device of this embodiment, when a voltage lower than that of the collector electrode C is applied to the emitter electrode E and a voltage equal to or higher than the threshold voltage in the insulated gate structure is applied to the gate electrode layer 15, an N-type inversion layer (i.e., channel) is formed in a portion of the base layer 12 in contact with the trench 13. In the main cell region Rm, electrons are supplied from the emitter region 16 to the drift layer 11 through the inversion layer, and holes are supplied from the collector layer 19 to the drift layer 11. Due to conductivity modulation, the resistance value of the drift layer 11 decreases and the collector current IC flows, resulting in an on state. In this embodiment, electrons correspond to the first carrier and holes correspond to the second carrier.
[0027] Here, in the energy band, since the energy is lower for holes supplied to the drift layer 11 in the P type than in the N type, a part of the holes supplied to the drift layer 11 becomes a hole current flowing into the P-type layer. In this embodiment, a P-type base layer 12 is formed in the main cell region Rm, and a P-type well layer 17 is formed in the sense cell region Rs. Therefore, as shown in FIG. 2, the hole current is divided into a main hole current MH flowing through the base layer 12 in the main cell region Rm and a sense hole current SH flowing through the well layer 17 in the sense cell region Rs. Note that the main hole current MH and the sense hole current SH flow at a predetermined ratio according to the impurity concentration and the like of the drift layer 11, the base layer 12, and the well layer 17.
[0028] And, the main current (i.e., collector current IC) of the main cell region Rm in the semiconductor device of this embodiment is detected using the circuit configuration as shown in FIG. 3. Specifically, in this circuit configuration, a detection resistor R composed of a shunt resistor is provided as a detection unit between the sense electrode S of the sense element Se and the emitter electrode E of the main element Me.
[0029] And, the main current flowing through the main element Me is detected based on the detection voltage Vs which is the voltage across the detection resistor R by a control unit (not shown) or the like. More specifically, first, the sense current flowing through the sense element Se is detected from the detection voltage Vs. Note that the sense current in this embodiment is the sense hole current SH. Also, in this embodiment, the detection voltage Vs corresponds to the detection result.
[0030] Here, the inventors of the present invention intensively studied the hole current density using the model shown in FIG. 4 and obtained the results shown in FIGS. 5A to 5C. As shown in FIGS. 5A to 5C, it is confirmed that the hole current density hardly changes even when the temperature changes. Note that the model shown in FIG. 4 has an area ratio of the main cell region Rm to the sense cell region Rs of 30:1.
[0031] And, the inventors of the present invention obtained the results shown in FIG. 6 regarding the relationship between the collector current IC (i.e., the main current) flowing through the main cell region Rm when the temperature is changed and the detection voltage Vs of the detection resistor R. As shown in FIG. 6, it is confirmed that the detection voltage Vs hardly depends on the temperature.
[0032] On the other hand, when a conventional semiconductor device in which the sense cell region Rs has the same configuration as the main cell region Rm is used as the semiconductor device of the comparative example, in the semiconductor device of the comparative example, as shown in FIG. 7, it is confirmed that the detection voltage Vs changes greatly depending on the temperature.
[0033] Note that the detection voltage Vs in FIGS. 6 and 7 is the result when the resistance value of the detection resistor R is 1 Ω. Also, FIGS. 6 and 7 are the results when the distance d is 13 μm. In other words, when the distance d is set to 13 μm, it means the case where the distance d is about 10% of the thickness of the semiconductor substrate 10.
[0034] And when the detection voltage Vs at 25 °C is taken as the Viterbi reference (i.e., Viterbi = 1), as shown in FIG. 8, in the semiconductor device of this embodiment, it is confirmed that the Viterbi hardly changes even when the temperature changes. In contrast, in the semiconductor device of the comparative example, it is confirmed that the Viterbi increases as the temperature increases. Note that the Viterbi in FIG. 8 is the result when the resistance value of the detection resistor R is 1 Ω and the collector current IC is 925 A. Also, FIG. 8 is the result when the distance d is 13 μm.
[0035] Furthermore, the inventors of the present invention have also intensively studied the electron current density for the model shown in FIG. 4 and obtained the results shown in FIGS. 9A to 9C. As shown in FIGS. 9A to 9C, it is confirmed that, similar to the hole current density, the electron current density hardly changes even when the temperature changes.
[0036] Then, the electron current and hole current flowing into the main cell region Rm flow at a predetermined ratio according to the impurity concentration of the drift layer 11, the base layer 12, the emitter region 16, and the like. Therefore, in the present embodiment, the ratio between the main hole current MH and the sense hole current SH is examined in advance by experiments or the like, and the ratio between the main hole current MH and the electron current in the main cell region Rm is also examined in advance. Then, when detecting the collector current IC flowing into the main cell region Rm, the main current is detected as follows based on the examined ratio between the main hole current MH and the sense hole current SH and the ratio between the main hole current MH and the electron current in the main cell region Rm. That is, the sense hole current SH is derived from the detection voltage Vs, and the main hole current MH is derived from the sense hole current SH. Then, the main current flowing into the main cell region Rm is detected by deriving the electron current from the main hole current MH. At this time, since the hole current density and the electron current density are not affected by temperature as described above, a circuit or the like for performing temperature correction is not particularly necessary. That is, according to the semiconductor device of the present embodiment, the main current can be detected while reducing the influence of temperature without performing temperature correction.
[0037] And in a semiconductor device such as the present embodiment, as described above, the sense hole current SH flows into the well layer 17 of the sense cell region Rs. In this case, if the distance d between the sense cell region Rs and the main cell region Rm is made too wide, it becomes difficult for the sense hole current SH to enter the well layer 17, and the detection voltage Vs may become too small. Therefore, the inventors defined the ratio of the distance d to the thickness of the semiconductor substrate 10 as the distance ratio, and intensively studied the relationship between the distance ratio and the detection voltage Vs to obtain the results shown in FIG. 10. The detection voltage Vs in FIG. 10 is the result when the resistance value of the detection resistor R is set to 1 Ω and the collector current IC is 925 A at 25°C.
[0038] As shown in FIG. 10, it is confirmed that the detected voltage Vs increases as the distance ratio increases when the distance ratio is 0.1 or less. Then, when the distance ratio is greater than 0.1, the detected voltage Vs decreases as the distance ratio increases, and when the distance ratio becomes 4 or more, it is confirmed that the detected voltage Vs is lower than that when the distance ratio is 0. Therefore, when separating between the main cell region Rm and the sense cell region Rs as in this embodiment, the distance d between the main cell region Rm and the sense cell region Rs is preferably adjusted so that the distance ratio is 4 or less.
[0039] Note that it is assumed that the detected voltage Vs becomes small when the distance ratio is 0 (that is, when the well layer 17 and the base layer 12 are connected) due to the following phenomenon. That is, when detecting the detected voltage Vs with the circuit configuration as shown in FIG. 3, if the well layer 17 and the base layer 12 are connected, the resistance between the well layer 17 and the base layer 12 is likely to be smaller than the detection resistance R. And, the sense hole current SH, after flowing into the well layer 17, partly escapes from the base layer 12 in the main cell region Rm. For this reason, when the distance ratio is 0, it is assumed that the sense hole current SH flowing through the detection resistance R decreases, so that the detected voltage Vs becomes small.
[0040] Therefore, when the detected voltage Vs becomes smaller than a desired value, it is preferable to appropriately adjust the magnitude of the detected voltage Vs by performing adjustments such as increasing the resistance value of the detection resistance R. However, if the resistance value of the detection resistance R is increased too much, the potential difference between the sense electrode S and the emitter electrode E becomes too large, and there is a possibility that this potential difference exceeds the breakdown voltage between the well layer 17 and the base layer 12. For this reason, when adjusting the resistance value of the detection resistance R, it is preferable to also consider the breakdown voltage between the well layer 17 and the base layer 12. Specifically, the resistance value of the detection resistance R is preferably set so that the potential of the sense electrode S becomes lower than the collector-emitter voltage between the main cell region Rm.
[0041] According to the present embodiment described above, in the sense cell region Rs, a P-type well layer 17 is formed on the drift layer 11, and when the main cell region Rm is in the on state, a part of the hole current flows in. Then, when a detection resistor R is connected to the sense cell region Rs and the voltage across the detection resistor R is detected as the detection voltage Vs, the detection voltage Vs is not affected by temperature. Therefore, by detecting the main current flowing through the main cell region Rm based on this detection voltage Vs, the main current can be detected with the influence of temperature reduced without performing temperature correction.
[0042] (1) In the present embodiment, the well layer 17 formed in the sense cell region Rs is formed apart from the base layer 12 formed in the main cell region Rm. Therefore, it becomes difficult for the holes flowing into the well layer 17 to escape from the base layer 12, and it is easy to increase the detection voltage Vs.
[0043] (2) In the present embodiment, by setting the distance ratio to 4 or less, the detection voltage Vs can be made larger than when the well layer 17 is connected to the base layer 12.
[0044] (Second Embodiment) The second embodiment will be described. This embodiment is the same as the first embodiment described above, except that the well layer 17 is connected to the base layer 12. Therefore, the description is omitted here.
[0045] In the semiconductor device of the present embodiment, as shown in FIG. 11, the base layer 12 of the main cell region Rm and the well layer 17 of the sense cell region Rs are connected. That is, the distance d between the main cell region Rm and the sense cell region Rs is set to 0, and the intermediate region Rt in the first embodiment is not arranged between the main cell region Rm and the sense cell region Rs. And in this embodiment, the well layer 17 is set to the same depth as the outer edge base layer 12a. Note that when such a semiconductor device is used, as described in the first embodiment, the detection voltage Vs tends to be small. Therefore, in this embodiment, it is preferable to appropriately adjust the resistance value of the detection resistor R.
[0046] According to the present embodiment described above, since the P-type well layer 17 is formed on the drift layer 11 in the sense cell region Rs, the same effects as those of the first embodiment can be obtained.
[0047] (1) In the present embodiment, the well layer 17 is connected to the base layer 12, and the intermediate region Rt is not arranged between the main cell region Rm and the sense cell region Rs. Therefore, the semiconductor device can be miniaturized, and the structure can be simplified because the breakdown voltage design for the intermediate region Rt is not required.
[0048] (Modification of the Second Embodiment) A modification of the second embodiment will be described. In the second embodiment, as shown in FIG. 12, the well layer 17 may have the same depth as the inner edge base layer 12b. That is, the well layer 11 does not have to have a uniform depth, and the depth may be adjusted according to the breakdown voltage design. For example, in FIG. 12, a portion having the same depth as the inner edge base layer 12b of the well layer 11 is formed between the deep portion of the well layer 11 and the base layer 12. Even with such a configuration, the same effects as those of the second embodiment can be obtained.
[0049] (Other Embodiments) Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent scope. In addition, various combinations and forms, and further other combinations and forms including only one element, more, or less thereof, are within the scope and spirit of the present disclosure.
[0050] For example, in each of the above embodiments, an example in which the first conductivity type is N-type and the second conductivity type is P-type has been described, but the first conductivity type can also be P-type and the second conductivity type can be N-type.
[0051] Also, in each of the above embodiments, the semiconductor device may be of a planar type in which the gate electrode layer 15 is disposed on one surface 10a of the semiconductor substrate 10 instead of the trench gate type.
[0052] Furthermore, in each of the above embodiments, the detection unit connected to the sense electrode S may be a current mirror circuit or the like instead of the detection resistor R.
Explanation of Reference Numerals
[0053] 11 Drift layer 12 Base layer 14 Gate insulating film 15 Gate electrode 16 Emitter region 17 Well layer 19 Collector layer C Collector electrode E Emitter electrode S Sense electrode
Claims
[Claim 1] A semiconductor device, A semiconductor device having a main cell region (Rm) in which a main element (Me) is formed and a sense cell region (Rs) in which a sense element (Se) is formed, wherein a detection unit (R) is connected to the sense element and a main current flowing through the main element is detected based on a detection result of the detection unit, The main element and the sense element have a semiconductor substrate (10) including a drift layer (11) of a first conductivity type, The main element has a base layer (12) of a second conductivity type formed on the drift layer, an emitter region (16) of a first conductivity type formed in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a gate insulating film (14) disposed on the surface of the base layer and disposed between the emitter region and the drift layer, a gate electrode layer (15) disposed on the gate insulating film, and a collector layer (19) formed on the opposite side of the drift layer from the base layer, The sense element has a well layer (17) of a second conductivity type formed on the drift layer, an emitter electrode (E) electrically connected to the emitter region and the base layer; a collector electrode (C) electrically connected to the collector layer; a sense electrode (S) electrically connected to the well layer, When a predetermined voltage is applied to the gate electrode layer, first carriers are supplied from the emitter electrode to the drift layer and second carriers are supplied from the collector electrode to the drift layer, and a portion of the second carriers supplied to the drift layer flows into the well layer, The well layer is spaced apart from the base layer of the main cell region, and a distance ratio, which is the ratio of the distance (d) between the well layer and the base layer to the thickness of the semiconductor substrate, is 4 or less.