Field effect transistor having field plate to be at least partially embedded

Abstract

To provide a semiconductor device including a field plate.SOLUTION: A semiconductor device includes: a semiconductor layer; a surface dielectric layer on the semiconductor layer; and at least one part of a gate of the surface dielectric layer. The surface dielectric layer includes an open to be separated to a lateral direction from the gate therein. The semiconductor device includes: an inter-layer dielectric layer on the surface dielectric layer; and a field plate on the inter-layer dielectric layer. The field plate is separated from the gate to the lateral direction, and at least one part of the field plate includes an embedded part to an upper direction of the open in the surface dielectric layer.SELECTED DRAWING: Figure 3A

Description

Technical Field

[0001] The present disclosure relates to transistor structures, and more particularly to electrolytic effect transistors including field plates.

Background Art

[0002] Narrow-bandgap semiconductor materials such as silicon (Si) and gallium arsenide (GaAs) are widely used for low-power applications and, in the case of Si, for semiconductor devices for low-frequency applications. However, these semiconductor materials have a relatively small bandgap (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and a relatively small breakdown voltage, and thus may not be very suitable for high-power and / or high-frequency applications.

[0003] Due to the interest in high-power, high-temperature, and / or high-frequency applications and devices, wide-bandgap semiconductor materials such as silicon carbide (3.2 eV for 4H-SiC at room temperature) and group III nitrides (e.g., 3.36 eV for GaN at room temperature) have attracted attention. These materials can have a higher breakdown field strength and a higher electron saturation velocity than GaAs and Si.

[0004] Particularly interesting devices for high-power and / or high-frequency applications are high electron mobility transistors (HEMTs), also known as modulation doped field effect transistors (MODFETs). In an HEMT device, a two-dimensional electron gas (2DEG) can be formed at the hetero-junction of two semiconductor materials with different bandgap energies, where the material with the smaller bandgap has a higher electron affinity than the wide-bandgap material. The 2DEG is an accumulation layer of the undoped small-bandgap material and has a relatively high sheet electron concentration, e.g., 10 13 carriers / cm 2It can contain a sheet electron concentration exceeding [a certain value]. Furthermore, electrons derived from a wider bandgap semiconductor may transfer to the 2DEG, and due to the reduction of scattering by ionized impurities, a relatively high electron mobility becomes possible. This combination of relatively high carrier concentration and carrier mobility can give a relatively large mutual conductance to the HEMT, bringing about a performance superiority over metal-semiconductor field effect transistors (MESFETs) for high-frequency applications.

[0005] HEMTs fabricated from gallium nitride / aluminum gallium nitride (GaN / AlGaN) material systems can generate a large amount of RF power due to a combination of material properties such as a relatively high breakdown electric field, a relatively wide bandgap, a relatively large conduction band offset, and / or a relatively high saturated electron drift velocity. Most of the electrons in the 2DEG may be due to polarization in AlGaN.

[0006] Field plates are used to improve the performance of GaN-based HEMTs at microwave frequencies, and the performance is improved compared to devices without field plates. In many field plate approaches, it involves connecting the field plate to the source of the transistor with the field plate placed on the drain side of the channel. This reduces the electric field on the gate-drain side of the transistor, thereby increasing the breakdown voltage and potentially reducing the high-field trapping effect. However, among transistors with a gate-drain field plate, there may be some that show relatively low reliability performance, especially in class C (or higher) operations where the electric field on the source side of the gate is important.

[0007] FIG. 1 shows a GaN-based HEMT 10 formed on a silicon carbide substrate 12. There is a GaN channel layer 16 on the substrate 12, and an AlGaN barrier layer 18 on the channel layer 16. A two-dimensional electron gas (2DEG) 20 is generated in the channel layer 16 adjacent to the barrier layer 18. Source contact 22 and drain contact 24 are formed on the channel layer 16. The conductivity of the 2DEG 20 is modulated by applying a voltage to a gate 26 formed on the barrier layer 18 between the source contact 22 and the drain contact 24. As shown in FIG. 1, the gate 26 may have a mushroom configuration or a T-top configuration in a relatively narrow contact region extending through the surface dielectric layer 25 where the gate 26 contacts the barrier layer 18.

[0008] HEMT 10 includes a field plate 28 connected to the source contact 22. The field plate 28 is separated from the gate 26 by an interlayer dielectric layer 21 and is separated from the barrier layer 18 by the interlayer dielectric layer 21 and the surface dielectric layer 25. The field plate 28 extends above the gate 26 and extends laterally toward the drain 24.

[0009] The field plate 28 is connected to the source contact 22. Connecting the field plate 28 to the source contact 22 can reduce the gate-to-drain capacitance (Cgd), and as a result, the gain of the device can be increased. In addition to reducing the gate-to-drain capacitance Cgd, the presence of the field plate 28 can improve the linearity of the device and / or reduce the capacitance drain-bias dependence. GaN-based HEMTs generally exhibit good linearity, but further improvement may be desired for high-power RF applications. Also, the structure shown in FIG. 1 can reduce the gate-to-drain capacitance Cgd compared to a structure without a field plate, while the gate-to-drain capacitance Cgd may still show a large dependence on the bias of the drain contact 24.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Patent Document 9

Patent Document 10

Patent Document 11

Patent Document 12

Patent Document 13

Summary of the Invention

Means for Solving the Problems

[0011] Transistor elements according to some embodiments include a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an opening therein that is laterally spaced from the gate. The transistor element includes an interlayer dielectric layer on the surface dielectric layer and a field plate on the interlayer dielectric layer. The field plate is laterally spaced from the gate, and at least a portion of the field plate is within the opening in the surface dielectric layer.

[0012] In some embodiments, the field plate includes a non-embedded portion that extends over the semiconductor layer. The embedded portion of the field plate is vertically spaced from the semiconductor layer by a shorter distance than the non-embedded portion is vertically spaced from the semiconductor layer.

[0013] The interlayer dielectric layer extends into the opening in the surface dielectric layer. In some embodiments, the opening in the surface dielectric layer extends completely through the surface dielectric layer to expose the semiconductor layer. In some embodiments, the gate extends completely through the surface dielectric layer and contacts the semiconductor layer.

[0014] The transistor element may further include a source contact and a drain contact on the semiconductor layer, where the gate is between the source contact and the drain contact. The non-embedded portion may include a drain-side wing that extends over the semiconductor layer toward the drain contact. In some embodiments, the field plate includes a source-side wing that extends over the semiconductor layer toward the source contact. The drain-side wing may have a width from about 0 nm to about 500 nm. In some embodiments, the drain-side wing is vertically spaced from the semiconductor layer by the combined thickness of the interlayer dielectric layer and the surface dielectric layer.

[0015] In some embodiments, the field plate is electrically connected to a source contact outside the active region of the transistor element. The electrical connection between the field plate and the source contact may not cross over the gate.

[0016] The transistor element may further include a second opening in the surface dielectric layer that is laterally spaced from the first opening. The embedded contact portion of the gate may extend through the second opening. The opening may have a chamfered or rounded edge.

[0017] In some embodiments, the embedded portion of the field plate is vertically spaced from the semiconductor layer by the thickness of the interlayer dielectric layer. The embedded portion of the field plate may be vertically spaced from the semiconductor layer by a distance of from about 60 nm to about 300 nm, in some embodiments by a distance of from about 100 nm to about 200 nm, and in still other embodiments by a distance of about 150 nm.

[0018] In some embodiments, the field plate is laterally spaced from the gate by the thickness of the interlayer dielectric layer. In some embodiments, the field plate is laterally spaced from the gate by a thickness of from about 200 nm to about 700 nm, and in still other embodiments by a thickness of from about 200 nm to about 400 nm.

[0019] The field plate may have an overall width from about 600 nm to 1500 nm, and the embedded portion of the field plate may have a width from about 500 nm to about 900 nm. The opening may have a chamfered or rounded edge.

[0020] A method of forming a transistor element according to some embodiments includes forming a surface dielectric layer on a semiconductor layer, forming an opening in the surface dielectric layer, and forming a gate on the surface dielectric layer. The gate is laterally spaced from the opening. The method further includes forming an interlayer dielectric layer on the gate and the surface dielectric layer, the surface dielectric layer extending into the opening, and forming a field plate on the interlayer dielectric layer above the opening.

[0021] This method may further include a step of forming a second opening in the surface dielectric layer, wherein the first and second openings are laterally spaced apart from each other. The gate may be formed over the second opening, and the gate may include an embedded contact portion extending through the second opening. The embedded contact portion of the gate may contact the semiconductor layer. The second opening may have a chamfered or rounded edge.

[0022] The steps of forming the first and second openings include forming a preliminary surface dielectric layer over the semiconductor layer, selectively etching the preliminary surface dielectric layer to form the first and second holes in the preliminary surface dielectric layer, depositing a sacrificial dielectric layer over the semiconductor layer and the preliminary surface dielectric layer, wherein the sacrificial dielectric layer fills the first and second holes, anisotropically etching the sacrificial dielectric layer to expose portions of the semiconductor layer within the first and second holes and leave lateral portions of the sacrificial dielectric layer on the inner sidewalls of the first and second holes, wherein the preliminary surface dielectric layer and the lateral portions define the surface dielectric layer.

[0023] This method may further include a step of forming source and drain contacts over the semiconductor layer, wherein the gate is between the source and drain contacts, and the field plate may include an embedded portion over the opening and a drain-side wing extending over the semiconductor layer toward the drain contact.

[0024] The field plate may include a source-side wing extending over the semiconductor layer toward the source contact.

[0025] The drain-side wing is vertically spaced from the semiconductor layer by a combined thickness of the interlayer dielectric layer and the surface dielectric layer. The drain-side wing may have a width from about 0 nm to about 500 nm. The embedded portion of the field plate may have a width from about 500 nm to about 900 nm.

[0026] The method may further include electrically connecting a field plate to a source contact outside the active region of the transistor element, wherein the electrical connection between the field plate and the source contact does not cross over the gate.

[0027] Transistor elements according to some embodiments include a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an opening therein that is laterally spaced from the gate. The transistor element further includes an interlayer dielectric layer on the surface dielectric layer having a recess above the opening, and at least a portion of a field plate within the recess.

[0028] The field plate may include a non-embedded portion extending over the semiconductor layer, wherein the portion of the field plate within the recess is vertically spaced from the semiconductor layer by a smaller distance than the non-embedded portion that is vertically spaced from the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4A

Figure 4B

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 5F

Figure 5G

Figure 5H

Figure 6

Figure 7

Figure 8

Figure 9A

Figure 9B

Figure 9C

Mode for Carrying Out the Invention

[0030] Next, embodiments of the inventive concept will be described in relation to the accompanying drawings. Some embodiments described herein provide transistor elements that include field plates that are automatically aligned with respect to the gate such that the field plate does not overlap the gate in the vertical direction, and in some embodiments, the field plates are laterally spaced from the gate. In some embodiments, the field plates are embedded toward the barrier layer in the embedded region. In yet another embodiment, the field plate may be connected to a source outside the active region of the element by a connection that does not cross over the gate of the element.

[0031] It should be understood that although ordinal numbers, such as first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element could be called the second element, and similarly, the second element could be called the first element without departing from the scope of the present disclosure.

[0032] Furthermore, relative terms such as "lower" or "bottom", and "upper" or "top" may be used herein to describe the relationship of one element to another, as shown in the drawings. It should be understood that relative terms are intended to encompass different orientations of the element in addition to the orientation depicted in the drawings. For example, if an element is turned over in one of the drawings, a feature described as being on the "lower" side of the element will face the "upper" side of that element. Thus, the exemplary term "lower" can describe both downward and upward directions depending on the particular orientation of the element. Similarly, if an element is turned over in one of the drawings, an element described as "lower" or "below" another element will be oriented above those other elements. Thus, the exemplary terms "below" or "lower" can describe both upward and downward orientations.

[0033] The terms used in the description of the disclosure herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. When used in the description of the present disclosure and the appended claims, the singular forms "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "comprise" and "comprising", as used herein, specify the presence of the stated steps, operations, features, elements, and / or components, but do not preclude the presence or addition of one or more other steps, operations, features, elements, components, and / or groups thereof.

[0034] Embodiments of the present disclosure are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments of the present disclosure. As such, variations from the shapes of the figures are to be expected, for example as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be construed as being limited to the specific shapes of the regions illustrated herein, but should include deviations in shape resulting from, for example, manufacturing. The regions illustrated in the drawings are essentially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the elements, and are not intended to limit the scope of the disclosure, unless otherwise specified. Further, for schematic reasons, lines that appear straight, horizontal, or vertical in the following drawings will often be inclined, curved, non-horizontal, or non-vertical. Further, the thickness of the elements is meant to be essentially schematic.

[0035] Unless otherwise defined, all terms used in disclosing embodiments of the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the relevant art and are not necessarily limited to the specific definitions known at the time of the present disclosure. Accordingly, these terms can include equivalent terms created after such time. Further, terms such as those defined in commonly used dictionaries are to be understood as having a meaning consistent with their meaning in the context of the present specification and the relevant art.

[0036] Referring to FIG. 2, transistor elements according to some embodiments are illustrated. In particular, FIG. 2 shows a high electron mobility transistor 100 formed on a substrate 112. A channel layer 116 is formed on the substrate 112, and a barrier layer 118 is on the channel layer 116.

[0037] The source contact 122 and the drain contact 124 are formed on the channel layer 116. The gate 126 is formed on the barrier layer 118 between the source contact 122 and the drain contact 124. As shown in FIG. 2, the gate 26 may have a mushroom configuration or a T-top configuration, in which the gate 126 contacts the barrier layer 118 in a relatively narrow contact region of the embedded contact portion 127 of the gate 126, and the embedded contact portion 127 extends through the surface dielectric layer 125 inside the gate opening 162 passing through the surface dielectric layer 125.

[0038] The surface dielectric layer 125 also includes a field-plate opening 164 passing through the surface dielectric layer 125, exposing the barrier layer 118.

[0039] In some embodiments, the substrate 112 includes silicon carbide, the channel layer 116 includes GaN, and the barrier layer includes AlGaN. However, it will be understood that other materials or combinations of materials may also be used. Further, the channel layer 116 and / or the barrier layer 118 may include an alloy such as Al x Ga 1-x N, where 0 ≦ x ≦ 1. Although a HEMT device is illustrated, it will be further understood that the device 100 may be another type of transistor device such as a metal-semiconductor field effect transistor (MESFET), a junction field effect transistor (JFET), or a metal oxide semiconductor field effect transistor (MOSFET).

[0040] The device 100 includes a field plate 140 connected to the source contact 122 through a connection outside the active region of the device, as will be described later with reference to FIGS. 6 and 7. As will be described later, in some embodiments, the connection between the field plate 140 and the source contact 122 does not cross over the gate 126.

[0041] The field plate 140 is laterally spaced from the gate 126 by the interlayer dielectric layer 121 and, as in the structure shown in FIG. 1, does not extend over or beyond the gate 126, which means that step coverage is insufficient and there is a possibility of cracks occurring in the metallization of the field plate. The field plate 140 is electrically connected to the source contact 122 outside the active region of the device (and outside the plane shown in FIG. 2).

[0042] Similar to the gate 126, the field plate 140 may have a mushroom configuration or a T-top configuration, which includes a central embedded portion 144 and one or more wing portions extending laterally from the embedded portion 144 and is partially embedded. In the embodiment shown in FIG. 2, the field plate 140 includes a source-side wing 146 extending laterally towards the source contact 122 and a drain-side wing 148 extending laterally towards the drain contact 124.

[0043] The field plate 140 is generally vertically spaced from the barrier layer 118 by the interlayer dielectric layer 121 and the surface dielectric layer 125. The distance d2 between the wing of the field plate 140 and the barrier layer 118 is equal to the total thickness of the interlayer dielectric layer 121 and the surface dielectric layer 125. The field plate 140 includes an embedded portion 144 above the field plate opening 164, and the embedded portion 144 is vertically spaced from the barrier layer 118 by a distance d1 equal to only the thickness of the interlayer dielectric layer 121 within the region above the field plate opening 164.

[0044] The field plate 140 has an overall width L1. The source-side wing 146 of the field plate 140 has a width L2, the embedded portion 144 of the field plate 140 has a width L3, and the drain-side wing 148 of the field plate 140 has a width L4. The embedded portion 144 of the field plate 140 is laterally spaced from the gate 126 by a distance L5, and the field plate 140 is laterally spaced from the gate 126 by a distance L6. As will be described below, by adjusting the distances d1, d2, and the widths L1-L6, several degrees of freedom are provided for modulating the gate-source capacitance and the gate-drain capacitance of the device.

[0045] A passivation layer 132 is formed over the interlayer dielectric layer 121 and the field plate 140, and a field dielectric layer 134 is formed over the passivation layer 132. The passivation layer 132 may fill the gap between the field plate 140 and the gate 126 that is not filled by the interlayer dielectric layer 121.

[0046] The surface dielectric layer 125, the interlayer dielectric layer 121, the passivation layer 132, and the field dielectric layer 134 may include one or more layers of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or other atomic layer deposition films, or a multilayer insulator structure such as an oxide-nitride-oxide layer. In a particular embodiment, the surface dielectric layer 125 and the interlayer dielectric layer 121 include silicon nitride, the passivation layer 132 includes silicon oxynitride, and the field dielectric layer 134 includes silicon nitride.

[0047] FIG. 3A shows a HEMT transistor device structure 200A according to yet another embodiment. The device 200 is similar to the device 100 shown in FIG. 2, and like numbers refer to like elements except that the device 200 does not include the source-side wing 146. That is, the distance L5 between the embedded portion 144 of the field plate 140 and the gate 126 defines the distance L6 between the field plate 140 and the gate 126, and the width L2 of the source-side wing 146 is zero.

[0048] By providing the embedded portion 144 of the field plate 140, the drain-source capacitance Cds and the gate-train capacitance Cgd of the device change. In particular, by providing the embedded portion 144 of the field plate 140, the gate-drain capacitance Cgd of the device for a certain level of drain voltage can be decreased at the expense of increasing the drain-source capacitance Cds at a low drain voltage.

[0049] FIG. 3B shows a HEMT transistor device structure 200B according to yet another embodiment. The device 200 is similar to the device 100 shown in FIG. 2, and like numbers refer to like elements except that the device 200 does not include the source-side wing 146 or the drain-side wing 148. That is, the width L4 of the drain-side wing 148 is zero.

[0050] For example, FIG. 4A is a graph of the simulated gate-drain capacitance Cgd for a device having a partially embedded field plate according to some embodiments, while FIG. 4B is a graph of the simulated drain-source capacitance Cds for a device having a partially embedded field plate according to some embodiments. Referring to FIG. 4A, the simulated curves of the gate-drain capacitance Cgd are plotted for devices where the distance d1 between the embedded portion 144 of the field plate 140 and the barrier layer 118 is 200 nm (curve 402) and 150 nm (curve 404). The distance d1 between the embedded portion 144 of the field plate 140 and the barrier layer 118 is defined by the thickness of the interlayer dielectric layer 121.

[0051] In some embodiments, the distance d1 between the embedded portion 144 of the field plate 140 and the barrier layer 118 is from about 60 nm to about 300 nm, and in some embodiments, it is between about 100 nm and 200 nm. As described herein, embedding a portion of the field plate 140 can reduce the gate-drain capacitance Cgd, which can improve the efficiency, linearity, gain, and / or bandwidth of an amplifier fabricated using this device. Further, by using an etching process to form a field plate opening 164 in the surface dielectric layer 125 that defines the position of the embedded portion 144 of the field plate 140, it is possible to precisely control the position of the embedded portion 144, thereby improving the process repeatability and manufacturability of the device while also more precisely controlling the electrical characteristics of the device.

[0052] Separating the field plate 140 laterally from the gate 126 (e.g., by preventing the field plate 140 from overlapping the gate 126) can reduce the gate-drain capacitance Cgd and / or the drain-source capacitance Cds of the device by enhancing the ability of the field plate 140 to block the feedback capacitance from the gate to the drain. That is, overlapping the field plate 140 and the gate 126 can introduce additional parasitic capacitance without any additional benefit.

[0053] As shown in FIG. 4A, for drain voltages above 30 V, particularly about 30 - 40 V, a simulated device having a distance d1 of 150 nm exhibits a lower gate-drain capacitance Cgd compared to a simulated device having a distance d1 of 200 nm.

[0054] Referring to FIG. 4B, the simulated device having a distance d1 of 150 nm exhibits an undesirably high drain-source capacitance Cds compared to the simulated device having a distance d1 of 200 nm for drain voltages of less than about 30V. However, since the normal operating point of the GaN-based HEMT is a drain voltage of about 50V, this increased drain-source capacitance Cds may not affect normal device operation.

[0055] Therefore, separating the field plate 140 laterally from the gate 126 is thought to be able to improve the drain-source capacitance Cds while impairing the effect of the field plate 140 on the gate-drain capacitance Cgd. Therefore, the distance of the gap L6 between the field plate 140 and the gate 126 (as shown in FIGS. 2 and 3) can be selected to reduce the gate-drain capacitance Cgd without adversely affecting the drain-source capacitance Cds. For example, in some embodiments, the gap L6 between the field plate 140 and the gate 126 may be from 0.2 microns to 0.7 microns. If the gap is less than 0.2 microns, reliability problems may occur, and if the gap exceeds 0.7 microns, the gate-drain capacitance Cgd may become undesirably high. In some embodiments, the gap L6 may be from about 0.2 microns to about 0.4 microns.

[0056] The overall width of the field plate 140 (L1 in FIGS. 2 and 3) may be from about 0.6 microns to about 1.5 microns.

[0057] The width of the embedded portion 144 of the field plate 140 (L3 in FIGS. 2 and 3) may be from about 0.5 microns to 0.9 microns.

[0058] In some embodiments, the gate opening 162 and the field plate opening 164 may be formed such that they have chamfered or rounded edges. Chamfering or rounding the edges of the gate opening 162 and the field plate opening 164 results in a shape corresponding to the embedded contact portion 127 of the gate 126 and the embedded portion 144 of the field plate 140, which helps to reduce field crowding around the gate 126 and the field plate 140.

[0059] The widths L2, L4 of the source side wing 146 and the drain side wing 148 of the field plate 140 may also affect the gate-drain capacitance Cgd and / or the drain-source capacitance Cds of the device. The lengths of the wings 146, 148 may involve a trade-off between the gate-drain capacitance Cgd and the drain-source capacitance Cds. For example, the drain side wing 148 can reduce the gate-drain capacitance Cgd, but can increase the drain-source capacitance Cds. The drain side wing 148 may have a length L4 (FIGS. 2 and 3) between about zero and 0.5 microns. In particular, the drain side wing 148 may have a length L4 of about 0.3 microns. The source side wing 146 may have a length L2 (FIGS. 2 and 3) between about zero and 0.3 microns. In particular, the source side wing 146 may have a length L2 of zero microns.

[0060] Furthermore, because the parasitic capacitance is reduced, the field plate 140 may not need to handle as high a level of current and thus may be formed to have a smaller thickness than would otherwise be required.

[0061] FIGS. 5A through 5H are cross-sectional views showing operations for manufacturing a transistor device including a field plate according to some embodiments.

[0062] Referring to FIG. 5A, a substrate 112 is provided on which a channel layer 116 and a barrier layer 118 are formed thereon. A preliminary surface dielectric layer 125' is formed on the barrier layer 118. A layer of photoresist 52 is formed on the preliminary surface dielectric layer 125' and patterned to form two holes 54, 56 therein.

[0063] Referring to FIG. 5B, the preliminary surface dielectric layer 125' is selectively etched through the two holes 54, 56, for example, using reactive ion etching or inductively coupled plasma, to form two corresponding holes 154, 156 therein.

[0064] Referring to FIG. 5C, a sacrificial dielectric layer 165 is blanket deposited on the preliminary surface dielectric layer 125' to fill the holes 154, 156. The sacrificial dielectric layer 165 may be formed of the same material as the preliminary surface dielectric layer 125'. For example, both the sacrificial dielectric layer 165 and the preliminary surface dielectric layer 125' may be formed of silicon nitride.

[0065] Referring to FIG. 5D, the sacrificial dielectric layer 165 is anisotropically etched, for example, using reactive ion etching or inductively coupled plasma 167, to remove portions of the sacrificial dielectric layer 165 except for the lateral portions 166 on the inner surface of the hole 154 of the preliminary surface dielectric layer 125' and the lateral portion 168 on the inner surface of the hole 156 of the preliminary surface dielectric layer 125', to form a gate opening 162 and a field plate opening 164 having rounded or beveled edges as shown in FIG. 5E. Together with the lateral portions 166, 168, the preliminary surface dielectric layer 125' forms a surface dielectric layer 125 on the barrier layer 118. When the lateral portion 166 is present, the width of the gate opening 162 is about 250 nm.

[0066] Referring to FIG. 5F, a metal such as gold is deposited and patterned to form a mushroom gate or a T-top gate 126 on the surface dielectric layer 125. The embedded contact portion of the gate 126 extends through the gate opening 162 and contacts the barrier layer 118. Next, the interlayer dielectric layer 121 is blanket deposited over the surface dielectric layer 125 and the gate 126. The interlayer dielectric layer 121 extends through the field plate opening 164 and contacts the barrier layer 118.

[0067] Referring to FIG. 5G, next, a metal such as gold is deposited and patterned over the interlayer dielectric layer 121 above the field plate opening 164 to form a field plate 140. The field plate 140 is spaced from the barrier layer 118 by a distance d1 corresponding to the thickness of the interlayer dielectric layer 121 inside the field plate opening 164 and by a distance d2 corresponding to the sum of the thicknesses of the interlayer dielectric layer 121 and the surface dielectric layer 125 outside the field plate opening 164. The field plate 140 is laterally spaced from the gate 126 by a distance L6 approximately equal to the thickness of the interlayer dielectric layer 121. Thus, the field plate 140 is automatically aligned with the gate 126 by the distance L6.

[0068] Referring to FIG. 5H, a passivation layer 132, such as a layer of SiON, is formed over the field plate 140 and the interlayer dielectric layer 121. Finally, a field dielectric layer 134, such as silicon nitride, is formed over the passivation layer 132.

[0069] As described above, in order to further reduce the gate-drain capacitance Cgd and / or the drain-source capacitance Cds, the field plate 140 may be connected to the source contact 122 outside the active region of the device such that the connection does not cross over the gate metal. For example, FIG. 6 is a plan view of a portion of a conventional transistor structure outside the active region 300 of the device, and the “active region of the device” generally refers to the region of the device where an electrical channel is formed between the source region and the drain region and electrical conduction occurs through the channel layer 116 during the on-state operation of the device. As shown in FIG. 6, in the conventional device structure, the field plate 140 metallization crosses over the gate 126 metallization and contacts the source overmetallization 222. This arrangement may increase the gate-drain capacitance Cgd and / or the drain-source capacitance Cds of the device.

[0070] FIG. 7 is a plan view of a portion of a transistor structure according to some embodiments outside the active region 300 of the device. As shown in FIG. 7, in some embodiments, the field plate 140 metallization extends around the distal end 126A of the gate 126 metallization (rather than crossing over the gate 126 metallization) and contacts the source overmetallization 222. This arrangement can reduce the gate-drain capacitance Cgd and / or the drain-source capacitance Cds of the device.

[0071] FIG. 8 is a block diagram showing an operation of forming a transistor element according to some embodiments. Referring to FIGS. 8 and 5A through 5H, a method of forming a transistor element according to some embodiments includes forming a surface dielectric layer 125 on a semiconductor layer (block 802), forming an opening 164 in the surface dielectric layer (block 804), forming a gate 126 on the surface dielectric layer 125, the gate being laterally spaced from the opening 164 (block 806), forming an interlayer dielectric layer 121 on the gate and the surface dielectric layer 125, the surface dielectric layer extending into the opening 164 (block 808), and forming a field plate 140 on the interlayer dielectric layer 121 above the opening 164 (block 810).

[0072] The method may further include forming a second opening in the surface dielectric layer, the first and second openings being laterally spaced from each other. The gate is formed over the second opening and includes an embedded contact portion passing through the second opening. The embedded contact portion of the gate may contact the semiconductor layer.

[0073] The method may further include forming a source contact and a drain contact on the semiconductor layer, the gate being between the source contact and the drain contact. The field plate may include an embedded portion above the opening and a drain side wing extending over the semiconductor layer toward the drain contact. In some embodiments, the field plate includes a source side wing extending over the semiconductor layer toward the source contact.

[0074] The embedded portion of the field plate may be vertically spaced from the semiconductor layer by the thickness of the interlayer dielectric layer. In some embodiments, the embedded portion of the field plate may be vertically spaced from the semiconductor layer by a distance of from about 60 nm to about 300 nm, in some embodiments by a distance of from about 100 nm to about 200 nm, and in some embodiments by a distance of about 150 nm.

[0075] The drain-side wing may be vertically spaced from the semiconductor layer by a combined thickness of the interlayer dielectric layer and the surface dielectric layer. In some embodiments, the drain-side wing has a width from about zero to about 500 nm.

[0076] The field plate may be laterally spaced from the gate by a thickness of the interlayer dielectric layer. In some embodiments, the field plate is laterally spaced by a thickness from about 200 nm to about 700 nm, and in some further embodiments, by a thickness from about 200 nm to about 400 nm.

[0077] In some embodiments, the field plate has an overall width from about 600 nm to about 1500 nm. In some embodiments, the embedded portion of the field plate has a width from about 500 nm to about 900 nm.

[0078] In some embodiments, the opening and / or the second opening have chamfered or rounded edges.

[0079] The step of forming the first and second openings may include forming a preliminary surface dielectric layer on the semiconductor layer, selectively etching the preliminary surface dielectric layer to form the first and second holes in the preliminary surface dielectric layer, and depositing a sacrificial dielectric layer on the semiconductor layer and the preliminary surface dielectric layer, the sacrificial dielectric layer filling the first and second holes. Anisotropic etching may be performed to expose portions of the semiconductor layer within the first and second holes and leave lateral portions of the sacrificial dielectric layer on the inner sidewalls of the first and second holes.

[0080] This method may further include connecting the field plate to a source contact outside the active region of the transistor element, the electrical connection between the field plate and the source contact extending around an end of the gate and not crossing over the gate.

[0081] The transistor elements described in this specification can be used in amplifiers operating in a wide variety of different frequency bands. In some embodiments, an RF transistor amplifier incorporating transistor elements as described in this specification can be configured to operate at frequencies above 1 GHz. In other embodiments, the RF transistor amplifier can be configured to operate at frequencies above 2.5 GHz. In yet another embodiment, the RF transistor amplifier can be configured to operate at frequencies above 3.1 GHz. In further additional embodiments, the RF transistor amplifier can be configured to operate at frequencies above 5 GHz. In some embodiments, the RF transistor amplifier can be configured to operate in at least one of the frequency bands of 2.5 - 2.7 GHz, 3.4 - 4.2 GHz, 5.1 - 5.8 GHz, 12 - 18 GHz, 18 - 27 GHz, 27 - 40 GHz or 40 - 75 GHz, or a sub - portion thereof.

[0082] Embodiments of the inventive concept have been discussed above with respect to HEMT elements, but it will be understood that the inventive concept described herein can be applied to other types of semiconductor elements such as MOSFETs, DMOS transistors, and / or laterally diffused MOS (LDMOS) transistors.

[0083] An RF transistor amplifier incorporating the transistor elements described in this specification can be used in a stand - alone RF transistor amplifier and / or in a plurality of RF transistor amplifiers. An example of how an RF transistor amplifier according to some embodiments can be used in an application including a plurality of amplifiers will be discussed with reference to FIGS. 9A - 9C.

[0084] Referring to FIG. 9A, an RF transistor amplifier 1000A is schematically illustrated, which includes a preamplifier 1010 and a main amplifier 1030 that are electrically connected in series. As shown in FIG. 9A, the RF transistor amplifier 1000A includes an RF input 1001, a preamplifier 1010, an inter-stage impedance matching network 1020, a main amplifier 1030, and an RF output 1002. The inter-stage impedance matching network 1020 may include inductors and / or capacitors arranged in an arbitrary and appropriate configuration, for example, to form a circuit that improves the impedance matching between the output of the preamplifier 1010 and the input of the main amplifier 1030. Although not shown in FIG. 9A, the RF transistor amplifier 1000A may further include an input matching network interposed between the RF input 1001 and the preamplifier 1010, and / or an output matching network interposed between the main amplifier 1030 and the RF output 1002. The RF transistor amplifier according to the embodiment may be used to implement either or both of the preamplifier 1010 and the main amplifier 1030.

[0085] Referring to FIG. 9B, an RF transistor amplifier 1000B is schematically illustrated, which includes an RF input 1001, a pair of preamplifiers 1010-1 and 1010-2, a pair of inter-stage impedance matching networks 1020-1 and 1020-2, a pair of main amplifiers 1030-1 and 1030-2, and an RF output 1002. A splitter 1003 and a combiner 1004 are also provided. The preamplifier 1010-1 and the main amplifier 1030-1 (electrically connected in series) are electrically arranged in parallel with the preamplifier 1010-2 and the main amplifier 1030-2 (electrically connected in series). Similar to the RF transistor amplifier 1000A in FIG. 9A, the RF transistor amplifier 1000B may further include an input matching network interposed between the RF input 1001 and the preamplifiers 1010-1 and 1010-2, and / or an output matching network interposed between the main amplifiers 1030-1 and 1030-2 and the RF output 1002.

[0086] As shown in FIG. 9C, RF transistor amplifiers according to some embodiments can also be used to implement a Doherty amplifier. As is known in the art, a Doherty amplifier circuit includes first and second (or higher) power-combined amplifiers. The first amplifier is referred to as the “main” or “carrier” amplifier, and the second amplifier is referred to as the “peaking” amplifier. The biasing of the two amplifiers may be different. For example, in one common Doherty amplifier implementation, the main amplifier may comprise a class AB or class B amplifier, while the peaking amplifier may be a class C amplifier. The Doherty amplifier can operate more efficiently than a balanced amplifier when operating at power levels that have backed off from saturation. The RF signal input to the Doherty amplifier is split (e.g., using a quadrature coupler), and the outputs of the two amplifiers are combined. The main amplifier is configured to turn on first (i.e., at lower input power levels), and for this reason, only the main amplifier operates at lower power levels. As the input power level increases towards saturation, the peaking amplifier turns on, and the input RF signal is split between the main amplifier and the peaking amplifier.

[0087] As shown in FIG. 9C, the Doherty RF transistor amplifier 1000C includes an RF input 1001, an input splitter 1003, a main amplifier 1040, a peaking amplifier 1050, an output combiner 1004, and an RF output 1002. The Doherty RF transistor amplifier 1000C includes a 90° transformer 1007 at the input of the peaking amplifier 1050 and a 90° transformer 1005 at the input of the main amplifier 1040, and optionally may include an input matching network and / or an output matching network (not shown). The main amplifier 1040 and / or the peaking amplifier 1050 can be implemented using any of the above-described RF transistor amplifiers according to embodiments.

[0088] The RF transistor amplifier according to the embodiment may be formed as a discrete device or as part of a monolithic microwave integrated circuit (MMIC). An MMIC refers to an integrated circuit that operates with radio frequency and / or microwave frequency signals in which all circuits of a specific function are integrated on a single semiconductor chip. An example of an MMIC device is a transistor amplifier that includes associated matching circuits, a power supply network, etc., all mounted on a common substrate. An MMIC transistor amplifier typically includes a plurality of unit cell HEMT transistors connected in parallel.

[0089] Many modifications are possible to the features of the above embodiments. Transistor structures having features that can be used in embodiments of the present invention are disclosed in the following commonly assigned publications, each of which is hereby incorporated by reference in its entirety: U.S. Patent No. 6,849,882, Chavarkar et al., "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; U.S. Patent No. 7,230,284, Parikh et al., "Insulating Gate AlGaN / GaN HEMT"; U.S. Patent No. 7,501,669, Parikh et al., "Wide Bandgap Transistor Devices With Field Plates"; U.S. Patent No. 7,126,426, Mishra et al., "Cascode Amplifier Structures Including Wide Bandgap Field Effect Transistor With Field Plates"; U.S. Patent No. 7,550,783, Wu et al., "Wide Bandgap HEMTs With Source Connected Field Plates"; U.S. Patent No. 7,573,078, Wu et al., "Wide Bandgap Transistors With Multiple Field Plates"; U.S. Patent Application Publication No. 2005 / 0253167, Wu et al., "Wide Bandgap Field Effect Transistors With Source Connected Field Plates"; U.S. Patent Application Publication No. 2006 / 0202272, Wu et al., "Wide Bandgap Transistors With Gate-Source Field Plates"; U.S. Patent Application Publication No. 2008 / 0128752, Wu, "GaN Based HEMTs With Buried Field Plates";U.S. Patent Application Publication No. 2010 / 0276698, Moore et al., "Gate Electrodes For Millimeter-Wave Operation and Methods of Fabrication"; U.S. Patent Application Publication No. 2012 / 0049973, Smith, Jr. et al., "High Power Gallium Nitride Field Effect Transistor Switches"; U.S. Patent Application Publication No. 2012 / 0194276, Fisher, "Low Noise Amplifiers Including Group III Nitride Based High Electron Mobility Transistors"; and U.S. Patent No. 9,847,411, Sriram et al., "Recessed field plate transistor structures".;

[0090] Embodiments of the inventive concept have been described in considerable detail with reference to its specific configurations, but other versions are possible. The field plates and gates can also have many different shapes and can be connected to the source contact in various ways. Accordingly, the spirit and scope of the present invention should not be limited to the specific embodiments described above.

Claims

1. A semiconductor layer; a surface dielectric layer on the semiconductor layer; at least a portion of a gate on the surface dielectric layer, the surface dielectric layer including an opening therein that is laterally spaced from the gate; an interlevel dielectric layer on the surface dielectric layer; a field plate on the interlevel dielectric layer, the field plate being laterally spaced from the gate, at least a portion of the field plate being within the opening in the surface dielectric layer; and A transistor element comprising:

2. 2. The transistor device of claim 1 , wherein the field plate includes a non-recessed portion that extends over the semiconductor layer, the buried portion of the field plate being vertically spaced from the semiconductor layer a distance less than the non-recessed portion is vertically spaced from the semiconductor layer.

3. The transistor device of claim 1 , wherein the interlevel dielectric layer extends into the opening in the surface dielectric layer.

4. The transistor device of claim 1 , wherein the opening in the surface dielectric layer extends completely through the surface dielectric layer to expose the semiconductor layer.

5. The transistor device of claim 1 , wherein the gate extends completely through the surface dielectric layer to contact the semiconductor layer.

6. 3. The transistor element of claim 2, further comprising a source contact and a drain contact on the semiconductor layer, the gate being between the source contact and the drain contact, and the non-recessed portion comprising a drain side wing extending over the semiconductor layer towards the drain contact.

7. The transistor device of claim 6 , wherein the field plate includes a source side wing that extends over the semiconductor layer toward the source contact.

8. The transistor device of claim 6 , wherein the drain side wing has a width from about 0 nm to about 500 nm.

9. 7. The transistor element of claim 6, wherein the field plate is electrically connected to the source contact outside an active area of ​​the transistor element, and wherein the electrical connection between the field plate and the source contact does not cross over the gate.

10. The transistor device of claim 6 , wherein the drain side wing is vertically spaced from the semiconductor layer by the combined thickness of the interlevel dielectric layer and the surface dielectric layer.

11. The opening includes a first opening, and the transistor element includes: a second opening in the surface dielectric layer laterally spaced from the first opening 7. The transistor device of claim 6, further comprising: a buried contact portion of the gate extending through the second opening.

12. The transistor element of claim 11 , wherein the second opening has chamfered or rounded edges.

13. 2. The transistor device of claim 1, wherein the buried portion of the field plate is vertically spaced from the semiconductor layer by a thickness of the interlevel dielectric layer.

14. 14. The transistor device of claim 13, wherein the buried portion of the field plate is vertically spaced from the semiconductor layer by a distance of about 60 nm to about 300 nm.

15. 15. The transistor device of claim 14, wherein the buried portion of the field plate is vertically spaced from the semiconductor layer by a distance of about 100 nm to about 200 nm.

16. 16. The transistor device of claim 15, wherein the buried portion of the field plate is vertically spaced from the semiconductor layer by a distance of about 150 nm.

17. 2. The transistor device of claim 1, wherein the field plate is laterally spaced from the gate by a thickness of the interlevel dielectric layer.

18. 10. The transistor device of claim 1, wherein the field plate is laterally spaced from the gate by a thickness of about 200 nm to about 700 nm.

19. 10. The transistor device of claim 1, wherein the field plate is laterally spaced from the gate by a thickness of about 200 nm to about 400 nm.

20. The transistor device of claim 1 , wherein the field plate has a total width of about 600 nm to 1500 nm.

21. 10. The transistor device of claim 1, wherein the buried portion of the field plate has a width of from about 500 nm to about 900 nm.

22. A transistor element as claimed in claim 6 , wherein the opening has chamfered or rounded edges.

23. 1. A method of forming a transistor device, comprising the steps of: forming a surface dielectric layer over the semiconductor layer; forming an opening in the surface dielectric layer; forming a gate on the surface dielectric layer, the gate being laterally spaced from the opening; forming an interlevel dielectric layer over the gate and the surface dielectric layer, the surface dielectric layer extending into the opening; forming a field plate on the interlevel dielectric layer over the opening; A method comprising:

24. The opening includes a first opening, and the method further comprises: forming a second opening in the surface dielectric layer, the first and second openings being laterally spaced from one another; 24. The method of claim 23, further comprising: the gate is formed over the second opening, the gate comprising a buried contact portion extending through the second opening.

25. 25. The method of claim 24, wherein the buried contact portion of the gate contacts the semiconductor layer.

26. 25. The method of claim 24, wherein the second opening has a chamfered or rounded edge.

27. The step of forming the first and second openings includes: forming a preliminary surface dielectric layer on the semiconductor layer; selectively etching the preliminary surface dielectric layer to form first and second holes in the preliminary surface dielectric layer; depositing a sacrificial dielectric layer over the semiconductor layer and the preliminary surface dielectric layer, the sacrificial dielectric layer filling the first and second holes; anisotropically etching the sacrificial dielectric layer to expose portions of the semiconductor layer in the first and second holes and to leave lateral portions of the sacrificial dielectric layer on interior sidewalls of the first and second holes, the preliminary surface dielectric layer and the lateral portions defining the surface dielectric layer; 25. The method of claim 24, comprising:

28. forming a source contact and a drain contact on the semiconductor layer, the gate being between the source contact and the drain contact; 24. The method of claim 23, further comprising: wherein the field plate includes a buried portion over the opening and a drain side wing extending over the semiconductor layer toward the drain contact.

29. 30. The method of claim 28, wherein the field plate includes a source side wing that extends over the semiconductor layer toward the source contact.

30. 30. The method of claim 28, wherein the drain side wing is vertically spaced from the semiconductor layer by the combined thickness of the interlevel dielectric layer and the surface dielectric layer.

31. 30. The method of claim 28, wherein the drain side wing has a width from about 0 nm to about 500 nm.

32. 30. The method of claim 28, wherein the buried portion of the field plate has a width from about 500 nm to about 900 nm.

33. electrically connecting the field plate to the source contact outside an active area of ​​the transistor element, wherein the electrical connection between the field plate and the source contact does not cross over the gate.

30. The method of claim 28, further comprising:

34. 30. The method of claim 28, wherein the buried portion of the field plate is vertically spaced from the semiconductor layer by a thickness of the interlevel dielectric layer.

35. 35. The method of claim 34, wherein the buried portion of the field plate is vertically spaced from the semiconductor layer by a distance of about 60 nm to about 300 nm.

36. 36. The method of claim 35, wherein the buried portion of the field plate is vertically spaced from the semiconductor layer by a distance of about 100 nm to about 200 nm.

37. 37. The method of claim 36, wherein the buried portion of the field plate is vertically spaced from the semiconductor layer by a distance of about 150 nm.

38. 24. The method of claim 23, wherein the field plate is laterally spaced from the gate by a thickness of the interlevel dielectric layer.

39. 24. The method of claim 23, wherein the field plate is laterally spaced from the gate by a thickness of about 200 nm to about 700 nm.

40. 24. The method of claim 23, wherein the field plate is laterally spaced from the gate by a thickness of about 200 nm to about 400 nm.

41. 24. The method of claim 23, wherein the field plate has a total width of about 600 nm to 1500 nm.

42. The method of claim 23 , wherein the opening has chamfered or rounded edges.

43. A semiconductor layer; a surface dielectric layer on the semiconductor layer; at least a portion of a gate on the surface dielectric layer, the surface dielectric layer including an opening therein that is laterally spaced from the gate; an interlevel dielectric layer on the surface dielectric layer having a recess above the opening; at least a portion of a field plate within the recess; A transistor element comprising:

44. 44. The transistor device of claim 43, wherein the field plate includes a non-recessed portion that extends above the semiconductor layer, the portion of the field plate within the recess being vertically spaced from the semiconductor layer a distance less than the non-recessed portion is vertically spaced from the semiconductor layer.

45. 44. The transistor device of claim 43, wherein the interlevel dielectric layer extends into the opening in the surface dielectric layer.

46. 45. The transistor element of claim 44, further comprising a source contact and a drain contact on the semiconductor layer, the gate being between the source contact and the drain contact, and the non-recessed portion including a drain side wing extending over the semiconductor layer towards the drain contact.

47. 47. The transistor element of claim 46, further comprising a source side wing extending over the semiconductor layer towards the source contact.

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