Imaging apparatus

Abstract

To provide an imaging apparatus with a new construction.SOLUTION: An imaging apparatus includes an imaging region to which a plurality of pixels are provided. In the plurality of pixels provided in the imaging region, a first pixel and a second pixel are contained. The imaging apparatus includes a function for selecting first or second regions. The first region contains as many pixels as that in the second region. The first region contains at least first and second pixel, and the second region contains at least the second pixel. The pixel provided to the first or second region includes a function for outputting an imaging signal acquired. The imaging apparatus reads out the imaging signal to be output by the pixel provided in the first region at the seme time, and calculates them to generate first image data. The imaging apparatus reads the imaging signal to be output by the pixel provided in the second region at the same time, and calculates them to generate second image data. A first imaging image can be generated by using the first and second image data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device or an imaging system including an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the present invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In particular, one embodiment of the present invention relates to a semiconductor device, an imaging device, a light receiving device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to an element, a circuit, a device, or the like that can function by utilizing semiconductor characteristics. As one example, a semiconductor element such as a transistor, a diode, a light receiving element, or a light emitting element is a semiconductor device. As another example, a circuit having a semiconductor element is a semiconductor device. As yet another example, a device including a circuit having a semiconductor element is a semiconductor device. [Background technology]

[0004] In recent years, the development of image recognition using artificial intelligence (AI) has progressed. The recognition rate of what is in an image as a subject continues to improve. However, although AI can handle content it has already learned, it has difficulty recognizing or explaining the components in an image from an image it has not learned before.

[0005] For example, in the production process, visual inspection is performed to check for foreign objects mixed in during production, manufacturing defects, etc. Recently, development has been underway to perform visual inspection efficiently by incorporating image inspection into visual inspection. For example, various detection algorithms have been proposed for machine vision (image processing systems that use computer systems). Among them, an algorithm inspired by the human visual mechanism has been proposed (Patent Document 1). This algorithm is inspired by the peripheral vision and fixational eye movement of the human visual mechanism, and is capable of detecting abnormalities that exist within a regular pattern.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] When digitally processing an algorithm for extracting features from an image using a processor or a GPU (Graphics Processing Unit) without using teacher data, there is a problem that the power consumption increases in proportion to the amount of computation. That is, the size of the target image has a problem of being proportional to the amount of computation and power consumption. In addition, when using the algorithm, there is a problem that the processing time becomes longer in proportion to the amount of computation. Further, the algorithm has a problem that it requires a data area larger than the image size in order to handle data larger than the image size in intermediate processing.

[0008] In view of the above problems, one aspect of the present invention is to provide an imaging device with a novel configuration as one of the problems. One aspect of the present invention is to provide an imaging device capable of handling data larger than the imaging area as one of the problems. One aspect of the present invention is to provide an imaging device that suppresses an increase in the processing time of operations as one of the problems. One aspect of the present invention is to provide an imaging device that suppresses an increase in power consumption as one of the problems.

[0009] One aspect of the present invention is to provide an imaging system with a novel configuration as one of the problems. One aspect of the present invention is to provide an imaging system capable of handling data larger than the imaging area as one of the problems. One aspect of the present invention is to provide an imaging system that suppresses an increase in the processing time of operations as one of the problems. One aspect of the present invention is to provide an imaging system that suppresses an increase in power consumption as one of the problems.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention is an imaging device having a first region and a second region in an imaging region, wherein the first region and the second region have the same number of a plurality of pixels, the first region includes a first pixel and a second pixel in the plurality of pixels, the second region includes a second pixel in the plurality of pixels, first image data is generated according to an imaging signal output by the plurality of pixels included in the first region, second image data is generated according to an imaging signal output by the plurality of pixels included in the second region, and a first image is generated according to the first image data and the second image data.

[0012] In the above configuration, it is preferable that the first image data is generated by averaging the imaging signals output by the plurality of pixels included in the first region, and the second image data is generated by averaging the imaging signals output by the plurality of pixels included in the second region.

[0013] In each of the above configurations, each of the plurality of pixels included in the first region has a function of converting the imaging signals output by the plurality of pixels into a first imaging signal by being given a weight coefficient, each of the plurality of pixels included in the second region has a function of converting the imaging signal output by the pixel into a second imaging signal by being given a weight coefficient, the first image data is generated by adding the first imaging signals output from each of the plurality of pixels included in the first region, and the second image data is generated by adding the second imaging signals output from each of the plurality of pixels included in the second region.

[0014] In each of the above configurations, it is preferable that the first region and the second region are composed of pixels selected in units of integer rows and integer columns.

[0015] In each of the above configurations, it further has a first circuit. The first circuit has a function of holding a potential, and it is preferable that the first circuit has a function as a substitute for a pixel in the first region or the first region.

[0016] In each of the above configurations, it is preferable that the transistor included in the pixel has a metal oxide in the semiconductor layer included in the transistor.

[0017] Another aspect of the present invention is an imaging system having an imaging region provided with a plurality of pixels. The imaging region includes a plurality of pixels, a first pixel, a second pixel, and a third pixel. The steps include: a step in which the plurality of pixels acquire an imaging signal; a step in which a first region having the first pixel to the third pixel is set in the imaging region; a step in which first phase image data is generated according to the imaging signals acquired by the first pixel and the second pixel included in the first region; a step in which second phase image data is generated according to the imaging signals acquired by the second pixel and the third pixel included in the first region; and a step in which first image data is generated by calculating the first phase image data and the second phase image data.

[0018] In each of the above configurations, it is preferable that the first image data is an image in which features are extracted from the imaging signal.

Advantages of the Invention

[0019] In view of the above problems, one aspect of the present invention can provide an imaging device with a novel configuration. One aspect of the present invention can provide an imaging device capable of handling data larger than the imaging region. One aspect of the present invention can provide an imaging device that suppresses an increase in the processing time of arithmetic operations. One aspect of the present invention can provide an imaging device that suppresses an increase in power consumption.

[0020] One aspect of the present invention can provide an imaging system with a novel configuration. One aspect of the present invention can provide an imaging system capable of handling data larger than the imaging region. One aspect of the present invention can provide an imaging system that suppresses an increase in the processing time of operations. One aspect of the present invention can provide an imaging system that suppresses an increase in power consumption.

[0021] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are effects not mentioned in this item as described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and / or other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.

Brief Description of the Drawings

[0022]

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DETAILED DESCRIPTION OF THE INVENTION

[0023] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having the same function are commonly used with the same reference numerals among different drawings, and the repeated description thereof will be omitted.

[0024] In addition, the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. in order to facilitate the understanding of the invention. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask or the like may be unintentionally reduced in size due to a process such as etching, but this may not be reflected in the drawing for the sake of easy understanding.

[0025] In addition, in a top view (also referred to as a "plan view") or a perspective view, etc., for the sake of easy understanding of the drawing, the description of some components may be omitted.

[0026] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0027] In addition, in this specification and the like, the "resistance" may be determined by the length of the wiring. Or, the resistance may also include cases where it is formed by connecting via a contact with a conductive layer having a lower efficiency different from the conductive layer used for the wiring. Or, the resistance value may be determined by doping an impurity into a semiconductor layer.

[0028] In addition, in this specification and the like, the "terminal" in an electric circuit refers to a part where current input or output, voltage input or output, or signal reception or transmission is performed. Therefore, a part of a wiring or an electrode may function as a terminal.

[0029] Note that in this specification and the like, the terms "above", "upper", "below", or "lower" do not limit the positional relationship of components to be directly above or below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be directly formed on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded. Also, in the expression "conductive layer D above conductive layer C", it is not necessary for conductive layer D to be directly formed on conductive layer C, and those including other components between conductive layer C and conductive layer D are not excluded. Also, "above" or "below" does not exclude cases where they are arranged obliquely.

[0030] In addition, since the functions of the source and drain are interchangeable depending on operating conditions such as when transistors with different polarities are employed or when the direction of current changes in circuit operation, it is difficult to limit which is the source or the drain. Therefore, in this specification, the terms source and drain can be used interchangeably.

[0031] In addition, in this specification and the like, "electrically connected" includes cases of direct connection and cases of being connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only wiring extends. Also, even when expressed as "direct connection", cases where wiring is formed via a contact in different conductive layers are included. Therefore, there are cases where the wiring includes one or more same elements in different conductive layers and cases where different elements are included.

[0032] Also, in this specification and the like, "parallel" means, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" and "orthogonal" mean, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0033] In addition, in this specification and the like, when referring to count values and measured values as "identical", "the same", "equal", or "uniform", etc., unless otherwise specified, they shall include an error of plus or minus 20%.

[0034] Also, voltage often indicates the potential difference between a certain potential and a reference potential (such as ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and the like, unless otherwise explicitly stated, voltage and potential can be used interchangeably.

[0035] In addition, even when denoted as "semiconductor", for example, when the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to replace "semiconductor" with "insulator" and use it. In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "insulator" described in this specification may be able to be read as each other in some cases.

[0036] Also, even when denoted as "semiconductor", for example, when the conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to replace "semiconductor" with "conductor" and use it. In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "conductor" described in this specification may be able to be read as each other in some cases.

[0037] Note that ordinal numbers such as "first" and "second" in this specification and the like are attached to avoid confusion of components, and do not indicate any order or rank such as the process order or the stacking order. Also, even for terms without ordinal numbers in this specification and the like, ordinal numbers may be attached in the claims to avoid confusion of components. Also, even for terms with ordinal numbers in this specification and the like, different ordinal numbers may be attached in the claims. Also, even for terms with ordinal numbers in this specification and the like, ordinal numbers may be omitted in the claims and the like.

[0038] Note that in this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as the "conductive state"). Also, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as the "non-conductive state").

[0039] Also, in this specification and the like, the "on current" may refer to the current flowing between the source and drain when the transistor is in the on state. Also, the "off current" may refer to the current flowing between the source and drain when the transistor is in the off state.

[0040] Also, in this specification and the like, the high power supply voltage VDD (hereinafter, also simply referred to as "VDD", "H voltage", or "H") indicates a power supply voltage with a voltage higher than the low power supply voltage VSS (hereinafter, also simply referred to as "VSS", "L voltage", or "L"). Also, VSS indicates a power supply voltage with a voltage lower than VDD. Also, the ground voltage (hereinafter, also simply referred to as "GND" or "GND voltage") can be used as VDD or VSS. For example, when VDD is the ground voltage, VSS is a voltage lower than the ground voltage, and when VSS is the ground voltage, VDD is a voltage higher than the ground voltage.

[0041] In addition, in this specification and the like, the gate refers to a part or all of the gate electrode and the gate wiring. The gate wiring refers to the wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0042] In addition, in this specification and the like, the source refers to a part or all of the source region, the source electrode, and the source wiring. The source region refers to the region in the semiconductor layer where the resistivity is below a certain value. The source electrode refers to the conductive layer connected to the source region. The source wiring refers to the wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0043] In addition, in this specification and the like, the drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to the region in the semiconductor layer where the resistivity is below a certain value. The drain electrode refers to the conductive layer connected to the drain region. The drain wiring refers to the wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0044] (Embodiment 1) In this embodiment, an imaging device according to an aspect of the present invention will be described. The imaging device has an imaging region provided with a plurality of pixels. The plurality of pixels included in the imaging region include a first pixel and a second pixel. As an example, the imaging device can select a first region and a second region. The first region or the second region is composed of pixels specified in units of an integer number of rows in the row direction and an integer number of columns in the column direction. Therefore, a group of pixels specified as the first region can be treated as one unit. That is, it means that the imaging region is divided by the first region. Also, the second region preferably includes the same number of pixels as the first region. Note that the first region preferably includes at least the first pixel and the second pixel, and the second region preferably includes at least the second pixel. The pixels included in the first region or the second region output imaging signals acquired by the respective pixels.

[0045] The imaging device can generate first image data by simultaneously reading and calculating the imaging signals output by the pixels included in the first region. Further, the imaging device can generate second image data by simultaneously reading and calculating the imaging signals output by the pixels included in the second region. Note that the calculation preferably includes an averaging process or the like.

[0046] Note that the imaging signals output by the pixels included in the first region may be converted into first imaging signals by being given weight coefficients. Also, the imaging signals output by the pixels included in the second region may be converted into second imaging signals by being given weight coefficients. Therefore, the imaging signals output by the pixels included in the first region can obtain the same value as when the imaging signals output by the pixels included in the first region are averaged by adding the first imaging signals. Also, the imaging signals output by the pixels included in the second region can obtain the same value as when the imaging signals output by the pixels included in the second region are averaged by adding the second imaging signals.

[0047] Therefore, the imaging device can generate a first image using the first image data and the second image data. The first image is an image obtained by extracting non - continuity features from the image captured by the imaging device.

[0048] When the second region is set, the second region may be outside the imaging region. In other words, the number of pixels that must be included in the second region may be insufficient within the imaging range. In the case described above, the imaging device preferably has a first circuit that functions as a substitute for the insufficient pixels as the second region. The first circuit has a function as a storage device, and it is preferable that the storage device can hold a voltage.

[0049] The pixel of the imaging device and the transistor of the storage device preferably have a metal oxide in the semiconductor layer of the transistor, and the transistor further preferably has a back gate.

[0050] Next, an imaging device according to an aspect of the present invention will be described with reference to the drawings. FIG. 1 is a diagram for explaining an imaging device 100. The imaging device 100 has an imaging region 300. The imaging region 300 has a plurality of pixels. As an example, the imaging region 300 shown in FIG. 1 has pixels P(1,1) to P(4,4). Note that the number of pixels in the imaging region 300 is not limited. For example, the imaging region 300 can have pixels P(1,1) to P(m,n). Note that m and n are positive integers.

[0051] The imaging device 100 can divide the imaging region 300 into a plurality of regions with the first region as a unit. As an example, when the first region is specified in units of two pixels in the row direction and two pixels in the column direction, the first region corresponds to the pixels P(1,1) to P(2,2) included in the region a11, and the second region corresponds to the pixels P(2,1) to P(3,2) included in the region a21. Note that the first region preferably includes the same number of pixels as the second region. Also, each pixel P included in the first region or the second region outputs the imaging signal acquired by each pixel P.

[0052] Here, the positional relationship between the first region and the second region in the imaging region 300 will be described. As shown in FIG. 1, the pixels P(2,1) and P(2,2) included in the first region are included in the second region. However, the pixels P(1,1) and P(1,2) included in the first region are not included in the second region. In other words, the second region is a region specified by moving the first region by one pixel in the x-axis direction.

[0053] Similarly, the region a31 is a region specified by moving the second region by one pixel in the x-axis direction, and the region a13 is a region specified by moving the first region by two pixels in the y-axis direction. Therefore, the imaging region 300 can be represented by compressing information into the regions a11 to a33.

[0054] Although not shown in FIG. 1, the region a41 is a region specified by moving the region a31 by one pixel in the x-axis direction. However, the region a41 must be composed of the pixels P(4,1) to P(5,2). However, in the example shown in FIG. 1, the imaging region 300 does not have the pixels P(5,1) and (5,2). Therefore, when specifying the region a41, it is necessary to prepare dummy pixels instead of the pixels P(5,1) and (5,2).

[0055] That is, the imaging device 100 can output image data corresponding to regions a11 to a33 by calculating the image signals output by each pixel P of pixels P(1,1) to P(4,4) for each region. Note that the image data corresponding to regions a11 to a33 is output as image data d11 to d33. The calculation includes addition, subtraction, multiplication, division, or averaging processing combining them.

[0056] Figures 2A to 2D are diagrams for explaining the imaging region 300. As an example, the imaging region 300 has pixels P(1,1) to P(8,9). In Figures 2A to 2D, the first region is composed of four pixels (specified in units of two pixels in the row direction and two pixels in the column direction, and may be called the grid size). Therefore, four different phase image data IM1 to IM4 having different phases with pixels P(1,1) to P(2,2) included in the first region as bases can be generated. Note that the phase image data IM1 to IM4 are generated by calculating using the image data output by the same number of pixels each region has.

[0057] The phase image data IM1 to IM4 will be described in detail. The phase image data IM1 shown in Figure 2A has regions a111 to a144 and image data d111 to d144. Also, the phase image data IM2 shown in Figure 2B has regions a211 to a244 and image data d211 to d244. Also, the phase image data IM3 shown in Figure 2C has regions a311 to a344 and image data d311 to d344. Also, the phase image data IM4 shown in Figure 2D has regions a411 to a444 and image data d411 to d444.

[0058] As an example, the phase image data IM2 shown in FIG. 2B is set with the pixels obtained by moving the region specified by the phase image data IM1 by one pixel in the x-axis direction as the base points. Also, the phase image data IM3 shown in FIG. 2C is set with the pixels obtained by moving the region specified by the phase image data IM1 by one pixel in the y-axis direction as the base points. Further, the phase image data IM3 shown in FIG. 2D is set with the pixels obtained by moving the region specified by the phase image data IM1 by one pixel in each of the x-axis direction and the y-axis direction as the base points.

[0059] In the example of the phase image data IM2 shown in FIG. 2B, instead of the pixels where the imaging region 300 does not exist in the regions a241, a242, a243, and a244, pixels DD(9,1) to DD(9,8) are added as dummy pixels.

[0060] Also, in the example of the phase image data IM4 shown in FIG. 2D, instead of the pixels where the imaging region 300 does not exist in the regions a441, a442, a443, and a444, pixels DD(9,2) to DD(9,9) are added as dummy pixels.

[0061] As described above, the process of making the number of data during calculation the same by adding dummy pixels that do not exist in the actual pixel region is sometimes called padding processing.

[0062] Figures 3A to 3C are diagrams for explaining the imaging region 300. Similar to FIG. 2, the imaging region 300 has pixels P(1,1) to P(8,9). However, in FIGS. 3A to 3C, the first region is composed of 16 pixels (lattice size: 4×4). Therefore, 16 different phase image data IM1 to IM16 having different phases with respect to pixels P(1,1) to P(4,4) included in the first region can be generated. Note that the phase image data IM1 to IM16 are generated by performing calculations using the image data output by the same number of pixels included in each region. In FIG. 3, the phase image data IM1, the phase image data IM2, and the phase image data IM16 are described, and the description of the others is omitted.

[0063] The phase image data IM1, the phase image data IM2, and the phase image data IM16 will be described in detail. The phase image data IM1 shown in FIG. 3A has regions a0111 to a0122 and has image data d0111 to d0122. Also, the phase image data IM2 shown in FIG. 3B has regions a0211 to a0222 and has image data d0211 to d0222. Further, the phase image data IM16 shown in FIG. 3C has regions a1611 to a1622 and has image data d1611 to d1622.

[0064] As an example, the phase image data IM2 shown in FIG. 3B is set with pixels obtained by moving the region with the phase image data IM1 as a reference by one pixel in the x-axis direction as a reference. Also, the phase image data IM16 shown in FIG. 3C is set with pixels obtained by moving the region with the phase image data IM1 as a reference by three pixels in each of the x-axis direction and the y-axis direction as a reference.

[0065] Note that in the example of the phase image data IM2 shown in FIG. 3B, instead of pixels where the imaging region 300 does not exist in the regions a0221 and a0222, pixels DD(9,1) to DD(9,8) are added as dummy pixels.

[0066] Also, in the example of the phase image data IM16 shown in FIG. 3C, instead of the pixels where the imaging region 300 does not exist in the regions a1621, a1612, and a1622, dummy pixels DD(9,4) to DD(11,9) in the x-axis direction and dummy pixels DD(4,10) to DD(11,11) in the y-axis direction are specified.

[0067] Here, the example of the phase image data IM16 will be described in detail. The region a1611 is composed of pixels P(4,4) to P(7,7). The region a1621 is composed of pixels P(8,4) to P(8,7) and dummy pixels DD(9,4) to DD(11,7). The region a1612 is composed of pixels P(4,8) to P(7,9) and dummy pixels DD(4,10) to DD(7,11). The region a1622 is composed of pixels P(8,8) and P(8,9), dummy pixels DD(9,8) to DD(11,9), and dummy pixels DD(8,10) to DD(11,11). Note that the dummy signal given to the dummy pixels can preferably be changed as needed.

[0068] FIG. 4 is a diagram for explaining the imaging device 100. The imaging device 100 includes an imaging region 300, a circuit 301, a circuit 302, a circuit 303, a circuit 304, and a circuit 305. The imaging region 300 has a plurality of pixels P.

[0069] The circuit 301 functions as a read selection driver. As an example, the circuit 301 is electrically connected to a plurality of pixels P via a wiring 122. The pixel P is electrically connected to the circuit 302 via a wiring 113. The circuit 302 is electrically connected to the circuit 303. The circuit 303 is electrically connected to the circuit 304. The circuit 304 is electrically connected to the circuit 305.

[0070] Circuit 302 functions as a switch module. Circuit 303 has the function of converting an imaging signal output by a pixel into a potential. Circuit 304 functions as a correlated double sampling circuit (CDS circuit). Circuit 305 functions as a storage device.

[0071] Circuit 301 can select a pixel that reads out an imaging signal from pixel P by applying a selection signal to wiring 122. Further, circuit 301 can apply selection signals to a plurality of wirings 122 simultaneously. By applying selection signals to the plurality of wirings 122 simultaneously, an imaging signal can be read out simultaneously from the pixel group selected by the above-described lattice size.

[0072] Circuit 302 is a switch module that switches a readout path in order to treat the pixel group selected by the lattice size as one region. Therefore, circuit 302 can calculate the imaging signal output by the pixel group and generate image data. The calculation is preferably integration. When the region selected by the lattice size includes dummy pixels, the padding circuit included in circuit 302 can supply dummy data in place of the insufficient pixels.

[0073] Circuit 303 converts the image data output as a current into a potential. The image data converted into the potential corresponds to the result of integrating the imaging signals output from a plurality of pixels.

[0074] Circuit 304 is a CDS circuit for removing variations and offset components of imaging device 100 in order to generate phase image data. More specifically, circuit 304 generates image data in which variations or offset components caused by parasitic capacitances or resistance components of each wiring, pixel, circuit 302, or circuit 303 are removed. The output of circuit 304 is stored in circuit 305. Note that circuit 305 is preferably an analog memory that can hold potential values. The analog memory will be described in detail with reference to FIG. 12.

[0075] FIG. 5A is a diagram for explaining the imaging device 100. For the sake of simplicity of explanation, the same reference numerals are commonly used for parts having the same functions, and repeated explanations thereof are omitted.

[0076] FIG. 5A is a diagram for explaining in detail the imaging region 300 and the circuit 302 included in the imaging device 100. The imaging region 300 includes a plurality of pixels P, wirings 113(1) to 113(k), and wirings 122(i) to 122(i + 1). As an example, the imaging region 300 includes pixels P(1,i) to P(k,i + 1). Note that i and k are positive integers.

[0077] The circuit 302 includes a plurality of circuits 320, circuits 330a, 330b, and a circuit 350. The circuit 320 includes a circuit 321, switches 322, and 323. Note that it is preferable to provide k - 1 circuits 320. The circuit 330a includes a circuit 331 and a circuit 332. The circuit 330b includes a circuit 331, a circuit 332, and a switch 333.

[0078] The circuit 350 is a control circuit. The circuit 350 controls the switches 322 and 323 via the circuit 321 that functions as a decoder circuit, and controls the switch 333 via the circuit 331 that functions as a decoder circuit. Note that the circuits 330a and 330b function as padding circuits and can perform padding processing.

[0079] Subsequently, the electrical connection of the imaging device 100 described with reference to FIG. 5A will be described. As an example, a case where the imaging region 300 includes at least a region a111 and a region a121, and each of the regions a111 and a121 is composed of four pixels will be described.

[0080] Region a111 is composed of pixel P(1,i), pixel P(2,i), pixel P(1,i + 1), and pixel P(2,i + 1). Wiring 122(i) is electrically connected to pixel P(1,i) and pixel P(2,i). Wiring 122(i + 1) is electrically connected to pixel P(1,i + 1) and pixel P(2,i + 1). Wiring 113(1) is electrically connected to pixel P(1,i) and pixel P(1,i + 1). Wiring 113(2) is electrically connected to pixel P(2,i) and pixel P(2,i + 1).

[0081] Region a121 is composed of pixel P(3,i), pixel P(4,i), pixel P(3,i + 1), and pixel P(4,i + 1). Wiring 122(i) is electrically connected to pixel P(3,i) and pixel P(4,i). Wiring 122(i + 1) is electrically connected to pixel P(3,i + 1) and pixel P(4,i + 1). Wiring 113(3) is electrically connected to pixel P(3,i) and pixel P(3,i + 1). Wiring 113(4) is electrically connected to pixel P(4,i) and pixel P(4,i + 1).

[0082] Also, wiring 122(i) is electrically connected to pixel P(k,i). Wiring 122(i + 1) is electrically connected to pixel P(k,i + 1). Wiring 113(k) is electrically connected to pixel P(k,i) and pixel P(k,i + 1).

[0083] Wiring 113(1) is electrically connected to circuit 332 of circuit 330a, terminal 1 of switch 322 of circuit 320(1), and terminal 1 of switch 323 of circuit 320(1). Terminal 2 of switch 322 of circuit 320(1) is electrically connected to wiring 113(2), terminal 1 of switch 322 of circuit 320(2), and terminal 1 of switch 323 of circuit 320(2). Terminal 2 of switch 323 of circuit 320(1) is electrically connected to circuit 303(1).

[0084] Terminal 2 of switch 323 included in circuit 320(2) is electrically connected to circuit 303(2). Terminal 2 of switch 322 included in circuit 320(2) is electrically connected to wiring 113(3), and terminals 1 of switch 322 and switch 323 included in circuit 320(3).

[0085] Terminal 2 of switch 323 included in circuit 320(3) is electrically connected to circuit 303(3). Terminal 2 of switch 322 included in circuit 320(3) is electrically connected to wiring 113(4), and terminals 1 of switch 322 and switch 323 included in circuit 320(4).

[0086] Terminal 2 of switch 323 included in circuit 320(4) is electrically connected to circuit 303(4). Terminal 2 of switch 322 included in circuit 320(4) is electrically connected to wiring 113(5) (not shown), and terminals 1 of switch 322 and switch 323 included in circuit 320(5) (not shown).

[0087] Next, circuit 330b will be described. Circuit 330b is electrically connected to wiring 113(k). Wiring 113(k) is electrically connected to terminal 2 of switch 322 included in circuit 320(k - 1) (not shown), and terminals 1 of circuit 332 and switch 333 included in circuit 330b. Terminal 2 of switch 333 is electrically connected to circuit 303(k).

[0088] Next, circuit 350 will be described. Circuit 350 is electrically connected to circuit 332 via circuit 331 included in circuit 330a. Circuit 350 is electrically connected to circuit 332 and terminal 3 of switch 333 included in circuit 330b via circuit 331 included in circuit 330b. Also, circuit 350 is electrically connected to terminal 3 of switch 322 and terminal 3 of switch 323 included in circuit 320(1) via circuit 321 included in circuit 320(1). Also, circuit 350 is electrically connected to terminal 3 of switch 322 and terminal 3 of switch 323 included in circuit 320(2) via circuit 321 included in circuit 320(2). Also, circuit 350 is electrically connected to terminal 3 of switch 322 and terminal 3 of switch 323 included in circuit 320(3) via circuit 321 included in circuit 320(3). Also, circuit 350 is electrically connected to terminal 3 of switch 322 and terminal 3 of switch 323 included in circuit 320(4) via circuit 321 included in circuit 320(4).

[0089] As an example, wiring 113(1) can be electrically connected to wiring 113(2) by turning on switch 322 included in circuit 320(1). Further, when switch 323 included in circuit 320(1) is turned on and switches 322 and 323 included in circuit 320(2) are turned off, the respective imaging signals output from pixel P(1,i), pixel P(2,i), pixel P(1,i + 1), and pixel P(2,i + 1) are supplied to circuit 303(1). Therefore, the image data output from region a111 is generated by adding the imaging signals output from pixel P(1,i), pixel P(2,i), pixel P(1,i + 1), and pixel P(2,i + 1).

[0090] Also, as an example, when a region including dummy pixels includes and is provided with pixels connected to wiring 113(1), circuit 330a functions as a padding circuit. Circuit 330a operates in place of the dummy pixels. The image data of the region including the dummy data is output to circuit 303(1). Similarly, when a region including dummy pixels includes and is provided with pixels connected to wiring 113(k), circuit 330b functions as a padding circuit. Circuit 330b operates in place of the dummy pixels. The image data of the region including the dummy data is output to circuit 303(k) via switch 333.

[0091] FIG. 5B is a diagram for explaining circuit 332 that functions as a padding circuit. Circuit 332 has register 340 and a plurality of switches. Register 340 has memories 341a to 341c and has switches 332a to 332c corresponding to the respective memories.

[0092] Memory 341a is electrically connected to wiring 113 via switch 332a. Memory 341b is electrically connected to wiring 113 via switch 332b. Memory 341c is electrically connected to wiring 113 via switch 332c. Note that switches 332a to 332c are independently controlled to be in an on state or an off state by circuit 331. Also, the operation of circuit 331 is preferably controlled by an instruction from circuit 350.

[0093] Note that memories 341a to 341c are preferably analog memories. As the dummy data, any potential stored in the analog memory can be used. Therefore, the memories included in register 340 correspond to dummy pixels. Thus, the number of memories included in register 340 is not limited. As an example, it is preferable that a potential corresponding to the intermediate value of the imaging signal is stored as dummy data in each memory. It is preferable that dummy data is supplied from the memories corresponding to the number of pixels added as dummy pixels.

[0094] Note that transistors can be used for switch 322, switch 323, switch 333, switches 332a to 332c. Also, transistors are used for the selection switches of the analog memory. Further, transistors are used for the plurality of switches included in pixel P.

[0095] The semiconductor layer of the transistor described above preferably has an oxide semiconductor. Note that a transistor including an oxide semiconductor (Oxide Semiconductor: OS), which is a kind of metal oxide, in the semiconductor layer where the channel of the transistor is formed is called an “OS transistor” or “OS-FET”. It is known that the OS transistor has small fluctuations in electrical characteristics due to temperature changes. Further, since the OS transistor has a large energy gap in the semiconductor layer, it can exhibit an extremely low off-current characteristic of several yA / μm (current value per 1-μm channel width). Therefore, the OS transistor is preferably applied to a memory device. Note that the OS transistor will be described in detail in Embodiment 3.

[0096] Also, the off-current of the OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200°C. Also, the on-current hardly decreases even in a high-temperature environment. Further, the OS transistor has a high breakdown voltage between the source and the drain. By using the OS transistor for the transistors constituting the semiconductor device, a semiconductor device with stable operation and good reliability can be realized even in a high-temperature environment.

[0097] Also, the OS transistor can be formed by using a sputtering method during a BEOL (Back end of line) process for forming wiring of the semiconductor device. Therefore, one imaging device 100 can be formed using transistors with different transistor characteristics. In other words, by using the OS transistor, an SOC (System on chip) can be easily formed.

[0098] FIG. 6 is a diagram for explaining the imaging device 100. In FIG. 6, the region a111, the circuit 302, and the circuit 303 included in the imaging device 100 will be described. For simplicity of explanation, the same reference numerals are commonly used for parts having the same functions, and the repeated description thereof will be omitted.

[0099] In FIG. 6, as an example, the explanation will be made using the pixels P(1, i) to P(2, i + 1) included in the region a111.

[0100] The pixels P(1, i) and P(1, i + 1) are electrically connected to the wiring 113(1). Further, the wiring 113(1) is electrically connected to the circuit 320(1) included in the circuit 302. The circuit 320(1) is electrically connected to the circuit 303(1) included in the circuit 303.

[0101] The pixels P(2, i) and P(2, i + 1) are electrically connected to the wiring 113(2). Further, the wiring 113(2) is electrically connected to the circuit 320(2) included in the circuit 302. The circuit 320(2) is electrically connected to the circuit 303(2) included in the circuit 303.

[0102] Note that the circuit 320(1) can be electrically connected to the circuit 320(2) under the control of the circuit 350. Although not shown, it can also be connected to the circuit 320(k). Further, different from FIG. 5A, the circuit 330a is electrically connected to each of the wirings 113. The circuit 330a connected to the wiring 113 is set when dummy pixels are provided in the y-axis direction of the imaging region 300. By providing the circuit 330a in each of the wirings 113, dummy data can be supplied when dummy pixels are provided.

[0103] Next, the circuit 303 will be described in detail. Here, as an example, the circuit 303(2) will be used for the explanation. The circuit 303(2) includes a capacitor 202, a transistor 203, a transistor 204, a transistor 205, a transistor 206, and a resistor 207.

[0104] One electrode of the capacitor 202 is electrically connected to one of the source or drain of the transistor 203. One of the source or drain of the transistor 203 is electrically connected to the gate of the transistor 204. One of the source or drain of the transistor 204 is electrically connected to one of the source or drain of the transistor 205. One of the source or drain of the transistor 205 is electrically connected to one of the source or drain of the transistor 206. One electrode of the resistor 207 is electrically connected to the other electrode of the capacitor 202.

[0105] The other electrode of the capacitor 202 is electrically connected to the wiring 113 via the circuit 320. The other of the source or drain of the transistor 203 is electrically connected to the wiring 218. The other of the source or drain of the transistor 204 is electrically connected to the wiring 219. The other of the source or drain of the transistor 205 is electrically connected to a reference power line such as a GND wiring. The other of the source or drain of the transistor 206 is electrically connected to the wiring 313. The other electrode of the resistor 207 is electrically connected to the wiring 217. The gate of the transistor 203 is electrically connected to the wiring 216. The gate of the transistor 205 is electrically connected to the wiring 215. The gate of the transistor 206 is electrically connected to the wiring 213.

[0106] The wiring 217, the wiring 218, and the wiring 219 can have the function as a power line. For example, the wiring 218 can have the function as a wiring for supplying a dedicated potential for reading. The wiring 217 and the wiring 219 can function as a high potential power line. The wiring 213, the wiring 215, and the wiring 216 can function as signal lines for controlling the conduction of each transistor. The wiring 313(2) is an output line and can be electrically connected to, for example, the circuit 304 shown in FIG. 4.

[0107] The transistor 203 can have a function of resetting the potential of the wiring 211 to the potential of the wiring 218. The transistors 204 and 205 can have a function as a source follower circuit. The transistor 206 can have a function of controlling reading. Note that the wiring 211 is a wiring that electrically connects one electrode of the capacitor 202, one of the source or drain of the transistor 203, and the gate of the transistor 204.

[0108] Note that the resistor 207 may be replaced with a capacitor. By using the capacitor, leakage current can be suppressed and current-voltage conversion with reduced power consumption can be performed. Also, when the capacitor is used, the capacitor 202 can be reduced from the components. Further, when the capacitor is used, it is preferable to use the pixel P shown in FIG. 7B or FIG. 7C described later.

[0109] FIGS. 7A to 7C are circuit diagrams for explaining the pixel P. The pixel P can have a photoelectric conversion device 101, a transistor 102, a transistor 103, a capacitor 104, a transistor 105, and a transistor 108, as shown in FIG. 7A.

[0110] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103. One of the source or drain of the transistor 103 is electrically connected to one electrode of the capacitor 104. One electrode of the capacitor 104 is electrically connected to the gate of the transistor 105. One of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 108. The other electrode of the capacitor 104 is electrically connected to the wiring 112.

[0111] The other electrode of the photoelectric conversion device 101 is electrically connected to the wiring 114. The gate of the transistor 102 is electrically connected to the wiring 116. The other of the source or drain of the transistor 103 is electrically connected to the wiring 115. The gate of the transistor 103 is electrically connected to the wiring 117. The other of the source or drain of the transistor 105 is electrically connected to the wiring 118. The other of the source or drain of the transistor 108 is electrically connected to the wiring 113. The gate of the transistor 108 is electrically connected to the wiring 122.

[0112] Here, the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, one electrode of the capacitor 104, and the gate of the transistor 105 have an electrical connection point (wiring) as the node N.

[0113] The wiring 114 and the wiring 115 can function as power supply lines. For example, the wiring 114 can function as a high-potential power supply line, and the wiring 115 can function as a low-potential power supply line. The wiring 116, the wiring 117, and the wiring 122 can function as signal lines for controlling the conduction of each transistor. The wiring 112 can function as a wiring for supplying a potential corresponding to the weighting coefficient to the pixel P. The wiring 113 can function as a wiring for electrically connecting the pixel P and the circuit 303.

[0114] Note that an amplification circuit or a gain adjustment circuit may be electrically connected to the wiring 113.

[0115] As the photoelectric conversion device 101, a photodiode can be used. When it is desired to enhance the light detection sensitivity in low illumination, it is preferable to use an avalanche photodiode.

[0116] Transistor 102 can have a function of controlling the potential of node N. Transistor 103 can have a function of initializing the potential of node N. Transistor 105 can have a function of controlling the magnitude of the current supplied to circuit 303 according to the potential of node N. Transistor 108 can have a function of selecting a pixel. Note that transistor 108 may be provided between wiring 118 and transistor 105.

[0117] As an example, a case where wiring 112 is electrically connected to all pixels P included in imaging region 300 will be described. The potential applied to wiring 112 can apply a potential corresponding to a weighting factor to node N via capacitor 104. When simultaneously processing imaging signals within a region divided in a grid pattern, which is one aspect of the present invention, weighting factors can be simultaneously applied to the target pixels.

[0118] In FIG. 7A, transistor 105 is preferably an n-channel type FET. When transistor 105 is an n-channel type FET, wiring 118 functions as a low potential power supply line. By wiring 118 functioning as a low potential power supply line, the potential between the gate and source of transistor 105 is determined by node N. Therefore, current flows from wiring 113 through transistor 105 in the direction of wiring 118 for pixel P. Note that transistor 102, transistor 103, or transistor 108 may be an n-channel type FET or a p-channel type FET.

[0119] Further, in FIG. 7B, transistor 105 is preferably a p-channel type FET. When transistor 105 is a p-channel type FET, wiring 118 functions as a high potential power supply line. By wiring 118 functioning as a high potential power supply line, the potential between the gate and source of transistor 105 is determined by node N. Therefore, in pixel P, current flows from wiring 118 through transistor 105 in the direction of wiring 113. Note that transistor 102, transistor 103, or transistor 108 may be an n-channel type FET or a p-channel type FET.

[0120] FIG. 7C is a circuit diagram for explaining a pixel P different from that in FIG. 7B. FIG. 7C is different from FIG. 7B in that it has transistors 102a, 103a, and 108a. Transistors 102a, 103a, and 108a each have a back gate.

[0121] As an example, when an avalanche photodiode is used for the photoelectric conversion device 101, a high potential may be applied, and it is preferable to use a transistor with a high breakdown voltage for the transistor connected to the photoelectric conversion device 101. As the transistor with a high breakdown voltage, for example, an OS transistor using a metal oxide in the channel formation region can be used. Specifically, it is preferable to apply an OS transistor to transistors 102 and 102a. Note that it is preferable to provide a back gate for the OS transistor. By providing a back gate for the OS transistor, the threshold voltage of the OS transistor can be controlled.

[0122] In addition, the OS transistor also has the characteristic of extremely low off-current. By using the OS transistor for transistors 102, 102a, 103, and 103a, the period during which charge can be held at node N can be made extremely long. Therefore, without complicating the circuit configuration and operation method, a global shutter method in which charge accumulation operations are performed simultaneously for all pixels can be applied. Also, while holding the imaging signal at node N, a plurality of operations using the imaging signal can be performed.

[0123] Also, the OS transistor can be used for transistors 108 and 108a. The pixel P can reduce variations and noise component generation caused by leakage current to wiring 113 by utilizing the characteristic of the extremely low off-current of the OS transistor.

[0124] On the other hand, it is desirable that transistor 105 has excellent amplification characteristics. Therefore, it is preferable to apply a transistor using silicon in the channel formation region (hereinafter, Si transistor) to transistor 105.

[0125] Note that the present invention is not limited to the above, and the OS transistor and the Si transistor may be combined and applied. Also, all the transistors may be OS transistors. Or, all the transistors may be Si transistors.

[0126] The potential of node N in pixel P is determined by capacitive coupling between the potential (imaging signal) obtained by adding the potential generated by photoelectric conversion by the photoelectric conversion device 101 to the reset potential supplied from wiring 115 and the potential corresponding to the weighting coefficient supplied from wiring 112. That is, a current flows through transistor 105 according to the potential obtained by giving an arbitrary weighting coefficient to the imaging signal.

[0127] FIG. 8 is a timing chart for explaining operations of acquiring data with imaging and data without imaging in region a111 and circuit 303. For convenience, the timings at which respective signals change are illustrated together, but actually, the timings inside the circuit can be compressed for operation. Also, it can be shifted in consideration of the delay of the timings inside the circuit.

[0128] First, the acquisition of data with imaging will be described. In the following description, a high potential is “H” and a low potential is “L”.

[0129] In period T1, the potential of wiring 117 is set to “H”, the potential of wiring 116 is set to “H”, and the node N of pixel P is set to the reset potential. Also, the potential of wiring 112 is set to “L” to initialize the weight coefficient.

[0130] In period T2, the potential of wiring 116 maintains “H”. Also, by setting the potential of wiring 117 to “L”, the potential X (imaging signal) of node N is updated by the current generated by the photoelectric conversion of photoelectric conversion device 101. Also, by setting wiring 216 to “H”, the potential Vr of wiring 218 is written to wiring 211. The operations in periods T1 and T2 correspond to the acquisition of data with imaging, and the data is represented as the potential Vr of wiring 211.

[0131] In period T3, a potential corresponding to the weight coefficient W is applied to wiring 112. The node N of each pixel P in imaging region 300 (the first and second rows) has the weight coefficient W added thereto via the capacitance of capacitor 104.

[0132] During period T4, the potentials of wirings 122_1 and 122_2 are set to "H" to select all pixels P in region a111. At this time, a current corresponding to the potential W+X flows through the transistors 105 of the pixels P in the first and second rows. Here, a potential is generated by the current flowing through the resistor 207 via the wiring 113. The potential Y generated by the current flowing through the resistor 207 is added to the potential Vr of the wiring 211 via the capacitor 202. Therefore, the potential of the wiring 211 becomes "Vr+Y". Here, considering Vr = 0, Y is the difference itself, which means that the data with imaging has been calculated. Also, by setting the wirings 213 and 215 to "H", the circuit 303 can output a signal potential corresponding to the data with imaging in the region a111 by means of a source follower operation.

[0133] Next, the acquisition of data without imaging will be described.

[0134] During period T5, the potential of the wiring 117 is set to "H", the potential of the wiring 116 is set to "H", and the node N of the pixel P is set to the reset potential. Also, by setting the potential of the wiring 112 to "L", the weight coefficient is initialized. Also, by setting the wiring 216 to "H", the potential Vr of the wiring 218 is written to the wiring 211.

[0135] During period T6, a potential corresponding to the weight coefficient W is applied to the wiring 112. The node N of each pixel P in the imaging region 300 (the first and second rows) has the weight coefficient W added via the capacitance of the capacitor 104.

[0136] During period T7, the potentials of wirings 122_1 and 122_2 are set to “H” to select all pixels P in region a111. At this time, a current corresponding to the potential W+X flows through the transistors 105 of the pixels P in the first and second rows. Here, a potential is generated by the current flowing through the resistor 207 via the wiring 113. The potential Y generated by the current flowing through the resistor 207 is added to the potential Vr of the wiring 211 via the capacitor 202. Therefore, the potential of the wiring 211 becomes “Vr+Y”. Here, considering Vr = 0, Y is the difference itself, which means that data without imaging has been calculated. Also, by setting the wirings 213 and 215 to “H”, the circuit 303 can output a signal potential corresponding to the data without imaging in the region a111 by means of a source follower operation. Note that the data without imaging includes circuit variations and unnecessary offset components.

[0137] The data with imaging and the data without imaging output from the circuit 303 by the above operation are input to the circuit 304. In the circuit 304, an operation of taking the difference between the data with imaging and the data without imaging is performed, and unnecessary offset components can be removed.

[0138] FIG. 9 is a diagram for explaining the signal output from the imaging region 300. In FIG. 9, for the sake of simplicity of explanation, as an example, it consists of four regions a (region a111, region a112, region a121, and region a122) divided in a grid pattern, and each region a has four pixels P (P11, P12, P21, P22).

[0139] The generation of the signal will be described taking region a111 as an example, but regions a121, a112, and a122 can also output signals with the same operation. Note that the case where region a111 includes four pixels will be described, but the number of pixels included in region a111 is not limited.

[0140] In region a111, for each pixel P, imaging signals P11, P12, P21, and P22 are held at node N. Here, the case where a weight coefficient W is given to each pixel P will be described. For a pixel given the weight coefficient W, the imaging signal output by the pixel can be corrected by the weight coefficient W. When region a111 has four pixels, it is preferable that the magnitude of the imaging signal output by the pixel given the weight coefficient W becomes one-fourth. The image data generated by simultaneously reading out the four pixels can obtain the same value as when the image data generated by reading out without giving the weight coefficient W to the pixels is averaged in post-processing.

[0141] More specifically, h11 (h11 = P11×W + P12×W + P21×W + P22×W), which is the calculation result of the imaging signals of P11, P12, P21, and P22, is output via wiring 113(1) and circuit 303(1). This gives the same calculation result as h11 = (P11 + P12 + P21 + P22)×W. That is, the same effect can be obtained as when the imaging signals output by each pixel in region a111 are added and output, and then a calculation using the weight coefficient W is performed on the output result. Therefore, the calculation process (hardware process or software process) can be simplified. Also, by simplifying the calculation process, the power consumption can be reduced.

[0142] In parallel, through the same process as above, h21, which is the calculation result of the imaging signal, is output from region a121 via wiring 113(2) and circuit 303(2), and the output of the first row of region a is completed.

[0143] Subsequently, in the second row of region a, through the same process as above, h12, which is the calculation result of the imaging signal, is output from region a112 via wiring 113(1) and circuit 303(1). Also in parallel, h22, which is the calculation result of the imaging signal, is output from region a122 via wiring 113(2) and circuit 303(2), and the output of the second row of region a is completed.

[0144] Repeat the above operations as necessary. Note that h11, h21, h12, and h22 described above correspond to data with imaging, and b11, b21, b12, and b22 correspond to data without imaging.

[0145] Figure 10 is a diagram for explaining circuit 304 and circuit 305. Circuit 304 functions as a CDS circuit. The CDS circuit may also be referred to as a differential detection circuit. Regarding the signal processing method, the output of circuit 303(1) will be taken as an example for explanation, but circuit 303(2) can also output signals with the same operation. Note that in Figure 10, the explanation of circuit 302 is omitted.

[0146] Circuit 304 (circuit 304a, circuit 304b) includes a selector circuit 361, a frame memory 362, and a differential circuit 363. First, the selector circuit 361 is supplied with image data (data with imaging or data without imaging) output from circuit 303(1) via wiring 313(1). The selector circuit 361 supplies data with imaging or data without imaging to the frame memory 362. The frame memory 362 stores data with imaging at even addresses (EV) and data without imaging at odd addresses (OD). Note that the frame memory 362 is preferably an analog memory. In the analog memory, data with imaging or data without imaging is stored as analog data (voltage values). By using an analog memory, the conversion cost and implementation area for quantizing data with imaging or data without imaging can be reduced.

[0147] Instead of the frame memory 362, a FIFO (First In First Out) circuit using an analog memory can be used. Note that in Figure 10, an example is shown in which data with imaging from h11 to h14 is stored and data without imaging from b11 to b14 is stored, but the number of data that can be stored is preferably set as necessary.

[0148] It is preferable to use a differential amplifier suitable for comparing analog data in the differential circuit 363. By using a differential amplifier in the differential circuit 363, the difference between the data without imaging stored at odd addresses and the data with imaging stored at even addresses is output as image data (e.g., d11 = h11 - b11) based on the data without imaging.

[0149] The image data output by the differential circuit 363 is stored in the circuit 305. FIG. 10 shows an example in which the image data d11 to the image data d44 are stored in the circuit 305. Therefore, the image data d11 to the image data d44 correspond to phase image data. Note that the number of data that can be stored in the circuit 305 is preferably set as needed. Further, the circuit 305 is preferably an analog memory. By using an analog memory, the circuit 305 can obtain the same effect as a frame memory.

[0150] Note that the frame memory 362 or the circuit 305 can use a digital memory. In order to use a digital memory, the data with imaging, the data without imaging, or the image data needs to be quantized. Note that by quantizing the data with imaging, the data without imaging, or the image data, the resistance to noise is increased. Also, by increasing the resistance to noise, it can be operated at high speed. Further, the power consumption due to the low voltage of the memory can be reduced.

[0151] Note that the differential circuit 363 can further have a comparison function. The comparison function can binarize the image data output by the differential circuit 363. The binarized image data can further emphasize and extract the features of the image data. Also, the binarized image data can reduce the memory capacity because the image data is compressed. Further, by reducing the memory capacity, the mounting area can be reduced and the power consumption can be reduced.

[0152] FIG. 11 is a diagram for explaining circuit 305. Circuit 305 has a plurality of memory cells 335. FIG. 11 has, as an example, memory cells 335(1,i) to memory cells 335(2,i + 1]. Note that all of the memory cells 335 have the same configuration and include transistor 161, transistor 162, and capacitor 163.

[0153] One of the source or drain of transistor 161 is electrically connected to the gate of transistor 162. The gate of transistor 162 is electrically connected to one electrode of capacitor 163. Here, the point where one of the source or drain of transistor 161, the gate of transistor 162, and one electrode of capacitor 163 are connected is defined as node NM.

[0154] The gate of transistor 161 is electrically connected to wiring WL. The other electrode of capacitor 163 is electrically connected to wiring RW. One of the source or drain of transistor 162 is electrically connected to a reference potential wiring such as a GND wiring.

[0155] In memory cell 335, the other of the source or drain of transistor 161 is electrically connected to wiring WD. The other of the source or drain of transistor 162 is electrically connected to wiring BL.

[0156] Wiring WL is preferably connected to a decoder or a shift register or the like.

[0157] A signal for reading out the image data written in memory cell 335 is applied to wiring RW. When applying image data to memory cell 335, a low potential is applied to wiring RW. When reading out image data from memory cell 335, a high potential is applied to wiring RW.

[0158] The wiring WD is electrically connected to the differential circuit 363. Therefore, image data is supplied to the wiring WD. Note that the image data is preferably supplied as analog data. Alternatively, the image data may be supplied as digital data obtained by binarizing the analog data.

[0159] The wiring BL can read out the image data stored in the memory cell 335. When the image data is analog data, the wiring BL is connected to the control unit (processor) via an analog-to-digital conversion circuit. Alternatively, when the image data is binarized digital data, the wiring BL is connected to the control unit via a register.

[0160] As described above, one aspect of the present invention can provide an imaging device having a novel configuration that can handle the outputs of a plurality of pixels included in a grid-like region as one imaging signal. Also, one aspect of the present invention can provide an imaging device that processes a part of the operation using a weighting coefficient. Also, one aspect of the present invention can provide an imaging device that can handle data larger than the imaging region by performing padding processing in the imaging device. One aspect of the present invention can provide an imaging device that suppresses an increase in the processing time of an operation using a weighting coefficient and padding processing. One aspect of the present invention can provide an imaging device that suppresses an increase in power consumption by reducing the amount of calculation by an operation using a weighting coefficient and padding processing.

[0161] This embodiment can be implemented by appropriately combining some of its parts.

[0162] (Embodiment 2) In this embodiment, an imaging system using the imaging device of Embodiment 1 will be described. An imaging system according to one aspect of the present invention can reduce the amount of calculation by using the imaging device, and can reduce the processing time and power consumption required for the calculation.

[0163] FIG. 12 is an image diagram for explaining an imaging system using an imaging device according to an aspect of the present invention. The imaging system can detect abnormal locations from imaging data acquired by the imaging device. Note that the imaging system includes at least the imaging device and a processor (not shown) that controls the imaging device.

[0164] First, the processing method of the imaging system will be described with reference to FIG. 12. The imaging system acquires imaging data to be evaluated using the imaging device. The imaging data preferably has regularity.

[0165] STEP1 is a step of setting a grid size KM to be applied to the imaging data. A plurality of such grid sizes can be set. As an example, when the imaging data has periodicity, it can be determined that the imaging data has regularity. Therefore, when the image data has periodicity, it is preferable to set the features that appear periodically as the interval of the grid size. Further, it is preferable to set a plurality of grid sizes centered on the interval set by the features that appear periodically. As an example, in FIG. 12, grid sizes KM1 to KMn are set.

[0166] STEP2 is a step of generating phase image data using the grid size KM. First, the method for generating the phase image data will be described. As an example, when the grid size KM1 is used, the grid size KM1 is such that the region a selected by the grid size KM1 includes four pixels. The phase image data is generated using a plurality of image data generated by calculating the imaging signals output by the pixels included in the region a. Therefore, four types of phase image data, namely phase image data IM11 to IM14, are generated for the phase image data generated using the grid size KM1.

[0167] As a different example, the grid size KM2 is such that the region a selected by the grid size KM2 contains 16 pixels. Therefore, 16 types of phase image data from phase image data IM21 to phase image data IM216 are generated using the grid size KM2. Thus, the larger the grid size, the greater the number of types of phase image data generated. Note that for the grid size KMn, the region a selected by the grid size KMn contains n pixels. Therefore, n types of phase image data are generated using the grid size KMn.

[0168] STEP3 is a step of calculating the phase image data generated using each grid size and generating a pop-up image. It is preferable to use multiplication or integration for the calculation.

[0169] As an example of preprocessing, the first image data is generated by integrating the phase image data IM11 to the phase image data IM14 generated using the grid size KM1. Subsequently, the second image data is generated by integrating the phase image data IM21 to the phase image data IM216 generated using the grid size KM2. Subsequently, the nth image data is generated by integrating the n types of phase image data generated using the grid size KMn.

[0170] Next, a pop-up image is generated by integrating the first image data to the nth image data. However, there is a problem that the first image data to the nth image data are each composed of different numbers of image data.

[0171] Therefore, when creating the first image data to the nth image data, the original imaging area is divided by the grid size used, and the first image data_b to the nth image data_b having the same number of image data are generated. Note that the first image data_b to the nth image data_b are image data in which regions having no regularity are extracted as features through the generation of phase image data.

[0172] Next, by integrating the first image data_b to the nth image data_b, a pop-up image is generated.

[0173] FIG. 13 is a flowchart for explaining an imaging system.

[0174] Step S00 is a step in which the imaging device acquires imaging data. It is preferable that the imaging device acquires imaging data in a global shutter method. The pixels of the imaging device have an OS transistor to suppress degradation of the imaging signal and to be able to hold the imaging signal.

[0175] Step S01 is a step in which the imaging system sets a flag rflag for managing a processing mode. The processing mode has a mode of reading and calculating imaging data and a mode of initializing and calculating imaging data. For the mode of reading and calculating imaging data, "0" is set in the flag rflag. For the mode of calculating the initialized imaging data, "1" is set in the flag rflag. Note that data with imaging is generated by the mode of reading and calculating imaging data, and data without imaging is generated by the mode of calculating imaging data output from the initialized pixels.

[0176] Step S02 is a step in which the imaging system makes various settings for processing imaging data. As an example, the lattice size to be applied is set. Also, the number of phases is set according to the lattice size. Also, the weighting factor is set according to the number of phases. Note that a plurality of types of lattice sizes can be set. Furthermore, the imaging system can have a step of extracting regularity from the imaging data.

[0177] Step S03 is a step of dividing an imaging area using a grid size. When dividing the imaging area, a reference point corresponding to the pixels included in the area set by the grid size is given. Also, to divide the imaging area using the grid size, the switch module is appropriately set by a control unit using a processor or the like. When the pixels included in the area do not actually exist (are insufficient), dummy pixels are set. The dummy pixels are virtually added to the area by being padded by a padding circuit. Note that it is preferable that the dummy data output by the dummy pixels can be appropriately set.

[0178] Step S04 is a step of reading out image data. Each image data is output as an integrated value of imaging signals output by a pixel group included in the area set by the grid size. By giving a weighting factor to the area, the integrated value can be averaged and output.

[0179] Step S05 is a step of generating data with imaging or data without imaging. In the case of a mode of reading out and calculating imaging data, data with imaging is generated. Also, in the case of a mode of calculating initialized imaging data, data without imaging is generated. Note that the data with imaging or the data without imaging is generated by reading out image data from the area set by the grid size.

[0180] Step S06 is a step of determining whether data with imaging or data without imaging corresponding to the number of phases set by the grid size has been acquired. If data with imaging or data without imaging corresponding to the set number of phases has been acquired, the process proceeds to step S07; otherwise, the process proceeds to step S03.

[0181] Step S07 is a step of determining whether data with imaging or data without imaging corresponding to the type of the set grid size has been acquired. If data with imaging or data without imaging corresponding to the set grid size has been acquired, the process proceeds to step S08; otherwise, the process proceeds to step S02.

[0182] Step S08 is a step of determining whether the flag rflag is "0". Immediately after the mode of reading and calculating the imaging data has ended, the flag rflag is "0". Therefore, if the flag rflag is "0", the process proceeds to step S02A; otherwise, the process proceeds to step S09.

[0183] Here, step S02A will be described. Step S02A is a step of initializing the imaging data acquired in S00 and shifting to the mode of calculation. The flag rflag is set to "1". Note that for the setting of the grid size, the setting of the number of phases, the setting of the weighting coefficient, etc., the information set in step S02 is used.

[0184] Step S09 is a step of generating phase image data using the difference between the data with imaging and the data without imaging. The phase image data is generated according to the type of the set grid size.

[0185] Step S10 is to generate a pop-up image by calculating a plurality of phase image data generated in step S09.

[0186] Figure 14 is a flowchart for explaining the creation of a pop-up image.

[0187] Step S10A is to calculate the phase image data associated with each grid size by the imaging system to generate image data. It is preferable to use multiplication or integration for the calculation.

[0188] A more detailed explanation will be given. As an example, the first image data is generated by integrating the phase image data IM1 to IM4 generated using the lattice size KM1. Subsequently, the second image data is generated by integrating the phase image data IM1 to IM16 generated using the lattice size KM2. Subsequently, the nth image data is generated by integrating n types of phase image data generated using the lattice size KMn.

[0189] Step S10B is a step in which the imaging system divides the image data into the same number as the number of pixels in the imaging region. The reason is that the first image data to the nth image data are each composed of different numbers of image data. Therefore, using the lattice sizes used when creating the first image data to the nth image data, the number of pixels in the original imaging region is divided to generate the first image data_b to the nth image data_b having the same number of image data.

[0190] Step S10C is a step in which the imaging system generates a pop-up image. The imaging system generates a pop-up image in which features are extracted by integrating the first image data_b to the nth image data_b.

[0191] FIG. 15 is an image diagram for explaining an imaging system different from that in FIG. 12. In the configuration described below, the same reference numerals are commonly used among different drawings for the same parts or parts having similar functions, and the repeated description thereof is omitted. Therefore, since STEP2 and STEP3 are the same as STEP2 and step 3 described in FIG. 12, the detailed description thereof is omitted.

[0192] Figure 15 is different from Figure 12 in that it has STEP2A. STEP2A is a step of binarizing the phase image data. As an example, the phase image data IM11 to IM14 generated in STEP2 are converted into the phase image data IN11 to IN14 by being binarized. Similarly, other phase image data are also binarized.

[0193] As an example, the first image data is generated by calculating the phase image data IN11 to IN14 generated using the grid size KM1. Subsequently, the second image data is generated by calculating the phase image data IN21 to IN216 generated using the grid size KM2. Subsequently, the nth image data is generated by calculating n types of phase image data generated using the grid size KMn.

[0194] Note that it is preferable to use multiplication for the calculation. As an example, when the image data of a certain region of the phase image data is "0", the result of calculating with the image data becomes "0" regardless of the value of the image data in the same region of other phase image data. Therefore, the amount of calculation can be reduced.

[0195] Figure 16 is a flowchart for explaining an imaging system having a binarization process. In the configuration described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same or similar functions, and the repeated description thereof is omitted.

[0196] The imaging system described in Figure 16 is different from Figure 13 in that it has step S20. By binarizing the phase image data generated in step S09, the amount of calculation for generating the pop-up image in step S10 can be reduced.

[0197] As described above, one aspect of the present invention can provide an imaging system with a novel configuration that can handle the outputs of a plurality of pixels included in a lattice-provided region as one imaging signal. Further, one aspect of the present invention can provide an imaging system that processes a part of the operation using a weighting coefficient. Further, one aspect of the present invention can provide an imaging system that can handle data larger than the imaging region by performing padding processing in the imaging device. One aspect of the present invention can provide an imaging system that suppresses an increase in the processing time of the operation using a weighting coefficient and padding processing. One aspect of the present invention can provide an imaging system that suppresses an increase in power consumption by reducing the amount of calculation by the operation using a weighting coefficient and padding processing.

[0198] This embodiment can be implemented by appropriately combining a part thereof.

[0199] (Embodiment 3) In this embodiment, a structural example of an imaging device according to one aspect of the present invention will be described.

[0200] <Structural example> FIG. 17A is a diagram showing an example of the structure of a pixel of an imaging device, and can be a laminated structure of layer 561 and layer 563.

[0201] Layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can have layer 565a and layer 565b as shown in FIG. 18A. In some cases, the layer may be rephrased as a region.

[0202] The photoelectric conversion device 101 shown in FIG. 18A is a pn junction type photodiode. For example, a p-type semiconductor can be used for layer 565a and an n-type semiconductor can be used for layer 565b. Alternatively, an n-type semiconductor can be used for layer 565a and a p-type semiconductor can be used for layer 565b.

[0203] The above pn junction type photodiode can typically be formed using single crystal silicon.

[0204] In addition, as shown in FIG. 18B, the photoelectric conversion device 101 included in layer 561 may be formed as a stack of layer 566a, layer 566b, layer 566c, and layer 566d. The photoelectric conversion device 101 shown in FIG. 18B is an example of an avalanche photodiode. Layer 566a and layer 566d correspond to electrodes, and layer 566b and 566c correspond to the photoelectric conversion section.

[0205] Layer 566a is preferably a low-resistance metal layer or the like. For example, aluminum, titanium, tungsten, tantalum, silver, or a stack thereof can be used.

[0206] For layer 566d, it is preferable to use a conductive layer having high transmittance for visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, or graphene can be used. Note that a configuration in which layer 566d is omitted is also possible.

[0207] Layers 566b and 566c of the photoelectric conversion section can be configured as a pn junction type photodiode having, for example, a selenium-based material as the photoelectric conversion layer. It is preferable to use a selenium-based material that is a p-type semiconductor for layer 566b and a gallium oxide or the like that is an n-type semiconductor for layer 566c.

[0208] A photoelectric conversion device using a selenium-based material has a characteristic of high external quantum efficiency for visible light. In this photoelectric conversion device, by utilizing avalanche multiplication, the amplification of electrons with respect to the amount of incident light can be increased. In addition, since the selenium-based material has a high light absorption coefficient, it has production advantages such as being able to fabricate the photoelectric conversion layer as a thin film. The thin film of the selenium-based material can be formed using a vacuum evaporation method, a sputtering method, or the like.

[0209] As the selenium-based material, crystalline selenium such as single-crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS), etc. can be used.

[0210] The n-type semiconductor is preferably formed of a material having a wide bandgap and being translucent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed, etc. can be used. Also, these materials also have a function as a hole injection blocking layer and can also reduce the dark current.

[0211] Also, as shown in FIG. 18C, the photoelectric conversion device 101 included in layer 561 may be a laminate of layer 567a, layer 567b, layer 567c, layer 567d, and layer 567e. The photoelectric conversion device 101 shown in FIG. 18C is an example of an organic photoconductive film. Layer 567a is a lower electrode, layer 567e is a translucent upper electrode, and layers 567b, 567c, and 567d correspond to the photoelectric conversion part.

[0212] Either one of layers 567b and 567d of the photoelectric conversion part can be a hole transport layer, and the other can be an electron transport layer. Also, layer 567c can be a photoelectric conversion layer.

[0213] As the hole transport layer, for example, molybdenum oxide, etc. can be used. As the electron transport layer, for example, 60 C 70 fullerenes such as C, or derivatives thereof, etc. can be used.

[0214] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

[0215] As the layer 563 shown in FIG. 17A, for example, a silicon substrate can be used. The silicon substrate has Si transistors or the like. Using the Si transistors, in addition to the pixel circuit, circuits for driving the pixel circuit, a circuit for reading an image signal, an image processing circuit, a neural network, a communication circuit, etc. can be formed. Also, a memory circuit such as a DRAM (Dynamic Random Access Memory), a CPU (Central Processing Unit), an MCU (Micro Controller Unit), etc. may be formed. In the present embodiment, the circuits other than the pixel circuit are referred to as functional circuits.

[0216] For example, in the transistors included in the pixel circuit (pixel P) and the functional circuits (circuits 301, 302, 303, 304, 305, etc.) described in Embodiment 1, part or all of them can be provided in the layer 563.

[0217] Also, the layer 563 may be a stack of a plurality of layers as shown in FIG. 17B. In FIG. 17B, three layers of layer 563a, 563b, and 563c are illustrated, but it may be two layers. Or, the layer 563 may be a stack of four or more layers. These layers can be stacked using, for example, a bonding process or the like. With such a configuration, the pixel circuit and the functional circuit can be dispersed in a plurality of layers and the pixel circuit and the functional circuit can be provided in an overlapping manner, so that a small and highly functional imaging device can be manufactured.

[0218] Also, the pixel may have a stacked structure of layer 561, layer 562, and layer 563 as shown in FIG. 17C.

[0219] The layer 562 can have OS transistors. One or more of the above-described functional circuits may be formed of OS transistors. Or, one or more of the functional circuits may be formed using the Si transistors in the layer 563 and the OS transistors in the layer 562.

[0220] For example, a normally-off CPU (also referred to as a "Noff-CPU") can be realized using an OS transistor and an Si transistor. Note that a Noff-CPU is an integrated circuit including a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.

[0221] The Noff-CPU can stop the power supply to circuits unnecessary for operation within the Noff-CPU and put the circuits in a standby state. In the circuits where the power supply is stopped and in the standby state, no power is consumed. Therefore, the Noff-CPU can minimize the power consumption. Also, the Noff-CPU can retain information necessary for operations such as set conditions for a long period even when the power supply is stopped. The return from the standby state only requires restarting the power supply to the circuit, and no rewriting such as set conditions is necessary. That is, a high-speed return from the standby state is possible. Thus, the Noff-CPU can reduce power consumption without significantly reducing the operating speed.

[0222] Also, as shown in FIG. 17D, the layer 562 may be a stack of a plurality of layers. In FIG. 17D, two layers, i.e., the layers 562a and 563b, are illustrated, but a stack of three or more layers may also be used. These layers can be formed, for example, by stacking them on the layer 563. Alternatively, they may be formed by bonding a layer formed on the layer 563 and a layer formed on the layer 561.

[0223] As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium, etc. can be used, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal and is suitable for transistors that emphasize reliability. Also, CAC-OS is suitable for transistors that perform high-speed driving because it exhibits high mobility characteristics.

[0224] Since the OS transistor has a large energy gap in the semiconductor layer, it exhibits extremely low off-current characteristics of several yA / μm (current value per 1-μm channel width). Also, the OS transistor has characteristics different from those of Si transistors, such as no occurrence of impact ionization, avalanche breakdown, and short-channel effects, and can form a high breakdown voltage and highly reliable circuit. Further, variations in electrical characteristics due to non-uniform crystallinity, which are a problem in Si transistors, are less likely to occur in OS transistors.

[0225] The semiconductor layer of the OS transistor can be a film represented by an In-M-Zn-based oxide containing, for example, indium, zinc, and one or more (such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) selected from metals. The In-M-Zn-based oxide can typically be formed by a sputtering method. Alternatively, it may be formed using an ALD (Atomic layer deposition) method.

[0226] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn-based oxide by the sputtering method preferably satisfies In≧M and Zn≧M. As such atomic ratios of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0227] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3Hereinafter, more preferably 1×10 13 / cm 3 Hereinafter, more preferably 1×10 11 / cm 3 Hereinafter, more preferably 1×10 10 / cm 3 less than, and an oxide semiconductor having a carrier density of 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect levels and stable characteristics.

[0228] Note that the present invention is not limited to these, and those having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate.

[0229] In the oxide semiconductor constituting the semiconductor layer, if silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and the semiconductor becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0230] In addition, when an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0231] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. For this reason, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5×10 18 atoms / cm 3 or less.

[0232] In addition, when hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen that binds to metal atoms to become water, so oxygen vacancies may be formed in the oxide semiconductor. When oxygen vacancies are contained in the channel formation region in the oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen enters oxygen vacancies may function as donors, and electrons as carriers may be generated. Also, a part of hydrogen may combine with oxygen that binds to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.

[0233] Defects in which hydrogen enters oxygen vacancies can function as donors of the oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in the oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may be paraphrased as the "donor concentration" in some cases.

[0234] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×10 18 atoms / cm 3 less than, even more preferably 1×10 18 atoms / cm 3 It is set to be less than. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0235] Further, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c-axis, polycrystalline structure, microcrystalline structure, or amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0236] The oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, the oxide film with an amorphous structure is, for example, a completely amorphous structure and has no crystal part.

[0237] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.

[0238] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

[0239] CAC-OS is, for example, a component of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size range of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following, in the oxide semiconductor, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size range of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0240] Note that the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may also be included.

[0241] For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO) refers to indium oxide (hereinafter, InO X1 (where X1 is a real number greater than 0).), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (where X2, Y2, and Z2 are real numbers greater than 0).), and gallium oxide (hereinafter, GaO X3 (where X3 is a real number greater than 0).), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are real numbers greater than 0).) and the like are separated into a mosaic state by the separation of the materials, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 is a configuration uniformly distributed in the film (hereinafter, also referred to as a cloud state).

[0242] That is, CAC-OS is a composite oxide semiconductor having a structure in which a region mainly composed of GaO X3 and a region mainly composed of In X2 Zn Y2 O Z2 or InO X1 are mixed. In this specification, for example, when the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, it is considered that the concentration of In in the first region is higher than that in the second region.

[0243] Note that IGZO is a common name and may refer to a single compound of In, Ga, Zn, and O. As a representative example, InGaO 3 (ZnO) m1 (where m1 is a natural number), or In (1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number).

[0244] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without orientation in the a-b plane.

[0245] On the other hand, CAC-OS relates to the material composition of an oxide semiconductor. CAC-OS refers to a structure in which in a material composition containing In, Ga, Zn, and O, a region observed as nanoparticle-like with Ga as a main component and a region observed as nanoparticle-like with In as a main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0246] Note that CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, a structure composed of two layers of a film mainly composed of In and a film mainly composed of Ga is not included.

[0247] Note that, for GaO X3 in the region where it is the main component, and In X2 Zn Y2 O Z2 or InO X1 in the region where it is the main component, there may be cases where a clear boundary cannot be observed.

[0248] Note that when one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. are included instead of gallium, CAC-OS refers to a configuration in which the region observed as nanoparticles mainly composed of the metal element in part and the region observed as nanoparticles mainly composed of In in part are randomly dispersed in a mosaic pattern.

[0249] CAC-OS can be formed by a sputtering method, for example, under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by the sputtering method, any one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. Also, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, it is preferable to set the flow rate ratio of oxygen gas to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0250] CAC-OS has the characteristic that no clear peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region.

[0251] In addition, in the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0252] In addition, for example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), GaO X3 regions that are the main components and In X2 Zn Y2 O Z2 or InO X1 regions that are the main components are unevenly distributed and mixed.

[0253] CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed and has properties different from those of the IGZO compound. That is, CAC-OS has a structure in which regions with GaO X3 etc. as the main components and regions with In X2 Zn Y2 O Z2 or InO X1 as the main components are phase-separated from each other, and regions with each element as the main component are mosaic-like.

[0254] Here, regions with In X2 Zn Y2 O Z2 or InO X1 as the main components are regions with higher conductivity compared to regions with GaO X3 etc. as the main components. That is, when carriers flow through regions with In X2 Zn Y2 O Z2 or InO X1 as the main components, conductivity as an oxide semiconductor is exhibited. Therefore, InX2 Zn Y2 O Z2 、 or InO X1 The region where Zn, O, or InO is the main component is distributed in a cloud shape in the oxide semiconductor, thereby achieving a high field-effect mobility (μ).

[0255] On the other hand, the region where GaO etc. is the main component is a region with high insulation compared to the region where In, Zn, O, or InO is the main component. That is, when the region where GaO etc. is the main component is distributed in the oxide semiconductor, the leakage current can be suppressed and a good switching operation can be realized. X3 such as X2 Zn Y2 O Z2 、 or InO X1 is a region with high insulation compared to the region where In, Zn, O, or InO is the main component. That is, when the region where GaO etc. is the main component is distributed in the oxide semiconductor, the leakage current can be suppressed and a good switching operation can be realized. X3 such as

[0256] Therefore, when CAC-OS is used in a semiconductor device, the insulation caused by GaO etc. and the conductivity caused by In, Zn, O, or InO act complementarily to realize a high on-current (I X3 ), and a high field-effect mobility (μ). X2 Zn Y2 O Z2 、 or InO X1 ), and a high field-effect mobility (μ). on ) can be realized.

[0257] In addition, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0258] <Stacked structure 1> Next, the stacked structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Or, some of the elements shown below may be omitted. Also, the stacked structure shown below can be formed using a bonding process, a polishing process, etc. as necessary.

[0259] FIG. 19 is an example of a cross-sectional view of a laminate having layers 560, 561, and 563 and having a bonding surface between layers 563a and 563b that constitute layer 563.

[0260] <layer 563b> Layer 563b has a functional circuit provided on silicon substrate 611. Here, as part of the functional circuit, capacitor 202, transistor 203, and transistor 204 included in circuit 303 are shown. One electrode of capacitor 202, one of the source or drain of transistor 203, and the gate of transistor 204 are electrically connected.

[0261] In layer 563b, silicon substrate 611, insulating layers 612, 613, 614, 615, 616, 617, 618 are provided. Insulating layer 612 functions as a protective film. Insulating layers 613, 613, 616, 617 function as interlayer insulating films and planarization films. Insulating layer 615 functions as a dielectric layer of capacitor 202. Insulating layer 618 and conductive layer 619 function as bonding layers. Conductive layer 619 is electrically connected to one electrode of capacitor 202.

[0262] As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As the interlayer insulating film and the planarization film, for example, an inorganic insulating film such as a silicon oxide film, an organic insulating film such as acrylic or polyimide can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. The bonding layer will be described later.

[0263] In addition, as the wiring, electrodes, and conductors that can be used for electrical connection between devices, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys containing the above-described metal elements as components, or alloys combining the above-described metal elements may be appropriately selected and used. The conductor is not limited to a single layer, and may be a plurality of layers composed of different materials.

[0264] <Layer 563a> Layer 563a has elements of pixel P. Here, as part of the elements of pixel P, transistor 102 and transistor 108 are shown. In the cross-sectional view shown in FIG. 19, the electrical connection between the two is not shown.

[0265] Silicon substrate 632, insulating layers 631, 633, 634, 635, 637, 638 are provided in layer 563a. Also, conductive layers 636, 639 are provided.

[0266] Insulating layer 631 and conductive layer 639 have the function as a bonding layer. Insulating layers 634, 635, 637 have the functions as an interlayer insulating film and a planarizing film. Insulating layer 633 has the function as a protective film. Insulating layer 638 has the function of insulating silicon substrate 632 and conductive layer 639. Insulating layer 638 can be formed of the same material as other insulating layers. Also, insulating layer 638 may be formed of the same material as insulating layer 631.

[0267] Conductive layer 639 is electrically connected to the other of the source or drain of transistor 108 and conductive layer 619. Also, conductive layer 636 is electrically connected to wiring 113 (see FIG. 3A).

[0268] The Si transistor shown in FIG. 19 is of a fin type having a channel formation region on a silicon substrate (silicon substrates 611 and 632). A cross-section in the channel width direction (the cross-section of A1 - A2 shown in layer 563a of FIG. 19) is shown in FIG. 20A. Note that the Si transistor may be of a planar type as shown in FIG. 20B.

[0269] Alternatively, as shown in FIG. 20C, it may be a transistor having a semiconductor layer 545 of a silicon thin film. The semiconductor layer 545 can be, for example, single-crystalline silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on the silicon substrate 611.

[0270] <layer 561> Layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on layer 563a. In FIG. 19, as the photoelectric conversion device 101, a configuration using the organic photoconductive film shown in FIG. 18C as the photoelectric conversion layer is shown. Here, layer 567a is used as the cathode and layer 567e is used as the anode.

[0271] Insulating layers 651, 652, 653, 654, and conductive layer 655 are provided in layer 561.

[0272] Insulating layers 651, 653, 654 have functions as an interlayer insulating film and a planarizing film. Also, insulating layer 654 is provided to cover the end portion of the photoelectric conversion device 101 and has a function of preventing a short circuit between layer 567e and layer 567a. Insulating layer 652 has a function as an element isolation layer. As the element isolation layer, it is preferable to use an organic insulating film or the like.

[0273] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102 that layer 563a has. The layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 that layer 563a has via the conductive layer 655.

[0274] <layer 560> Layer 560 is formed on layer 561. Layer 560 has a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0275] The light-shielding layer 671 can suppress the inflow of light into adjacent pixels. As the light-shielding layer 671, a metal layer such as aluminum or tungsten can be used. Also, a dielectric film having a function as an antireflection film may be laminated on the metal layer.

[0276] A color filter can be used for the optical conversion layer 672. By assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel of the color filter, a color image can be obtained.

[0277] Also, if a wavelength cut filter is used for the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be achieved.

[0278] For example, if a filter that blocks light having a wavelength equal to or less than the wavelength of visible light is used for the optical conversion layer 672, an infrared imaging device can be achieved. Also, if a filter that blocks light having a wavelength equal to or less than the wavelength of near-infrared light is used for the optical conversion layer 672, a far-infrared imaging device can be achieved. Also, if a filter that blocks light having a wavelength equal to or greater than the wavelength of visible light is used for the optical conversion layer 672, an ultraviolet imaging device can be achieved.

[0279] Also, if a scintillator is used for the optical conversion layer 672, an imaging device capable of obtaining an image in which the intensity of radiation used in an X-ray imaging device or the like is visualized can be achieved. When radiation such as X-rays transmitted through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is acquired by detecting the light with the photoelectric conversion device 101. Also, an imaging device having such a configuration may be used for a radiation detector or the like.

[0280] A scintillator contains a substance that absorbs the energy of radiation such as X-rays and gamma rays and emits visible light or ultraviolet light. For example, Gd 2 O 2 S:Tb, Gd 2 O 2 S:Pr, Gd 2 O 2 S:Eu, BaFCl:Eu, NaI, CsI, CaF 2 , BaF 2 , CeF 3 , LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0281] A microlens array 673 is provided on the optical conversion layer 672. The light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, the condensed light can be incident on the photoelectric conversion device 101, so that photoelectric conversion can be performed efficiently. The microlens array 673 is preferably formed of a resin or glass having high translucency to visible light.

[0282] <Lamination> Next, the lamination of layer 563b and layer 563a will be described.

[0283] An insulating layer 618 and a conductive layer 619 are provided on layer 563b. The conductive layer 619 has a region embedded in the insulating layer 618. Also, the surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that their heights match respectively.

[0284] An insulating layer 631 and a conductive layer 639 are provided on layer 563a. The conductive layer 639 has a region embedded in the insulating layer 631. Also, the surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that their heights match respectively.

[0285] Here, it is preferable that the main components of the conductive layer 619 and the conductive layer 639 are the same metal element. Also, it is preferable that the insulating layer 618 and the insulating layer 631 are composed of the same components.

[0286] For example, for the conductive layers 619 and 639, Cu, Al, Sn, Zn, W, Ag, Pt, Au, etc. can be used. From the viewpoint of ease of bonding, it is preferable to use Cu, Al, W, or Au. Also, for the insulating layers 618 and 631, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used.

[0287] That is, it is preferable to use the same metal material shown above for each of the conductive layer 619 and the conductive layer 639. Also, it is preferable to use the same insulating material shown above for each of the insulating layer 618 and the insulating layer 631. With such a configuration, bonding can be performed with the boundary between the layer 563b and the layer 563a as the bonding position.

[0288] Note that the conductive layer 619 and the conductive layer 639 may have a multilayer structure of a plurality of layers. In that case, it is sufficient that the surface layer (bonding surface) is the same metal material. Also, the insulating layer 618 and the insulating layer 631 may also have a multilayer structure of a plurality of layers. In that case, it is sufficient that the surface layer (bonding surface) is the same insulating material.

[0289] By such bonding, electrical connection between the conductive layer 619 and the conductive layer 639 can be obtained. Also, a connection having the mechanical strength of the insulating layer 618 and the insulating layer 631 can be obtained.

[0290] For the bonding between metal layers, a surface activation bonding method can be used in which the oxide film on the surface and the adsorption layer of impurities are removed by sputtering treatment or the like, and the cleaned and activated surfaces are brought into contact and bonded. Or, a diffusion bonding method in which the surfaces are bonded using a combination of temperature and pressure can be used. Since bonding occurs at the atomic level in both cases, excellent bonding can be obtained not only electrically but also mechanically.

[0291] In addition, for the bonding between insulating layers, after obtaining high flatness by polishing or the like, hydrophilic surfaces obtained by hydrophilic treatment with oxygen plasma or the like are brought into contact with each other for temporary bonding, and a hydrophilic bonding method in which permanent bonding is performed by dehydration through heat treatment can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, a mechanically excellent bond can be obtained.

[0292] When bonding layer 563b and layer 563a, since an insulating layer and a metal layer are mixed on each bonding surface, for example, a surface activation bonding method and a hydrophilic bonding method may be combined and used.

[0293] For example, a method of cleaning the surface after polishing, performing an antioxidant treatment on the surface of the metal layer, and then performing a hydrophilic treatment for bonding can be used. Also, the surface of the metal layer may be made of a metal with poor oxidation resistance such as Au, and a hydrophilic treatment may be performed. In addition, a bonding method other than the methods described above may be used.

[0294] By the above bonding, the circuit 303 included in layer 563b and the elements of the pixel P included in layer 563a can be electrically connected.

[0295] <Modification Example of Stacked Structure 1> FIG. 21 is a modification example of the stacked structure shown in FIG. 19, in which the configuration of the photoelectric conversion device 101 included in layer 561 and a partial configuration of layer 563a are different, and there is also a bonding surface between layer 561 and layer 563a.

[0296] Layer 561 has a photoelectric conversion device 101, insulating layers 661, 662, 664, 665, and conductive layers 135, 136.

[0297] The photoelectric conversion device 101 is a pn junction type photodiode formed on a silicon substrate, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. The photoelectric conversion device 101 is an embedded type photodiode, and the dark current can be suppressed and the noise can be reduced by a thin p-type region (a part of layer 565b) provided on the surface side (current extraction side) of layer 565a.

[0298] The insulating layer 661, and the conductive layers 135 and 136 have the function as a bonding layer. The insulating layer 662 has the functions as an interlayer insulating film and a planarizing film. The insulating layer 664 has the function as an element isolation layer. The insulating layer 665 has the function of suppressing the outflow of carriers.

[0299] The silicon substrate is provided with grooves for separating pixels, and the insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 665, it is possible to suppress the outflow of carriers generated in the photoelectric conversion device 101 to adjacent pixels. Further, the insulating layer 665 also has the function of suppressing the intrusion of stray light. Therefore, color mixing can be suppressed by the insulating layer 665. Note that an antireflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0300] The element isolation layer can be formed using the LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed using the STI (Shallow Trench Isolation) method or the like. As the insulating layer 665, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used. Note that the insulating layer 665 may have a multilayer structure.

[0301] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 135. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 136. The conductive layers 135 and 136 have regions embedded in the insulating layer 661. Further, the surfaces of the insulating layer 661 and the conductive layers 135 and 136 are planarized so that their heights are the same.

[0302] In the layer 563a, an insulating layer 638 is formed on the insulating layer 637. Further, a conductive layer 133 electrically connected to one of the source or drain of the transistor 102, and a conductive layer 134 electrically connected to the conductive layer 636 are formed.

[0303] The insulating layer 638 and the conductive layers 133 and 134 have the function as a bonding layer. The conductive layers 133 and 134 have regions embedded in the insulating layer 638. Also, the surfaces of the insulating layer 638 and the conductive layers 133 and 134 are flattened so that their heights match respectively.

[0304] Here, the conductive layers 133, 134, 135, and 136 are the same bonding layers as the aforementioned conductive layers 619 and 639. Also, the insulating layers 638 and 661 are the same bonding layers as the aforementioned insulating layers 618 and 631.

[0305] Therefore, by bonding the conductive layer 133 and the conductive layer 135, one of the source or drain of the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device and the transistor 102 can be electrically connected. Also, by bonding the conductive layer 134 and the conductive layer 136, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring 113 (see FIG. 3) can be electrically connected. Also, by bonding the insulating layer 638 and the insulating layer 661, the electrical and mechanical bonding between the layer 561 and the layer 563a can be performed.

[0306] <Stacked Structure 2> FIG. 22 is an example of a cross-sectional view of a laminate having layers 560, 561, 562, and 563 and having no bonding surface. An Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Here, an example will be described in which components of a memory circuit are provided in the layer 562 and the layer 563, and a drive circuit of the memory circuit is provided in the layer 563. Note that since the configurations of the layers 561 and 560 are the same as those shown in FIG. 19, the description thereof is omitted here.

[0307] <Layer 563> The layer 563 has a functional circuit provided on the silicon substrate 611. Here, as part of the functional circuit, the transistors 251 included in the drive circuit of the memory circuit, and the transistors 252 and 253 included in the memory circuit are shown.

[0308] <Layer 562b> Layer 562b is formed on layer 563. Layer 562b has an OS transistor. Here, transistor 254 is shown as part of a memory circuit.

[0309] Insulating layers 621, 622, 623, 624, 625, 626, 628, and 629 are provided in layer 562b. Also, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to wiring 113 (see FIG. 3).

[0310] Insulating layer 621 has a function as a blocking layer. Insulating layers 622, 623, 625, 626, 628, and 629 have functions as interlayer insulating films and planarization films. Insulating layer 624 has a function as a protective film.

[0311] As the blocking layer, it is preferable to use a film having a function of preventing hydrogen diffusion. In an Si device, hydrogen is required to terminate dangling bonds, but hydrogen near the OS transistor becomes one of the factors generating carriers in the oxide semiconductor layer and reduces reliability. Therefore, it is preferable to provide a hydrogen blocking film between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0312] As the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0313] Here, the memory circuit included in layer 563 and layer 562b has transistors 254, 253, and 252 in a memory cell. One of the source or drain of transistor 254 is electrically connected to the gate of transistor 253. The gate of transistor 254 is electrically connected to transistor 251 included in the drive circuit of the memory circuit.

[0314] The memory cell uses the gate of transistor 253 as a data holding section, and writes data with transistor 254. The memory cell is read by turning on transistor 252. By using an OS transistor with a small off-current for transistor 254 connected to the data holding section, the data holding time can be extended. For details, reference can be made to the description of NOSRAM and the like in the embodiments described later.

[0315] Fig. 23A shows the details of the OS transistor. The OS transistor shown in Fig. 23A has a self-aligned structure in which an insulating layer is provided on a stack of an oxide semiconductor layer and a conductive layer, and source electrode 705 and drain electrode 706 are formed by providing an opening reaching the oxide semiconductor layer.

[0316] The OS transistor can be configured to have a channel formation region, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the groove.

[0317] As shown in Fig. 23B, the OS transistor may have a self-aligned structure in which source region 703 and drain region 704 are formed in the semiconductor layer using gate electrode 701 as a mask.

[0318] Alternatively, as shown in Fig. 23C, it may be a non-self-aligned top-gate transistor having a region where source electrode 705 or drain electrode 706 overlaps with gate electrode 701.

[0319] The OS transistor shows a structure having a back gate 535, but it may also have a structure without a back gate. The back gate 535 may be electrically connected to the front gate of the transistor provided opposite thereto, as in the cross-sectional view in the channel width direction of the transistor shown in FIG. 23D. Note that FIG. 23D shows the cross-section of B1 - B2 of the transistor in FIG. 23A as an example, and the same applies to transistors with other structures. Also, it may be configured to supply a fixed potential different from the front gate to the back gate 535.

[0320] <Layer 562a> Layer 562a is formed on layer 562b. Layer 562a has elements of the pixel P having an OS transistor. Here, transistors 102 and 103 are shown as part of the elements of the pixel P.

[0321] Insulating layers 641, 642, 643, 644, 645, 647 are provided in layer 562a. Also, a conductive layer 646 is provided.

[0322] Insulating layers 641, 642, 644, 645, 647 function as an interlayer insulating film and a planarization film. Insulating layer 643 functions as a protective film.

[0323] One of the source or drain of transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in layer 561. Conductive layer 646 is electrically connected to the anode of the photoelectric conversion device 101 included in layer 561 and the conductive layer 627 included in layer 562b.

[0324] Although not shown in the cross-sectional view in FIG. 22, the pixel circuit included in layer 562a can be electrically connected to the circuit 303 included in layer 563. Also, circuit 303 can be electrically connected to other functional circuits.

[0325] <Modification Example of Stacked Structure 2> FIG. 24 is a modified example of the stacked structure shown in FIG. 23, in which the configuration of the photoelectric conversion device 101 included in layer 561 and a part of the configuration of layer 562a are different, and it has a bonding surface between layer 561 and layer 562a.

[0326] The photoelectric conversion device 101 included in layer 561 is a pn junction type photodiode formed on a silicon substrate, and is the same as the configuration shown in FIG. 21.

[0327] In layer 562a, an insulating layer 648 is formed on the insulating layer 647. Also, a conductive layer 138 electrically connected to one of the source or drain of the transistor 102 and a conductive layer 139 electrically connected to the conductive layer 646 are formed.

[0328] The insulating layer 648, the conductive layers 138 and 139 have the function as a bonding layer. The conductive layers 138 and 139 have regions embedded in the insulating layer 648. Also, the surfaces of the insulating layer 648 and the conductive layers 133 and 134 are flattened so that their heights are the same.

[0329] Here, the conductive layers 138 and 139 are the same bonding layers as the above-described conductive layers 619 and 639. Also, the insulating layer 648 is the same bonding layer as the above-described insulating layers 618 and 631.

[0330] Therefore, by bonding the conductive layer 138 and the conductive layer 135, one of the source or drain of the transistor 102 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device. Also, by bonding the conductive layer 139 and the conductive layer 136, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device can be electrically connected to the wiring 113 (see FIG. 3). Also, by bonding the insulating layer 648 and the insulating layer 661, the electrical and mechanical bonding between layer 561 and layer 562a can be performed.

[0331] When stacking multiple Si devices, multiple polishing processes and bonding processes are required. Therefore, there are problems such as a large number of processes, the need for dedicated equipment, and low yield, and the manufacturing cost is also high. Since the OS transistor can be formed by stacking on a silicon substrate on which a device is formed, the bonding process can be reduced.

[0332] FIG. 25A1 is an external perspective view of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450 (see FIG. 25A3), a cover glass 420, an adhesive 430 for bonding the two, and the like.

[0333] FIG. 25A2 is an external perspective view of the lower surface side of the package. The lower surface of the package has a BGA (Ball grid array) with solder balls as bumps 440. Note that not limited to BGA, it may have LGA (Land grid array), PGA (Pin Grid Array), or the like.

[0334] FIG. 26A3 is a perspective view of the package shown with a part of the cover glass 420 and the adhesive 430 omitted. An electrode pad 460 is formed on the package substrate 410, and the electrode pad 460 and the bump 440 are electrically connected via a through hole. The electrode pad 460 is electrically connected to the image sensor chip 450 by a wire 470.

[0335] Further, FIG. 25B1 is an external perspective view of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing an image sensor chip 451 (see FIG. 25B3), a lens cover 421, a lens 435, and the like. Also, an IC chip 490 (see FIG. 25B3) having functions such as a drive circuit and a signal conversion circuit of the imaging device is provided between the package substrate 411 and the image sensor chip 451, and has a configuration as a SiP (System in package).

[0336] FIG. 25B2 is an external perspective view of the lower surface side of the camera module. The lower surface and side surfaces of the package substrate 411 have a QFN (Quad flat no-lead package) configuration provided with mounting lands 441. Note that this configuration is an example, and a QFP (Quad flat package) or the aforementioned BGA may be provided.

[0337] FIG. 25B3 is a perspective view of the module shown with a part of the lens cover 421 and the lens 435 omitted. The land 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 by a wire 471.

[0338] By housing the image sensor chip in a package of the form described above, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0339] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0340] (Embodiment 4) As an electronic device that can use the imaging device according to one aspect of the present invention, there are a display device, a personal computer, an image storage device or an image playback device including a recording medium, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, cameras such as a digital still camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copying machine, a facsimile machine, a printer, a printer multifunction machine, an automated teller machine (ATM), a vending machine, and the like. Specific examples of these electronic devices are shown in FIGS. 26A to 26F.

[0341] FIG. 26A shows an example of a mobile phone, which includes a housing 981, a display unit 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone is equipped with a touch sensor on the display unit 982. All operations such as making a call or inputting characters can be performed by touching the display unit 982 with a finger or a stylus. The imaging device and its operation method according to an aspect of the present invention can be applied to the mobile phone.

[0342] FIG. 26B is a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Information can be input and output by the touch panel function of the display unit 912. Also, characters or the like can be recognized from the image acquired by the camera 919, and the characters can be output as voice by the speaker 913. The imaging device and its operation method according to an aspect of the present invention can be applied to the portable data terminal.

[0343] FIG. 26C is a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, etc. A rotation mechanism or the like is provided in the camera unit 952, and by installing it on the ceiling, imaging of the entire surrounding can be performed. The imaging device and its operation method according to an aspect of the present invention can be applied to the elements for image acquisition in the camera unit. Note that the surveillance camera is a common name and does not limit the use. For example, a device having the function of a surveillance camera is also called a camera or a video camera.

[0344] FIG. 26D is a video camera, which includes a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection part 976, a speaker 977, a microphone 978, etc. The operation keys 974 and the lens 975 are provided on the first housing 971, and the display unit 973 is provided on the second housing 972. The imaging device and its operation method according to an aspect of the present invention can be applied to the video camera.

[0345] FIG. 26E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting unit 967, a lens 965, etc. The imaging device and its operation method according to an aspect of the present invention can be applied to the digital camera.

[0346] FIG. 26F is a wristwatch-type information terminal, which includes a display unit 932, a housing-cum-wristband 933, a camera 939, etc. The display unit 932 includes a touch panel for operating the information terminal. The display unit 932 and the housing-cum-wristband 933 are flexible and have excellent wearability on the body. The imaging device and its operation method according to an aspect of the present invention can be applied to the information terminal.

[0347] This embodiment can be appropriately combined with the descriptions of other embodiments.

Description of Reference Numerals

[0348] :a11: area, a13: area, a21: area, a31: area, a33: area, a41: area, a0111: area, a111: area, a112: area, a121: area, a0122: area, a122: area, a144: area, a0211: area, a211: area, a0221: area, a0222: area, a241: area, a242: area, a243: area, a244: area, a311: area, a344: area, a411: area, a441: area, a442: area, a443: area, a444: area, a1611: area, a1612: area, a1621: area, a1622: area, d11: image data, d33: image data, d44: image data, d0111: image data, d111: image data, d0122: image data, d144: image data, d0211: image data, d211: image data, d0222: image data, d244: image data, d311: image data, d344: image data, d411: image data, d444: image data, d1611: image data, d1622: image data, IM1: phase image data, IM2: phase image data, IM3: phase image data, IM4: phase image data, IM11: phase image data, IM14: phase image data, IM16: phase image data, IM21: phase image data, IM216: phase image data, IN11: phase image data, IN14: phase image data, IN21: phase image data, IN216: phase image data, KM1: lattice size, KM2: lattice size, 100: imaging device, 101: photoelectric conversion device, 102: transistor, 102a: transistor, 103: transistor, 103a: transistor, 104: capacitor, 105: transistor, 105a: transistor, 108: transistor, 108a: transistor, 112: wiring, 113: wiring, 114: wiring, 115: wiring, 116: wiring, 117: wiring, 118: wiring, 122: wiring, 133: conductive layer, 134: conductive layer, 135: conductive layer, 136: conductive layer, 138: conductive layer, 139: conductive layer, 161: transistor, 162: transistor, 163: capacitor, 202: capacitor, 203: transistor, 204: transistor, 205: transistor, 206: transistor, 207: resistor, 211: wiring, 212: wiring, 213: wiring,215: Wiring, 216: Wiring, 217: Wiring, 218: Wiring, 219: Wiring, 251: Transistor, 252: Transistor, 253: Transistor, 254: Transistor, 300: Imaging Region, 301: Circuit, 302: Circuit, 303: Circuit, 303(1): Circuit, 303(2): Circuit, 303e: Circuit, 304: Circuit, 304a: Circuit, 305: Circuit, 313: Wiring, 320: Circuit, 320(1): Circuit, 320(2): Circuit, 320(3): Circuit, 321: Circuit, 322: Switch, 323: Switch, 330a: Circuit, 330b: Circuit, 331: Circuit, 332: Circuit, 332a: Switch, 332b: Switch, 332c: Switch, 333: Switch, 335: Memory Cell, 340: Register, 341a: Memory, 341b: Memory, 341c: Memory, 350: Circuit, 361: Selector Circuit, 362: Frame Memory, 363: Differential Circuit, 410: Package Substrate, 411: Package Substrate, 420: Cover Glass, 421: Lens Cover, 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image Sensor Chip, 451: Image Sensor Chip, 460: Electrode Pad, 461: Electrode Pad, 470: Wire, 471: Wire, 490: IC Chip, 535: Back Gate, 545: Semiconductor Layer, 546: Insulating Layer, 560: Layer, 561: Layer, 562: Layer, 562a: Layer, 562b: Layer, 563: Layer, 563a: Layer, 563b: Layer, 563c: Layer, 565a: Layer, 565b: Layer, 566a: Layer, 566b: Layer, 566c: Layer, 566d: Layer, 567a: Layer, 567b: Layer, 567c: Layer, 567d: Layer, 567e: Layer, 611: Silicon Substrate, 612: Insulating Layer, 613: Insulating Layer, 614: Insulating Layer, 615: Insulating Layer, 616: Insulating Layer, 617: Insulating Layer, 618: Insulating Layer, 619: Conductive Layer, 621: Insulating Layer, 622: Insulating Layer, 623: Insulating Layer, 624: Insulating Layer, 625: Insulating Layer, 626: Insulating Layer, 627: Conductive Layer, 628: Insulating Layer, 629: Insulating Layer, 631: Insulating Layer, 632: Silicon Substrate, 633: Insulating Layer, 634: Insulating Layer, 635: Insulating Layer, 636: Conductive Layer, 637: Insulating Layer, 638: Insulating Layer, 639: Conductive Layer, 641: Insulating Layer, 642: Insulating Layer, 643: Insulating Layer, 644: Insulating Layer, 645: Insulating Layer, 646: Conductive Layer, 647: Insulating Layer, 648: Insulating Layer, 651: Insulating Layer,652: Insulating layer, 653: Insulating layer, 654: Insulating layer, 655: Conductive layer, 661: Insulating layer, 662: Insulating layer, 664: Insulating layer, 665: Insulating layer, 671: Light-shielding layer, 672: Optical conversion layer, 673: Micro lens array, 701: Gate electrode, 702: Gate insulating film, 703: Source region, 704: Drain region, 705: Source electrode, 706: Drain electrode, 707: Oxide semiconductor layer, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 932: Display unit, 933: Housing-cum-wristband, 939: Camera, 951: Support base, 952: Camera unit, 953: Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens, 967: Light-emitting part, 971: Housing, 972: Housing, 973: Display unit, 974: Operation key, 975: Lens, 976: Connection part, 977: Speaker, 978: Microphone, 981: Housing, 982: Display unit, 983: Operation button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera,

Claims

1. An imaging device having M×N pixels (M and N are natural numbers) arranged in a matrix, during a first period, a plurality of first regions each including m×n pixels (m is a natural number smaller than M, and n is a natural number smaller than N) are set so as not to overlap among the M×N pixels, and image signals of pixels included in each of the first regions are weighted by each pixel and then added together to output the weighted data, thereby generating first phase image data; During a second period, the first regions are set so as to have a combination of pixels different from those during the first period, each of which is not overlapped with M×N pixels, and image signals of pixels included in each of the first regions are weighted by each pixel and then added together to output the weighted data, thereby generating second phase image data; generating first image data by adding or multiplying the first phase image data and the second phase image data; during a third period, a plurality of second regions each including p×q pixels (p is a natural number smaller than M, q is a natural number smaller than N, and p is different from m or q is different from n) are set so as not to overlap with the M×N pixels, and an operation is performed in which imaging signals of pixels included in each of the second regions are weighted by each pixel and then added together to output data, thereby generating third phase image data; During a fourth period, the second regions are set so as to have a combination of pixels different from those during the third period, with the pixels not overlapping each other, and image signals of pixels included in each of the second regions are weighted by each pixel and then added together to output the weighted data, thereby generating fourth phase image data; An imaging apparatus that generates second image data by adding or multiplying the third phase image data and the fourth phase image data.

2. In claim 1, Dividing each element of the first image data into m×n elements to generate third image data; Dividing each element of the second image data into p×q elements to generate fourth image data; The imaging device creates a pop-up image by adding or multiplying the third image data and the fourth image data.

3. In claim 1 or 2, The pixel includes a transistor. The imaging device, wherein the transistor has a semiconductor layer including a metal oxide.

4. In claim 3, The metal oxide comprises indium.

Images