Semiconductor element and semiconductor assembly including the same

Abstract

To provide a semiconductor element and a semiconductor assembly including the semiconductor element.SOLUTION: A semiconductor element includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region is located between the first semiconductor structure and the second semiconductor structure and includes the first dopant. This semiconductor element has a maximum external quantum efficiency of Emax% under a current density of J_EmaxA / cm2, and the semiconductor element has an external quantum efficiency of 15% or more of Emax% under a current density of 0.001*(J_Emax)A / cm2.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor light-emitting devices, such as light-emitting diodes.

Background Art

[0002] The applications of semiconductor devices are very wide, and the development and research of related materials are also continuing. For example, group III-V semiconductor materials containing group 3 and group 5 elements can be applied to various optoelectronic semiconductor devices, such as light-emitting diodes (LEDs), laser diodes (LDs), photodetectors, or solar cells, or can be power elements of switches or rectifiers that can be used in fields such as lighting, medical treatment, displays, communications, sensing, and power systems. As one of the semiconductor light-emitting devices, light-emitting diodes have advantages such as low power consumption and long service life, and are thus widely used.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to provide a semiconductor device and a semiconductor assembly including the same.

Means for Solving the Problems

[0004] According to the content of the present invention, a semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region is located between the first semiconductor structure and the second semiconductor structure and includes the first dopant. This semiconductor device has a maximum external quantum efficiency E max A / cm 2 under a current density of max %, where 0.001 A / cm 2 ≦ J_E max A / cm 2≤100 A / cm 2 and, under a current density of 0.001*(J_E max ) A / cm 2 , the semiconductor device has an external quantum efficiency of 15% or more of E max %.

Brief Description of the Drawings

[0005]

Figure 1A

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Embodiments for Carrying Out the Invention

[0006] Hereinafter, several embodiments will be described to enable those skilled in the art to more easily understand the present invention. It should be noted that these embodiments are merely illustrative and do not limit the present invention. Also, those skilled in the art may adjust the embodiments described below according to needs. For example, the order of the processes may be changed, and / or some steps may be increased or decreased.

[0007] Unless otherwise specified, the general formula InGaP represents In x0 Ga 1-x0 P, where 0 < x0 < 1; the general formula AlInP represents Al x1 In 1-x1 P, where 0 < x1 < 1; the general formula AlGaInP represents Al x2 Ga x3 In 1-x2-x3 P, where 0 < x2 < 1, 0 < x3 < 1; the general formula InGaAsP represents In x4 Ga 1-x4 As x5 P 1-x5 where 0 < x4 < 1, 0 < x5 < 1; the general formula AlGaInAs represents Al x6 Ga x7 In 1-x6-x7 As, where 0 < x6 < 1, 0 < x7 < 1; the general formula InGaNAs represents In x8 Ga 1-x8 N x9 As 1-x9 where 0 < x8 < 1, 0 < x9 < 1; the general formula InGaAs represents In x10 Ga 1-x10represents As, where 0 < x10 < 1; the general formula AlGaAs represents Al x11 Ga 1-x11 represents As, where 0 < x11 < 1; the general formula InGaN represents In x12 Ga 1-x12 represents N, where 0 < x12 < 1; the general formula AlGaN represents Al x13 Ga 1-x13 represents N, where 0 < x13 < 1; the general formula AlGaAsP represents Al x14 Ga 1-x14 As x15 P 1-x15 represents, where 0 < x14 < 1 and 0 < x15 < 1; the general formula InGaAsN represents In x16 Ga 1-x16 As x17 N 1-x17 represents, where 0 < x16 < 1 and 0 < x17 < 1; the general formula AlInGaN represents Al x18 In x19 Ga 1-x18-x19 represents N, where 0 < x18 < 1 and 0 < x19 < 1. Also, the content of each element can be adjusted according to different purposes. For example, it is not limited to adjusting the magnitude of the energy level, or when the semiconductor device is a light-emitting device, the main wavelength or peak wavelength of the light-emitting device can be adjusted thereby.

[0008] The semiconductor device of the present invention is, for example, a light-emitting device (e.g., a light-emitting diode, a laser diode), a light-absorbing device (e.g., a photo-detector), or a non-light-emitting device. The components and dopants of each layer included in the semiconductor device of the present invention can be obtained by analyzing in any appropriate manner. For example, a secondary ion mass spectrometer (SIMS) may be used. Also, the thickness of each layer can be obtained by analyzing in any appropriate manner. For example, a transmission electron microscope (TEM), a scanning electron microscope (SEM), etc. may be used.

[0009] Those skilled in the art should understand that other components may be added based on each embodiment described below. For example, unless otherwise specified, a description such as "the first layer (or structure) is located on the second layer (or structure)" may include an embodiment in which the first layer (or structure) is in direct contact with the second layer (or structure), and may also include an embodiment in which there is another structure between the first layer (or structure) and the second layer (or structure) and the two do not directly contact each other. Also, it should be understood that the vertical positional relationship of each layer (or structure) etc. may change depending on the observation direction.

[0010] Also, in the present invention, a description such as "a layer or structure is 'essentially composed of M'" represents that the main component of this layer or structure is M, but does not exclude the inclusion of dopants or inevitable impurities in this layer or structure.

[0011] FIG. 1A is a top view of the semiconductor device 10 in one embodiment of the present invention. FIG. 1B is a diagram showing a cross-sectional structure along the line X-X' of the semiconductor device 10 in FIG. 1A. FIG. 1C is a partially enlarged view of the region R in the semiconductor device 10 shown in FIG. 1B. As shown in FIG. 1A, in a top view, the semiconductor device 10 has a length L 0 and a width W0 may have. The length L 0 and the width W 0 are each, for example, 500 μm or less, for example, 450 μm, 400 μm, 350 μm, 300 μm, 250 μm, 200 μm, 150 μm, 100 μm, 50 μm, 30 μm, or 10 μm or less, and may also be 1 μm or more. In top view, the semiconductor element 10 may have a rectangular or circular shape. In one embodiment, the length L 0 and the width W 0 are substantially equal and may exhibit a square shape. In one embodiment, in top view, the area (L 0 *W 0 ) of the upper surface of the semiconductor element 10 is 10,000 μm 2 or less, for example, 1 μm 2 to 5000 μm 2 within the range (for example, 100 μm 2 , 625 μm 2 , 1250 μm 2 , 2000 μm 2 or 2500 μm 2 ). As shown in FIGS. 1A and 1B, the semiconductor element 10 includes a base 100, an epitaxial structure 102, a first electrode 110, and a second electrode 112. The epitaxial structure 102 is located on the base 100. The first electrode 110 is located on the epitaxial structure 102, and the second electrode 112 is located under the base 100.

[0012] The base 100 includes a conductive or insulating material. The conductive material is, for example, GaAs, InP, SiC, GaP, ZnO, GaN, AlN, Ge, Si, etc. The insulating material is, for example, Sapphire, etc. In one embodiment, the base 100 is a growth substrate, that is, on the base 100, for example, an epitaxial structure 102 can be formed by metalorganic chemical vapor deposition (MOCVD). In one embodiment, the base 100 is not a growth substrate but a bonding substrate, which can be bonded to the epitaxial structure 102 by an adhesive material.

[0013] As shown in FIG. 1B, the epitaxial structure 102 includes a first semiconductor structure 104, a second semiconductor structure 106, and an active region 108 between the first semiconductor structure 104 and the second semiconductor structure 106. The first semiconductor structure 104 and the second semiconductor structure 106 have opposite conductivity types. For example, the first semiconductor structure 104 is n-type and the second semiconductor structure 106 is p-type, or the first semiconductor structure 104 is p-type and the second semiconductor structure 106 is n-type. Thereby, the first semiconductor structure 104 and the second semiconductor structure 106 can provide electrons and holes, respectively. The first semiconductor structure 104, the second semiconductor structure 106, and the active region 108 may each include a group III-V semiconductor material. The group III-V semiconductor material may include Al, Ga, As, P, N, or In. In one embodiment, the first semiconductor structure 104, the second semiconductor structure 106, and the active region 108 may not include N. Specifically, the above-mentioned group III-V semiconductor materials may be binary compound semiconductors (e.g., GaAs, GaP, or GaN), ternary compound semiconductors (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN), or quaternary compound semiconductors (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the active region 108 consists essentially of a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP).

[0014] The semiconductor device 10 may include a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum wells (MQW) structure. According to one embodiment, when the semiconductor device 10 is a light-emitting device and when the semiconductor device 10 operates, the active region 108 can emit a light beam. The light beam includes visible light or invisible light. The light beam emitted by the semiconductor device 10 depends on the material components of the active region 108. For example, when the material of the active region 108 includes an InGaN system, for example, it can emit blue light, deep blue light with a peak wavelength of 400 nm to 490 nm, or green light with a peak wavelength of 490 nm to 550 nm. When the material of the active region 108 includes an AlGaN system, for example, it can emit ultraviolet light with a peak wavelength of 250 nm to 400 nm. When the material of the active region 108 includes an InGaAs system, an InGaAsP system, an AlGaAs system, or an AlGaInAs system, for example, it can emit infrared light with a peak wavelength of 700 to 1700 nm. When the material of the active region 108 includes an InGaP system or an AlGaInP system, for example, it can emit red light with a peak wavelength of 610 nm to 700 nm, or yellow light with a peak wavelength of 530 nm to 600 nm.

[0015] In one embodiment, the active region 108 may include a semiconductor stack layer 108c composed of a barrier layer 108a and an adjacent well layer 108b. That is, a pair of semiconductor stack layers 108c includes one barrier layer 108a and one well layer 108b. Specifically, the active region 108 may include one pair or a plurality of pairs of semiconductor stack layers 108c. In one embodiment, the number of pairs of semiconductor stack layers 108c is 2 or more. In one embodiment, the number of pairs of semiconductor stack layers 108c may be 20 or less, and may also be 10 or less. The number of pairs of semiconductor stack layers 108c is, for example, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, or 19. In one embodiment, when the active region 108 includes 5 or less pairs of semiconductor stack layers 108c (i.e., 5 or less barrier layers 108a and 5 or less well layers 108b), the semiconductor device 10 has a relatively high quantum efficiency. In particular, when operating under a low current density (e.g., 1 A / cm 2 or less) or a low current (e.g., 10 mA or less), the efficiency of the device is high. Specifically, the current density can be obtained by dividing the magnitude of the current applied to the semiconductor device 10 (unit: ampere (A)) by the upper surface area of the epitaxial structure 102 (unit: cm 2 ). In one embodiment, the upper surface area of the epitaxial structure 102 may be in the range of 1 μm 2 to 2500 μm 2 , for example, 50 μm 2 to 100 μm 2 , 600 μm 2 , 1200 μm 2 , 1500 μm 2 , or 2000 μm 2 . In top view, when the epitaxial structure 102 has areas of a plurality of different sizes, the aforementioned upper surface area refers to the largest of these areas.

[0016] The barrier layer 108a and / or the well layer 108b may contain AL (aluminum). In one embodiment, the active region 108 includes n pairs of semiconductor stack layers 108c, and thus has n barrier layers 108a and n well layers 108b, where n is a positive integer. Each barrier layer 108a may have a first aluminum content (percentage) (ai%, i = 1, 2,..., n), and each well layer 108b may have a second aluminum content (percentage) (bi%, i = 1, 2,..., n). a1% is the first aluminum content (percentage) of the first layer barrier layer 108a, a2% is the first aluminum content (percentage) of the second layer barrier layer 108a, and an% is the first aluminum content (percentage) of the nth layer barrier layer 108a. b1% is the second aluminum content (percentage) of the first layer well layer 108b, b2% is the second aluminum content (percentage) of the second layer well layer 108b, and bn% is the second aluminum content (percentage) of the nth layer well layer 108b. In one embodiment, the first aluminum content (percentage) of the barrier layers 108a of each layer may be the same or different. The difference in the aluminum content (percentage) (Al%) between the barrier layers 108a may be between 0 and 1 atom%. In one embodiment, the second aluminum content (percentage) of the well layers 108b of each layer may be the same or different. The difference in the aluminum content (percentage) (Al%) between the well layers 108b may be between 0 and 1 atom%.

[0017] Specifically, the first and second aluminum contents (percentages) respectively refer to the number of Al atoms (percentage) (atom%) in the barrier layer 108a and the well layer 108b, and can be obtained, for example, by measuring the barrier layer 108a and the well layer 108b respectively with an Energy Dispersive Spectrometer (EDX). For example, the barrier layer 108a contains Al z1 Ga 0.5-z1 In 0.5 P (where 0 ≤ z1 ≤ 0.5), and the well layer 108b contains Al z2 Ga 0.5-z2 In0.5 When P (where 0 ≤ z2 ≤ 0.5) is included, z1 and z2 can be obtained from the EDX measurement results. Here, the first aluminum content (percentage) (ai%) of the barrier layer 108a can be defined as z1 * 100%, and the second aluminum content (percentage) (bi%) of the well layer 108b can be defined as z2 * 100%. That is, the aluminum content (percentage) represents the ratio of Al to the total atomic number (percentage) of all group 3 elements. For example, when z1 = 0.3, it indicates that the first aluminum content (percentage) is 30%. In one embodiment, the aluminum content (percentage) of the barrier layer 108a and the well layer 108b can also be obtained by analyzing using SIMS. In one embodiment, the first aluminum content (percentage) is greater than the second aluminum content (percentage). In one embodiment, the first aluminum content (percentage) may be in the range of 15% to 50%, for example, 20%, 25%, 30%, 35%, 40%, 45% or 50%. In one embodiment, the second aluminum content (percentage) may be in the range of 0% to 15%, for example, 5% or 10%. In one embodiment, when the first aluminum content (percentage) is 25% or more, the electron confinement ability of the barrier layer 108a can be further improved, and it has a relatively good quantum efficiency (for example, EQE or IQE). In one embodiment, when the first aluminum content (percentage) is 35% or more, it has a better quantum efficiency.

[0018] In one embodiment, the active region 108 includes n pairs of semiconductor stack layers 108c, and thus has n barrier layers 108a and n well layers 108b, where n is a positive integer. Each barrier layer 108a may have a first thickness (t1i, i = 1, 2, …, n), and each well layer 108b may have a second thickness (t2i, i = 1, 2, …, n). The first thickness may be equal to or greater than the second thickness. t11 is the first thickness of the first layer barrier layer 108a, t12 is the first thickness of the second layer barrier layer 108a, and t1n is the first thickness of the nth layer barrier layer 108a. t21 is the second thickness of the first layer well layer 108b, t22 is the second thickness of the second layer well layer 108b, and t2n is the second thickness of the nth layer well layer 108b. In one embodiment, the first thicknesses of the barrier layers 108a of each layer may be the same or different, and the difference in thickness between the barrier layers 108a may be between 0 and 1 nm. In one embodiment, the second thicknesses of the well layers 108b of each layer may be the same or different, and the difference in thickness between the well layers 108b may be between 0 and 1 nm. The first thickness and the second thickness may each be 200 Å or less, for example, each may be about 150 Å, 100 Å, 50 Å, or 10 Å. In one embodiment, when the thicknesses of the barrier layer 108a and the well layer 108b are all 200 Å or less, the quantum efficiency of the semiconductor element 10 is good. In one embodiment, the ratio of the first thickness (t1i) to the second thickness (t2i) is in the range of 2:1 to 40:1. For example, the ratio of the first thickness to the second thickness (t1i / t2i) may be in the range of 10:1 to 35:1. By having a relatively large first thickness, the electron confinement ability of the barrier layer 108a can be improved. In one embodiment, the first thickness may be in the range of 20 Å to 4000 Å, for example, 100 Å or more and 2000 Å or less. The second thickness may be in the range of 10 Å to 200 Å, for example, 150 Å, 100 Å, or 50 Å.

[0019] As shown in FIG. 1B, the first semiconductor structure 104 includes a first confinement layer 114, and the second semiconductor structure 106 includes a second confinement layer 116. In this embodiment, the first confinement layer 114 and the second confinement layer 116 are adjacent to and in direct contact with the active region 108. The first confinement layer 114 and the second confinement layer 116 may each include a group 3, 5 semiconductor material, such as a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the first confinement layer 114 and the second confinement layer 116 have the same material as the barrier layer 108a. The first confinement layer 114 and / or the second confinement layer 116 may include aluminum. The first confinement layer 114 may have a third aluminum content (percentage), and the second confinement layer 116 may have a fourth aluminum content (percentage). Similar to the foregoing, the aluminum content (percentage) here represents the ratio of Al to the total number of atoms of all group 3 elements (percentage). In one embodiment, both the third aluminum content (percentage) and the fourth aluminum content (percentage) are greater than the second aluminum content (percentage). In one embodiment, the third aluminum content (percentage) and the fourth aluminum content (percentage) are equal to or greater than the first aluminum content (percentage). In one embodiment, the first confinement layer 114 may have a third thickness (t3), and the second confinement layer 116 may have a fourth thickness (t4). The third thickness and the fourth thickness may be the same or different. In one embodiment, the third thickness is equal to or greater than the second thickness, and the fourth thickness is equal to or greater than the second thickness. Thereby, the electron confinement ability of the first confinement layer 114 and the second confinement layer 116 can be improved. In one embodiment, the ratio of the third thickness to the first thickness or the second thickness (t3 / t1i or t3 / t2i) is in the range of 1.5:1 to 10:1, for example, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1.In one embodiment, the ratio of the fourth thickness to the first thickness or the second thickness (t4 / t1i or t4 / t2i) is in the range of 1.5:1 to 10:1. For example, it can be 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1. In one embodiment, when t3 / t1i, t3 / t2i, t4 / t1i or t4 / t2i is within the above range, the electron confinement ability of the first confinement layer 114 / second confinement layer 116 can be further improved.

[0020] In one embodiment, the active region 108 includes a first dopant. The first dopant has a doping concentration in the active region 108. The first dopant may be an n-type or p-type dopant with respect to the active region 108. In one embodiment, the first dopant may include a Group II, Group IV, or Group VI element in the periodic table. In one embodiment, the first dopant includes C, Zn, Si, Ge, Sn, Se, Mg, or Te. In one embodiment, the doping concentration of the first dopant in the active region 108 is 1x10 16 / cm 3 or higher. In one embodiment, the doping concentration of the first dopant in the active region 108 is less than 1x10 18 / cm 3 Specifically, the doping concentration of the first dopant in the active region 108 is 5x10 15 / cm 3 ~1x10 16 / cm 3 、5x10 16 / cm 3 、8x10 16 / cm 3 、1x10 17 / cm 3 or 5x10 17 / cm 3It may also be within the range. The first dopant may be distributed in the first semiconductor structure 104 and / or the second semiconductor structure 106. In one embodiment, the doping concentration of the first dopant in the first semiconductor structure 104 is higher than the doping concentration in the active region 108 of the first dopant. In one embodiment, the first dopant is distributed at least in the first confinement layer 114 and the active region 108. In one embodiment, the first dopant is continuously and uninterruptedly distributed in the first confinement layer 114 and the active region 108, and 1x10 16 / cm 3 or higher doping concentration. "Continuously and uninterruptedly distributed in the first confinement layer 114 and the active region 108" means that when analyzing the first confinement layer 114 and the active region 108 by SIMS, signals of the first dopant can be obtained at each depth position in the first confinement layer 114 and the active region 108. Specifically, in one embodiment, when analyzing the first dopant using SIMS, the first dopant exists at least between the surface of the first confinement layer 114 away from the active region 108 side to the interface between the active region 108 and the second confinement layer 116, and exists in each barrier layer 108a and each well layer 108b of the active region 108.

[0021] In one embodiment, in the semiconductor stack layer 108c of the active region 108 closest to the first confinement layer 114, the doping concentration of the first dopant is 1x10 16 / cm 3 or higher and 1x10 18 / cm 3 or lower may also be acceptable. In one embodiment, in the semiconductor stack layer 108c of the active region 108 closest to the second confinement layer 116, the doping concentration of the first dopant is 1x10 16 / cm 3 or higher and 1x10 17 / cm 3The following may be the case. In one embodiment, the doping concentration of the first dopant in the semiconductor stack layer 108c of the active region 108 closest to the first confinement layer 114 is equal to or higher than the doping concentration of the first dopant in the semiconductor stack layer 108c of the active region 108 closest to the second confinement layer 116. In one embodiment, the first dopant is distributed at least in the first confinement layer 114, the second confinement layer 116, and the active region 108. In one embodiment, the doping concentration of the first dopant in the first confinement layer 114 is equal to or higher than the doping concentration of the first dopant in the active region 108. In one embodiment, the doping concentration of the first dopant in the active region 108 is equal to or higher than the doping concentration of the first dopant in the second confinement layer 116. In one embodiment, the doping concentration of the first dopant gradually decreases from the first confinement layer 114 to the second confinement layer 116. Specifically, in one embodiment, the first dopant in the first confinement layer 114 may have a minimum doping concentration c1, the first dopant in the second confinement layer 116 may have a minimum doping concentration c2, and the first dopant in the active region 108 may have a minimum doping concentration c3, where c1 ≧ c3 ≧ c2. The minimum doping concentrations c1, c2, and c3 may be the minimum values of the doping concentrations of the first dopant in the first confinement layer 114, the second confinement layer 116, and the active region 108, respectively. When analyzing the first dopant using SIMS, the above-mentioned minimum values may correspond to the positions of the lowest valleys of the first dopant concentration curve in the SIMS analysis results in the first confinement layer 114, the second confinement layer 116, and the active region 108 (when there is no obvious valley, it refers to the minimum value of the detectable concentration).

[0022] The first semiconductor structure 104 may further include a first capping layer 118 located below the first confinement layer 114. The first capping layer 118 may include a group III-V semiconductor material, such as a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the first capping layer 118 also includes a first dopant. In one embodiment, the doping concentration of the first dopant in the first capping layer 118 is equal to or greater than the doping concentration of the first dopant in the first confinement layer 114.

[0023] In one embodiment, the first semiconductor structure 104 may optionally further include a first window layer (not shown) located below the first capping layer 118. The first window layer may include a group III-V semiconductor material, such as a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). The material of the first window layer may be different from the material of the first capping layer 118. In one embodiment, the thickness of the first window layer is greater than the thickness of the first capping layer 118. In one embodiment, the first window layer also includes a first dopant. In one embodiment, the doping concentration of the first dopant in the first window layer is equal to or greater than the doping concentration of the first dopant in the first capping layer 118 or the first confinement layer 114. In one embodiment, in the first capping layer 118 and / or the first window layer, the doping concentration of the first dopant is 1x10 19 / cm 3 or less, for example, in the range of 5x10 17 / cm 3 to 1x10 18 / cm 3 , 2x10 18 / cm 3 or 3x10 18 / cm 3 .

[0024] In one embodiment, the second semiconductor structure 106 further includes a second cladding layer 119 located above the second confinement layer 116. The second cladding layer 119 may include a group III-V semiconductor material, for example, a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN or AlGaAsP). In one embodiment, the second cladding layer 119 includes a second dopant different from the first dopant. In one embodiment, the second dopant may include a group II, group IV or group VI element in the periodic table. In one embodiment, the second dopant includes C, Zn, Si, Ge, Sn, Se, Mg or Te. The second dopant may also be distributed in the active region 108 and / or the second confinement layer 116. In one embodiment, the first dopant and the second dopant may be present simultaneously in the second confinement layer 116 and / or the second cladding layer 119. In one embodiment, the second dopant in the second confinement layer 116 and / or the second cladding layer 119 may have a doping concentration of 1x10 16 / cm 3 or more.

[0025] In one embodiment, the first semiconductor structure 104 may include a third dopant different from the first dopant and the second dopant. In one embodiment, the third dopant is distributed in the first cladding layer 118 and / or the first window layer. In one embodiment, the first dopant is distributed in the first cladding layer 118, the first confinement layer 114 and the active region 108, and the third dopant is mainly distributed in the first window layer. In one embodiment, the first dopant and the third dopant are not present simultaneously in the first confinement layer 114, the active region 108, the first cladding layer 118 or the first window layer. For example, in the first confinement layer 114, the active region 108, the first cladding layer 118 or the first window layer, the minimum doping concentration of one of the first dopant and the third dopant is 1x10 16 / cm 3Lower. In one embodiment, the third dopant may include a Group II, Group IV, or Group VI element in the periodic table. In one embodiment, the third dopant includes C, Zn, Si, Ge, Sn, Se, Mg, or Te. In one embodiment, the atomic radius of the third dopant is smaller than the atomic radius of the first dopant or the second dopant. In one embodiment, for the first semiconductor structure 104, the first dopant and the third dopant are dopants of the same conductivity type, and the second dopant is a dopant of the opposite conductivity type. For example, for the first semiconductor structure 104, the first dopant and the third dopant are p-type dopants, and the second dopant is an n-type dopant, or the first dopant and the third dopant are n-type dopants, and the second dopant is a p-type dopant. In one embodiment, the first dopant is continuously and uninterruptedly distributed in the first cladding layer 118 to the second confinement layer 116. For example, when analyzing the first cladding layer 118 to the second confinement layer 116 by SIMS, signals of the first dopant can be obtained at each depth position in the first cladding layer 118 to the second confinement layer 116. In one embodiment, the second dopant is continuously and uninterruptedly distributed in the second cladding layer 119. For example, when analyzing the second cladding layer 119 by SIMS, signals of the second dopant can be obtained at each depth position in the second cladding layer 119. In one embodiment, the third dopant is continuously and uninterruptedly distributed in the first window layer. For example, when analyzing the first window layer by SIMS, signals of the third dopant can be obtained at each depth position in the first window layer. In one embodiment, the doping concentration of the second dopant in the second confinement layer 116 may be slightly lower than the doping concentration of the second dopant in the second cladding layer 119. In one embodiment, the doping concentration of the third dopant in the first window layer may be higher than the doping concentration of the third dopant in the first cladding layer 118. In one embodiment, the first dopant and the third dopant can be simultaneously present at the interface between the first window layer and the first cladding layer 118.

[0026] The first electrode 110 and the second electrode 112 are used to be electrically connected to an external power source. The materials of the first electrode 110 and the second electrode 112 may be the same or different, and include, for example, a metal oxide material, a metal, or an alloy respectively. The metal oxide material includes ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO, IZO, etc. The metal may be, for example, Ge, Be, Zn, Au, Pt, Ti, Al, Ni, Cu, etc. The alloy may include at least two selected from the group consisting of these metals, for example, GeAuNi, BeAu, GeAu, ZnAu, etc. As shown in FIG. 1A, the first electrode 110 may include an electrode pad 110a and an extended electrode 110b connected to the electrode pad 110a. In this embodiment, the extended electrode 110b includes a first extension 110b1 and a second extension 110b2. The first extension 110b1 is in direct contact with the electrode pad 110a, and the second extension 110b2 is in direct contact with the first extension 110b1 and may extend in a direction perpendicular to the first extension 110b1. In one embodiment, the semiconductor element 10 may have only the electrode pad 110a, but is not limited thereto.

[0027] FIG. 1D is a diagram showing a cross-sectional structure of a semiconductor element 20 according to an embodiment of the present invention. The main difference between the semiconductor element 20 of this embodiment and the semiconductor element 10 is that the semiconductor element 20 further includes an insulating layer 120, a conductive layer 122, a reflective layer 124, and a bonding structure 128. The insulating layer 120, the conductive layer 122, the reflective layer 124, and the bonding structure 128 are located between the epitaxial structure 102 and the base 100. In this embodiment, the insulating layer 120 is in contact with the second semiconductor structure 106, the first electrode 110 is located on the first semiconductor structure 104, and is in contact with and electrically connected to the first semiconductor structure 104. The conductive layer 122 covers the insulating layer 120, the reflective layer 124 covers the conductive layer 122, and the bonding structure 128 is located between the base 100 and the reflective layer 124.

[0028] The insulating layer 120 may be a patterned dielectric material layer, for example, an insulating material having a refractive index less than 2, for example, SiN x 、AlOx , SiO x , MgF x or a combination thereof may be included. In one embodiment, x = 1.5 or 2. As shown in FIG. 1D, the insulating layer 120 has a plurality of pores 126, and the conductive layer 122 can cover the insulating layer 120 and fill the pores 126, and the conductive layer 122 and the epitaxial structure 102 can form a contact region at the pores 126. Thereby, the conductive layer 122 can be electrically connected to the epitaxial structure 102. The conductive layer 122 may include a metal or a metal oxide. The metal may include Ag, Ge, Au, Ni, or a combination thereof. The metal oxide may include ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO, IZO, or a combination of these materials.

[0029] The reflective layer 124 can reflect the light beam emitted from the active region 108 and emit it out of the semiconductor device 20 toward the first electrode 110. The reflective layer 124 may include a semiconductor material, a metal, or an alloy. The semiconductor material may include group 3, 5 semiconductor materials, for example, binary, ternary, or quaternary group 3, 5 semiconductor materials. The metal may include, but is not limited to, Cu, Al, Sn, Au, Ag, Pb, Ti, Ni, Pt, W, etc. The alloy may include at least two selected from the group consisting of these metals. In one embodiment, the reflective layer 124 may include a Distributed Bragg Reflector structure (DBR). The Bragg reflection structure may be formed by alternately stacking (stacking) two or more semiconductor materials with different refractive indices, for example, formed by AlAs / GaAs, AlGaAs / GaAs, or InGaP / GaAs.

[0030] The bonding structure 128 is connected to the base 100 and the reflective layer 124. In one embodiment, the bonding structure 128 may be a single layer or multiple layers (not shown). The material of the bonding structure 128 may include a transparent conductive material, a metal, or an alloy. The transparent conductive material may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, ZnO, GaP, ICO, IWO, ITiO, IZO, IGO, GAZO, graphene, or a combination of these materials. The metal may include, but is not limited to, Cu, Al, Sn, Au, Ag, Pb, Ti, Ni, Pt, W, etc. The alloy may include at least two selected from the group consisting of these metals.

[0031] In FIG. 1D, it is shown that the first semiconductor structure 104 is located above the active region 108 and the second semiconductor structure 106 is located below the active region 108. However, in another embodiment, the following aspect may also be possible, that is, the first semiconductor structure 104 is located below the active region 108 and is in contact with the insulating layer 120 and the conductive layer 122, and the second semiconductor structure 106 is located above the active region 108 and is in contact with the first electrode 110. Since the content and structural variations of the positions, relative relationships, material components, etc. of each other layer or structure in this embodiment have all been described in detail in the previous embodiment, the detailed description thereof is omitted here.

[0032] FIG. 1E is a top view of a semiconductor device 40 according to an embodiment of the present invention. FIG. 1F is a cross-sectional structure diagram along the Y-Y' line of the semiconductor device 40 in FIG. 1E. The main difference between the semiconductor device 40 of this embodiment and the semiconductor device 10 is that the first electrode 110 and the second electrode 112 in the semiconductor device 40 are located on the same side of the base 100, while the first electrode 110 and the second electrode 112 in the semiconductor device 10 are located on both sides of the base 100, respectively. In this embodiment, the epitaxial structure 102 is located on the base 100, and the first electrode 110 and the second electrode 112 are located on the epitaxial structure 102. The first electrode 110 can be in contact with the second semiconductor structure 106, and the second electrode 112 can be in contact with the first semiconductor structure 104. In this embodiment, the first semiconductor structure 104 and the active region 108 have a width smaller than the width of the second semiconductor structure 106. Although FIG. 1F shows that the first semiconductor structure 104 is located above the active region 108 and the second semiconductor structure 106 is located below the active region 108, in another embodiment, the first semiconductor structure 104 may be located below the active region 108 and in contact with the base 100, and the second semiconductor structure 106 may be located above the active region 108 and in contact with the second electrode 112. Similarly, the insulating layer 120, the conductive layer 122, the reflective layer 124, or the bonding structure 128 described in the previous embodiment may be located between the second semiconductor structure 106 and the base 100. The bonding structure 128 may include a conductive or non-conductive material. In addition, the positions, relative relationships, material components, etc. of each other layer or structure in this embodiment, as well as the modification examples of the structure, have all been described in detail in the previous embodiment, so the detailed description thereof is omitted here.

[0033] FIG. 2A is a diagram showing the relationship between the current density and the internal quantum efficiency (IQE) of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 2A shows an IQE curve obtained by performing a simulation on a semiconductor device using simulation software APSYS (Crosslight Software Inc.). The semiconductor device corresponding to curve C1 has a structure that is not doped in the active region 108, and the semiconductor device corresponding to curve C2 has an approximately 1x10 doping in the active region 108 16 / cm 3 includes a structure having a first dopant with a doping concentration of. As shown in FIG. 2A, both have a maximum IQE value where the current density is about 30 A / cm 2 . Also, within the low current density range of 1 A / cm 2 or less, the semiconductor device having the first dopant in the active region 108 has a relatively high IQE value compared to the semiconductor device not doped in the active region 108. Therefore, the presence of the first dopant in the active region can help improve the IQE value, especially in an environment of low current density (for example, 1 A / cm 2 or less), the IQE value can be significantly improved.

[0034] FIG. 2B is a diagram showing the relationship between the current density and the external quantum efficiency (EQE) of the semiconductor device in the embodiment of the invention. The semiconductor device corresponding to curve F1 has a structure not doped in the active region 108, and the semiconductor device corresponding to curve F2 includes a structure having a first dopant in the active region 108. As shown in FIG. 2B, within the low current density range of 1 A / cm 2 or less (for example, 0.001 to 1 A / cm 2 ), the semiconductor device having the first dopant in the active region 108 has a relatively high external quantum efficiency.

[0035] FIG. 2C is a diagram showing the relationship between the R value and the relative EQE ratio of the semiconductor device in the embodiment of the present invention. The semiconductor device corresponding to curve G1 has a structure not doped in the active region 108, and the semiconductor device corresponding to curve G2 includes a structure having a first dopant in the active region 108. When the semiconductor devices corresponding to curve G1 and curve G2 are measured within the current density range of 0.001 A / cm 2 to 100 A / cm 2 , within this current density range, the semiconductor device can have a maximum external quantum efficiency E max %, and the current density corresponding to this maximum external quantum efficiency is J_E max A / cm 2 is defined as. R value = 1 in FIG. 2C means that the current density is 1*(J_ Emax ) A / cm2 corresponds to the result that, and FIG. 2C shows 0.001*(J_E max ) A / cm 2 ~1*(J_E max ) A / cm 2 and shows the relative EQE ratio within the current density range. In other words, this relative EQE ratio is obtained by setting E max % to 100% and calculating the percentage that the EQE values obtained under different current densities occupy in E max %. As shown in FIG. 2C, the semiconductor element having the first dopant in the active region 108 has relatively good EQE in all current density ranges lower than J_E max . For example, under the current density of 0.001*(J_E max ) A / cm 2 , the semiconductor element having the first dopant in the active region 108 is much better than the semiconductor element not doped in the active region 108.

[0036] FIG. 2D is a diagram showing the relationship between the current density and the external quantum efficiency (EQE) of the semiconductor element in the embodiment of the present invention. The difference points of the semiconductor elements of curves Q1 to Q3 are in the aluminum content (percentage) in the barrier layer. For the semiconductor element corresponding to curve Q1, the aluminum content (percentage) of each barrier layer 108a is about 17.5%. For the semiconductor element corresponding to curve Q2, the aluminum content (percentage) of each barrier layer 108a is about 35%. For the semiconductor element corresponding to curve Q3, the aluminum content (percentage) of each barrier layer 108a is about 50%. As can be seen from FIG. 2D, when the current density is 1 A / cm 2 or less, increasing the aluminum content (percentage) of the barrier layer 108a can help improve the EQE of the semiconductor element.

[0037] FIG. 3 is a diagram showing the relationship between the concentration and depth of elements in a partial region of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 3 is the result of analyzing a partial structure of a semiconductor device 10 including a first dopant and a second dopant by SIMS. As shown in FIG. 3, the semiconductor device 10 of this embodiment includes, in order, a second coating layer 119, a second confinement layer 116, an active region 108, a first confinement layer 114, a first coating layer 118, and a first window layer 130. In this embodiment, the second coating layer 119 contains AlInP, the second confinement layer 116 contains AlGaInP, the active region 108 contains 16 pairs of semiconductor stack layers 108c (16 barrier layers 108a and 16 well layers 108b), and all of the barrier layers 108a and well layers 108b contain AlGaInP, the first confinement layer 114 contains AlGaInP, the first coating layer 118 contains AlInP, and the first window layer 130 contains AlGaInP. Curve D1 in FIG. 3 represents the dopant concentration of the first dopant, and curve D2 represents the dopant concentration of the second dopant. In this embodiment, the first dopant is distributed at least within the range from the first window layer 130 to the second confinement layer 116, and the second dopant is mainly distributed in the second coating layer 119 and the second confinement layer 116. As shown in FIG. 3, the doping concentration of the second dopant in the second confinement layer 116 is significantly lower than the doping concentration of the second dopant in the second coating layer 119.

[0038] FIG. 4 is a diagram showing the relationship between the current density and the internal quantum efficiency (IQE) of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 4 is an IQE curve obtained by performing a simulation on a semiconductor device using simulation software APSYS (Crosslight Software Inc.). The difference between each semiconductor device lies in the first dopant having different doping concentrations in the active region 108. Specifically speaking, the semiconductor device corresponding to curve E0 has a structure that is not doped in the active region 108, and curves E1 to E5 each have a doping concentration of the first dopant of about 1x10 16 / cm 3 、5x1016 / cm 3 and 1×10 17 / cm 3 and 5×10 17 / cm 3 and 1×10 18 / cm 3 corresponds to the structure. As shown in FIG. 4, in this embodiment, at a low current density of 1 A / cm 2 or less, the doping concentration of the first dopant is about 1×10 16 / cm 3 to 1×10 17 / cm 3 The IQEs of all the structures (curves E1 to E3) within the range are all significantly better than that of the structure (curve E0) not doped in the active region 108. In this embodiment, when the doping concentration of the first dopant increases to 1×10 17 / cm 3 and in the case of 1 A / cm 2 or less, it has the maximum IQE value. When the doping concentration of the first dopant increases to 5×10 17 / cm 3 or 1×10 18 / cm 3 (curves E4 to E5), within some current density ranges, the IQE is still better than that of the structure (curve E0) not doped in the active region 108. As can be seen from FIG. 4, in this embodiment, due to the presence of the first dopant within a specific doping concentration range in the active region 108, the quantum efficiency in an environment with a low current density (for example, 1 A / cm 2 or less) can be improved while maintaining the maximum quantum efficiency.

[0039] FIG. 5A is a diagram showing a cross-sectional structure of a semiconductor assembly 200 in an embodiment of the present invention. As shown in FIG. 5A, the semiconductor assembly 200 includes a mounting substrate 22, an adhesive layer 24 located on the mounting substrate 22, and a plurality of semiconductor elements 10' located on the adhesive layer 24. In this embodiment, the semiconductor element 10' does not include a base, and the semiconductor element 10' includes the epitaxial structure 102 described in each embodiment and a first electrode 110 and a second electrode 112 located on both sides of the epitaxial structure 102, respectively. The mounting substrate 22 is in contact with the semiconductor element 10' through the adhesive layer 24. The mounting substrate 22 may include a conductive or insulating material, such as sapphire, glass, GaAs, InP, SiC, GaP, ZnO, GaN, AlN, Ge, Si, etc. The material of the adhesive layer 24 may include a polymer material, such as benzocyclobutene (BCB), epoxy resin, polyimide, silicone resin, or SOG (Spin On Glass). Note that the content and structural variations of the positions, relative relationships, material components, etc. of the other layers or structures in this embodiment have been described in detail in the previous embodiment, so the detailed description thereof is omitted here.

[0040] FIG. 5B is a diagram showing a cross-sectional structure of a semiconductor assembly 400 in an embodiment of the present invention. As shown in FIG. 5B, the semiconductor assembly 400 includes a mounting substrate 42, an adhesive layer 44 located on the mounting substrate 42, and a plurality of semiconductor elements 40' located on the adhesive layer 44. In this embodiment, the semiconductor element 40' does not include a base, and the semiconductor element 40' may include the epitaxial structure 102 described in the previous embodiment, and a first electrode 110 and a second electrode 112 located on one side of the epitaxial structure 102. The semiconductor element 40' further includes a first contact structure 140a located between the first electrode 110 and the epitaxial structure 102, and a second contact structure 140b located between the second electrode 112 and the epitaxial structure 102. The first contact structure 140a and the second contact structure 140b may each include a group III-V semiconductor material, a metal, or an alloy. The semiconductor element 40' further includes a dielectric material layer 160 that covers the epitaxial structure 102 and has an opening. As shown in FIG. 5B, the first electrode 110 and the second electrode 112 may fill the opening of the dielectric material layer 160 and be electrically connected to the first contact structure 140a and the second contact structure 140b, respectively. Note that for the mounting substrate 42 and the adhesive layer 44, the descriptions of the mounting substrate 22 and the adhesive layer 24 can be referred to respectively. In addition, since the contents and structural variations such as the positions, relative relationships, and material components of the other layers or structures in this embodiment have been described in detail in the previous embodiment, the detailed description thereof is omitted here.

[0041] FIG. 6 is a diagram showing a cross-sectional structure of a semiconductor assembly 600 according to an embodiment of the present invention. Referring to FIG. 6, the semiconductor assembly 600 includes a semiconductor element 60, a package substrate 61, a carrier 63, bonding wires 65, a contact structure 66, and a package layer 68. The package substrate 61 may include a ceramic or glass material. The package substrate 61 has a plurality of through holes 62. By filling the through holes 62 with a conductive material, such as a metal, etc., conduction and / or heat dissipation can be assisted. The carrier 63 is located on a surface of one side of the package substrate 61 and may include a conductive material, such as a metal. The contact structure 66 is located on a surface of the other side of the package substrate 61. In this embodiment, the contact structure 66 includes a first contact pad 66a and a second contact pad 66b, and the first contact pad 66a and the second contact pad 66b can be electrically connected to the carrier 63 through the through holes 62. In one embodiment, the contact structure 66 may further include a thermal pad (not shown), and the thermal pad is located, for example, between the first contact pad 66a and the second contact pad 66b.

[0042] The semiconductor element 60 is located on the carrier 63. The semiconductor element 60 may be the semiconductor element described in any embodiment of the present invention (for example, semiconductor elements 10, 10’, 20, 40, 40’). In this embodiment, the carrier 63 includes a first portion 63a and a second portion 63b, and the semiconductor element 60 is electrically connected to the second portion 63b of the carrier 63 by the bonding wires 65. The material of the bonding wires 65 may include a metal, such as gold, silver, copper, aluminum, or an alloy containing at least one of these elements. The package layer 68 covers the semiconductor element 60 and has the effect of protecting the semiconductor element 60. Specifically, the package layer 68 may include a resin material, such as an epoxy resin, a silicone resin, etc. The package layer 68 may further include a plurality of wavelength conversion particles (not shown) for converting the first light emitted from the semiconductor element 60 into second light. The wavelength of the second light is longer than the wavelength of the first light.

[0043] FIG. 7 is a top view of a semiconductor assembly 800 in an embodiment of the present invention. The semiconductor assembly 800 of this embodiment is, for example, a display unit. As shown in FIG. 7, the semiconductor assembly 800 includes a carrier 80 and a plurality of pixel units 82 located on the carrier 80. The plurality of pixel units 82 are arranged in an array in directions parallel to the x-axis and the y-axis, and are arranged at intervals d in a direction parallel to the x-axis. The number of pixel units 82 may be adjusted according to needs. For example, in one embodiment, the plurality of pixel units 82 included in the semiconductor assembly 800 can provide a resolution of 1920×1080 pixels. In one embodiment, the interval d is smaller than 1.4 mm. For example, the interval d is between 0.2 mm and 1.3 mm. Specifically, for example, it is 0.75 mm, 0.8 mm, 1 mm, or 1.25 mm. As shown in FIG. 7, each pixel unit 82 includes a first semiconductor element 84, a second semiconductor element 86, and a third semiconductor element 88 arranged in a direction parallel to the y-axis. One or more of the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 may be the semiconductor elements (for example, semiconductor elements 10, 10', 20, 40, 40') described in any embodiment of the present invention. In one embodiment, the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 are all light-emitting elements and can emit red light, green light, and blue light respectively. In one embodiment, the arrangement order of these light-emitting elements may also be adjusted according to needs. For example, the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 may emit red light, blue light, and green light respectively. Each pixel unit 82 can be electrically connected to a circuit (not shown) on the surface of the carrier 80 so that the light-emitting elements therein receive an external signal and emit light based on the external signal. The carrier 80 may have a single-layer or multi-layer structure. The material of the carrier 80 may include polyester, polyimide (PI), BT resin (Bismaleimide Triazine), PTFE resin (Polytetrafluoroethylene), phenol resin (PF), or glass fiber epoxy resin (FR4).In one embodiment, the carrier 80 can be bent and can withstand, for example, a state where the radius of curvature is less than 50 mm, for example, 25 mm or 32 mm.

[0044] As can be seen from the above, the length L of the semiconductor element 0 and the width W 0 are within the above-mentioned range (500 μm or less), and the operating current of the semiconductor element is between 0.001 mA and 100 mA and / or the current density is between 0.001 A / cm 2 and 100 A / cm 2 When between them, the number of pairs of the semiconductor stack layer 108c in the active region 108, and / or the first aluminum content (percentage), and / or the thicknesses of the barrier layer 108a and the well layer 108b, and / or the thicknesses of the first or second confinement layer, and / or the aluminum content of the first or second confinement layer, and / or the concentration of the first dopant in the active region 108, etc., can all affect the quantum efficiency of the semiconductor element.

[0045] Specifically, in one embodiment, when the operating current is between 0.01 mA and 5 mA and / or the current density is between 0.01 A / cm 2 and 5 A / cm 2 When between them, an epitaxial structure or a semiconductor element that satisfies any one or any combination of two or more of the following conditions (i) to (vi) has a relatively high quantum efficiency, that is, (i) the first aluminum content (percentage) is 25% or more; (ii) the ratio of the first thickness to the second thickness is within the range of 2:1 to 40:1; (iii) the number of pairs of the semiconductor stack layer 108c in the active region 108 is 10 pairs or less; (iv) the third / fourth aluminum content (percentage) is greater than the second aluminum content (percentage); (v) the third thickness is greater than or equal to the second thickness, and the fourth thickness is greater than or equal to the second thickness; and, (vi) the active region 108 contains the first dopant. Furthermore, the length L of the semiconductor element 10 0 is less than 200 μm, the width W 0 is less than 200 μm, and / or the upper surface area of the epitaxial structure 102 is 50 μm 2 ~2000 μm2 When within the range of, an epitaxial structure or a semiconductor device that satisfies any one or any combination of two or more of the above-mentioned conditions (i) to (vi) is more remarkable in terms of improving the quantum efficiency.

[0046] According to one embodiment, under different current densities (for example, within the range of 0.001 to 100 A / cm 2 and, for example, 0.001 to 0.01, 0.1, 1, 5, 10 or 50 A / cm 2 ), when measuring the external quantum efficiency (for example, in units of %) of an epitaxial structure or a semiconductor device, an epitaxial structure or a semiconductor device that satisfies any one or any combination of two or more of the above-mentioned conditions (i) to (vi) has the maximum external quantum efficiency E 1max % within the above-mentioned current density range, and the current density corresponding to the maximum external quantum efficiency E 1max % is defined as J_E 1max A / cm 2 . The external quantum efficiency can be obtained, for example, by measuring with an integrating sphere system. Under a current density of 0.1*(J_E 1max ) A / cm 2 , the aforementioned epitaxial structure or semiconductor device has an external quantum efficiency of 80% or more of E 1max %, and preferably can have an external quantum efficiency of 85% or 90% or more of E 1max %. Under a current density of 0.01*(J_E 1max ) A / cm 2 , the aforementioned epitaxial structure or semiconductor device has an external quantum efficiency of 50% or more of E 1max %, and preferably can have an external quantum efficiency of 60% or 70% or more of E 1max %. Under a current density of 0.001*(J_E 1max ) A / cm 2 , the aforementioned epitaxial structure or semiconductor device has an external quantum efficiency of 15% or more of E 1max %, and preferably E 1maxIt can have an external quantum efficiency of 20%, 25%, 30% or 40% or more.

[0047] According to one embodiment, when measuring the external quantum efficiency (e.g., in units of %) of an epitaxial structure or a semiconductor device under different current intensities (e.g., within the range of 0.001 to 100 mA, e.g., 0.001 to 0.01, 0.1, 1, 5, 10, 20, 30, 40 or 50 mA), the epitaxial structure or semiconductor device that satisfies any one or any combination of two or more of the above conditions (i) to (vi) has a maximum external quantum efficiency E 2max % within the above current range, and the current density corresponding to the maximum external quantum efficiency E 2max % is defined as C_E 2max mA. The external quantum efficiency can be obtained, for example, by measuring with an integrating sphere system. E 2max % is 80% or more, and preferably, E 2max % can be 85% or 90% or more. Under a current of 0.01*(C_E 2max ) mA, the aforementioned epitaxial structure or semiconductor device has an external quantum efficiency of 50% or more of E 2max %, and preferably, it can have an external quantum efficiency of 60% or 70% or more of E 2max %. Under a current of 0.001*(C_E 2max ) mA, the aforementioned epitaxial structure or semiconductor device has an external quantum efficiency of 15% or more of E 2max %, and preferably, it can have an external quantum efficiency of 20%, 25%, 30% or 40% or more of E 2max %.

[0048] According to one embodiment, an epitaxial structure or a semiconductor device that satisfies any one or any combination of two or more of the above conditions (i) to (vi) has a first light output value O1 (for example, in units of lumen (lm)) under a first temperature, and has a second light output value O2 under a second temperature, where the second temperature is lower than the first temperature. The first temperature and the second temperature are, for example, different environmental temperatures for testing or operating the epitaxial structure and / or the semiconductor device. The ratio of the first light output value O1 to the second light output value O2 may be 30% or more, for example, 40%, 50%, 60%, 70%, 80%, 90%. The ratio of the first light output value O1 to the second light output value O2 may be 100% or less. The difference between the first temperature and the second temperature may be 30 ° C or more, for example, about 40 ° C, 50 ° C, 60 ° C, 70 ° C or 80 ° C. In one embodiment, the second temperature is room temperature (for example, about 25 ° C), and the first temperature is about 85 ° C. That is, the light output value of the epitaxial structure or the semiconductor device that satisfies any one or any combination of two or more of the above conditions (i) to (vi) is relatively little affected by the change in temperature and can have a relatively low temperature dependence.

[0049] From the above, according to the embodiments of the present invention, an epitaxial structure, a semiconductor device, or a semiconductor assembly can be provided, and characteristics such as internal or external quantum efficiency can be further improved. In particular, low current (for example, 10 mA or less) or low current density (for example, 1 A / cm 2It can be applied when operations and / or miniaturization as described below are necessary. Specifically, the epitaxial structure, semiconductor device, or semiconductor assembly of the present invention can be improved in terms of surface recombination velocity (SRV), temperature dependence, current spreading, and droop in operation efficiency. Specifically, the epitaxial structure, semiconductor device, and semiconductor assembly of the present invention can be applied to products in fields such as lighting, medical, display, communication, sensing, power systems, etc., for example, lighting fixtures, monitors, mobile phones, tablet computers, in-vehicle instrument panels, televisions, computers, wearable devices (such as wristwatches, bracelets, necklaces, etc.), traffic signal lights, outdoor displays, medical equipment, etc.

[0050] As described above, the preferred embodiments of the present invention have been described. However, the present invention is not limited to these embodiments, and any modifications to the present invention that do not depart from the spirit of the present invention are still within the technical scope of the present invention.

Explanation of Reference Numerals

[0051] 10, 10’, 20, 40, 40’: Semiconductor devices 22, 42: Mounting substrates 24, 44: Adhesive layers 200, 400, 600, 800: Semiconductor assemblies 61: Package substrate 62: Through-hole 63: Carrier 63a: First part 63b: Second part 65: Bonding wire 66: Contact structure 66a: First contact pad 66b: Second contact pad 68: Package layer 80: Carrier 82: Pixel unit 84: First semiconductor device 86: Second semiconductor device 88: Third semiconductor device 100: Base 102: Epitaxial structure 104: First semiconductor structure 106: Second semiconductor structure 108: Active region 108a: Barrier layer 108b: Well layer 108c: Semiconductor stack layer 110: First electrode 110a: Electrode pad 110b: Extended electrode 110b1: First extension 110b2: Second extension 112: Second electrode 114: First confinement layer 116: Second confinement layer 118: First coating layer 119: Second coating layer 130: First window layer 140a: First contact structure 140b: Second contact structure 160: Dielectric material layer 120: Insulating layer 122: Conductive layer 124: Reflective layer 126: Pore 128: Bonding structure R: Region L 0 : Length W 0 : Width C1, C2, D1, D2, E0, E1, E2, E3, E4, E5, F1, F2, G1, G2, Q1, Q2, Q3: Curve X-X’, Y-Y’: Line

Claims

1. A semiconductor device, a first semiconductor structure including a first confinement layer and a first dopant; a second semiconductor structure overlying the first semiconductor structure, the second semiconductor structure including a second confinement layer and a second dopant different from the first dopant; and an active region located between the first semiconductor structure and the second semiconductor structure and including a plurality of pairs of semiconductor stack layers, each of the semiconductor stack layers including a barrier layer and a well layer, and the active region including the first dopant; a first thickness and a first aluminum content (percentage), the well layer having a second thickness and a second aluminum content (percentage), the first aluminum content (percentage) being greater than the second aluminum content (percentage), the first and second confinement layers are adjacent to but in direct contact with the active region, the first confinement layer having a third thickness and a third aluminum content (percentage), the second confinement layer having a fourth thickness and a fourth aluminum content (percentage), the third aluminum content (percentage) and the fourth aluminum content (percentage) being greater than the second aluminum content (percentage), the third thickness being greater than or equal to the second thickness, and the fourth thickness being greater than or equal to the second thickness.

2. 2. The semiconductor device of claim 1 , A semiconductor device, wherein the number of pairs of semiconductor stack layers in the plurality of pairs is 2 or more and 20 or less.

3. 2. The semiconductor device of claim 1 , The second thickness is in the range of 10 angstroms to 200 angstroms.

4. 2. The semiconductor device of claim 1 , The second aluminum content (percentage) is in the range of 0% to 15%.

5. 2. The semiconductor device of claim 1 , The first confinement layer and the second confinement layer comprise a ternary compound semiconductor.

6. 4. The semiconductor device according to claim 3, A semiconductor device, wherein a ratio of the fourth thickness to the first thickness or the second thickness is in the range of 1.5:1 to 10:

1.

7. 2. The semiconductor device of claim 1 , A semiconductor device, wherein a ratio of the third thickness to the first thickness or the second thickness is in the range of 1.5:1 to 10:

1.

8. 2. The semiconductor device of claim 1 , In the top view, the area of ​​the upper surface of the semiconductor element is 10,000 μm ２ is as follows: The semiconductor device is J_E ｍａｘ A / cm ２ Maximum external quantum efficiency E at a current density of ｍａｘ %, and 0.1×(J_E ｍａｘ ) A / cm ２ Under a current density of E ｍａｘ % of the external quantum efficiency of the semiconductor device is 80% or more.

9. 2. The semiconductor device of claim 1 , the semiconductor element has a length and a width, the length being less than 200 μm and the width being less than 200 μm, the semiconductor element having a first light output value under a first temperature and a second light output value under a second temperature lower than the first temperature, a difference between the first temperature and the second temperature being 30° C. or more, and a ratio of the first light output value to the second light output value being 30% or more.

10. A semiconductor assembly comprising a semiconductor element according to any one of claims 1 to 9.

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