Driving device

Abstract

To precisely communicate between circuits in a driving device for power semiconductor.SOLUTION: There is provided a driving device for the power semiconductor, and the driving device comprises a first circuit, a second circuit, a status signal generation part which generates a first status signal representing the status of the first circuit with a multi-bit digital value, and a communication control part which controls an output period in which the first circuit outputs the first status signal based upon a load status signal indicating ON-OFF transition timing of the power semiconductor.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present invention relates to a drive device.

Background Art

[0002] Conventionally, in a drive device that drives a target device such as a power semiconductor, a configuration for outputting the state of the drive device such as temperature is known (see, for example, Patent Documents 1 to 3). Patent Document 1 Japanese Patent Application Laid-Open No. 2014-93903 Patent Document 2 Japanese Patent Application Laid-Open No. 2009-258016 Patent Document 3 US Patent No. 5210846

Summary of the Invention

Problems to be Solved by the Invention

[0003] It is preferable to perform communication between circuits in the drive device with high accuracy.

Means for Solving the Problems

[0004] In order to solve the above problems, in a first aspect of the present invention, a drive device for a power semiconductor is provided. The drive device may include a first circuit. Any of the drive devices may include a second circuit. Any of the drive devices may include a state signal generation unit that generates a first state signal indicating the state of the first circuit as a digital value of a plurality of bits. Any of the drive devices may include a communication control unit that controls an output period during which the first circuit outputs the first state signal based on a load state signal indicating the on / off transition timing of the power semiconductor.

[0005] In any of the drive devices, the communication control unit may permit the output of the first state signal after a predetermined stop period has elapsed from the timing when the on / off of the power semiconductor has transitioned.

[0006] In any of the above drive devices, the first circuit may output the first state signal in response to a clock signal input from the second circuit. In any of the above drive devices, the communication control unit may control an input period during which the clock signal is input from the second circuit to the first circuit based on the load state signal.

[0007] In any of the above drive devices, the communication control unit may control the stop period according to the characteristics of the power semiconductor.

[0008] In any of the above drive devices, the communication control unit may control the stop period according to the magnitude of the power supply voltage applied to the power semiconductor.

[0009] In any of the above drive devices, the communication control unit may control the stop period according to the capacitance of the load connected to the power semiconductor.

[0010] In any of the above drive devices, the second circuit may control the period of the clock signal according to the length of the output period.

[0011] In any of the above drive devices, the first circuit may be a low-side circuit operating at a first reference voltage. In any of the above drive devices, the second circuit may be a high-side circuit operating at a second reference voltage higher than the first reference voltage. Any of the above drive devices may include a transmission unit that converts the reference voltage of the first state signal according to the first reference voltage and transmits the first state signal with the converted reference voltage to the low-side circuit.

[0012] In any of the above drive devices, the transmission unit may have a capacitor provided between the high-side circuit and the low-side circuit.

[0013] In a second aspect of the present invention, a driving device for a power semiconductor is provided. The driving device may include a low-side circuit operating at a first reference voltage. Any of the driving devices may include a high-side circuit operating at a second reference voltage higher than the first reference voltage. Any of the driving devices may include a state signal generation unit that generates a high-side state signal indicating the state of the high-side circuit as a digital value of a plurality of bits. Any of the driving devices may include a transmission unit that converts the reference voltage of the high-side state signal according to the first reference voltage and transmits the high-side state signal with the converted reference voltage to the low-side circuit.

[0014] In any of the driving devices, the low-side circuit may have a transmission unit that transmits the high-side state signal to the outside.

[0015] In any of the driving devices, the low-side circuit may generate a low-side state signal indicating the state of the low-side circuit as a digital value. In any of the driving devices, the transmission unit may output the high-side state signal and the low-side state signal from a common terminal.

[0016] In any of the driving devices, the transmission unit may include an insulating element that transmits the high-side state signal in a state where the high-side circuit and the low-side circuit are electrically insulated.

[0017] In any of the driving devices, the transmission unit may have a level shift circuit that converts the signal level of the high-side state signal according to the first reference voltage.

[0018] In any of the driving devices, the high-side state signal may have a plurality of bit periods corresponding to the plurality of bits of the digital value, and the signal level in each bit period may indicate a value corresponding to the value of each bit of the digital value. Note that the bit period is the period occupied by 1-bit information in a digital signal.

[0019] In any of the above-described drive devices, the state signal generation unit may include a pulse generation unit that generates a start pulse indicating the start timing of each of the bit periods and an end pulse indicating the end timing of each of the bit periods. In any of the above-described drive devices, the state signal generation unit may include a signal synthesis unit that generates the high-side state signal including the start pulse and the end pulse and having a signal level during a period between the start pulse and the end pulse set to a level corresponding to the digital value.

[0020] In any of the above-described drive devices, polarities of the start pulse and the end pulse may be inverted.

[0021] In any of the above-described drive devices, the low-side circuit may extract the start timing or the end timing of each of the bit periods in the high-side state signal received from the transmission unit and detect a signal level of the high-side state signal at a detection timing preset based on the start timing or the end timing.

[0022] Any of the above-described drive devices may include a communication control unit that controls a period during which the high-side circuit outputs the high-side state signal based on a load state signal indicating an on / off transition timing of the power semiconductor.

[0023] In any of the above-described drive devices, the communication control unit may permit output of the high-side state signal after a predetermined period has elapsed from a timing at which the on / off of the power semiconductor has transitioned.

[0024] In any of the above-described drive devices, the high-side circuit may output the high-side state signal in response to a clock signal input from the low-side circuit. In any of the above-described drive devices, the communication control unit may control a period during which the clock signal is input from the low-side circuit to the high-side circuit based on the load state signal.

[0025] The above summary of the invention does not enumerate all the features of the present invention. Also, sub-combinations of these groups of features can also be inventions.

Brief Description of the Drawings

[0026]

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Embodiments for Carrying Out the Invention

[0027] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention. In this specification and the drawings, elements having substantially the same function and configuration are denoted by the same reference numerals to omit redundant description, and elements not directly related to the present invention are omitted from the illustration. Also, in one drawing, elements having the same function and configuration may be representatively labeled, and other elements may be omitted from labeling.

[0028] In this specification, when referred to as "identical" or "equal", it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.

[0029] FIG. 1 is a diagram showing an example of a power supply device 300 according to an embodiment of the present invention. The power supply device 300 supplies power to a load. The load is, for example, a circuit provided in a vehicle or an industrial robot, but is not limited thereto. The power supply device 300 includes a driving device 100 and an output device 200.

[0030] The output device 200 supplies power to the load. The output device 200 includes a power semiconductor 202 and a power semiconductor 204. The power semiconductor 202 and the power semiconductor 204 may be, for example, IGBTs or MOSFETs, or may be other devices. In this example, the power semiconductor 202 and the power semiconductor 204 are provided in series between a high-voltage wiring VDD and a ground potential GND.

[0031] In this example, the power semiconductor 202 is a high-side MOSFET whose drain terminal is connected to the high-voltage wiring VDD and whose source terminal is connected to the load. The power semiconductor 204 is a low-side MOSFET whose drain terminal is connected to the load and whose source terminal is connected to the ground potential GND. The output device 200 may have a plurality of sets of the power semiconductor 202 and the power semiconductor 204. For example, the output device 200 may be a three-phase circuit having three sets of the power semiconductor 202 and the power semiconductor 204.

[0032] The driving device 100 drives the power semiconductor 202 and the power semiconductor 204. In this example, the driving device 100 controls the switching operations of the power semiconductor 202 and the power semiconductor 204. The driving device 100 includes a high-side circuit section 11, a transmission section 30, and a low-side circuit 50.

[0033] The high-side circuit section 11 controls the switching operation of the power semiconductor 202 based on the input control signal. A second power supply voltage VH_U and a second reference voltage VS_U are applied to the high-side circuit section 11. The high-side circuit section 11 operates based on the second power supply voltage VH_U and the second reference voltage VS_U. The second reference voltage VS_U is a voltage higher than the first reference voltage GND of the low-side circuit 50. The second reference voltage VS_U in this example is the voltage of the source terminal of the power semiconductor 202.

[0034] The control signal input to the high-side circuit section 11 is a signal that controls the timing of switching the power semiconductor 202. For example, the control signal is a signal that becomes the H level during the period when the power semiconductor 202 should be in the on state and becomes the L level during the period when the power semiconductor 202 should be in the off state.

[0035] The high-side circuit section 11 applies a drive signal having a waveform corresponding to the control signal to the power semiconductor 202. The drive signal may be input to the gate terminal of the power semiconductor 202. The drive signal may have the same logical value pattern as the control signal. The high-side circuit section 11 may output a drive signal at a level corresponding to the second power supply voltage VH_U during the period when the power semiconductor 202 should be turned on, and may output a drive signal at a level corresponding to the second reference voltage VS_U during the period when the power semiconductor 202 should be turned off.

[0036] The high-side circuit section 11 has one or more high-side circuits 10 corresponding to the number of power semiconductors 202 to be controlled. The high-side circuit section 11 in this example has three high-side circuits 10-U, 10-V, and 10-W. Each high-side circuit 10 outputs a drive signal for the corresponding power semiconductor 202. Each high-side circuit 10 may be connected to a respective power supply. Respective power supply voltages VH_U, VH_V, and VH_W are applied to each high-side circuit 10. Respective second reference voltages VS_U, VS_V, and VS_W are applied to each high-side circuit 10.

[0037] The low-side circuit 50 controls the switching operation of the power semiconductor 204 based on the input control signal. The first power supply voltage VH_L and the first reference voltage GND are applied to the low-side circuit 50. The low-side circuit 50 operates based on the first power supply voltage VH_L and the first reference voltage GND. The first power supply voltage VH_L is lower than the second power supply voltage VH_U. The first reference voltage GND is lower than the second reference voltage VS. The first reference voltage GND may be the ground voltage.

[0038] The control signal input to the low-side circuit 50 is a signal that controls the timing of switching the power semiconductor 204. For example, the control signal is a signal that becomes the H level during the period when the power semiconductor 204 should be in the on state and becomes the L level during the period when the power semiconductor 204 should be in the off state.

[0039] The low-side circuit 50 applies a drive signal having a waveform corresponding to the control signal to the power semiconductor 204. The drive signal may be input to the gate terminal of the power semiconductor 204. The drive signal may have the same logical value pattern as the control signal. The low-side circuit 50 may output a drive signal at a level corresponding to the first power supply voltage VH_L during the period when the power semiconductor 204 should be turned on, and may output a drive signal at a level corresponding to the first reference voltage GND during the period when the power semiconductor 204 should be turned off. The low-side circuit 50 outputs one or more drive signals corresponding to the number of power semiconductors 204 to be controlled.

[0040] The low-side circuit 50 outputs a status signal SCL indicating the status of the drive device 100. The status signal SCL is a digital signal. The status signal SCL may be output to a control device that controls the drive device 100. The control device may control the drive device 100 based on the status signal SCL. For example, the control device may stop the operation of the drive device 100 when an abnormality occurs in the drive device 100.

[0041] The status signal SCL includes information indicating the status of the high-side circuit 10. The status signal SCL may further include information indicating the status of the low-side circuit 50. The low-side circuit 50 in this example outputs a status signal SCL including both the status of the high-side circuit 10 and the status of the low-side circuit 50. The status signal SCL may include information indicating at least any one of the value of the temperature at a predetermined location in each circuit, the current flowing through the predetermined location, and the voltage applied to the predetermined location. The status signal SCL may also include information indicating whether at least any one of the temperature, current, and voltage of each circuit is within a predetermined allowable range.

[0042] Each high-side circuit 10 generates a high-side status signal HSD_U indicating the status of the high-side circuit 10 with a multi-bit digital value. The high-side status signal HSD_U in this example is a signal that becomes a voltage corresponding to the second power supply voltage VH_U during the period of H logic and becomes a voltage corresponding to the second reference voltage VS during the period of L logic. In this specification, the logical value 1 may be referred to as H logic and the logical value 0 may be referred to as L logic.

[0043] In the example of FIG. 1, the high-side circuits 10-U, 10-V, 10-W generate high-side status signals HSD_UU, HSD_UV, HSD_UW. Each high-side status signal HSD_U includes information indicating at least any one of the temperature, current, and voltage in the corresponding high-side circuit 10, and whether these values are within the allowable range.

[0044] The transmission unit 30 generates a high-side status signal HSD_L in which the second reference voltage VS of the high-side status signal HSD_U is converted to the first reference voltage GND. The transmission unit 30 in this example converts the high-side status signals HSD_UU, HSD_UV, HSD_UW into high-side status signals HSD_LU, HSD_LV, HSD_LW. The high-side status signals HSD_LU, HSD_LV, HSD_LW may be signals having the same logical value pattern as the high-side status signals HSD_UU, HSD_UV, HSD_UW and having the same bit period. The bit period is the period occupied by 1-bit information in the signal.

[0045] The high-side state signal HSD_L in this example is a signal that becomes a voltage corresponding to the first reference voltage VS during the period of L logic. The high-side state signal HSD_L may become a voltage corresponding to the first power supply voltage VH_L during the period of H logic, or may become another voltage.

[0046] The transmission unit 30 transmits the high-side state signal HSD_L to the low-side circuit 50. The low-side circuit 50 outputs a state signal SCL that includes the information included in the high-side state signal HSD_L.

[0047] The second reference voltage VS in the high-side circuit 10 changes according to the operating states of the power semiconductor 202 and the power semiconductor 204. Therefore, the reference voltage of the high-side state signal HSD_U also fluctuates. According to this example, the transmission unit 30 converts the reference voltage of the high-side state signal HSD into a reference voltage suitable for the processing of the low-side circuit 50. Therefore, the low-side circuit 50 can easily process the high-side state signal HSD. In addition, the low-side circuit 50 can generate a state signal SCL that includes both the state of the low-side circuit 50 and the state of the high-side circuit 10. Therefore, the state of the high-side circuit 10 can be notified to the outside with a simple configuration.

[0048] The transmission unit 30 in this example has one or more insulating elements 32 corresponding to one or more high-side circuits 10. The insulating element 32 converts and transmits the reference voltage of the high-side state signal HSD while electrically insulating the high-side circuit 10 and the low-side circuit 50.

[0049] FIG. 2 is a diagram showing an example of the insulating element 32. The insulating element 32 in this example is a photocoupler having a light-emitting element 27 and a light-receiving element 29. The light-emitting element 27 emits light according to the high-side state signal HSD_U. The light-emitting element 27 is, for example, a light-emitting diode. The second reference voltage VS is applied to the cathode terminal of the light-emitting element 27. The high-side state signal HSD_U is applied to the anode terminal of the light-emitting element 27.

[0050] The light-receiving element 29 receives the light emission signal from the light-emitting element 27 and generates a high-side state signal HSD_L. The light-receiving element 29 is, for example, a phototransistor. A first reference voltage GND is applied to the emitter terminal of the light-receiving element 29. The voltage of the collector terminal of the light-receiving element 29 is output as the high-side state signal HSD_L. The light-receiving element 29 may generate a high-side state signal HSD_L that becomes a predetermined high voltage during a period in which light of a predetermined intensity or more is received and becomes the first reference voltage GND during a period in which light of a predetermined intensity or more is not received. The high voltage of the high-side state signal HSD_L may be the same as or different from the first power supply voltage VH_L.

[0051] Figure 3 is a block diagram showing a configuration example of the high-side circuit 10. The high-side circuit 10 in this example includes a driver circuit 12, a voltage detection circuit 14, a current detection circuit 16, a temperature detection circuit 18, and a state signal generation unit 20. The driver circuit 12 outputs a drive signal for controlling the power semiconductor 202 based on a control signal input from an external control device or the like.

[0052] The voltage detection circuit 14 detects the voltage at a predetermined location in the high-side circuit 10. For example, the voltage detection circuit 14 may detect the power supply voltage VH_U at a location where the power supply voltage VH_U is applied. The voltage detection circuit 14 may determine whether the difference between the detected voltage and a reference value is within an allowable range. The voltage detection circuit 14 may notify the driver circuit 12 of the determination result. The driver circuit 12 may control the power semiconductor 202 to be in an off state when the difference between the voltage detected by the voltage detection circuit 14 and the reference value is not within the allowable range.

[0053] The current detection circuit 16 detects the current flowing through a predetermined location in the high-side circuit 10. For example, the current detection circuit 16 may detect the current flowing from the driver circuit 12 to the power semiconductor 202. The current detection circuit 16 may determine whether the difference between the detected current and the reference value is within the allowable range. The current detection circuit 16 may notify the driver circuit 12 of the determination result. When the difference between the current detected by the current detection circuit 16 and the reference value is not within the allowable range, the driver circuit 12 may control the power semiconductor 202 to be in the off state.

[0054] The temperature detection circuit 18 detects the temperature of a predetermined location in the high-side circuit 10. For example, the temperature detection circuit 18 may detect the temperature of the driver circuit 12. The temperature detection circuit 18 may determine whether the difference between the detected temperature and the reference value is within the allowable range. The temperature detection circuit 18 may notify the driver circuit 12 of the determination result. When the difference between the temperature detected by the temperature detection circuit 18 and the reference value is not within the allowable range, the driver circuit 12 may control the power semiconductor 202 to be in the off state.

[0055] The voltage detection circuit 14, the current detection circuit 16, and the temperature detection circuit 18 may detect the voltage, current, and temperature of the output device 200. The voltage detection circuit 14, the current detection circuit 16, and the temperature detection circuit 18 may detect the voltage, current, and temperature of the power semiconductor 202.

[0056] The state signal generation unit 20 generates a high-side state signal HSD_U indicating the state of the high-side circuit 10 based on at least one of the voltage detected by the voltage detection circuit 14, the current detected by the current detection circuit 16, and the temperature detected by the temperature detection circuit 18. The high-side state signal HSD_U may include at least one value (V, A, °C) of voltage, current, and temperature, and may also include the determination result in at least one of the voltage detection circuit 14, the current detection circuit 16, and the temperature detection circuit 18. The high-side state signal HSD_U may also include information indicating other states of the high-side circuit 10. The high-side state signal HSD_U may include information regarding the frequency of the voltage or current in the high-side circuit 10, may include information regarding the cumulative operation time, and may also include other information. The high-side state signal HSD_U may include information indicating the state of the high-side circuit 10 at the current time, and may also include information indicating the state of the high-side circuit 10 in the past.

[0057] FIG. 4 is a block diagram showing a configuration example of the low-side circuit 50. The low-side circuit 50 in this example includes a driver circuit 52, a voltage detection circuit 54, a current detection circuit 56, a temperature detection circuit 58, a transmission unit 60, and an input circuit 62. The driver circuit 52 outputs a drive signal for controlling the power semiconductor 204 based on a control signal input from an external control device or the like.

[0058] The voltage detection circuit 54 detects the voltage at a predetermined location in the low-side circuit 50. For example, the voltage detection circuit 54 may detect the power supply voltage VH_L at a location where the power supply voltage VH_L is applied. The voltage detection circuit 54 may determine whether the difference between the detected voltage and a reference value is within an allowable range. The voltage detection circuit 54 may notify the driver circuit 52 of the determination result. When the difference between the voltage detected by the voltage detection circuit 54 and the reference value is not within the allowable range, the driver circuit 52 may control the power semiconductor 204 to be in an off state.

[0059] The current detection circuit 56 detects the current flowing through a predetermined location in the low-side circuit 50. For example, the current detection circuit 56 may detect the current flowing from the driver circuit 52 to the power semiconductor 204. The current detection circuit 56 may determine whether the difference between the detected current and a reference value is within an allowable range. The current detection circuit 56 may notify the driver circuit 52 of the determination result. When the difference between the current detected by the current detection circuit 56 and the reference value is not within the allowable range, the driver circuit 52 may control the power semiconductor 204 to be in an off state.

[0060] The temperature detection circuit 58 detects the temperature of a predetermined location in the low-side circuit 50. For example, the temperature detection circuit 58 may detect the temperature of the driver circuit 52. The temperature detection circuit 58 may determine whether the difference between the detected temperature and a reference value is within an allowable range. The temperature detection circuit 58 may notify the driver circuit 52 of the determination result. When the difference between the temperature detected by the temperature detection circuit 58 and the reference value is not within the allowable range, the driver circuit 52 may control the power semiconductor 204 to be in an off state.

[0061] The voltage detection circuit 54, the current detection circuit 56, and the temperature detection circuit 58 may detect the voltage, current, and temperature of the output device 200. The voltage detection circuit 54, the current detection circuit 56, and the temperature detection circuit 58 may detect the voltage, current, and temperature of the power semiconductor 204.

[0062] Based on at least one of the voltage detected by the voltage detection circuit 54, the current detected by the current detection circuit 56, and the temperature detected by the temperature detection circuit 58, the transmission unit 60 generates a low-side state signal that indicates the state of the low-side circuit 50 in digital values. The low-side state signal may include information similar to the high-side state signal regarding the low-side circuit 50.

[0063] One or more high-side state signals HSD_L are input to the input circuit 62 from the transmission unit 30. In the input circuit 62 of this example, high-side state signals HSD_LU, HSD_LV, and HSD_LW are input. The input circuit 62 outputs digital signals DOUT_U, DOUT_V, and DOUT_W indicating the information included in the high-side state signals HSD_LU, HSD_LV, and HSD_LW as digital values of a plurality of bits.

[0064] The transmission unit 60 transmits a state signal SCL including the digital signal DOUT of the high-side state signal HSD_L to an external device. In the transmission unit 60 of this example, the digital signal DOUT of the high-side state signal and the digital signal of the low-side state signal are output from a common terminal 61. The state signals SCL and SDA may include information on both the digital signal DOUT of the high-side state signal and the digital signal of the low-side state signal. The state signal SCL may include the digital signal DOUT of the high-side state signal and the digital signal of the low-side state signal in a time-division manner. The transmission unit 60 may output the state signal SCL to a display device that displays the state of the drive device 100, and may also output the state signal SCL to a recording device that records the state of the drive device 100.

[0065] FIG. 5 is a block diagram showing a configuration example of the state signal generation unit 20 and the input circuit 62. The state signal generation unit 20 of this example includes a digital signal generation unit 26, a selector circuit 21, a signal synthesis unit 22, an output circuit 23, a pulse generation unit 24, and an oscillation circuit 25. The input circuit 62 of this example includes an input unit 63, an edge detection circuit 64, a latch circuit 65, a data holding circuit 66, a timer circuit 67, and a control circuit 68.

[0066] FIG. 6 is a timing chart for explaining an operation example of the state signal generation unit 20 shown in FIG. 5. The oscillation circuit 25 generates a clock signal T having a predetermined period. Each component of the state signal generation unit 20 may operate with the clock signal T input thereto and at the period of the clock signal T. Further, an enable signal DEN indicating the start of the operation may be input to the state signal generation unit 20. In this example, the operation of the state signal generation unit 20 is started at the timing when the enable signal DEN transitions from the L level to the H level.

[0067] The digital signal generation unit 26 receives detection results from one or more state detection circuits such as the voltage detection circuit 14, the current detection circuit 16, and the temperature detection circuit 18. The digital signal generation unit 26 generates a digital signal D indicating the input detection results. The digital signal in this example is an 8-bit signal, but the number of bits of the digital signal is not limited to this.

[0068] The digital signal D may include at least one value (V, A, °C) of the voltage, current, and temperature of the high-side circuit 10, and may also include a determination result in at least one of the voltage detection circuit 14, the current detection circuit 16, and the temperature detection circuit 18. The digital signal generation unit 26 in the example of FIG. 6 generates a digital signal D having a logical value pattern of 0110_0101. The logical value pattern is information indicating the state of the high-side circuit 10. In FIG. 6, an example in which the digital signal D has the logical value pattern is described.

[0069] The pulse generation unit 24 generates a count signal DS whose value increases every predetermined period. The pulse generation unit 24 in this example counts the number of bit periods with four periods of the clock signal T as one bit period and generates a count signal DS indicating the count value. The count signal DS is a signal whose value increases by 1 from an initial value (for example, 0) and returns to the initial value (for example, 0) when a predetermined upper limit value (for example, 9) is reached.

[0070] The number of count values from the initial value to the upper limit value of the count signal DS is greater than the number of bits of the digital signal D. Since the digital signal D in this example is 8 bits, the number of count values from the initial value to the upper limit value of the count signal DS is 9 or more. The number of count values of the count signal DS in the example of FIG. 6 is 10 integers from 0 to 9.

[0071] The selector circuit 21 outputs a binary digital signal S based on the digital signal D and the count signal DS. The digital signal S is a binary digital signal having a waveform corresponding to the logical value pattern of the digital signal D. The digital signal S in this example is a signal whose signal level in each bit period transitions to either an H level corresponding to the logical value 1 or an L level corresponding to the logical value 0. The bit period is the period occupied by 1-bit information in the digital signal S. In the example of FIG. 6, the bit period is 4 times the period of the clock signal T.

[0072] The selector circuit 21 in this example reads the logical value of the bit corresponding to the count value of the count signal DS among each bit of the digital signal D, and generates the digital signal S according to the read logical value. For example, the initial value of the count value corresponds to the most significant bit of the digital signal D, and the upper limit value of the count value corresponds to the least significant bit of the digital signal D.

[0073] In the example of FIG. 6, since the logical value of the most significant bit of the digital signal D is 0, the signal level of the digital signal S is the L level during the bit period when the count value of the count signal DS indicates the initial value 0. Similarly, the logical values of the digital signal D corresponding to the count values 1, 2, ··· 7 of the count signal DS are 1, 1, 0, 0, 1, 0, 1. Therefore, the signal level of each bit period of the digital signal S sequentially transitions to H, H, L, L, H, L, H.

[0074] The periods when the count value of the count signal DS is 8 and 9 are blank periods. After the blank period has elapsed, processing for the next digital value of the digital signal D (1011_1101 in FIG. 6) starts. In this example, the signal level of the digital signal S during the blank period is the L level.

[0075] The pulse generation unit 24 generates a start pulse T1 indicating the start timing of each bit period and an end pulse T2 indicating the end timing of each bit period. The start pulse T1 in this example is a pulse train arranged at the start timing of each bit period. As an example, the timing of the leading edge of the pulse of the start pulse T1 coincides with the start timing of the bit period. The end pulse T2 in this example is a pulse train arranged at the end timing of each bit period. As an example, the timing of the trailing edge of the pulse of the end pulse T2 coincides with the end timing of the bit period. The pulse width of each pulse of the start pulse T1 and the end pulse T2 is smaller than half of one bit period. The pulse width in this example is 1 / 4 of one bit period (that is, one cycle of the clock signal T).

[0076] The pulse generation unit 24 may output a blank signal BK. The blank signal BK in this example is a signal that becomes high level during the blank period and low level in other periods.

[0077] The state signal HS_STATE in FIG. 6 is a signal indicating the operating state of the state signal generation unit 20. The state HIDLE indicates an idle state where the enable signal DEN is at low level. The state HSERPAR indicates a state where the enable signal DEN is at high level and processing on the digital signal D is being performed. Note that in the state HSERPAR, the blank signal BK is at low level. The state HBK indicates a blank state where the enable signal DEN is at high level and the blank signal BK is at high level. When the enable signal DEN transitions to high level in the standby state, processing on the next digital value of the digital signal D starts.

[0078] The signal synthesizing unit 22 generates a high-side state signal SS based on the digital signal S. The high-side state signal SS has a plurality of bit periods corresponding to a plurality of bits of the digital value of the digital signal D. In the example of FIG. 6, each bit period of the high-side state signal SS is indicated by DATA0 or DATA1.

[0079] The signal level in each bit period of the high-side state signal SS indicates a value corresponding to each bit of the digital value of the digital signal D. In the example of FIG. 6, DATA0 is a bit period with a logical value of 0, and DATA1 is a bit period with a logical value of 1.

[0080] The signal synthesizing unit 22 in this example generates a high-side state signal SS that includes a start pulse T1 and an end pulse T2, and the signal level during the period between the start pulse T1 and the end pulse T2 is set to a level corresponding to the digital value of the digital signal D. In this example, the signal level during the period between the start pulse T1 and the end pulse T2 is the same as the signal level of the digital signal S. The signal synthesizing unit 22 may generate the high-side state signal SS by inserting the start pulse T1 and the end pulse T2 into the signal waveform of the digital signal S. The high-side state signal SS is a signal having the same waveform pattern as the high-side state signal HSD_U described above. According to this example, the start timing and the end timing of each bit period can be specified. Therefore, in a subsequent circuit such as the input circuit 62, the digital value of the high-side state signal can be accurately detected.

[0081] The polarities of the start pulse T1 and the end pulse T2 may be inverted. The polarity of a pulse is determined by whether the leading edge of the two edges is a rising edge or a falling edge. In the example of FIG. 6, the start pulse T1 is a pulse whose leading edge is a falling edge. The end pulse T2 is a pulse whose leading edge is a rising edge. The signal synthesizing unit 22 arranges the start pulse T1 and the end pulse T2 so that the trailing edge of the end pulse T2 in the previous bit period and the leading edge of the start pulse T1 in the current bit period are common edges. By making the polarities of the start pulse T1 and the end pulse T2 different, an edge can always be arranged at the boundary timing of each bit period. In the example of FIG. 6, in the high-side state signal SS, a falling edge is always arranged at the boundary timing of each bit period. Also, in the high-side state signal SS, no falling edge is arranged except at the boundary timing of each bit period.

[0082] The high-side state signal SS in this example transitions to a signal level corresponding to the digital value after the pulse time of the start pulse T1 (for example, one cycle of the clock signal T) has elapsed from the falling edge. During the period of DATA0, the signal level of the high-side state signal SS is maintained at the L level even after the pulse time of the start pulse T1 has elapsed. However, at the timing of the leading edge of the end pulse T2, the signal level of the high-side state signal SS transitions to the H level. Also, during the period of DATA1, when the pulse time of the start pulse T1 has elapsed, the signal level of the high-side state signal SS transitions to the H level. The signal level of the high-side state signal SS is maintained at the H level until the start timing of the next bit period.

[0083] In this example, during the blank period when the blank signal BK is at the H level, the high-side state signal SS is maintained at the H level. That is, the signal level of the high-side state signal SS during the blank period is the same as the signal level immediately before the leading edge of the start pulse T1. Thereby, in the processing of the next digital value of the digital signal D, the leading edge of the start pulse T1 can be arranged at the start timing of the first bit period.

[0084] The output circuit 23 outputs a high-side state signal HSD_U based on the high-side state signal SS. The high-side state signal HSD_U has the same waveform pattern as the high-side state signal SS. The high-side state signal HSD_U may have a predetermined delay time with respect to the high-side state signal SS. The output circuit 23 in this example latches the value of the high-side state signal SS at the period of the clock signal T and sequentially outputs it as the high-side state signal HSD_U. In this case, the high-side state signal HSD_U is delayed by one period of the clock signal T with respect to the high-side state signal SS.

[0085] FIG. 7 is a timing chart for explaining an operation example of the input circuit 62 shown in FIG. 5. The input circuit 62 may operate at the same period as the clock signal T shown in FIG. 6, or may operate at other periods.

[0086] An enable signal LDEN indicating the start of operation may be input to the input circuit 62. In this example, signal processing for the high-side state signal HSD_L is started at the timing when the enable signal LDEN transitions from the L level to the H level.

[0087] The input section 63 generates an input signal DI based on the high-side state signal HSD_U. The input signal DI may have the same waveform pattern as the high-side state signal HSD_U. The input section 63 may generate the input signal DI by sampling the high-side state signal HSD_U at a predetermined period. That is, the input signal DI is a signal equivalent to the high-side state signal HSD_U. In this specification, the input signal DI may be treated as the high-side state signal HSD_U in some cases.

[0088] The input signal DI may be a binary digital signal with the first reference voltage GND as the L level and the first power supply voltage VH_L as the H level. Similar to the high-side state signal HSD_U shown in FIG. 6, the input signal DI has a plurality of bit periods DATA0, DATA1. Also, each bit period of the input signal DI includes a start pulse T1 and an end pulse T2, similar to the high-side state signal HSD_U.

[0089] The edge detection circuit 64 detects an edge arranged at the boundary of each bit period of the input signal DI. Thereby, the start timing or the end timing of each bit period in the high-side state signal HSD_L (input signal DI in this example) received from the transmission unit 30 can be extracted. The edge detection circuit 64 generates an edge detection signal DE corresponding to the detected edge. The edge detection signal DE is a signal indicating the start timing or the end timing of each bit period of the input signal DI.

[0090] The edge detection circuit 64 in this example detects a falling edge in the input signal DI. The edge detection circuit 64 generates an edge detection signal DE having an edge at the timing of the falling edge. The edge detection signal DE in this example has a rising edge at the timing of the falling edge in the input signal DI. The edge detection signal DE in this example maintains the H level for a holding period shorter than one bit period after the rising edge. After the holding period has elapsed, the edge detection signal DE transitions to the L level. And at the start timing of the next bit period, it transitions to the H level. Thereby, a rising edge can be arranged in the edge detection signal DE in synchronization with the start timing of each bit period in the input signal DI. In the blank period after each bit period, the signal level of the edge detection signal DE in this example is maintained at the L level.

[0091] The timer circuit 67 generates a strobe signal SLT based on the edge detection signal DE. The strobe signal SLT is a signal in which an edge is arranged with a predetermined delay time with respect to the rising edge of the edge detection signal DE. The strobe signal SLT in this example has a rising edge with a predetermined delay time with respect to the rising edge of the edge detection signal DE. The strobe signal SLT has a pulse that maintains the H level for a predetermined pulse width from the rising edge. The pulse width is shorter than the bit period. The pulse width may be the same as the pulse width of the start pulse T1 or the end pulse T2.

[0092] The delay time is larger than the pulse width of the start pulse T1. Also, the delay time is shorter than the time from the start timing of the bit period to the front edge of the end pulse. That is, the rising edge of the strobe signal SLT in this example is arranged in a period indicating a signal level corresponding to the logical value in each bit period. The rising edge of the strobe signal SLT may be arranged at the center of each bit period.

[0093] The latch circuit 65 detects the signal level of the input signal DI at a detection timing set based on the start timing or the end timing of each bit period of the input signal DI. The latch circuit 65 in this example latches the signal level of the input signal DI at the timing of the rising edge of the strobe signal SLT. Thereby, the latch circuit 65 can detect the signal level corresponding to the logical value of each bit period of the input signal DI. The latch circuit 65 generates a multi-bit digital signal DL based on the signal level detected in each bit period. The number of bits of the digital signal DL is the same as the number of bits of the digital signal D (8 bits in this example).

[0094] The latch circuit 65 in this example sequentially inserts the logical value detected in response to the rising edge of the strobe signal SLT into the least significant bit of the digital signal DL. Before inserting the logical value into the least significant bit of the digital signal DL, the latch circuit 65 shifts the logical value of each bit of the digital signal DL by one bit toward the more significant bit side. By such processing, a digital signal DL corresponding to the logical value pattern of the input signal DI can be generated.

[0095] The control circuit 68 may generate a count signal DCNT that counts a predetermined edge in the edge detection signal DE. The count signal DCNT is a signal whose count value increases by 1 each time a bit period elapses. The initial value of the count signal DCNT in this example is 0.

[0096] The control circuit 68 outputs an output control signal PLT having a pulse at a timing when a predetermined time has elapsed after the count value of the count signal DCNT reaches the upper limit value. The upper limit value of the count value of the count signal DCNT corresponds to the number of bits of the digital signal DL. The upper limit value in this example is 7. The predetermined time may be measured by the timer circuit 67. The predetermined time may be longer than one bit period. Thereby, after the processing for the last bit of the digital signal DL is completed, a pulse of the output control signal PLT can be generated. The control circuit 68 may output a pulse of the output control signal PLT when the predetermined time has elapsed and the edge detection signal DE is at the L level.

[0097] The data holding circuit 66 captures the digital value of the digital signal DL in response to the pulse of the output control signal PLT. Thereby, the data holding circuit 66 can capture the digital signal DL after the logical values of all bits (8 bits in this example) of the digital value are inserted. The data holding circuit 66 holds the captured digital value of the digital signal DL in a register or the like. The data holding circuit 66 outputs the held digital value as a digital signal DOUT.

[0098] The control circuit 68 may set the count value of the count signal DCNT to the initial value at the timing of the pulse of the output control signal PLT. Thereby, the count signal DCNT with the initial value can be used for the processing of the next digital value.

[0099] The latch circuit 65 may set the logical value of each bit of the digital signal DL to the initial value (for example, 0) at the timing of the pulse of the output control signal PLT. Thereby, the digital signal DL with the initial value can be used for the processing of the next digital value.

[0100] The state signal LS_STATE in FIG. 7 is a signal indicating the operating state of the input circuit 62. The state LIDLE indicates an idle state where the enable signal LDEN is at the L level. The state LSERPAR indicates a state where the enable signal LDEN is at the H level and the processing for the high-side state signal HSD_L is being performed. The state LBK indicates a blank state where the enable signal LDEN is at the H level and the count signal DCNT is at the upper limit value.

[0101] FIG. 8 is a conceptual diagram of a state machine showing the state transition of the state signal generation unit 20. Each state HIDLE, HSERPAR, HBK in the state machine of FIG. 8 is the same as each state described in the state signal HS_STATE of FIG. 6.

[0102] The state signal generation unit 20 enters the standby state HIDLE while the enable signal DEN indicates 0. When the enable signal DEN transitions from 0 to 1, the state signal generation unit 20 transitions to the processing state HSERPAR. In the processing state HSERPAR, as described in FIG. 6, the state signal generation unit 20 performs processing on the digital signal D.

[0103] When the count value of the count signal DS becomes the value corresponding to the last bit of the digital signal D (in this example, DS = 7) and the end pulse T2 is generated, the processing up to the last bit of the digital signal D is completed. In this case, the state signal generation unit 20 transitions to the blank state HBK.

[0104] The blank state HBK continues until the count value of the count signal DS reaches the upper limit value (DS = 9 in this example) and the end pulse T2 is generated. When the enable signal DEN is at the L level (DEN = 0) at the timing when the blank state HBK ends, the state signal generation unit 20 transitions to the standby state HIDLE. When the enable signal DEN is at the H level (DEN = 1) at the timing when the blank state HBK ends, the state signal generation unit 20 transitions to the processing state HSERPAR and performs processing on the next digital value of the digital signal D.

[0105] FIG. 9 is a conceptual diagram of a state machine showing the state transition of the input circuit 62. Each state LIDLE, LSERPAR, LBK in the state machine of FIG. 9 is the same as each state described in the state signal LS_STATE of FIG. 7.

[0106] The input circuit 62 is in the standby state LIDLE while the enable signal LDEN indicates 0. When the enable signal LDEN transitions from 0 to 1, the input circuit 62 transitions to the processing state LSERPAR. In the processing state LSERPAR, as described in FIG. 7, the input circuit 62 performs processing on the high-side state signal HSD_U.

[0107] In the processing state LSERPAR, when the count value of the count signal DCNT reaches the value immediately before the upper limit value (DNCT = 6) and a falling edge occurs in the input signal DI, the input circuit 62 starts processing on the last bit of the input signal DI. After starting the processing on the last bit, the input circuit 62 transitions to the blank state HBK and maintains the count value of the count signal DCNT at the upper limit value.

[0108] The blank state HBK continues until a pulse of the output control signal PLT (PLT = 1) occurs. When a pulse of the output control signal PLT occurs, the input circuit 62 transitions to the idle state LIDLE. In the idle state LIDLE, when the enable signal DEN becomes high level (DEN = 1), the input circuit 62 processes the next digital value of the high-side state signal HSD_L.

[0109] FIG. 10 is a diagram showing another example of the transmission unit 30. The transmission unit 30 in this example has a level shift circuit 34 instead of the insulating element 32 described in FIG. 1 and the like. The configuration other than the transmission unit 30 is the same as any of the aspects described in this specification.

[0110] The level shift circuit 34 generates a high-side state signal HSD_L in which the signal level of the high-side state signal HSD_U is shifted according to the first reference voltage GND. The level shift circuit 34 in this example generates a high-side state signal HSD_L in which the second reference voltage VS of the high-side state signal HSD_U is converted to the first reference voltage GND. The level shift circuit 34 does not electrically insulate the state signal generation unit 20 and the input circuit 62.

[0111] FIG. 11 is a diagram showing a configuration example of the level shift circuit 34. The level shift circuit 34 in this example has a transistor 35, a resistor 36, and a diode 37. The transistor 35 is provided between a node to which the second power supply voltage VH_U is applied and the first reference voltage GND, and the high-side state signal HSD_U is input to the gate terminal. The transistor 35 in this example is a p-channel MOSFET. The transistor 35 turns off during the period when the high-side state signal HSD_U is at the high level and turns on during the period when it is at the low level.

[0112] The resistor 36 is provided between the node of the first reference voltage GND and the transistor 35. Also, the diode 37 is provided in parallel with the resistor 36 between the node of the first reference voltage GND and the transistor 35. The first reference voltage GND is applied to the anode terminal of the diode 37. The level shift circuit 34 in this example outputs the voltage of the cathode terminal of the diode 37 as the high-side state signal HSD_L.

[0113] During the period when the high-side state signal HSD_U is at the H level, the transistor 35 is in the off state. In this case, the diode 37 does not conduct in reverse, and the voltage of the anode terminal becomes a predetermined voltage. The first power supply voltage VH_L may be applied to the cathode terminal of the diode 37, or other voltages may be applied. The H level of the high-side state signal HSD_L may be the same as or different from the first power supply voltage VH_L.

[0114] During the period when the high-side state signal HSD_U is at the L level, the transistor 35 is in the on state. The second power supply voltage VH_U is applied to the cathode terminal of the diode 37. The diode 37 conducts in reverse, and the voltage of the cathode terminal becomes the first reference voltage GND. Thereby, the L level of the high-side state signal HSD_L becomes the first reference voltage GND. According to the level shift circuit 34 in this example, the high-side state signal HSD_U can be level-shifted to the high-side state signal HSD_L with a simple configuration.

[0115] FIG. 12 is a diagram showing another example of the driving device 100. The driving device 100 of the present invention includes a communication control unit 70. Other structures and functions are the same as those in any of the examples described in this specification. In the driving device 100 in this example, when the first state signal is output from the first circuit to the second circuit in the driving device 100, the first circuit controls the output period during which the first state signal can be output. The first state signal is a signal indicating the state of the first circuit by a digital value of a plurality of bits.

[0116] In the example of FIG. 12, the high-side circuit section 11 or each high-side circuit 10 is the first circuit, and the low-side circuit 50 is the second circuit. The high-side state signal HSD_U output by the high-side circuit 10 is an example of the first state signal. However, the first circuit and the second circuit are not limited to these. For example, the first circuit may be a sensor circuit that detects the temperature or current of the output device 200 or the like and outputs a first state signal according to the detection result. The second circuit may be a circuit that controls the drive device 100 or the output device 200 according to the detection result in the first circuit.

[0117] The communication control unit 70 controls the above-described output period based on a load state signal indicating the on / off transition timing of at least one of the power semiconductors 202 and 204. In this specification, the power semiconductors 202 and 204 may be collectively referred to as the output device 200.

[0118] The load state signal is, for example, a control signal input to the drive device 100, but is not limited thereto. Any signal indicating the transition timing of the output device 200 can be used as the load state signal. For example, the gate signal input to the gate terminal of the output device 200 may be used as the load state signal. In this example, the control signal may be referred to as DRVIN.

[0119] At the timing when the on / off state of the output device 200 transitions, the voltage and current at a predetermined node of the output device 200 change greatly. The voltage and current fluctuations in the output device 200 can affect signal transmission in the drive device 100. For example, when a common power supply voltage or reference voltage is applied to both the output device 200 and the drive device 100, the power supply voltage or reference voltage in the drive device 100 may change due to the voltage and current fluctuations in the output device 200. Also, even when the power supply voltage or reference voltage is not common, the radiation noise due to the voltage and current fluctuations in the output device 200 may affect signal transmission in the drive device 100.

[0120] The communication control unit 70 in this example stops the output of the high-side state signal HSD_U from the high-side circuit 10 from the timing when the on / off state of the output device 200 transitions until a predetermined stop period elapses. After the stop period has elapsed, the communication control unit 70 permits the output of the high-side state signal HSD_U from the high-side circuit 10. Thereby, the influence of the switching of the output device 200 is reduced, and the high-side state signal HSD_U can be accurately transmitted from the high-side circuit 10 to the low-side circuit 50. The stop period may be preset by the manufacturer or user of the drive device 100. The stop period may be longer than the period from the start of the switching of the output device 200 until the voltage or current of the output device 200 stabilizes.

[0121] The high-side circuit 10 in this example outputs the high-side state signal HSD_U in response to the clock signal CLK_U input from the low-side circuit 50. The high-side circuit 10 outputs the high-side state signal HSD_U during the period when the clock signal CLK_U is being input, and does not output the high-side state signal HSD_U during the period when the clock signal CLK_U is not being input.

[0122] The communication control unit 70 in this example controls the input period for inputting the clock signal CLK_U from the low-side circuit 50 to the high-side circuit 10 based on the control signal DRVIN. The communication control unit 70 may control the input of the clock signal CLK_U to the high-side circuit 10 by controlling the output of the clock signal CLK_L from the low-side circuit 50. Thereby, it is possible to control whether or not the high-side state signal HSD_U is output from the high-side circuit 10.

[0123] In addition to the functions described with reference to FIGS. 1 to 11, the transmission unit 30 in this example has a function of transmitting the clock signal CLK. The transmission unit 30 has one or more high-voltage withstand elements 33 provided corresponding to each high-side circuit 10.

[0124] As described with reference to FIGS. 1 to 11, each high-voltage element 33 converts the reference voltage of the high-side state signal HSD_U from the high-side circuit 10 to the first reference voltage GND of the low-side circuit 50. The high-voltage element 33 transmits the high-side state signal HSD_L with the converted reference voltage to the low-side circuit 50. Also, each high-voltage element 33 converts the reference voltage of the clock signal CLK_L from the low-side circuit 50 to the second reference voltage VS of the high-side circuit 10. The high-voltage element 33 transmits the clock signal CLK_U with the converted reference voltage to the high-side circuit 10. The high-voltage element 33 may be the same element as the insulating element 32 in the examples in FIGS. 1 to 11, or may be an element with another structure.

[0125] FIG. 13 is a diagram showing an example of the signal waveforms of the control signal DRVIN, the clock signal CLK, and the output voltage VOUT. The clock signal CLK is the clock signal CLK_L output from the low-side circuit 50 or the clock signal CLK_U input to the high-side circuit 10. The clock signal CLK_L and the clock signal CLK_U have time waveforms synchronized with each other. The output voltage VOUT is the voltage output from the output device 200 to the load.

[0126] With the transition of the logic value of the control signal DRVIN, the output device 200 switches. With the switching of the output device 200, the output voltage VOUT of the output device 200 transitions between the H level and the L level. As described above, the variation in the output voltage VOUT can affect the signal transmission in the driving device 100.

[0127] The communication control unit 70 of this example stops the input of the clock signal to the high-side circuit 10 until a predetermined stop period P1 elapses from the transition timing of the control signal DRVIN. Thereby, the output of the high-side state signal HSD_U from the high-side circuit 10 during the stop period P1 can be stopped. The communication control unit 70 permits the input of the clock signal to the high-side circuit 10 during an output period P2 from the timing when the stop period P1 has elapsed to the next transition timing of the control signal DRVIN. By such control, the influence of the switching of the output device 200 can be reduced, and the high-side state signal HSD_U can be transmitted accurately.

[0128] The communication control unit 70 may control the length of the stop period P1 according to the characteristics of the output device 200 (that is, the power semiconductors 202 and 204). The characteristics of the output device 200 may be characteristics that affect the length of a transient period P3 from the timing when the control signal DRVIN transitions until the output voltage VOUT stabilizes.

[0129] The communication control unit 70 may make the stop period P1 longer than the transient period P3. Thereby, the high-side state signal HSD_U can be transmitted more accurately. On the other hand, if the stop period P1 is too long, the period during which the high-side state signal HSD_U can be transmitted becomes short. The stop period P1 may be equal to or less than twice the length of the transient period P3. The communication control unit 70 may control the stop period P1 based on the length of the transient period P3.

[0130] The communication control unit 70 may control the length of the stop period P1 according to the slope of the edge 110 of the output voltage VOUT (that is, the time derivative value dV / dt of the voltage). The edge 110 may be a rising edge or a falling edge. The edge 110 may be the one with the smaller slope among the rising edge and the falling edge. The smaller the slope of the edge 110, the longer the transient period P3 becomes. The communication control unit 70 may make the stop period P1 longer as the slope of the edge 110 becomes smaller.

[0131] The communication control unit 70 may control the length of the stop period P1 according to the magnitude of the power supply voltage VDD of the output device 200. The larger the power supply voltage VDD, the longer the transition period P3. The communication control unit 70 may increase the length of the stop period P1 as the power supply voltage VDD increases.

[0132] The communication control unit 70 may control the length of the stop period P1 according to the capacitance of the load connected to the output device 200. The larger the capacitance of the load, the longer the transition period P3. The communication control unit 70 may increase the length of the stop period P1 as the capacitance of the load increases.

[0133] The low-side circuit 50 may control the period of the clock signal CLK_L according to the length of the output period P2. The length of the output period P2 may be the length of the output period P2 when the control signal DRVIN indicates H logic, may be the length of the output period P2 when the control signal DRVIN indicates L logic, or may be the shorter of these lengths.

[0134] By providing the stop period P1, the output period P2 becomes shorter, and the number of pulses of the clock signal CLK included in the output period P2 decreases. The high-side circuit 10 outputs the high-side state signal HSD_U according to the pulses of the clock signal CLK. Therefore, when the number of pulses of the clock signal CLK included in the output period P2 decreases, the number of bits that can be transmitted during one output period P2 decreases. The low-side circuit 50 may shorten the period of the clock signal CLK_L as the output period P2 becomes shorter. The low-side circuit 50 may control the period of the clock signal CLK_L so that the number of pulses of the clock signal CLK_L included in one output period P2 is equal to or greater than a set value. Thereby, the high-side state signal HSD_U with a set number of bits can be transmitted during one output period P2.

[0135] The high-side circuit 10 may control the content of the data included in the high-side state signal HSD_U according to the length of the output period P2. The shorter the output period P2 is, the less data the high-side circuit 10 may include in the high-side state signal HSD_U. For example, the high-side circuit 10 may select the number of detection results to be included in the high-side state signal HSD_U from among the voltage detection result, the current detection result, and the temperature detection result described in FIG. 3 according to the length of the output period P2.

[0136] FIG. 14 is a block diagram showing a configuration example of the high-side circuit 10 shown in FIG. 12. The high-side circuit 10 in this example has the same configuration as the high-side circuit 10 shown in FIG. 3. However, a clock signal CLK_U from the low-side circuit 50 is input to the state signal generation unit 20 in this example. The state signal generation unit 20 outputs the high-side state signal HSD_U according to the pulse of the clock signal CLK_U. Therefore, by controlling the clock signal CLK_U, it is possible to control whether or not the high-side state signal USD_U is output.

[0137] FIG. 15 is a block diagram showing a configuration example of the low-side circuit 50 shown in FIG. 12. The low-side circuit 50 in this example has the same configuration as the low-side circuit 50 shown in FIG. 4. However, the input circuit 62 in this example is an input / output circuit to which the high-side state signal HSD_L is input and which outputs the clock signal CLK_L. The communication control unit 70 controls whether or not the clock signal CLK_L is output in the input circuit 62. As described above, by controlling the clock signal CLK_L, it is possible to control whether or not the high-side state signal USD_U is output.

[0138] The communication control unit 70 in this example is provided outside the low-side circuit 50. In other examples, the communication control unit 70 may be provided inside the low-side circuit 50. The input circuit 62 may function as the communication control unit 70. The communication control unit 70 may operate at the reference voltage of the low-side circuit 50.

[0139] FIG. 16 is a block diagram showing a configuration example of the state signal generation unit 20 and the input circuit 62 in the drive device 100 shown in FIGS. 12 to 15. The state signal generation unit 20 in this example further includes an input circuit 72 with respect to the configuration of the state signal generation unit 20 shown in FIG. 5. However, in FIG. 16, the selector circuit 21, the signal synthesizing unit 22, the pulse generation unit 24, and the oscillation circuit 25 shown in FIG. 5 are collectively referred to as a high-side communication circuit 71. The high-side communication circuit 71 may further include other configurations.

[0140] The input circuit 72 receives the clock signal CLK_U and outputs an internal clock signal CKU. The internal clock signal CKU may have the same pulse pattern as the clock signal CLK_U. Each component of the high-side communication circuit 71 may operate in accordance with the pulses of the internal clock signal CKU. Thereby, the high-side communication circuit 71 outputs a high-side state signal SS during the period when the clock signal CLK_U is input, and stops generating and outputting the high-side state signal SS when the input of the clock signal CLK_U stops.

[0141] The input circuit 62 in this example further includes an output unit 74 with respect to the configuration of the input circuit 62 shown in FIG. 5. However, in FIG. 16, the edge detection circuit 64, the latch circuit 65, the timer circuit 67, and the control circuit 68 shown in FIG. 5 are collectively referred to as a low-side communication circuit 73. The low-side communication circuit 73 in this example further has a configuration that outputs an internal clock CKL to the output unit 74.

[0142] The communication control unit 70 controls whether to output the internal clock CKL from the low-side communication circuit 73 to the output unit 74. The communication control unit 70 may be provided in the low-side communication circuit 73.

[0143] The output unit 74 outputs a clock signal CLK_L in accordance with the internal clock CKL. The clock signal CLK_L may have the same pulse pattern as the internal clock CKL. With such a configuration, the period during which the high-side communication circuit 71 outputs the high-side state signal SS can be controlled using the clock signal CLK_L.

[0144] FIG. 17 is a diagram showing an example of the high-voltage withstand element 33. The high-voltage withstand element 33 in this example has a capacitor 31 provided between the high-side circuit 10 and the low-side circuit 50. The high-voltage withstand element 33 has a capacitor 31 for each signal to be transmitted. The high-voltage withstand element 33 in this example has a capacitor 31 for each of the clock signal CLK and the high-side signal HSD. In the example of FIG. 17, the clock signal CLK and the high-side signal HSD are differential signals respectively. In this case, two capacitors 31 are provided for each of the clock signal CLK and the high-side signal HSD. The capacitance of each capacitor 31 may be less than 1 pF. The capacitance of the capacitor 31 may be greater than 0.05 pF.

[0145] By using the capacitor 31 in the transmission unit 30, the circuit cost can be reduced. On the other hand, by using the capacitor 31, the transmission unit 30 is more likely to be affected by the operation of the output device 200. In this example, since the transmission of the high-side state signal HSD is stopped according to the transition timing of the output device 200, the high-side state signal HSD and the clock signal CLK can be accurately transmitted while using the low-cost transmission unit 30.

[0146] FIG. 18 is a diagram showing an example of the output unit 74. The output unit 74 in this example includes a buffer 81, an inverter 82, a diode 83, and a diode 84. The buffer 81 outputs the internal clock CKL as the clock signal CLK_LP. The inverter 82 inverts the logical value of the internal clock CKL and outputs it as the clock signal CLK_LN. The diode 83 clamps the voltage at the output terminal of the buffer 81 to a voltage not exceeding a certain voltage. The diode 84 clamps the voltage at the output terminal of the inverter 82 to a voltage not exceeding a certain voltage. With such a configuration, the output unit 74 outputs differential clock signals CLK_LP and CLK_LN. Note that the output circuit 23 may have the same configuration as the output unit 74. In the output circuit 23, the high-side state signal SS is input to the buffer 81 and the inverter 82, and differential high-side state signals HSD_UP and HSD_UN are output.

[0147] FIG. 19 is a diagram showing an example of the input circuit 72. The input circuit 72 generates the internal clock CKU from differential clock signals CLK_UP and CLK_UN. The input circuit 72 in this example includes a differential circuit 91, a pull-up resistor 87, a pull-up resistor 88, a diode 85, a diode 86, a pull-down resistor 89, and a pull-down resistor 90.

[0148] The differential circuit 91 outputs an internal clock CKU in response to the difference between the clock signals CLK_UP and CLK_UN. Thereby, common-mode noise can be removed. The pull-up resistor 87 connects the transmission path of the clock signal CLK_UP to the high potential VDDU. The pull-down resistor 89 connects the transmission path to the reference potential GNDU. The diode 85 clamps the voltage of the transmission path to a voltage below a certain level. The pull-up resistor 88 connects the transmission path of the clock signal CLK_UN to the high potential VDDU. The pull-down resistor 90 connects the transmission path to the reference potential GNDU. The diode 86 clamps the voltage of the transmission path to a voltage below a certain level. Note that the input section 63 may have the same configuration as the input circuit 72. In the input section 63, instead of the clock signal CLK_U, a high-side state signal HSD_L is input, and instead of the internal clock CKU, an input signal DI is output. Also, in the input section 63, instead of the high potential VDDU and the reference potential GNDU of the high-side circuit 10, the high potential VDDL and the reference potential GNDL of the low-side circuit 50 are applied.

[0149] Figure 20 is a diagram showing an example of the time waveforms of the respective signals in the driving device 100. In Figure 20, only one waveform (N side) of the differential signal is shown. As described above, the communication control unit 70 stops the output of the internal clock CKL in the low-side communication circuit 73 from the transition timing of the control signal DRVIN until the stop period P1 elapses. Thereby, in the stop period P1, the clock signals CLK_LN and CLK_UN do not have pulses. In Figure 20, the waveform of the clock signal CLK_UN is smoothed by the capacitor 31.

[0150] The internal clock CKU in the high-side circuit 10 has the same pulse pattern as the clock signal CLK_UN. However, the waveform of the internal clock CKU is shaped by the input circuit 72.

[0151] The high-side communication circuit 71 outputs a high-side state signal SS in response to the pulse of the internal clock CKU. The high-side state signal SS in this example is a signal whose pulse width is modulated according to the value of the information to be transmitted. The high-side state signal SS has no pulse during the stop period P1. Similarly, the high-side state signals HSD_UN and LN also have no pulse during the stop period P1. In FIG. 20, the waveform of the high-side state signal HSD_LN is smoothed by the capacitor 31.

[0152] The input section 63 outputs an input signal DI obtained by shaping the waveform of the high-side state signal HSD_LN. The low-side communication circuit 73 converts the input signal DI into a digital signal DL and outputs it. The low-side communication circuit 73 may output the digital signal DL even during the stop period P1. The data holding circuit 66 outputs a digital signal DOUT according to the digital signal DL.

[0153] FIG. 21 is a block diagram showing another configuration example of the state signal generation section 20 and the input circuit 62 in the drive device 100 shown in FIGS. 12 to 15. The state signal generation section 20 in this example has an input / output circuit 93 instead of the output circuit 23. The input circuit 62 in this example has an input / output section 94 instead of the input section 63. Other configurations are the same as any of the examples described in FIGS. 12 to 20.

[0154] The input / output circuit 93 and the input / output section 94 in this example transmit signals bidirectionally with each other. The input / output circuit 93 outputs a high-side state signal HSD_U in response to the high-side state signal SS in the same manner as the example in FIGS. 12 to 20. Also, a low-side signal LSD_U from the low-side circuit 50 is input to the input / output circuit 93 in this example. The input / output circuit 93 generates an input signal SDU according to the low-side signal LSD_U and inputs it to the high-side communication circuit 71. The low-side signal LSD_U may be a signal for controlling the operation of the high-side circuit 10.

[0155] The input / output circuit 93 may receive an output control signal DOEU that switches between outputting a high-side state signal HSD_U according to the high-side state signal SS or outputting an input signal SDU according to the low-side signal LSD. The output control signal DOEU may be generated by the high-side communication circuit 71.

[0156] The input / output unit 94 outputs an input signal DI according to the high-side state signal HSD_L in the same manner as the examples in FIGS. 12 to 20. Also, the input / output unit 94 in this example outputs a low-side signal LSD_L according to the low-side signal DOUTL.

[0157] The input / output unit 94 may receive an output control signal DOEL that switches between outputting a low-side signal LSD_L according to the low-side signal DOUTL or outputting a high-side state signal HSD_U according to the high-side state signal SS. The low-side signal LSD_L and the output control signal DOEL may be generated by the low-side communication circuit 73. The communication control unit 70 may stop the output of the low-side signal LSD_L by setting the logical value of the output control signal DOUEL to the L logic during the stop period P1. Alternatively, the communication control unit 70 may stop the output of the low-side signal DOUTL from the low-side communication circuit 73 during the stop period P1.

[0158] FIG. 22 is a diagram showing an example of the input / output circuit 93. The input / output circuit 93 in this example includes a buffer 107, an inverter 108, diodes 101, 102, pull-up resistors 105, 106, pull-down resistors 103, 104, a differential circuit 109, input / output terminals 111, and input / output terminals 112.

[0159] Pull-up resistor 105 connects the input / output terminal 111 to the high potential VDDU. Pull-down resistor 103 connects the input / output terminal 111 to the reference potential GNDU. Diode 101 clamps the voltage of the input / output terminal 111 to a voltage below a certain level. Pull-up resistor 106 connects the input / output terminal 112 to the high potential VDDU. Pull-down resistor 104 connects the input / output terminal 112 to the reference potential GNDU. Diode 102 clamps the voltage of the input / output terminal 112 to a voltage below a certain level.

[0160] Buffer 107 outputs the high-side state signal SS. Inverter 108 outputs a signal obtained by inverting the high-side state signal SS. However, the control signal DOEU is input to the power supply terminals of buffer 107 and inverter 108. When the control signal DOEU indicates the L logic (reference potential), buffer 107 and inverter 108 output a high impedance regardless of the logic value of the high-side state signal SS.

[0161] When the control signal DOUE indicates the H logic, buffer 107 outputs the high-side signal HSD_UP corresponding to the high-side state signal SS to the input / output terminal 111. Inverter 108 outputs the high-side signal HSD_UN obtained by inverting the high-side state signal SS to the input / output terminal 112. In this case, differential circuit 109 may output the input signal SDU corresponding to the difference between the high-side state signal SS and the inverted signal of the high-side state signal SS.

[0162] When the control signal DOUE indicates the L logic, the low-side signal LSD_UP and the low-side signal LSD_UN are input to the differential circuit 109 via the input / output terminal 111 and the input / output terminal 112. In this case, differential circuit 109 outputs the input signal SDU corresponding to the difference between the low-side signal LSD_UP and the low-side signal LSD_UN.

[0163] The input / output unit 94 may have the same configuration as the input / output circuit 93 in FIG. 22. In the input / output unit 94, instead of the high-side state signal SS and the control signal DOEU, a low-side signal DOUTL and a control signal DOEL are input, and instead of the input signal SDU, an input signal DI is output. Also, for the input / output terminal 111, a high-side signal HSD_LP is input and a low-side signal LSD_LP is output. For the input / output terminal 112, a high-side signal HSD_LN is input and a low-side signal LSD_LN is output.

[0164] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

Explanation of Reference Numerals

[0165] 10 ··· High-side circuit, 11 ··· High-side circuit section, 12 ··· Driver circuit, 14 ··· Voltage detection circuit, 16 ··· Current detection circuit, 18 ··· Temperature detection circuit, 20 ··· State signal generation section, 21 ··· Selector circuit, 22 ··· Signal synthesis section, 23 ··· Output circuit, 24 ··· Pulse generation section, 25 ··· Oscillation circuit, 26 ··· Digital signal generation section, 27 ··· Light-emitting element, 29 ··· Light-receiving element, 30 ··· Transmission section, 31 ··· Capacitor, 32 ··· Insulating element, 33 ··· High-voltage withstand element, 34 ··· Level shift circuit, 35 ··· Transistor, 36 ··· Resistor, 37 ··· Diode, 50 ··· Low-side circuit, 52 ··· Driver circuit, 54 ··· Voltage detection circuit, 56 ··· Current detection circuit, 58 ··· Temperature detection circuit, 60 ··· Transmitter, 61 ··· Terminal, 62 ··· Input circuit, 63 ··· Input section, 64 ··· Edge detection circuit, 65 ··· Latch circuit, 66 ··· Data holding circuit, 67 ··· Timer circuit, 68 ··· Control circuit, 70 ··· Communication control section, 71 ··· High-side communication circuit, 72 ··· Input circuit, 73 ··· Low-side communication circuit, 74 ··· Output section, 81 ··· Buffer, 82 ··· Inverter, 83, 84, 85, 86 ··· Diodes, 87, 88 ··· Pull-up resistors, 89, 90 ··· Pull-down resistors, 91 ··· Differential circuit, 93 ··· Input / output circuit, 94 ··· Input / output section, 100 ··· Driving device, 101, 102 ··· Diodes, 103, 104 ··· Pull-down resistors, 105, 106 ··· Pull-up resistors, 107 ··· Buffer, 108 ··· Inverter, 109 ··· Differential circuit, 110 ··· Edge, 111, 112 ··· Input / output terminals, 200 ··· Output device, 202, 204 ··· Power semiconductors, 300 ··· Power supply device

Claims

1. A drive device for a power semiconductor, A first circuit; A second circuit; a state signal generating unit that generates a first state signal that indicates a state of the first circuit by a multi-bit digital value; a communication control unit that controls an output period during which the first circuit outputs the first state signal based on a load state signal that indicates an on / off transition timing of the power semiconductor; A drive unit comprising:

2. The communication control unit permits output of the first state signal after a predetermined stop period has elapsed from a timing when the power semiconductor transitions between on and off. The drive device according to claim 1 .

3. the first circuit outputs the first state signal in response to a clock signal input from the second circuit; The communication control unit controls an input period for inputting the clock signal from the second circuit to the first circuit based on the load state signal. The drive device according to claim 1 .

4. The communication control unit controls the stop period in accordance with a characteristic of the power semiconductor. The drive device according to claim 2.

5. The communication control unit controls the stop period in accordance with a magnitude of a power supply voltage applied to the power semiconductor. The drive device according to claim 2.

6. The communication control unit controls the stop period in accordance with a capacity of a load connected to the power semiconductor. The drive device according to claim 2.

7. The second circuit controls the cycle of the clock signal in accordance with the length of the output period. The drive device according to claim 3.

8. the first circuit is a low-side circuit that operates on a first reference voltage; the second circuit is a high-side circuit that operates at a second reference voltage higher than the first reference voltage; a transmission unit that converts a reference voltage of the first state signal in accordance with the first reference voltage and transmits the first state signal obtained by converting the reference voltage to the low-side circuit. A drive arrangement according to any one of claims 1 to 7.

9. The transmission section has a capacitor provided between the high-side circuit and the low-side circuit.

9. The drive arrangement according to claim 8.

10. A drive device for a power semiconductor, a low-side circuit that operates on a first reference voltage; a high-side circuit that operates at a second reference voltage higher than the first reference voltage; a state signal generating unit that generates a high side state signal that indicates a state of the high side circuit by a multi-bit digital value; a transmission unit that converts a reference voltage of the high-side state signal in accordance with the first reference voltage and transmits the high-side state signal obtained by converting the reference voltage to the low-side circuit; A drive unit comprising:

11. The low-side circuit has a transmission unit that transmits the high-side state signal to an external device. The drive arrangement according to claim 10.

12. the low-side circuit generates a low-side state signal that indicates a state of the low-side circuit by a digital value; The transmission unit outputs the high side state signal and the low side state signal from a common terminal. The drive arrangement according to claim 11.

13. The transmission unit includes an isolation element that transmits the high-side state signal while electrically isolating the high-side circuit and the low-side circuit. A drive arrangement according to any one of claims 10 to 12.

14. The transmission unit has a level shift circuit that converts the signal level of the high side state signal in accordance with the first reference voltage. A drive arrangement according to any one of claims 10 to 12.

15. The high side state signal has a plurality of bit periods corresponding to the plurality of bits of the digital value, and a signal level in each bit period indicates a value corresponding to a value of each bit of the digital value. A drive arrangement according to any one of claims 10 to 12.

16. The state signal generating unit is a pulse generating unit that generates a start pulse indicating a start timing of each of the bit periods and an end pulse indicating an end timing of each of the bit periods; a signal synthesis unit that generates the high side state signal, which includes the start pulse and the end pulse, and has a signal level during a period between the start pulse and the end pulse that corresponds to the digital value; 16. The drive arrangement of claim 15, comprising:

17. The polarity of the start pulse and the end pulse are inverted.

17. The drive arrangement according to claim 16.

18. The low side circuit extracts the start timing or the end timing of each of the bit periods in the high side state signal received from the transmission unit, and detects the signal level of the high side state signal at a detection timing that is preset based on the start timing or the end timing.

17. The drive arrangement according to claim 16.

19. a communication control unit that controls a period during which the high side circuit outputs the high side state signal based on a load state signal that indicates an on / off transition timing of the power semiconductor. A drive arrangement according to any one of claims 10 to 12.

20. The communication control unit permits output of the high side state signal after a predetermined period has elapsed since the timing of the on / off transition of the power semiconductor.

20. The drive arrangement of claim 19.

21. the high-side circuit outputs the high-side state signal in response to a clock signal input from the low-side circuit; The communication control unit controls a period during which the clock signal is input from the low-side circuit to the high-side circuit based on the load state signal.

20. The drive arrangement of claim 19.

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