Semiconductor element

Abstract

To suppress hole injection to a drift region.SOLUTION: In a semiconductor element, a semiconductor substrate has: an IGBT region that is a range overlapping with a collector region; and a diode region that is a range overlapping with a cathode region. A part of a plurality of inter-trench semiconductor regions has a hole injection suppression structure having an n-type barrier region in contact with a body region from below, and a pillar region extending from the barrier region to an emitter electrode and in Schottky contact with the emitter electrode. The IGBT region has a boundary region formed by the plurality of inter-trench semiconductor regions existing between a main region and the diode region. The hole injection suppression structure is provided in the diode region and each inter-trench semiconductor region in the boundary region. A width of the boundary region in the second direction is 80% or more of a thickness of the semiconductor substrate.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] Patent Document 1 discloses a semiconductor element having an IGBT (Insulate Gate Bipolar Transistor) and a diode. A plurality of trenches are provided on the upper surface of a semiconductor substrate across an IGBT region and a diode region. A trench insulating film and a trench electrode are disposed in each trench. The trench electrode is insulated from the semiconductor substrate by the trench insulating film. The trench electrode in the IGBT region functions as a gate electrode. A p-type body region and an n-type drift region are provided across the IGBT region and the diode region in a range including the upper surface of the semiconductor substrate. The drift region is in contact with the body region from below. A channel is formed in the body region in the IGBT region. The body region in the diode region functions as an anode. A p-type collector region is provided below the drift region in the IGBT region. An n-type cathode region is provided below the drift region in the diode region. A hole injection suppression structure is provided in a semiconductor region sandwiched between a plurality of trenches (hereinafter referred to as an inter-trench semiconductor region). The hole injection suppression structure has an n-type barrier region that contacts the body region from below, and an n-type pillar region that extends from the barrier region to the emitter electrode. The pillar region is in Schottky contact with the emitter electrode. The hole injection suppression structure is provided over the entire IGBT region and diode region. The hole injection suppression structure suppresses the injection of holes from the body region to the drift region when the diode is turned on. Therefore, the recovery current is suppressed when the diode performs recovery operation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-225345 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device of Patent Document 1, a hole injection suppression structure is provided in the entire IGBT region and diode region. If a hole injection suppression structure is provided in the IGBT region, it is possible to suppress the injection of holes from the body region to the drift region at the boundary between the IGBT region and the diode region. On the other hand, if a hole injection suppression structure is provided in the entire IGBT region, leakage current is likely to occur in the IGBT region. This specification proposes a technique for effectively suppressing hole injection into the drift region when a hole injection suppression structure is partially provided in the IGBT region. [Means for solving the problem]

[0005] The first semiconductor element disclosed in this specification has a semiconductor substrate, an emitter electrode in contact with an upper surface of the semiconductor substrate, and a collector electrode in contact with a lower surface of the semiconductor substrate. The semiconductor substrate has a p-type collector region in contact with the collector electrode, and an n-type cathode region in contact with the collector electrode. When the semiconductor substrate is viewed along the thickness direction, a region overlapping with the collector region is an IGBT region, and a region overlapping with the cathode region is a diode region. When a direction along the boundary between the IGBT region and the diode region on the upper surface is a first direction, and a direction from the IGBT region toward the diode region on the upper surface is a second direction, a plurality of trenches extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction. An inner surface of each of the trenches is covered with a trench insulating film. A trench electrode is arranged in each of the trenches. A plurality of inter-trench semiconductor regions, which are semiconductor regions sandwiched between the plurality of trenches, are arranged in each of the IGBT region and the diode region. Each of the inter-trench semiconductor regions in the IGBT region and the diode region has a p-type body region in contact with the emitter electrode and the trench insulating film. At least a portion of the inter-trench semiconductor regions in the IGBT region has an n-type emitter region in contact with the emitter electrode and in contact with the trench insulating film above the body region. The semiconductor substrate has an n-type drift region distributed across the IGBT region and the diode region and disposed below the body region. Some of the inter-trench semiconductor regions have a hole injection suppression structure including an n-type barrier region in contact with the body region from below and a pillar region extending from the barrier region to the emitter electrode and in Schottky contact with the emitter electrode. The IGBT region has a main region formed by the inter-trench semiconductor regions in which the hole injection suppression structure is not provided, and a boundary region formed by the inter-trench semiconductor regions located between the main region and the diode region.The hole injection suppression structure is provided in each of the inter-trench semiconductor regions in the diode region and the boundary region, and a width of the boundary region in the second direction is 80% or more of a thickness of the semiconductor substrate.

[0006] If the width of the boundary region is 80% or more of the thickness of the semiconductor substrate, the injection of holes into the drift region can be effectively suppressed, and the reverse recovery current of the diode can be effectively suppressed. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a plan view of the semiconductor element of the first embodiment. [Diagram 2] 2 is a cross-sectional view of the semiconductor element of the first embodiment (a cross-sectional view taken along line AA in FIG. 1). [Diagram 3] Graph showing the relationship between the value W / T and the recovery charge Qrr. [Figure 4] FIG. 11 is a cross-sectional view of a semiconductor element according to a second embodiment. [Diagram 5] 3 is a cross-sectional view of a semiconductor element according to a third embodiment of the present invention; [Figure 6] 1 is a cross-sectional view of a semiconductor element according to a modified example; [Figure 7] 4 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention; [Figure 8] 1 is a cross-sectional view of a semiconductor element according to a modified example; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In the first semiconductor element, a work function at an interface between the pillar region and the emitter electrode in the boundary region may be lower than a work function at an interface between the pillar region and the emitter electrode in the diode region.

[0009] According to this configuration, the injection of holes into the drift region in the boundary region can be more effectively suppressed.

[0010] In the first semiconductor element, each of the trench electrodes in the main region may be a gate electrode, and at least one of the trench electrodes in the boundary region may be a dummy electrode connected to the emitter electrode.

[0011] The second semiconductor element disclosed in this specification has a semiconductor substrate, an emitter electrode in contact with the upper surface of the semiconductor substrate, and a collector electrode in contact with the lower surface of the semiconductor substrate. The semiconductor substrate has a p-type collector region in contact with the collector electrode, and an n-type cathode region in contact with the collector electrode. When the semiconductor substrate is viewed along the thickness direction, a region overlapping with the collector region is an IGBT region, and a region overlapping with the cathode region is a diode region. When a direction along the boundary between the IGBT region and the diode region on the upper surface is a first direction, and a direction from the IGBT region toward the diode region on the upper surface is a second direction, a plurality of trenches extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction. An inner surface of each of the trenches is covered with a trench insulating film. A trench electrode is arranged in each of the trenches. A plurality of inter-trench semiconductor regions, which are semiconductor regions sandwiched by the plurality of trenches, are arranged in each of the IGBT region and the diode region. Each of the inter-trench semiconductor regions in the IGBT region and the diode region has a p-type body region in contact with the emitter electrode and the trench insulating film. At least a portion of the inter-trench semiconductor regions in the IGBT region has an n-type emitter region in contact with the emitter electrode and in contact with the trench insulating film above the body region. The semiconductor substrate has an n-type drift region distributed across the IGBT region and the diode region and disposed below the body region. Some of the inter-trench semiconductor regions have a hole injection suppression structure including an n-type barrier region in contact with the body region from below and a pillar region extending from the barrier region to the emitter electrode and in Schottky contact with the emitter electrode. The IGBT region has a main region formed by the inter-trench semiconductor regions in which the hole injection suppression structure is not provided, and a boundary region formed by the inter-trench semiconductor regions located between the main region and the diode region.The hole injection suppression structure is provided in the inter-trench semiconductor region in the diode region and in the boundary region, and a work function at an interface between the pillar region and the emitter electrode in the boundary region is lower than a work function at an interface between the pillar region and the emitter electrode in the diode region.

[0012] According to this configuration, the injection of holes into the drift region in the boundary region can be effectively suppressed.

[0013] A third semiconductor element disclosed in this specification includes a semiconductor substrate, an emitter electrode in contact with an upper surface of the semiconductor substrate, and a collector electrode in contact with a lower surface of the semiconductor substrate. The semiconductor substrate includes a p-type collector region in contact with the collector electrode, and an n-type cathode region in contact with the collector electrode. When the semiconductor substrate is viewed along the thickness direction, a region overlapping with the collector region is an IGBT region, and a region overlapping with the cathode region is a diode region. When a direction along the boundary between the IGBT region and the diode region on the upper surface is a first direction, and a direction from the IGBT region toward the diode region on the upper surface is a second direction, a plurality of trenches extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction. An inner surface of each of the trenches is covered with a trench insulating film. A trench electrode is arranged in each of the trenches. A plurality of inter-trench semiconductor regions, which are semiconductor regions sandwiched between the plurality of trenches, are arranged in each of the IGBT region and the diode region. Each of the inter-trench semiconductor regions in the IGBT region and the diode region has a p-type body region in contact with the emitter electrode and the trench insulating film. At least a portion of the inter-trench semiconductor regions in the IGBT region has an n-type emitter region in contact with the emitter electrode and in contact with the trench insulating film above the body region. The semiconductor substrate has an n-type drift region distributed across the IGBT region and the diode region and disposed below the body region. Some of the inter-trench semiconductor regions have a hole injection suppression structure including an n-type barrier region in contact with the body region from below and a pillar region extending from the barrier region to the emitter electrode and in Schottky contact with the emitter electrode. Some of the inter-trench semiconductor regions have a floating structure in which the upper surface is covered with an interlayer insulating film.The IGBT region has a main region formed by the inter-trench semiconductor regions in which the hole injection suppression structure is not provided, and a boundary region formed by the inter-trench semiconductor regions located between the main region and the diode region. Each of the inter-trench semiconductor regions in the diode region has the hole injection suppression structure. Each of the inter-trench semiconductor regions in the boundary region has at least one of the hole injection suppression structure and the floating structure.

[0014] According to this configuration, the injection of holes into the drift region in the boundary region can be effectively suppressed. EXAMPLES

[0015] As shown in FIG. 1, the semiconductor device 10 of the first embodiment has a semiconductor substrate 12 made of silicon. When viewed from above as shown in FIG. 1, the semiconductor substrate 12 is partitioned into an element portion 14 and an outer peripheral portion 17. The element portion 14 is partitioned into a plurality of IGBT regions 15 and a plurality of diode regions 16. An IGBT is provided in the IGBT region 15, and a diode is provided in the diode region 16. Each of the IGBT region 15 and the diode region 16 has a rectangular shape that is long in the x direction. The IGBT regions 15 and the diode regions 16 are alternately arranged in the y direction. Therefore, the boundary between the IGBT region 15 and the diode region 16 extends along the x direction. Although not shown, a voltage-resistant structure such as a guard ring is provided on the outer peripheral portion 17. Furthermore, a signal electrode pad 18 is provided on the outer peripheral portion 17. One of the signal electrode pads 18 is a gate pad that controls the gate voltage of the IGBT.

[0016] 2 shows a cross section of the semiconductor element 10 cut in the y direction in a range spanning the IGBT region 15 and the diode region 16. A p-type collector region 20 and an n-type cathode region 22 are arranged in a range including the lower surface 12b of the semiconductor substrate 12. The collector region 20 is provided in the IGBT region 15, and the cathode region 22 is provided in the diode region 16. In other words, when the semiconductor substrate 12 is viewed in the thickness direction, the range overlapping with the collector region 20 is the IGBT region 15, and the range overlapping with the cathode region 22 is the diode region 16.

[0017] A plurality of trenches 60 are provided on the upper surface 12a of the semiconductor substrate 12. On the upper surface 12a of the semiconductor substrate 12, each trench 60 extends long along the x direction. On the upper surface 12a of the semiconductor substrate 12, the plurality of trenches 60 are arranged at intervals in the y direction. A plurality of trenches 60 are provided in each of the IGBT region 15 and the diode region 16. Hereinafter, a region sandwiched between two trenches 60 in the semiconductor region of the semiconductor substrate 12 is referred to as an inter-trench semiconductor region 66. A plurality of inter-trench semiconductor regions 66 are provided in each of the IGBT region 15 and the diode region 16. The inner surface of each trench 60 is covered with a trench insulating film 62. A trench electrode 64 is arranged inside each trench 60. The trench electrode 64 is insulated from the semiconductor substrate 12 by the trench insulating film 62.

[0018] An interlayer insulating film 68 and an emitter electrode 70 are provided on the upper part of the semiconductor substrate 12. The interlayer insulating film 68 covers the upper surface of the trench electrode 64 in the IGBT region 15. The emitter electrode 70 is made of a metal (for example, an AlSi alloy). The emitter electrode 70 is provided across the IGBT region 15 and the diode region 16, and covers the upper surface 12a and the interlayer insulating film 68. The trench electrode 64 in the IGBT region 15 is insulated from the emitter electrode 70 by the interlayer insulating film 68. Although not shown, the trench electrode 64 in the IGBT region 15 is connected to a gate pad by a wiring. The trench electrode 64 in the IGBT region 15 is a gate electrode 64a whose potential can be changed by the gate pad. The trench electrode 64 in the diode region 16 is connected to the emitter electrode 70. The trench electrode 64 in the diode region 16 is a dummy electrode 64b fixed to the same potential as the emitter electrode 70.

[0019] A collector electrode 72 is provided on the lower part of the semiconductor substrate 12. The collector electrode 72 is provided across the IGBT region 15 and the diode region 16, and covers the lower surface 12b. The collector region 20 and the cathode region 22 are in ohmic contact with the collector electrode 72.

[0020] Each inter-trench semiconductor region 66 in the IGBT region 15 and the diode region 16 has a p-type upper body region 34. The upper body region 34 is in contact with the emitter electrode 70 and is in contact with the trench insulating film 62 on the side surface of the trench 60. The upper body region 34 has a contact region 34a and a low-concentration region 34b having a p-type impurity concentration lower than that of the contact region 34a. The contact region 34a is disposed at a position including the upper surface 12a and is in ohmic contact with the emitter electrode 70. The low-concentration region 34b is in contact with the contact region 34a from below. The low-concentration region 34b is in contact with the trench insulating film 62 on the side surface of the trench 60.

[0021] Each inter-trench semiconductor region 66 in the IGBT region 15 has an n-type emitter region 32. Each emitter region 32 is disposed at a position including the upper surface 12a, and is in ohmic contact with the emitter electrode 70. Each emitter region 32 is in contact with the trench insulating film 62 on the side of the trench 60. The low concentration region 34b is in contact with each emitter region 32 from below. Each emitter region 32 is in contact with the trench insulating film 62 above the low concentration region 34b. In this embodiment, the emitter region 32 is not provided in the diode region 16, but there is no problem even if the emitter region 32 is provided in the diode region 16.

[0022] Each inter-trench semiconductor region 66 in the IGBT region 15 and the diode region 16 has an n-type barrier region 30. The n-type impurity concentration of the barrier region 30 is lower than the n-type impurity concentration of the emitter region 32. The barrier region 30 is disposed below the low concentration region 34b. The barrier region 30 contacts the trench insulating film 62 on the side surface of the trench 60.

[0023] Each inter-trench semiconductor region 66 in the IGBT region 15 and the diode region 16 has a p-type lower body region 28. The p-type impurity concentration of the lower body region 28 is lower than the p-type impurity concentration of the contact region 34a. The lower body region 28 is disposed below the barrier region 30. The lower body region 28 contacts the trench insulating film 62 on the side surface of the trench 60. The lower body region 28 is separated from the upper body region 34 by the barrier region 30. In other words, the barrier region 30 separates the p-type body region into the upper body region 34 and the lower body region 28.

[0024] The IGBT region 15 has a main region 15a and a boundary region 15b. The boundary region 15b is a region adjacent to the diode region 16 and has a plurality of inter-trench semiconductor regions 66. The main region 15a is a region disposed at a position away from the diode region 16 in the y direction and has a plurality of inter-trench semiconductor regions 66. In other words, the region between the main region 15a and the diode region 16 is the boundary region 15b. An n-type pillar region 26 is provided in each inter-trench semiconductor region 66 in the diode region 16 and the boundary region 15b. No pillar region 26 is provided in each inter-trench semiconductor region 66 in the main region 15a. In other words, the region adjacent to the diode region 16 and constituted by a plurality of inter-trench semiconductor regions 66 having the pillar region 26 is the boundary region 15b, and the region disposed at a position away from the diode region 16 and constituted by a plurality of inter-trench semiconductor regions 66 not having the pillar region 26 is the main region 15a. The n-type impurity concentration of the pillar regions 26 is lower than the n-type impurity concentration of the emitter regions 32. Each pillar region 26 extends from the barrier region 30 to the emitter electrode 70. Each pillar region 26 is in Schottky contact with the emitter electrode 70. Hereinafter, a set of the barrier region 30 and the pillar region 26 is referred to as a hole injection suppression structure 31. The hole injection suppression structure 31 is provided in each inter-trench semiconductor region 66 in the diode region 16 and the boundary region 15b. The hole injection suppression structure 31 is not provided in each inter-trench semiconductor region 66 in the main region 15a.

[0025] The semiconductor substrate 12 has an n-type intermediate region 24. The intermediate region 24 is distributed across the IGBT region 15 and the diode region 16. The intermediate region 24 is disposed between the upper structure (i.e., the upper body region 34, the emitter region 32, the barrier region 30, the lower body region 28, etc.) and the lower structure (i.e., the collector region 20 and the cathode region 22) of the semiconductor substrate 12. The intermediate region 24 has a drift region 24a and a buffer region 24b.

[0026] The drift region 24a is an n-type region having a lower n-type impurity concentration than the barrier region 30 and the pillar region 26. The drift region 24a is distributed across the IGBT region 15 and the diode region 16. The drift region 24a is disposed below the upper body region 34, the barrier region 30, and the lower body region 28. The drift region 24a contacts the lower body region 28 from below. In addition, the drift region 24a contacts the trench insulating film 62 at the lower end of each trench 60.

[0027] The buffer region 24b is an n-type region having an n-type impurity concentration higher than that of the drift region 24a and lower than that of the cathode region 22. The buffer region 24b is distributed across the IGBT region 15 and the diode region 16. The buffer region 24b contacts the drift region 24a from below. The buffer region 24b contacts the collector region 20 and the cathode region 22 from above.

[0028] 2, width W is the width of boundary region 15b in the y direction, and thickness T is the thickness of semiconductor substrate 12. In the first embodiment, width W is 80% of thickness T or more.

[0029] An IGBT is formed in the IGBT region 15. The IGBT switches when a potential higher than that of the emitter electrode 70 is applied to the collector electrode 72. When a potential higher than the gate threshold is applied to the gate electrode 64a, a channel is formed in the upper body region 34 and the lower body region 28 in an area adjacent to the trench insulating film 62. This turns on the IGBT, and a current flows from the collector electrode 72 to the emitter electrode 70. When the potential of the gate electrode 64a is reduced to a potential lower than the gate threshold, the channel disappears and the IGBT turns off.

[0030] A diode is formed in the diode region 16. When a potential higher than that of the collector electrode 72 is applied to the emitter electrode 70, holes are injected from the upper body region 34 to the drift region 24a in the diode region 16, as shown by an arrow 100 in FIG. 2. Then, the electrical resistance of the drift region 24a decreases due to conductivity modulation. Therefore, electrons flow from the collector electrode 72 to the collector electrode 70 through the cathode region 22, the buffer region 24b, the drift region 24a, the lower body region 28, the barrier region 30, and the upper body region 34. That is, the diode is turned on. In addition, when the diode is turned on, holes are injected from the upper body region 34 to the drift region 24a even in the boundary region 15b adjacent to the diode region 16, as shown by an arrow 102. However, in the first embodiment, the hole injection suppression structure 31 suppresses the injection of holes into the drift region 24a. That is, in the hole injection suppression structure 31, the barrier region 30 is connected to the emitter electrode 70 having a low potential by the pillar region 26, so that the potential of the barrier region 30 is low. This suppresses the injection of holes from the upper body region 34 to the drift region 24a. Since the hole injection suppression structure 31 is provided between the diode region 16 and the boundary region 15b, the injection of holes into the drift region 24a is suppressed between the diode region 16 and the boundary region 15b. That is, the injection of holes indicated by the arrows 100 and 102 is suppressed.

[0031] When the potential applied to the emitter electrode 70 is switched to a potential lower than that of the collector electrode 72 while the diode is on, the diode performs a recovery operation. That is, holes present in the drift region 24a are discharged to the emitter electrode 70, and a reverse current (so-called recovery current) flows instantaneously through the diode. In the first embodiment, when the diode is on, the injection of holes into the drift region 24a is suppressed by both the diode region 16 and the boundary region 15b, so that few holes are discharged from the drift region 24a to the emitter electrode 70 during the recovery operation. Therefore, a recovery current is unlikely to occur.

[0032] As described above, the hole injection suppression structure 31 is provided in the diode region 16 and the boundary region 15b, so that the recovery current can be suppressed. FIG. 3 shows the results of manufacturing semiconductor elements having different widths W of the boundary region 15b and measuring the recovery charge Qrr generated in each semiconductor element. The recovery charge Qrr is the total amount of charge flowing as the recovery current (i.e., the value obtained by integrating the recovery current generated in the diode with respect to time). The horizontal axis shows the value W / T obtained by dividing the width W by the thickness T. As shown in FIG. 3, when the value W / T is in the range of 0 to 0.8, the recovery charge Qrr decreases rapidly as the value W / T increases. When the value W / T is in the range of 0.8 or more, the recovery charge Qrr decreases gently as the value W / T increases. It can be seen from FIG. 3 that the recovery charge Qrr can be effectively reduced by setting the value W / T to 0.8 or more. As described above, in the semiconductor element 10 of the first embodiment, the value W / T is 0.8 or more, so that the recovery charge Qrr can be effectively reduced. The value W / T may be 8.0 or less (that is, the width W is 8.0 times the thickness of the semiconductor substrate 12 or less). EXAMPLES

[0033] 4 differs from Example 1 in that the emitter electrode 70 has a first metal layer 70a and a second metal layer 70b. Other configurations of the switching element of Example 2 are the same as those of Example 1.

[0034] The first metal layer 70a and the second metal layer 70b are made of different metals. The second metal layer 70b covers the upper surface 12a in the boundary region 15b. The second metal layer 70b is in ohmic contact with the contact region 34a and the emitter region 32 in the boundary region 15b, and is in Schottky contact with the pillar region 26. The first metal layer 70a covers the upper surface 12a in the diode region 16 and the main region 15a. The first metal layer 70a also covers the upper surface of the second metal layer 70b. The first metal layer 70a is in ohmic contact with the contact region 34a and the emitter region 32 in the diode region 16 and the main region 15a, and is in Schottky contact with the pillar region 26. The materials of the first metal layer 70a and the second metal layer 70b are selected so that the work function φBn2 at the interface between the second metal layer 70b and the pillar region 26 is lower than the work function φBn1 at the interface between the first metal layer 70a and the pillar region 26. For example, the first metal layer 70a may be made of an AlSi alloy, and the second metal layer 70b may be made of titanium.

[0035] In the second embodiment, since the work function at the interface between the pillar region 26 and the emitter electrode 70 in the boundary region 15b is low, the potential of the barrier region 30 in the boundary region 15b is likely to be lower when the diode is on. Therefore, when the diode is on, the injection of holes into the drift region 24a can be more effectively suppressed in the boundary region 15b. Therefore, the recovery current can be effectively suppressed in the boundary region 15b.

[0036] In the second embodiment, the width W may be 80% or more of the thickness T, or may be less than 80% of the thickness T. EXAMPLES

[0037] 5 differs from Example 1 in that the trench electrodes 64 arranged in some of the trenches 60x in the boundary region 15b are dummy electrodes 64b. The other configurations of the switching element of Example 3 are the same as those of Example 1. With this configuration, the potential in the boundary region 15b is likely to be stabilized.

[0038] In FIG. 5, the dummy electrodes 64b are provided in some of the trenches 60 in the boundary region 15b, but the dummy electrodes 64b may be provided in all of the trenches 60 in the boundary region 15b.

[0039] Moreover, as shown in FIG. 6, the second and third embodiments may be combined. EXAMPLES

[0040] In the switching element of Example 4 shown in FIG. 7, the upper surface 12a is covered by an interlayer insulating film 68 in a part of the inter-trench semiconductor region 66x in the boundary region 15b. In the inter-trench semiconductor region 66x covered by the interlayer insulating film 68, the upper body region 34 is insulated from the emitter electrode 70, and the potential of the upper body region 34 is floating. Hereinafter, a structure in which the upper body region 34 is insulated from the emitter electrode 70 by the interlayer insulating film 68 is referred to as a floating structure. The other inter-trench semiconductor regions 66 in the boundary region 15b (i.e., the inter-trench semiconductor regions 66 not having a floating structure) have a hole injection suppression structure 31. Other configurations of the switching element of Example 4 are the same as those of Example 1.

[0041] In the switching element of Example 4, when the diode is turned on, no holes are injected from the upper body region 34 to the drift region 24a in the inter-trench semiconductor region 66 having a floating structure. Moreover, in the other inter-trench semiconductor regions 66 in the boundary region 15b (i.e., the inter-trench semiconductor regions 66 not having a floating structure), the hole injection suppression structure 31 suppresses the injection of holes from the upper body region 34 to the drift region 24a. Therefore, a recovery current is unlikely to occur in the diode.

[0042] In the fourth embodiment, the width W may be 80% or more of the thickness T, or may be less than 80% of the thickness T.

[0043] Moreover, the fourth embodiment may be combined with at least one of the second and third embodiments.

[0044] In the above-described first to fourth embodiments, the barrier region 30 is provided in each inter-trench semiconductor region 66 in the main region 15a. However, the barrier region 30 does not have to be provided in each inter-trench semiconductor region 66 in the main region 15a.

[0045] In addition, in the above-described first to fourth embodiments, the dummy electrodes 64b are provided in the trenches 60 in the diode region 16. However, the gate electrodes 64a may be provided in at least some of the trenches 60 in the diode region 16.

[0046] Furthermore, although the semiconductor elements of the above-described Examples 1 to 4 have the lower body region 28, the techniques of Examples 1 to 4 may be applied to a semiconductor element that does not have the lower body region 28. For example, Fig. 8 shows an example in which the technique of Example 1 is applied to a semiconductor element that does not have the lower body region 28. As shown in Fig. 8, the lower body region 28 may not exist, and the drift region 24a may be in contact with the barrier region 30 from below.

[0047] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0048] 15: IGBT region, 15a: main region, 15b: boundary region, 16: diode region, 20: collector region, 22: cathode region, 24a: drift region, 26: pillar region, 28: lower body region, 30: barrier region, 31: hole injection suppression structure, 32: emitter region, 34: upper body region, 60: trench

Claims

1. A semiconductor device, A semiconductor substrate; an emitter electrode in contact with an upper surface of the semiconductor substrate; a collector electrode in contact with a lower surface of the semiconductor substrate; having The semiconductor substrate is a p-type collector region in contact with the collector electrode; an n-type cathode region in contact with the collector electrode; having When the semiconductor substrate is viewed in a thickness direction, a region overlapping with the collector region is an IGBT region, and a region overlapping with the cathode region is a diode region, a first direction is a direction along a boundary between the IGBT region and the diode region on the top surface, and a second direction is a direction from the IGBT region toward the diode region on the top surface, a plurality of trenches extending along the first direction are provided on the top surface, and the plurality of trenches are arranged at intervals in the second direction, the inner surface of each trench is covered with a trench insulating film; a trench electrode is disposed within each of the trenches; a plurality of inter-trench semiconductor regions, which are semiconductor regions sandwiched between the plurality of trenches, are disposed in each of the IGBT region and the diode region; each of the inter-trench semiconductor regions in the IGBT region and the diode region has a p-type body region in contact with the emitter electrode and the trench insulating film; at least a portion of the inter-trench semiconductor region in the IGBT region has an n-type emitter region in contact with the emitter electrode and in contact with the trench insulating film above the body region, the semiconductor substrate has an n-type drift region that is distributed across the IGBT region and the diode region and is disposed below the body region; a part of the plurality of inter-trench semiconductor regions has a hole injection suppression structure including an n-type barrier region in contact with the body region from below, and a pillar region extending from the barrier region to the emitter electrode and in Schottky contact with the emitter electrode, the IGBT region has a main region formed by the plurality of inter-trench semiconductor regions in which the hole injection suppression structure is not provided, and a boundary region formed by the plurality of inter-trench semiconductor regions located between the main region and the diode region, the hole injection suppression structure is provided in each of the inter-trench semiconductor regions in the diode region and in the boundary region; a width of the boundary region in the second direction is 80% or more of a thickness of the semiconductor substrate; Semiconductor element.

2. The semiconductor device of claim 1 , wherein a work function at an interface between the pillar region and the emitter electrode in the boundary region is lower than a work function at an interface between the pillar region and the emitter electrode in the diode region.

3. each of the trench electrodes in the main region is a gate electrode; The semiconductor device according to claim 1 , wherein at least one of the trench electrodes in the boundary region is a dummy electrode connected to the emitter electrode.

4. A semiconductor device, A semiconductor substrate; an emitter electrode in contact with an upper surface of the semiconductor substrate; a collector electrode in contact with a lower surface of the semiconductor substrate; having The semiconductor substrate is a p-type collector region in contact with the collector electrode; an n-type cathode region in contact with the collector electrode; having When the semiconductor substrate is viewed in a thickness direction, a region overlapping with the collector region is an IGBT region, and a region overlapping with the cathode region is a diode region, a first direction is a direction along a boundary between the IGBT region and the diode region on the top surface, and a second direction is a direction from the IGBT region toward the diode region on the top surface, a plurality of trenches extending along the first direction are provided on the top surface, and the plurality of trenches are arranged at intervals in the second direction, the inner surface of each trench is covered with a trench insulating film; a trench electrode is disposed within each of the trenches; a plurality of inter-trench semiconductor regions, which are semiconductor regions sandwiched between the plurality of trenches, are disposed in each of the IGBT region and the diode region; each of the inter-trench semiconductor regions in the IGBT region and the diode region has a p-type body region in contact with the emitter electrode and the trench insulating film; at least a portion of the inter-trench semiconductor region in the IGBT region has an n-type emitter region in contact with the emitter electrode and in contact with the trench insulating film above the body region, the semiconductor substrate has an n-type drift region that is distributed across the IGBT region and the diode region and is disposed below the body region; a part of the plurality of inter-trench semiconductor regions has a hole injection suppression structure including an n-type barrier region in contact with the body region from below, and a pillar region extending from the barrier region to the emitter electrode and in Schottky contact with the emitter electrode, the IGBT region has a main region formed by the plurality of inter-trench semiconductor regions in which the hole injection suppression structure is not provided, and a boundary region formed by the plurality of inter-trench semiconductor regions located between the main region and the diode region, the hole injection suppression structure is provided in each of the inter-trench semiconductor regions in the diode region and in the boundary region; a work function at an interface between the pillar region and the emitter electrode in the boundary region is lower than a work function at an interface between the pillar region and the emitter electrode in the diode region; Semiconductor element.

5. A semiconductor device, A semiconductor substrate; an emitter electrode in contact with an upper surface of the semiconductor substrate; a collector electrode in contact with a lower surface of the semiconductor substrate; having The semiconductor substrate is a p-type collector region in contact with the collector electrode; an n-type cathode region in contact with the collector electrode; having When the semiconductor substrate is viewed in a thickness direction, a region overlapping with the collector region is an IGBT region, and a region overlapping with the cathode region is a diode region, a first direction is a direction along a boundary between the IGBT region and the diode region on the top surface, and a second direction is a direction from the IGBT region toward the diode region on the top surface, a plurality of trenches extending along the first direction are provided on the top surface, and the plurality of trenches are arranged at intervals in the second direction, the inner surface of each trench is covered with a trench insulating film; a trench electrode is disposed within each of the trenches; a plurality of inter-trench semiconductor regions, which are semiconductor regions sandwiched between the plurality of trenches, are disposed in each of the IGBT region and the diode region; each of the inter-trench semiconductor regions in the IGBT region and the diode region has a p-type body region in contact with the emitter electrode and the trench insulating film; at least a portion of the inter-trench semiconductor region in the IGBT region has an n-type emitter region in contact with the emitter electrode and in contact with the trench insulating film above the body region, the semiconductor substrate has an n-type drift region that is distributed across the IGBT region and the diode region and is disposed below the body region; a part of the plurality of inter-trench semiconductor regions has a hole injection suppression structure including an n-type barrier region in contact with the body region from below, and a pillar region extending from the barrier region to the emitter electrode and in Schottky contact with the emitter electrode, Some of the inter-trench semiconductor regions have a floating structure in which the upper surface is covered with an interlayer insulating film, the IGBT region has a main region formed by the plurality of inter-trench semiconductor regions in which the hole injection suppression structure is not provided, and a boundary region formed by the plurality of inter-trench semiconductor regions located between the main region and the diode region, each of the inter-trench semiconductor regions in the diode region has the hole injection suppression structure; each of the inter-trench semiconductor regions in the boundary region has at least one of the hole injection suppression structure and the floating structure; Semiconductor element.

Images