Semiconductor device

Abstract

To provide a semiconductor device with reduced on-resistance.SOLUTION: A semiconductor device 100 includes a semiconductor layer 101 including a semiconductor substrate 101c having a first thickness and having a main surface 101a, a main surface electrode 102 disposed on the main surface 101a and having a second thickness less than the first thickness, a pad electrode 105 disposed above the main surface electrode 102 and having a third thickness exceeding the first thickness, and a resin 106 covering the periphery of the main surface electrode 102 so that the inner portion of the main surface electrode 102 is exposed. The pad electrode 105 is disposed above the inner portion of the main surface electrode 102.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] This application corresponds to Japanese Patent Application No. 2020-082730 filed with the Japan Patent Office on May 8, 2020, the entire disclosure of which is incorporated herein by reference. The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a technique relating to a vertical semiconductor element using a SiC semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-79945 A Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device with reduced on-resistance. [Means for solving the problem]

[0005] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, a first electrode layer formed on the first main surface, a second electrode layer formed on the second main surface, an insulating film covering an end of the first electrode layer, a plating layer covering at least a portion of the first electrode layer other than the end, and a mold layer covering the insulating film, wherein the semiconductor layer includes a semiconductor substrate constituting the second main surface, and a thickness of the semiconductor substrate is thinner than a thickness of the plating layer.

[0006] One embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first electrode layer on the first main surface of the semiconductor layer, the first electrode layer comprising a semiconductor substrate constituting the second main surface, forming an insulating film covering an end of the first electrode layer, forming a plating layer covering at least a portion of the first electrode layer other than the end, forming a mold layer covering the insulating film, grinding the semiconductor substrate from the second main surface until the thickness of the semiconductor substrate becomes thinner than the thickness of the plating layer, and forming a second electrode layer on the second main surface of the semiconductor substrate after the semiconductor substrate has been ground.

[0007] One embodiment of the present invention provides a semiconductor device including a semiconductor layer including a semiconductor substrate having a first thickness and having a main surface, a main surface electrode disposed on the main surface and having a second thickness less than the first thickness, and a pad electrode disposed on the main surface electrode and having a third thickness greater than the first thickness.

[0008] One embodiment of the present invention provides a semiconductor device including a semiconductor layer having a first thickness and including a main surface; a main surface electrode disposed on the main surface and having a second thickness less than the first thickness; a photosensitive resin layer covering a peripheral portion of the main surface electrode to expose an inner portion of the main surface electrode and having a third thickness greater than the second thickness; a thermosetting resin layer sandwiching the photosensitive resin layer and covering the peripheral portion of the main surface electrode to expose the inner portion of the main surface electrode and having a fourth thickness greater than the third thickness; and a pad electrode disposed on the inner portion of the main surface electrode and having a fifth thickness greater than the third thickness.

[0009] The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of the semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. [Diagram 3] FIG. 3 is a diagram showing a detailed configuration of the outer periphery of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a diagram showing a detailed configuration of a semiconductor layer of the semiconductor device shown in FIG. [Figure 5A] FIG. 5A is a first cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. [Figure 5B] 1. FIG. 5B is a second cross-sectional view showing the method for manufacturing the semiconductor device shown in FIG. [Figure 5C] 1. FIG. 5C is a third cross-sectional view showing the method for manufacturing the semiconductor device shown in FIG. [Figure 5D] 1. FIG. 5D is a fourth cross-sectional view showing the method for manufacturing the semiconductor device shown in FIG. [Figure 5E] 1. FIG. 5E is a fifth cross-sectional view showing a manufacturing method of the semiconductor device shown in FIG. [Figure 5F] 1. FIG. 5F is a sixth cross-sectional view showing the method for manufacturing the semiconductor device shown in FIG. [Figure 5G] 1. FIG. 5G is a seventh cross-sectional view showing the manufacturing method of the semiconductor device shown in FIG. [Figure 6A] FIG. 6A is a first cross-sectional view showing a method for grinding a semiconductor substrate. [Figure 6B] FIG. 6B is a second cross-sectional view showing the method of grinding the semiconductor substrate. [Figure 6C] FIG. 6C is a third cross-sectional view showing the method of grinding the semiconductor substrate. [Figure 7] FIG. 7 is a diagram showing the relationship between the thickness of a semiconductor substrate and the on-resistance. [Figure 8] FIG. 8 is a plan view of the semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view of the semiconductor device shown in FIG. [Figure 10] FIG. 10 is a diagram showing a detailed configuration of the outer periphery of the semiconductor device shown in FIG. [Figure 11] FIG. 11 is a diagram illustrating an example of a semiconductor package according to the third embodiment. [Figure 12]FIG. 12 is a diagram illustrating an example of the semiconductor package illustrated in FIG. [Figure 13] FIG. 13 is a diagram showing another example of the semiconductor package according to the third embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a semiconductor device having a structure in which a nickel layer is formed on a plating layer. [Figure 15] FIG. 15 is a cross-sectional view of a semiconductor device including a plating layer having a two-layer structure. [Figure 16] FIG. 16 is a plan view of a semiconductor device according to a modified example. [Figure 17A] FIG. 17A is a first cross-sectional view showing a dicing step according to one modified example. [Figure 17B] FIG. 17B is a second cross-sectional view showing a dicing step according to one modified example. [Figure 17C] FIG. 17C is a third cross-sectional view showing a dicing step according to one modified example. [Figure 18A] FIG. 18A is a first cross-sectional view showing a dicing step according to another modified example. [Figure 18B] FIG. 18B is a second cross-sectional view showing a dicing step according to another modified example. [Figure 18C] FIG. 18C is a third cross-sectional view showing a dicing step according to another modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangement positions, component connection forms, steps, and step sequences shown in the following embodiments are merely examples and are not intended to limit the present invention. Components in the following embodiments that are not described in the independent claims are described as optional components.

[0012] The attached drawings are schematic diagrams and are not necessarily precisely illustrated. Therefore, for example, the scales of the attached drawings are not necessarily the same. In the attached drawings, the same reference numerals are used for substantially the same configurations, and duplicated explanations are omitted or simplified.

[0013] In this specification, terms indicating the relationship between elements, such as vertical and horizontal, terms indicating the shape of an element, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that include a substantially equivalent range.

[0014] In addition, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked structure. Specifically, in this specification, the first main surface side of one of the semiconductor layers is described as the upper side (upper), and the second main surface side of the other is described as the lower side (lower). When the semiconductor device (vertical transistor) is actually used, the first main surface side may be the lower side (lower) and the second main surface side may be the upper side (upper). Alternatively, the semiconductor device (vertical transistor) may be used in an orientation in which the first main surface and the second main surface are inclined or perpendicular to the horizontal plane.

[0015] In addition, the terms "above" and "below" apply not only when two components are arranged with a gap between them so that another component is interposed between them, but also when two components are arranged in close contact with each other.

[0016] The configuration of the semiconductor device according to the first embodiment will be described below. Fig. 1 is a plan view of the semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view (cross-sectional view taken along line II-II in Fig. 1) of the semiconductor device shown in Fig. 1.

[0017] The semiconductor device 100 shown in Fig. 1 is a semiconductor chip that functions as a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). The semiconductor device 100 is, for example, a power semiconductor device used for supplying and controlling power. Specifically, the semiconductor device 100 includes a semiconductor layer 101, a first electrode layer 102, a second electrode layer 103, an insulating film 104, a plating layer 105, and a mold layer 106.

[0018] The semiconductor layer 101 is a SiC semiconductor layer containing SiC (silicon carbide) single crystal as an example of a wide band gap semiconductor. The semiconductor layer 101 is formed in a rectangular plate shape in a plan view. In this specification, a plan view means a view from a direction perpendicular to the first main surface 101a or the second main surface 101b (viewed from the z-axis direction in the figure). The length of one side of the semiconductor layer 101 is, for example, 1 mm or more and 10 mm or less, but may be 2 mm or more and 5 mm or less.

[0019] The semiconductor layer 101 has a first major surface 101a and a second major surface 101b facing the first major surface 101a. The semiconductor layer 101 also includes a semiconductor substrate 101c constituting the second major surface 101b, and an epitaxial layer 101d located on the semiconductor substrate 101c. The epitaxial layer 101d is obtained by epitaxial growth of the semiconductor substrate 101c.

[0020] The thickness t1 of the semiconductor layer 101 is smaller than the thickness t2 of the plating layer 105 described later, and smaller than the thickness t3 of the mold layer 106. The thickness of the semiconductor substrate 101c is, for example, 5 μm or more and 40 μm or less, more preferably 5 μm or more and 20 μm or less. The thickness of the epitaxial layer 101d is, for example, 10 μm or more and 20 μm or less. Preferably, the thickness of the semiconductor substrate 101c is smaller than the thickness of the epitaxial layer 101d. The semiconductor layer 101 is not limited to a SiC semiconductor layer, and may be a semiconductor layer made of another wide band gap semiconductor such as GaN, or may be a Si semiconductor layer.

[0021] The first electrode layer 102 is formed on the first major surface 101a. The first electrode layer 102 may be referred to as a "first major surface electrode." The first electrode layer 102 includes a first electrode layer 102g that functions as a gate electrode and a first electrode layer 102s that functions as a source electrode. The first electrode layer 102 is formed of, for example, aluminum. The first electrode layer 102 may be formed of other materials such as titanium, nickel, copper, silver, gold, titanium nitride, and tungsten.

[0022] The first electrode layer 102s may have an area of ​​50% or more of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a planar view. Preferably, the first electrode layer 102s may have an area of ​​70% or more of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a planar view. Meanwhile, the first electrode layer 102g may have an area of ​​20% or less of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a planar view. Preferably, the first electrode layer 102g may have an area of ​​10% or less of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a planar view.

[0023] The first electrode layer 102s is disposed in a region including the center position of the semiconductor substrate 101c in a plan view. The first electrode layer 102g is disposed in a region avoiding the first electrode layer 102s. However, the first electrode layer 102g may be disposed in a region including the center position of the semiconductor substrate 101c in a plan view, and the first electrode layer 102s may be disposed so as to surround the periphery of the first electrode layer 102g.

[0024] The second electrode layer 103 is formed on the second principal surface 101b. The second electrode layer 103 may be referred to as a "second principal surface electrode." The second electrode layer 103 functions as a drain electrode. The second electrode layer 103 is formed, for example, of a laminated film of titanium, nickel, and gold. The second electrode layer 103 may be formed of other materials such as aluminum, copper, silver, titanium nitride, and tungsten.

[0025] The insulating film 104 covers the entire circumference of the outer periphery of the first electrode layer 102 (i.e., both ends in the x-axis direction and both ends in the y-axis direction). The outer periphery of the first electrode layer 102 may be referred to as the peripheral portion of the first electrode layer 102. The insulating film 104 includes a first portion 104a and a second portion 104b. The first portion 104a runs over the first electrode layer 102. More specifically, the first portion 104a runs over the peripheral portion of the first electrode layer 102. The second portion 104b is located outside the first portion 104a and covers the area other than the first electrode layer 102. In other words, the second portion 104b does not run over the first electrode layer 102.

[0026] The first portion 104a further includes an inner end 104a1 and a flat portion 104a2. The inner end 104a1 is an end of a portion of the first portion 104a that is located on the inner side of the semiconductor layer 101 in a plan view. The inner end 104a1 slopes obliquely downward toward the inner portion of the first electrode layer 102 in a cross-sectional view. The flat portion 104a2 is located outside the inner end 104a1 (on the peripheral edge side of the semiconductor layer 101) and has a substantially uniform thickness.

[0027] The insulating film 104 is, for example, an organic film containing a photosensitive resin. The insulating film 104 is formed of, for example, polyimide, PBO (polybenzoxazole), or the like. The insulating film 104 may be an inorganic film formed of silicon nitride (SiN), silicon oxide (SiO2), or the like. The insulating film 104 may have a single-layer structure, or may have a laminated structure in which a plurality of types of materials are laminated. When the insulating film 104 has a laminated structure, the insulating film 104 may include both an organic film and an inorganic film. In this case, the insulating film 104 preferably includes an inorganic film and an organic film laminated in this order from the first main surface 101a side. The insulating film 104 has a thickness of about 10 μm at most.

[0028] The plating layer 105 is a metal layer covering at least a portion of the first electrode layer 102. The plating layer 105 covers at least a portion of the first electrode layer 102 other than the end portion (i.e., the portion covered with the insulating film 104). As shown in Fig. 1, the plating layer 105 is surrounded by the mold layer 106 in a plan view. The plating layer 105 includes a plating layer 105 (first plating layer) on the first electrode layer 102g side and a plating layer 105 (second plating layer) on the first electrode layer 102s side.

[0029] The plating layer 105 formed on the first electrode layer 102g functions as a gate pad (pad electrode) having a rectangular shape in a plan view. The plating layer 105 formed on the first electrode layer 102s functions as a source pad (pad electrode). The pad is a portion to which a bonding wire is bonded when the semiconductor device 100 is packaged. The plating layer 105 also functions as a support member for the mold layer 106.

[0030] The plating layer 105 is formed of, for example, a material different from the first electrode layer 102. The plating layer 105 is formed of, for example, copper or a copper alloy mainly composed of copper. The plating layer 105 may be formed of other metal materials. The thickness t2 of the plating layer 105 is greater than the thickness of the insulating film 104. More specifically, the thickness t2 of the plating layer 105 is greater than the maximum thickness of the insulating film 104 located on the first electrode layer 102. As a result, the top of the plating layer 105 is higher than the top of the insulating film 104. The thickness t2 of the plating layer 105 is, for example, 30 μm or more and 100 μm or less. The thickness t2 of the plating layer 105 may be 100 μm or more and 200 μm or less.

[0031] The side surface 105a of the plating layer 105 extends vertically or substantially vertically. The side surface 105a does not necessarily extend linearly in a cross-sectional view, and may include curves or irregularities. The side surface 105a is located in a region where both the first electrode layer 102 and the insulating film 104 overlap each other. More specifically, the side surface 105a is located on the flat portion 104a2 of the insulating film 104. That is, the plating layer 105 covers the inner end portion 104a1 and the flat portion 104a2 of the first portion 104a. By positioning the side surface 105a on the flat portion 104a2, the plating layer 105 can be formed more stably than when the side surface 105a is positioned on the inner end portion 104a1, which has a relatively large thickness variation.

[0032] The mold layer 106 is a resin layer that covers at least a portion of the insulating film 104. In this embodiment, the mold layer 106 also covers a portion of the first main surface 101a. The mold layer 106 is located on the outer periphery of the semiconductor layer 101 on the first main surface 101a side. The outer periphery of the semiconductor layer 101 (first main surface 101a) may be referred to as the peripheral portion of the semiconductor layer 101 (first main surface 101a).

[0033] In a plan view, the mold layer 106 has a rectangular ring shape that follows the outer periphery of the semiconductor layer 101. The mold layer 106 is also located between the gate pad (the plating layer 105 on the first electrode layer 102g) and the source pad (the plating layer 105 on the first electrode layer 102s). In other words, the mold layer 106 is formed only on the first major surface 101a of the semiconductor layer 101, and exposes the second major surface 101b and side surfaces of the semiconductor layer 101.

[0034] The inner surface of the mold layer 106 is in direct contact with the side surface 105a of the plating layer 105. The inner surface of the mold layer 106 includes an inner surface (first inner surface) on the first electrode layer 102g side and an inner surface (second inner surface) on the first electrode layer 102s side. The mold layer 106 is formed of, for example, a thermosetting resin (epoxy resin). The mold layer 106 may be formed of an epoxy resin containing carbon and glass fiber. The thickness t3 of the mold layer 106 is, for example, 30 μm or more and 100 μm or less. The thickness t3 of the mold layer 106 may be 100 μm or more and 200 μm or less. The upper surface of the mold layer 106 and the upper surface of the plating layer 105 are flush or substantially flush with each other.

[0035] The source pad may have an area of ​​50% or more of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view. Preferably, the source pad may have an area of ​​70% or more of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view. Meanwhile, the gate pad may have an area of ​​20% or less of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view. Preferably, the gate pad may have an area of ​​10% or less of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view.

[0036] The source pad is disposed in a region including the center position of the semiconductor substrate 101c in a plan view. The gate pad is disposed in a region avoiding the source pad. However, the gate pad may be disposed in a region including the center position of the semiconductor substrate 101c in a plan view, and the source pad may be disposed so as to surround the periphery of the gate pad.

[0037] Next, a detailed configuration of the outer periphery (in other words, the end) of the semiconductor device 100 will be described. Fig. 3 is a diagram showing a detailed configuration of the outer periphery of the semiconductor device 100 (a cross-sectional view showing details of region III in Fig. 2). In Fig. 3, in addition to the first electrode layer 102s, the gate finger 102a and the outer periphery source contact 102b are also shown.

[0038] The end of the first electrode layer 102s is covered with an insulating film 104. Specifically, the insulating film 104 includes a first insulating film 104c located on the first electrode layer 102s and a second insulating film 104d located on the first insulating film 104c. The first insulating film 104c is an inorganic film made of silicon nitride, silicon oxide, or the like. The second insulating film 104d is an organic film made of polyimide, PBO, or the like.

[0039] The insulating film 104 also includes a third insulating film 104e located under the peripheral source contact 102b. More specifically, the third insulating film 104e is located between the peripheral source contact 102b and the semiconductor layer 101. The third insulating film 104e is an inorganic film made of silicon nitride, silicon oxide, or the like.

[0040] In a typical semiconductor device, the insulating film 104 is provided to suppress the intrusion of moisture into the end of the first electrode layer 102s and the occurrence of ion migration. However, when a durability test in a high-temperature and high-humidity environment or a reliability test such as a temperature cycle test is performed, the insulating film 104 may deteriorate, and moisture may intrude from the deteriorated portion or ion migration may occur at the deteriorated portion. In other words, the deterioration of the insulating film 104 may cause a failure of the semiconductor device.

[0041] Therefore, in the semiconductor device 100, the insulating film 104 is further covered with a mold layer 106. This suppresses deterioration of the insulating film 104, and improves the reliability of the semiconductor device 100.

[0042] The end of the first electrode layer 102s, the gate finger 102a, and the peripheral source contact 102b are basically covered by the first insulating film 104c, but in the example of Fig. 3, the outermost end of the first electrode layer 102s, the gate finger 102a, and the peripheral source contact 102b are covered by the second insulating film 104d, and the first insulating film 104c is omitted. This configuration relieves stress.

[0043] Next, the detailed structure of the semiconductor layer 101 will be described. Fig. 4 is a diagram showing the detailed configuration of the semiconductor layer 101. In Fig. 4, the semiconductor layer 101 is not shaded to represent a cross section in order to make the drawing easier to see. As shown in Figs. 3 and 4, the semiconductor layer 101 specifically includes a semiconductor substrate 101c and an epitaxial layer 101d.

[0044] The semiconductor device 100 shown in Fig. 4 is an example of a switching device and includes a vertical transistor 2. The vertical transistor 2 is, for example, a vertical MISFET. As shown in Fig. 4, the semiconductor device 100 includes a semiconductor layer 101, a gate electrode 20, a source electrode 30, and a drain electrode 40. The drain electrode 40 corresponds to a second electrode layer 103.

[0045] The semiconductor layer 101 includes a semiconductor layer 101 containing SiC (silicon carbide) as a main component. Specifically, the semiconductor layer 101 is an n-type SiC semiconductor layer containing a SiC single crystal. The SiC single crystal is, for example, a 4H-SiC single crystal.

[0046] The 4H—SiC single crystal has an off-angle inclined from the (0001) plane at an angle of 10° or less with respect to the [11-20] direction. The off-angle may be 0° or more and 4° or less. The off-angle may be more than 0° and less than 4°. The off-angle is set, for example, to 2° or 4°, in the range of 2°±0.2°, or in the range of 4°±0.4°.

[0047] The semiconductor layer 101 is formed in the shape of a rectangular parallelepiped chip. The semiconductor layer 101 has a first main surface 101a and a second main surface 101b. The semiconductor layer 101 has a semiconductor substrate 101c and an epitaxial layer 101d. The semiconductor substrate 101c includes a SiC single crystal. The lower surface of the semiconductor substrate 101c is the second main surface 101b. This second main surface 101b is a carbon surface (000-1) where carbon of the SiC crystal is exposed. The epitaxial layer 101d is stacked on the upper surface of the semiconductor substrate 101c, and is an n-type epitaxial layer including a SiC single crystal. -The epitaxial layer 101d is a SiC semiconductor layer of a type. The upper surface of the epitaxial layer 101d is the first main surface 101a. The first main surface 101a is a silicon surface (0001) where silicon of the SiC crystal is exposed.

[0048] A drain electrode 40 is connected to the second major surface 101b of the semiconductor layer 101. The semiconductor substrate 101c is + The epitaxial layer 101d is provided as an n-type drain region. - The drain drift region is provided as a drain-drift region of the semiconductor substrate.

[0049] The n-type impurity concentration of the semiconductor substrate 101c is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The n-type impurity concentration of the epitaxial layer 101d is lower than the n-type impurity concentration of the semiconductor substrate 101c, and is, for example, 1.0×10 15 cm -3 Above 1.0×10 17 cm -3 In this specification, the term "impurity concentration" refers to the peak value of the impurity concentration.

[0050] The epitaxial layer 101d of the semiconductor layer 101 includes a deep well region 15, a body region 16, a source region 17, and a contact region 18, as shown in FIG.

[0051] The deep well region 15 is formed in a region along the source trench 32 in the semiconductor layer 101. The deep well region 15 is also called a breakdown voltage holding region. The deep well region 15 is p - The p-type impurity concentration of the deep well region 15 is, for example, 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 The p-type impurity concentration of the deep well region 15 is higher than the n-type impurity concentration of the epitaxial layer 101d, for example.

[0052] The deep well region 15 includes a sidewall portion 15a along the sidewall 32a of the source trench 32 and a bottom wall portion 15b along the bottom wall 32b of the source trench 32. The thickness (length in the z-axis direction) of the bottom wall portion 15b is, for example, equal to or greater than the thickness (length in the x-axis direction) of the sidewall portion 15a. At least a portion of the bottom wall portion 15b may be located within the semiconductor substrate 101c.

[0053] The body region 16 is a p - The body region 16 is a type semiconductor region. In a plan view, the body region 16 is provided between the gate trench 22 and the source trench 32. In a plan view, the body region 16 is provided in a strip shape extending along the y-axis direction. The body region 16 is continuous with the deep well region 15.

[0054] The p-type impurity concentration of the body region 16 is, for example, 1.0×10 16 cm -3 Above 1.0×10 19 cm -3 The p-type impurity concentration of the body region 16 may be equal to that of the deep well region 15. The p-type impurity concentration of the body region 16 may be higher than that of the deep well region 15.

[0055] The source region 17 is an n-type semiconductor layer provided in a surface layer portion of the first major surface 101a of the semiconductor layer 101. + The source region 17 is a type semiconductor region. The source region 17 is a part of the body region 16. The source region 17 is provided in a region along the gate trench 22. The source region 17 is in contact with the gate insulating layer 23.

[0056] The source region 17 is provided in a band shape extending along the y-axis direction in a plan view. The width (length in the x-axis direction) of the source region 17 is, for example, 0.2 μm or more and 0.6 μm or less. As an example, the width of the source region 17 may be about 0.4 μm. The n-type impurity concentration of the source region 17 is, for example, 1.0×10 18 cm -3Above 1.0×10 21 cm -3 The following is the result.

[0057] The contact region 18 is a p + The contact region 18 is a type semiconductor region. The contact region 18 may be considered to be a part (high concentration portion) of the body region 16. The contact region 18 is provided in a region along the source trench 32. The contact region 18 is in contact with the barrier formation layer 33. The contact region 18 is also connected to the source region 17.

[0058] The contact region 18 is provided in a band shape extending along the y-axis direction in a plan view. The width (length in the x-axis direction) of the contact region 18 is, for example, 0.1 μm or more and 0.4 μm or less. As an example, the width of the contact region 18 may be about 0.2 μm. The p-type impurity concentration of the contact region 18 is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The following is the result.

[0059] A plurality of trench gate structures 21 and a plurality of trench source structures 31 are provided on the first main surface 101a of the semiconductor layer 101. The trench gate structures 21 and the trench source structures 31 are alternately provided one by one along the x-axis direction. In Fig. 4, only the range in which one trench gate structure 21 is sandwiched between two trench source structures 31 is shown.

[0060] Both the trench gate structure 21 and the trench source structure 31 are provided in a strip shape extending along the y-axis direction. For example, the x-axis direction is the [11-20] direction, and the y-axis direction is the [1-100] direction. The x-axis direction may be the [1-100] direction ([-1100] direction). In this case, the y-axis direction may be the [11-20] direction.

[0061] The trench gate structures 21 and the trench source structures 31 are alternately arranged along the x-axis direction to form a striped structure in plan view. The distance between the trench gate structures 21 and the trench source structures 31 is, for example, not less than 0.3 μm and not more than 1.0 μm.

[0062] The trench gate structure 21 includes a gate trench 22, a gate insulating layer 23 and a gate electrode 20, as shown in FIG.

[0063] The gate trench 22 is formed by digging down the first major surface 101a of the semiconductor layer 101 toward the second major surface 101b. The gate trench 22 is a long and narrow groove-shaped recess having a rectangular cross-sectional shape in the xz cross section and extending along the y-axis direction. The gate trench 22 has a length on the order of millimeters in the longitudinal direction (y-axis direction). The gate trench 22 has a length of, for example, 1 mm or more and 10 mm or less. The length of the gate trench 22 may be 2 mm or more and 5 mm or less. The total extension of one or more gate trenches 22 per unit area is 0.5 μm / μm. 2 More than 0.75μm / μm 2 It may be the following.

[0064] The gate insulating layer 23 is provided in the form of a film along the sidewall 22a and the bottom wall 22b of the gate trench 22. The gate insulating layer 23 defines a concave space inside the gate trench 22. The gate insulating layer 23 includes, for example, silicon oxide. The gate insulating layer 23 may include at least one of undoped silicon, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride.

[0065] The thickness of the gate insulating layer 23 is, for example, 0.01 μm or more and 0.5 μm or less. The thickness of the gate insulating layer 23 may be uniform or may vary depending on the portion. For example, the gate insulating layer 23 includes a sidewall portion 23a along the sidewall 22a of the gate trench 22 and a bottom wall portion 23b along the bottom wall 22b of the gate trench 22. The thickness of the bottom wall portion 23b may be thicker than the thickness of the sidewall portion 23a. The thickness of the bottom wall portion 23b is, for example, 0.01 μm or more and 0.2 μm or less. The thickness of the sidewall portion 23a is, for example, 0.05 μm or more and 0.5 μm or less. The gate insulating layer 23 may also include an upper surface portion provided on the upper surface of the source region 17 outside the gate trench 22. The thickness of the upper surface portion may be thicker than the thickness of the sidewall portion 23a.

[0066] The gate electrode 20 is an example of a control electrode of the vertical transistor 2. The gate electrode 20 is embedded in a gate trench 22. A gate insulating layer 23 is provided between the gate electrode 20 and a side wall 22a and a bottom wall 22b of the gate trench 22. That is, the gate electrode 20 is embedded in a concave space partitioned by the gate insulating layer 23. The gate electrode 20 is, for example, a conductive layer including conductive polysilicon. The gate electrode 20 may include at least one of metals such as titanium, nickel, copper, aluminum, silver, gold, and tungsten, or conductive metal nitrides such as titanium nitride.

[0067] The aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21. The aspect ratio of the trench gate structure 21 is, for example, the same as the aspect ratio of the gate trench 22. The aspect ratio of the trench gate structure 21 is, for example, not less than 0.25 and not more than 15.0. The width of the trench gate structure 21 is, for example, not less than 0.2 μm and not more than 2.0 μm. As an example, the width of the trench gate structure 21 may be about 0.4 μm. The depth of the trench gate structure 21 is, for example, not less than 0.5 μm and not more than 3.0 μm. As an example, the depth of the trench gate structure 21 may be about 1.0 μm.

[0068] The trench source structure 31 includes a deep well region 15, a source trench 32, a barrier-forming layer 33 and a source electrode 30, as shown in FIG.

[0069] The source trench 32 is formed by digging down the first major surface 101a of the semiconductor layer 101 toward the second major surface 101b. The source trench 32 is a long and narrow groove-like recess having a rectangular cross-sectional shape in the xz cross section and extending along the y-axis direction. The source trench 32 is deeper than the gate trench 22, for example. That is, the bottom wall 32b of the source trench 32 is located closer to the second major surface 101b than the bottom wall 22b of the gate trench 22.

[0070] The barrier-forming layer 33 is provided in the form of a film along the sidewall 32a and the bottom wall 32b of the source trench 32. The barrier-forming layer 33 defines a concave space inside the source trench 32. The barrier-forming layer 33 is formed using a material different from that of the source electrode 30. The barrier-forming layer 33 has a potential barrier higher than the potential barrier between the source electrode 30 and the deep well region 15.

[0071] The barrier-forming layer 33 is an insulating barrier-forming layer. In this case, the barrier-forming layer 33 contains at least one of undoped silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride. The barrier-forming layer 33 may be formed using the same material as the gate insulating layer 23. In this case, the barrier-forming layer 33 may have the same film thickness as the gate insulating layer 23.

[0072] For example, when the barrier-forming layer 33 and the gate insulating layer 23 are formed using silicon oxide, they can be formed simultaneously by a thermal oxidation process. The barrier-forming layer 33 may be a conductive barrier-forming layer. In this case, the barrier-forming layer 33 contains at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, and molybdenum.

[0073] The source electrode 30 is embedded in the source trench 32. A barrier-forming layer 33 is provided between the source electrode 30 and the side wall 32a and bottom wall 32b of the source trench 32. In other words, the source electrode 30 is embedded in a concave space defined by the barrier-forming layer 33.

[0074] The source electrode 30 is, for example, a conductive layer including conductive polysilicon. The source electrode 30 may be n-type polysilicon doped with n-type impurities or p-type polysilicon doped with p-type impurities. The source electrode 30 may include at least one of metals such as titanium, nickel, copper, aluminum, silver, gold, and tungsten, or conductive metal nitrides such as titanium nitride. The source electrode 30 may be formed using the same material as the gate electrode 20. In this case, the source electrode 30 and the gate electrode 20 can be formed in the same process.

[0075] The aspect ratio of the trench source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench source structure 31 to the width (length in the x-axis direction) of the trench source structure 31. The width of the trench source structure 31 is, for example, the sum of the width of the source trench 32 and the width of the sidewall portions 15a of the deep well region 15 located on both sides of the source trench 32. The width of the trench source structure 31 is, for example, not less than 0.6 μm and not more than 2.4 μm.

[0076] As an example, the width of the trench source structure 31 may be about 0.8 μm. The depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15. The depth of the trench source structure 31 is, for example, not less than 1.5 μm and not more than 11 μm. As an example, the depth of the trench source structure 31 may be about 2.5 μm.

[0077] The aspect ratio of the trench source structure 31 is larger than that of the trench gate structure 21. For example, the aspect ratio of the trench source structure 31 is equal to or greater than 1.5 and equal to or less than 4.0. By increasing the depth of the trench source structure 31, the effect of maintaining a withstand voltage due to the super junction (SJ) structure can be improved.

[0078] The drain electrode 40 corresponds to the second electrode layer 103. The drain electrode 40 may contain at least one of titanium, nickel, copper, aluminum, gold, and silver. For example, the drain electrode 40 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from the second main surface 101b of the semiconductor layer 101. The drain electrode 40 may have a four-layer structure including a Ti layer, an AlCu layer, a Ni layer, and an Au layer stacked in this order from the second main surface 101b of the semiconductor layer 101. The AlCu layer is an alloy layer of aluminum and copper.

[0079] The drain electrode 40 may have a four-layer structure including a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer, which are stacked in this order from the second main surface 101b of the semiconductor layer 101. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. The drain electrode 40 may include a single layer structure made of a TiN layer, or a stacked structure including a Ti layer and a TiN layer, instead of the Ti layer.

[0080] The semiconductor device 100 configured as above can switch between an ON state in which a drain current flows and an OFF state in which a drain current does not flow, depending on the gate voltage applied to the gate electrode 20 of the vertical transistor 2. The gate voltage is, for example, a voltage between 10V and 50V. As an example, the gate voltage may be 30V. The source voltage applied to the source electrode 30 is a reference voltage such as a ground voltage (0V). The drain voltage applied to the drain electrode 40 is a voltage equal to or greater than the source voltage. The drain voltage is, for example, a voltage between 0V and 10000V. The drain voltage may be a voltage equal to or greater than 1000V.

[0081] When a gate voltage is applied to the gate electrode 20, p - A channel is formed in a portion of the body region 16 of the semiconductor device 100 that contacts the gate insulating layer 23. This forms a current path from the source electrode 30 through the contact region 18, the source region 17, the channel of the body region 16, the epitaxial layer 101d, and the semiconductor substrate 101c in this order to the drain electrode 40. Since the drain electrode 40 has a higher potential than the source electrode 30, the drain current flows from the drain electrode 40 through the semiconductor substrate 101c, the epitaxial layer 101d, the channel of the body region 16, the source region 17, and the contact region 18 in this order to the source electrode 30. In this way, the drain current flows along the thickness direction of the semiconductor device 100.

[0082] p - Deep well region 15 and n - A pn junction is formed between the epitaxial layer 101d and the vertical transistor 2. When the vertical transistor 2 is in an on-state,- A source voltage is applied to the n-type deep well region 15 via a source electrode 30. - A drain voltage higher than the source voltage is applied to the epitaxial layer 101d via the drain electrode 40.

[0083] That is, a reverse bias voltage is applied to the pn junction between the deep well region 15 and the epitaxial layer 101d. Since the n-type impurity concentration of the epitaxial layer 101d is lower than the p-type impurity concentration of the deep well region 15, a depletion layer spreads from the interface between the deep well region 15 and the epitaxial layer 101d toward the drain electrode 40. This increases the breakdown voltage of the vertical transistor 2.

[0084] The source electrode 30 is electrically connected to a first electrode layer 102s provided on the source electrode 30. The gate electrode 20 is insulated from the first electrode layer 102s by an insulating layer 61, and is electrically connected to the first electrode layer 102g via a gate finger (such as the gate finger 102a in FIG. 3) provided above the outer periphery of the semiconductor layer 101. The insulating layer 61 contains, for example, silicon oxide or silicon nitride as a main component.

[0085] Next, a method for manufacturing the semiconductor device 100 will be described. Figures 5A to 5G are cross-sectional views showing the method for manufacturing the semiconductor device 100. First, as shown in Figure 5A, a semiconductor layer 101 is formed, and a first electrode layer 102 is formed on a first main surface 101a of the semiconductor layer 101. Various existing methods can be used to form the semiconductor layer 101. The first electrode layer 102 is formed by, for example, a sputtering method, a vapor deposition method, or the like.

[0086] Next, as shown in FIG. 5B, the outer periphery of the first electrode layer 102 is covered with an insulating film 104. The insulating film 104 is formed, for example, through a coating process and an exposure and development process. In the coating process, a liquid photosensitive resin material that is the source of the insulating film 104 is applied to the first electrode layer 102 by a spin coating method. In the exposure and development process, the photosensitive resin material is hardened by exposure to light, and then unnecessary portions of the photosensitive resin material are removed by an ashing method, a wet etching method, or the like. In this way, the insulating film 104 is formed.

[0087] 5C, a plating layer 105 is formed on the first electrode layer 102. The plating layer 105 is formed on the first electrode layer 102 by, for example, an electrolytic plating method or an electroless plating method. The plating layer 105 is selectively formed on at least a portion of the portion of the first electrode layer 102 that is not covered with the insulating film 104.

[0088] 5D, liquid resin material 106a (e.g., thermosetting resin) that is the source of mold layer 106 is applied or printed on the entire surface of first main surface 101a side of semiconductor layer 101. As a result, insulating film 104 and plating layer 105 are covered with resin material 106a. Resin material 106a also penetrates between plating layer 105 on first electrode layer 102g and plating layer 105 on first electrode layer 102s. The applied or printed resin material 106a is cured, for example, by heating.

[0089] 5E, the upper surface (surface) of the resin material 106a is ground until the plating layer 105 is exposed. As a result, the upper surface (surface) of the plating layer 105 and the upper surface (surface) of the mold layer 106 become flush with each other. In other words, the upper surface (surface) of the plating layer 105 and the upper surface (surface) of the mold layer 106 are composed of ground surfaces that are continuous with each other.

[0090] 5F, the second principal surface 101b side of the semiconductor layer 101 (that is, the semiconductor substrate 101c) is ground to reduce the thickness of the semiconductor layer 101. The method of grinding the semiconductor layer 101 will be described later.

[0091] Next, as shown in FIG. 5G, a second electrode layer 103 is formed on the second main surface 101b of the semiconductor layer 101. The second electrode layer 103 is formed by, for example, a sputtering method, a vapor deposition method, or the like. Finally, the wafer is cut along the scribe lines SL by a dicing blade, so that the wafer is divided into individual pieces. The dicing blade simultaneously cuts the semiconductor layer 101 and the mold layer 106. As a result, the side surface of the semiconductor layer 101 and the side surface of the mold layer 106 become flush with each other. That is, the side surface of the semiconductor layer 101 and the side surface of the mold layer 106 are made of grinding surfaces that are continuous with each other. As a result, the semiconductor device 100 as shown in FIG. 2 is obtained. The lower surface of the second electrode layer 103, the upper surface of the plating layer 105, the side surface of the plating layer 105, and the upper surface of the mold layer 106 constitute the outer surface of the semiconductor device 100 (chip).

[0092] Next, an example of a method for grinding the semiconductor layer 101 (specifically, the semiconductor substrate 101c) in Fig. 5F will be described in detail. Fig. 6A to Fig. 6C are cross-sectional views showing a method for grinding the semiconductor substrate 101c.

[0093] 6A, glass plate 150 is attached to first main surface 101a of semiconductor layer 101. In this process, glass plate 150 having protective tape 151 attached to its upper surface is prepared, and the upper surfaces of plating layer 105 and mold layer 106 of a work-in-progress (a wafer of semiconductor device 100 in the middle of manufacture) are bonded to the protective tape 151 side of glass plate 150.

[0094] 6B, in this state, the second main surface 101b side of the semiconductor layer 101 is ground. For example, a diamond grindstone is used for the grinding. The grinding is performed until the thickness of the semiconductor substrate 101c of the semiconductor layer 101 becomes 5 μm or more and 20 μm or less.

[0095] Next, as shown in Fig. 6C, the protective tape 151 is irradiated with a laser beam. The protective tape 151 is preferably irradiated with the laser beam from the first main surface 101a side through the glass plate 150. In this step, the work-in-progress is turned upside down and irradiated with the laser beam. This causes the protective tape 151 to deteriorate, and the glass plate 150 is removed. Thereafter, the protective tape 151 remaining on the wafer (semiconductor layer 101) is removed.

[0096] In a typical semiconductor device, if the thickness of the semiconductor substrate 101c is reduced to 150 μm or less, there is a problem that the semiconductor substrate 101c warps or cracks after the glass plate 150 that supports the semiconductor substrate 101c is removed. In other words, there is a limit to how thin the semiconductor substrate 101c can be in a typical semiconductor device. In particular, a SiC substrate is more susceptible to cracking or chipping than a Si substrate.

[0097] In contrast, in the semiconductor device 100, the plating layer 105 and the mold layer 106 function as a support for the semiconductor substrate 101c, so that the semiconductor substrate 101c is prevented from warping or cracking even after the glass plate 150 is removed. That is, the plating layer 105 and the mold layer 106 allow the thickness of the semiconductor substrate 101c to be extremely thin. As described above, the thickness of the semiconductor substrate 101c is, for example, 5 μm or more and 20 μm or less, which is thinner than both the thickness t2 of the plating layer 105 and the thickness t3 of the mold layer 106. It is also possible to make the thickness of the semiconductor substrate 101c the same as or thinner than the thickness of the epitaxial layer 101d.

[0098] By thinning the thickness of the semiconductor substrate 101c in this way, the on-resistance of the semiconductor substrate 101c can be reduced. Fig. 7 is a diagram showing the relationship between the thickness (350 μm, 150 μm, 20 μm) of the semiconductor substrate 101c and the on-resistance. In Fig. 7, in addition to the resistance value of the semiconductor substrate 101c, the on-resistance of the epitaxial layer 101d is also shown.

[0099] As shown in FIG. 7, if the thickness of the semiconductor substrate 101c is reduced to 20 μm, the on-resistance of the semiconductor substrate 101c can be significantly reduced. When the semiconductor layer 101 is a SiC semiconductor layer, if the thickness of the epitaxial layer 101d is 5 μm to 10 μm, the semiconductor device 100 can have a withstand voltage of 600 V to 1200 V. Since the semiconductor substrate 101c does not contribute to the withstand voltage, there is no problem in device characteristics even if the semiconductor substrate 101c is thinned. From this point of view, there is no problem even if the thickness of the semiconductor substrate 101c is reduced to 5 μm or less, and the semiconductor substrate 101c may be completely removed. In other words, the semiconductor layer 101 may have a single-layer structure made of the epitaxial layer 101d.

[0100] In the method (wafer support system) described in FIGS. 6A to 6C, the glass plate 150 is attached to the workpiece. However, the plating layer 105 and the mold layer 106 can be used as a support for grinding instead of the glass plate 150. By using the plating layer 105 and the mold layer 106 as a support for grinding, the step of adhering the workpiece to the glass plate 150 (FIG. 6A) and the step of removing the workpiece from the glass plate 150 (FIG. 6C) can be omitted. In other words, the manufacturing process of the semiconductor device 100 can be simplified.

[0101] It is not essential to use a wafer support system for grinding the semiconductor substrate 101c, and other existing methods may be used. In the above example, the SiC substrate is thinned by grinding the back surface, but the present invention is not limited to this. For example, the unnecessary portion of the SiC substrate may be peeled off (specifically, cleaved) by irradiating a laser at a predetermined depth position of the SiC substrate. This makes it easy to thin the SiC substrate, which is difficult to process.

[0102] Next, the configuration of the semiconductor device according to the second embodiment will be described. Fig. 8 is a plan view of the semiconductor device according to the second embodiment. Fig. 9 is a cross-sectional view (cross-sectional view taken along line IX-IX in Fig. 8) of the semiconductor device shown in Fig. 8.

[0103] 8 is a semiconductor chip that functions as a vertical Schottky barrier diode by utilizing a Schottky barrier generated by the junction between a semiconductor layer 201 and a first electrode layer 202. The semiconductor device 200 is, for example, a power semiconductor device used for supplying and controlling power. Specifically, the semiconductor device 200 includes a semiconductor layer 201, a first electrode layer 202, a second electrode layer 203, an insulating film 204, a plating layer 205, and a mold layer 206.

[0104] The semiconductor layer 201 is a SiC semiconductor layer including a SiC (silicon carbide) single crystal as an example of a wide band gap semiconductor. In the semiconductor device 200, the entire semiconductor layer 201 corresponds to a semiconductor substrate (for example, the semiconductor substrate 101c). The conductivity type of the semiconductor layer 201 is, for example, an n-type. The semiconductor layer 201 is formed into a rectangular plate shape in a planar view. The length of one side of the semiconductor layer 201 is, for example, 1 mm or more and 10 mm or less, but may be 2 mm or more and 5 mm or less.

[0105] The semiconductor layer 201 has a first main surface 201a and a second main surface 201b facing the first main surface 201a. The thickness t4 of the semiconductor layer 201 (semiconductor substrate) is, for example, 5 μm or more and 40 μm or less, and more preferably 5 μm or more and 20 μm or less. The semiconductor layer 201 is not limited to a SiC semiconductor layer, and may be a semiconductor layer made of other wide band gap semiconductors such as GaN, or may be a Si semiconductor layer. Of course, the semiconductor layer 201 may have a layered structure including the above-mentioned semiconductor substrate 101c and the above-mentioned epitaxial layer 101d.

[0106] The first electrode layer 202 is formed on the first main surface 201a. The first electrode layer 202 functions as an anode of a Schottky barrier diode. The first electrode layer 202 is formed of, for example, aluminum. The first electrode layer 202 may be formed of other materials such as titanium, nickel, copper, silver, gold, titanium nitride, and tungsten.

[0107] The second electrode layer 203 is formed on the second main surface 201b. The second electrode layer 203 functions as a cathode of a Schottky barrier diode. The second electrode layer 203 is formed, for example, of a laminated film of titanium, nickel, and gold. The second electrode layer 203 may be formed of other materials such as aluminum, copper, silver, titanium nitride, and tungsten.

[0108] The insulating film 204 covers the entire circumference of the outer periphery of the first electrode layer 202 (i.e., both ends in the X-axis direction and both ends in the Y-axis direction). The insulating film 204 includes a first portion 204a and a second portion 204b. The first portion 204a rides on the first electrode layer 202. More specifically, the first portion 204a rides on the peripheral edge of the first electrode layer 202. The second portion 204b is located outside the first portion 204a and covers the area other than the first electrode layer 202. In other words, the second portion 204b does not ride on the first electrode layer 202.

[0109] The first portion 204a further includes an inner end 204a1 and a flat portion 204a2. The inner end 204a1 is an end of a portion of the first portion 204a that is located on the inner side of the semiconductor layer 201 in a plan view. The inner end 204a1 slopes obliquely downward toward the inner portion of the first electrode layer 202 in a cross-sectional view. The flat portion 104a2 is located outside the inner end 204a1 (on the peripheral edge side of the semiconductor layer 101) and has a substantially uniform thickness.

[0110] The insulating film 204 is, for example, an organic film containing a photosensitive resin. The insulating film 204 is formed, for example, of polyimide, PBO (polybenzoxazole), or the like. The insulating film 204 may be an inorganic film formed of silicon nitride, silicon oxide, or the like. The insulating film 204 may have a single-layer structure, or may have a laminated structure in which a plurality of types of materials are laminated. When the insulating film 204 has a laminated structure, the insulating film 204 may include both an organic film and an inorganic film. In this case, the insulating film 204 preferably includes an inorganic film and an organic film laminated in this order from the first main surface 201a side. The insulating film 204 has a thickness of about 10 μm at most.

[0111] The plating layer 205 is a metal layer that covers at least a portion of the first electrode layer 202. The plating layer 205 covers at least a portion of the first electrode layer 202 other than the end portion (i.e., the portion covered with the insulating film 204). As shown in FIG. 8, the plating layer 205 is surrounded by the mold layer 206 in a plan view. The plating layer 205 formed on the first electrode layer 202 functions as a pad having a rectangular shape in a plan view. The pad is a portion to which a bonding wire is bonded when the semiconductor device 200 is packaged. The plating layer 205 also functions as a support member for the mold layer 206.

[0112] The plating layer 205 is formed, for example, of a material different from the first electrode layer 202. The plating layer 205 is formed, for example, of copper or a copper alloy mainly composed of copper. The plating layer 205 may be formed of other metal materials. The thickness t5 of the plating layer 205 is greater than the thickness of the insulating film 204. More specifically, the thickness t5 of the plating layer 205 is greater than the maximum thickness of the insulating film 204 located on the first electrode layer 202. As a result, the top of the plating layer 205 is higher than the top of the insulating film 204. The thickness t5 of the plating layer 205 is, for example, 30 μm or more and 100 μm or less. The thickness t5 of the plating layer 205 may be 100 μm or more and 200 μm or less.

[0113] The side surface 205a of the plating layer 205 extends vertically or substantially vertically. The side surface 205a does not necessarily extend linearly in a cross-sectional view, and may include curves or irregularities. The side surface 205a is located in a region where both the first electrode layer 202 and the insulating film 204 overlap each other. More specifically, the side surface 205a is located on the flat portion 204a2 of the insulating film 204. That is, the plating layer 205 covers the inner end portion 204a1 and the flat portion 204a2 of the first portion 204a. By positioning the side surface 205a on the flat portion 204a2, the plating layer 205 can be formed more stably than when the side surface 205a is positioned on the inner end portion 204a1, which has a relatively large thickness variation.

[0114] The mold layer 206 is a resin layer that covers a part of the insulating film 204. In this embodiment, the mold layer 206 also covers a part of the first main surface 201a. The mold layer 206 is located on the outer periphery of the first main surface 201a side of the semiconductor layer 201. In a plan view, the mold layer 206 has a rectangular ring shape that follows the outer periphery of the semiconductor layer 201. The inner surface of the mold layer 206 is in direct contact with the side surface 205a of the plating layer 205. The mold layer 206 is formed only on the first main surface 201a of the semiconductor layer 201, and exposes the second main surface 201b and the side surface of the semiconductor layer 201.

[0115] The mold layer 206 is formed of, for example, a thermosetting resin (epoxy resin). The mold layer 106 may be formed of an epoxy resin containing carbon and glass fiber. The thickness t6 of the mold layer 206 is, for example, 30 μm or more and 100 μm or less, but may be 100 μm or more and 200 μm or less. The upper surface of the mold layer 206 and the upper surface of the plating layer 205 are flush or substantially flush with each other.

[0116] Next, a detailed configuration of the outer periphery (in other words, the end) of the semiconductor device 200 will be described. Fig. 10 is a diagram showing a detailed configuration of the outer periphery of the semiconductor device 200 (a cross-sectional view showing details of region X in Fig. 9).

[0117] The end of the first electrode layer 202 is covered with an insulating film 204. Specifically, the insulating film 204 includes a first insulating film 204c located on the first electrode layer 202, a second insulating film 204d located on the first insulating film 204c, and a third insulating film 204e located under the first electrode layer 202. More specifically, the third insulating film 204e is located between the first electrode layer 202 and the semiconductor layer 201. The first insulating film 204c is an inorganic film formed of silicon nitride, silicon oxide, or the like. The second insulating film 204d is an organic film formed of polyimide, PBO, or the like. The third insulating film 204e is an inorganic film formed of silicon nitride, silicon oxide, or the like.

[0118] In a typical semiconductor device, the insulating film 204 is provided to suppress the intrusion of moisture into the end of the first electrode layer 202 and the occurrence of ion migration. However, when a durability test in a high-temperature and high-humidity environment or a reliability test such as a temperature cycle test is performed, the insulating film 204 may deteriorate, and moisture may intrude from the deteriorated portion or ion migration may occur at the deteriorated portion. In other words, the deterioration of the insulating film 204 may cause a failure of the semiconductor device.

[0119] Therefore, in the semiconductor device 200, the insulating film 204 is further covered with a mold layer 206. This suppresses deterioration of the insulating film 204, and improves the reliability of the semiconductor device 200. As shown in FIG. 10, the outermost portion of the first electrode layer 202 is covered with the second insulating film 204d, and the first insulating film 204c is omitted. This configuration relieves stress. The manufacturing method of the semiconductor device 200 is the same as the manufacturing method of the semiconductor device 100, so a detailed description of the manufacturing method of the semiconductor device 200 will be omitted. It can be said that the semiconductor device 200 is also a semiconductor device with reduced on-resistance.

[0120] In the third embodiment, a semiconductor package having a semiconductor device will be described. Figures 11 and 12 are diagrams showing an example of a semiconductor package according to the third embodiment. Figure 12 is a diagram showing an internal structure of the semiconductor package 300 shown in Figure 11 when viewed from the opposite side to that in Figure 11.

[0121] The semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package. The semiconductor package 300 includes a package body 301, a terminal 302d, a terminal 302g, a terminal 302s, a bonding wire 303g, a bonding wire 303s, and the semiconductor device 100.

[0122] The package body 301 has a rectangular parallelepiped shape, and terminals 302d, 302g, and 302s protrude from the bottom of the package body 301. The package body 301 also houses the semiconductor device 100. In other words, the package body 301 is a sealing body that seals the semiconductor device 100. The package body 301 is formed of, for example, an epoxy resin. The package body 301 may be formed of an epoxy resin containing carbon, glass fiber, or the like.

[0123] Terminals 302d, 302g, and 302s are arranged in a row and protrude from the bottom of package body 301. Terminals 302d, 302g, and 302s are each made of aluminum, for example. Terminals 302d, 302g, and 302s may also be made of other metal materials, such as copper.

[0124] Inside the package body 301, the gate pad (plating layer 105 on the first electrode layer 102g) included in the semiconductor device 100 is electrically connected to the terminal 302g by a bonding wire 303g. The source pad (plating layer 105 on the first electrode layer 102s) included in the semiconductor device 100 is electrically connected to the terminal 302s by a bonding wire 303s. The drain electrode (second electrode layer 103) included in the semiconductor device 100 is joined to a wide portion of the terminal 302d located inside the package body 301 by solder or a sintered layer made of silver or copper.

[0125] The semiconductor package 300 may include a semiconductor device 200 instead of the semiconductor device 100. In this case, the semiconductor package 300 includes two terminals, and inside the package body 301, an anode (first electrode layer 202) included in the semiconductor device 200 is electrically connected to one of the two terminals by a bonding wire or the like, and a cathode (second electrode layer 203) is joined to the other of the two terminals, a wide portion located inside the package body 401, by solder or a sintered layer made of silver or copper, or the like.

[0126] The semiconductor package 300 described above includes the semiconductor device 100 (or the semiconductor device 200) and therefore has higher reliability than a typical semiconductor device. Also, the semiconductor package 300 has a lower on-resistance than a typical semiconductor device.

[0127] Next, another example of the semiconductor package according to the third embodiment will be described. Fig. 13 is a diagram showing another example of the semiconductor package according to the third embodiment. The semiconductor package 400 shown in Fig. 13 is a so-called DIP (Dual In-line Package) type semiconductor package. The semiconductor package 400 includes a package body 401, a plurality of terminals 402, and a semiconductor device 100.

[0128] The package body 401 has a rectangular parallelepiped shape, and a plurality of terminals 402 protrude from the package body 401. The package body 401 also houses the semiconductor device 100. In other words, the package body 401 is a sealing body that seals the semiconductor device 100. The package body 401 is formed, for example, from an epoxy resin containing carbon and glass fiber.

[0129] The multiple terminals 402 are arranged side by side along the long side of the package body 401. The multiple terminals 402 are each formed of aluminum, for example. The multiple terminals 402 may also be each formed of other metal materials, such as copper.

[0130] Inside the package body 401, the gate pad (plating layer 105 on the first electrode layer 102g), the source pad (plating layer 105 on the first electrode layer 102s), and the drain electrode (second electrode layer 103) included in the semiconductor device 100 are electrically connected to corresponding terminals 402 by bonding wires or the like. The semiconductor package 400 may include a plurality of semiconductor devices 100. In other words, the package body 401 may have a plurality of semiconductor devices 100 built in.

[0131] Furthermore, the semiconductor package 400 may include a semiconductor device 200 instead of or in addition to the semiconductor device 100. In this case, inside the package body 401, the anode (first electrode layer 202) and the cathode (second electrode layer 203) included in the semiconductor device 200 are each electrically connected to a corresponding terminal 402 by a bonding wire or the like.

[0132] The semiconductor package 400 described above includes the semiconductor device 100 (or the semiconductor device 200) and therefore has higher reliability than a package including a general semiconductor device. Moreover, the semiconductor package 400 has a lower on-resistance than a package including a general semiconductor device.

[0133] As described above, a bonding wire is used for electrically connecting a terminal included in the semiconductor package 300 or the semiconductor package 400 to the semiconductor device 100 (or the semiconductor device 200). When the bonding wire is an aluminum wire, it is preferable that a nickel layer is formed on the plating layer 105, as shown in Fig. 14. Fig. 14 is a cross-sectional view of a semiconductor device 100 having a structure in which a nickel layer is formed on the plating layer 105.

[0134] 14, bonding wire 303g and bonding wire 303s are also shown as examples of bonding wires. Nickel layer 107 is an example of a metal layer formed of a metal material different from the metal material forming plating layer 105. Although not shown, a nickel layer may be formed on plating layer 205 in semiconductor device 200 as well.

[0135] Also, as shown in Fig. 15, the plating layer 105 may be composed of a first plating layer 1051 made of copper and a second plating layer 1052 made of nickel. Fig. 15 is a cross-sectional view of a semiconductor device 100 including a plating layer having a two-layer structure. This eliminates the need to form an additional nickel layer as in the example of Fig. 14. In the example of Fig. 15, the upper surface of the second plating layer 1052 and the upper surface of the mold layer are flush with each other.

[0136] 14 and 15, a nickel layer is formed on the outermost surface of plating layer 105, which is the bonding portion with the aluminum bonding wire, but other layer configurations may be formed instead of the nickel layer on the outermost surface of plating layer 105. For example, the outermost surface of plating layer 105 may be a two-layer structure (i.e., a NiPd layer) in which a palladium layer is formed on a nickel layer.

[0137] The top surface of plating layer 105 may have a three-layer structure (for example, a NiPdAu layer) in which another metal layer is further formed on the palladium layer. Such NiPd and NiPdAu layers are suitable not only for cases in which a bonding wire is bonded to plating layer 105 functioning as a source pad, but also for cases in which an external terminal is bonded to plating layer 105 functioning as a source pad by silver sintering.

[0138] The form of the semiconductor package including the semiconductor device 100 (or the semiconductor device 200) is not limited to the forms such as the semiconductor package 300 and the semiconductor package 400. As the semiconductor package, a small outline package (SOP), a quad flat non-lead package (QFN), a dual flat package (DFP), a quad flat package (QFP), a single inline package (SIP), or a small outline J-leaded package (SOJ) may be adopted. In addition, various semiconductor packages similar to these may be adopted as the semiconductor package.

[0139] As described above, the semiconductor device 100 includes the semiconductor layer 101, the first electrode layer 102, the second electrode layer 103, the insulating film 104, the plating layer 105, and the mold layer 106. The semiconductor layer 101 has a first main surface 101a and a second main surface 101b facing away from the first main surface 101a. The first electrode layer 102 is formed on the first main surface 101a. The second electrode layer 103 is formed on the second main surface 101b.

[0140] The insulating film 104 covers the ends of the first electrode layer 102. The plating layer 105 covers at least a portion of the first electrode layer 102 other than the ends. The mold layer 106 covers the insulating film 104. The semiconductor layer 101 includes a semiconductor substrate 101c constituting the second main surface 101b, and the thickness of the semiconductor substrate 101c is thinner than the thickness of the plating layer 105.

[0141] According to such a semiconductor device 100, since the insulating film 104 covering the end portion of the first electrode layer 102 is further covered with the mold layer 106, deterioration of the insulating film 104 can be suppressed. In other words, the semiconductor device 100 can be said to be a semiconductor device with improved reliability. Furthermore, since the thickness of the semiconductor substrate 101c is thinner than the thickness of the plating layer 105, the on-resistance of the semiconductor device 100 is reduced.

[0142] For example, the thickness of the semiconductor substrate 101c is 5 μm or more and 20 μm or less. In such a semiconductor device 100, the on-resistance is significantly reduced. For example, in a plan view, the mold layer 106 is annular along the outer periphery of the semiconductor layer 101. In such a semiconductor device 100, the reliability is further improved by covering the outer periphery of the semiconductor layer 101 with the mold layer 106.

[0143] For example, the surface of the plating layer 105 is flush with the surface of the mold layer 106. Such a semiconductor device 100 can be manufactured by applying or printing a resin material 106a onto the first main surface 101a side of the semiconductor layer 101, and then grinding until the plating layer 105 is exposed.

[0144] For example, the plating layer 105 and the mold layer 106 are in direct contact with each other. In such a semiconductor device 100, the plating layer 105 can be used as a support for the mold layer 106. For example, the semiconductor layer 101 is made of SiC. In such a semiconductor device 100, a relatively high dielectric breakdown field strength can be obtained.

[0145] For example, the semiconductor device 100 may function as a transistor. In this case, the semiconductor layer 101 may include a semiconductor substrate 101c and an epitaxial layer 101d on the semiconductor substrate 101c. In this case, the second electrode layer 103 may be a drain electrode of the transistor. In this case, the first electrode layer 102 may be a source electrode of the transistor and The first electrode layer 102 may include a gate electrode of a transistor. The gate electrode is insulated from the source electrode in the first electrode layer 102. Such a semiconductor device 100 can function as a transistor.

[0146] For example, the semiconductor device 200 functions as a Schottky barrier diode with the first electrode layer 202 as an anode and the second electrode layer 203 as a cathode. Such a semiconductor device 100 can function as a Schottky barrier diode.

[0147] The manufacturing method of the semiconductor device 100 includes first to seventh steps. In the first step, a semiconductor layer 101 having a first main surface 101a and a second main surface 101b facing away from the first main surface 101a, the semiconductor layer 101 including a semiconductor substrate 101c constituting the second main surface 101b, is prepared. In the second step, a first electrode layer 102 is formed on the first main surface 101a of the semiconductor layer 101.

[0148] In the third step, an insulating film 104 is formed to cover the end of the first electrode layer 102. In the fourth step, a plating layer 105 is formed to cover at least a part of the first electrode layer 102 other than the end. In the fifth step, a mold layer 106 is formed to cover the insulating film 104. In the sixth step, a semiconductor The semiconductor substrate 101c is ground from the second main surface side until the thickness of the semiconductor substrate 101c becomes thinner than the thickness of the plating layer 105. In a seventh step, a second electrode layer 103 is formed on the second main surface 101b of the semiconductor layer 101 after the semiconductor substrate 101c is ground.

[0149] This manufacturing method makes it possible to manufacture the semiconductor device 100 with improved reliability. Furthermore, in the semiconductor device 100, the thickness of the semiconductor substrate 101c is thinner than the thickness of the plating layer 105, so that the on-resistance is reduced.

[0150] In the above embodiment, an example of a semiconductor device (semiconductor device 100) has been described in which a plating layer 105 functioning as a gate pad and a plating layer 105 functioning as a source pad are provided on the upper surface. Here, the semiconductor device may further include a plating layer 105 functioning as a current sensing pad and a plating layer 105 functioning as a temperature sensing pad. Fig. 16 is a plan view of a semiconductor device according to one modified example having such a structure.

[0151] As shown in FIG. 16, the semiconductor device 100a includes, in addition to a gate pad 105g (a plating layer 105 functioning as a gate pad; the same applies below) and a source pad 105s, a current sensing pad 105c (pad electrode) and a pair of temperature sensing pads 105t (pad electrodes).

[0152] The semiconductor device 100a includes a first electrode layer 102s having a plurality of isolated portions that are separated from each other. The current sensing pad 105c is a plating layer connected to a portion (isolated portion) of the first electrode layer 102s included in the semiconductor device 100a. When a current flows between the source pad 105s and the second electrode layer 103 included in the semiconductor device 100a, a current smaller than the above current flows between the current sensing pad 105c and the second electrode layer 103. By monitoring such a current, an increase in the current can be detected.

[0153] The semiconductor device 100a includes a diode (temperature-sensitive diode) provided on the first main surface 101a of the semiconductor layer 101. One of the pair of temperature sensing pads 105t is a plating layer electrically connected to the anode of the diode (temperature-sensitive diode) included in the semiconductor device 100a. The other of the pair of temperature sensing pads 105t is a plating layer electrically connected to the cathode of the diode (temperature-sensitive diode). The temperature of the semiconductor device 100a can be detected based on the magnitude of the voltage between the pair of temperature sensing pads 105t.

[0154] As described above, the present invention can be realized as a semiconductor device 100a including the current sensing pad 105c and a pair of temperature sensing pads 105t. The present invention may be realized as a semiconductor device including at least one of the current sensing pad 105c and the pair of temperature sensing pads 105t.

[0155] In the above embodiment, the mold layer 106 and the semiconductor layer 101 are simultaneously cut by a dicing blade, but the present invention is not limited to this. For example, a two-stage dicing process may be combined. Figures 17A to 17C are cross-sectional views for explaining a dicing process according to a modified example having such a two-stage dicing process.

[0156] First, as shown in Fig. 17A, the entire mold layer 106 and a part of the semiconductor layer 101 are cut by a first dicing blade DB1 having a first width w1. Then, as shown in Fig. 17B, the entire semiconductor substrate 101c is cut by a second dicing blade DB2 having a second width w2 smaller than the first width w1 and having the same rotation axis as the first dicing blade DB1. As shown in Fig. 17C, the semiconductor device 100b singulated by this method has a side surface of the mold layer 106 located inside the side surface of the semiconductor layer 101, and has a step near the boundary between the mold layer 106 and the semiconductor layer 101.

[0157] Dicing may be performed with the wafer turned upside down. That is, dicing may be performed with the back surface (carbon surface) of the semiconductor substrate 101c facing up. The rotation direction of the dicing blade is preferably set to cut from the carbon surface toward the silicon surface. Figures 18A to 18C are cross-sectional views for explaining a dicing process according to another modified example having such a two-stage dicing process.

[0158] First, as shown in Fig. 18A, the entire semiconductor layer 101 and a part of the mold layer 106 are cut by a first dicing blade DB1 having a first width w1. Then, as shown in Fig. 18B, the entire mold layer 106 is cut by a second dicing blade DB2 having a second width w2 smaller than the first width w1 and having the same rotation axis as the first dicing blade DB1. As shown in Fig. 18C, in the semiconductor device 100c singulated by this method, the side of the semiconductor layer 101 is located inside the side of the mold layer 106c, and a step is formed near the boundary between the mold layer 106 and the semiconductor layer 101.

[0159] The two-stage dicing process shown in FIGS. 17A to 17C and the two-stage dicing process shown in FIGS. 18A to 18C are applicable not only to semiconductor devices functioning as transistors, but also to semiconductor devices functioning as Schottky barrier diodes.

[0160] Although the semiconductor device according to the embodiment has been described above, the present invention is not limited to the above embodiment. For example, all the numbers used in the description of the above embodiment are merely examples for specifically explaining the present invention, and the present invention is not limited to the exemplified numbers.

[0161] In addition, in the above embodiment, the main materials of the components included in the semiconductor device are exemplified, but each layer of the stacked structure included in the semiconductor device may contain other materials to the extent that the same functions as the stacked structure of the above embodiment can be realized. In addition, in the drawings, the corners and sides of each component are drawn as straight lines, but the present invention also includes those with rounded corners and sides due to manufacturing reasons, etc. In addition, the present invention also includes semiconductor devices having a structure in which the conductivity types described in the above embodiment are reversed.

[0162] Although the semiconductor device according to one or more aspects has been described based on the embodiments, the present invention is not limited to these embodiments. As long as it does not deviate from the gist of the present invention, various modifications that a person skilled in the art may make to the embodiments and modifications constructed by combining components in different embodiments are also included within the scope of the present invention.

[0163] Furthermore, each of the above embodiments can be modified, substituted, added, omitted, and the like in various ways within the scope of the claims or their equivalents.

[0164] For example, in the above embodiment, a power semiconductor device using a SiC substrate has been described, but the present invention is also applicable to a power semiconductor device (IGBT or MOSFET) using a Si substrate. The present invention is industrially applicable to semiconductor devices, semiconductor packages, etc.

[0165] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each item to the embodiments. [A1] to [A9] provide a semiconductor device with reduced on-resistance and a method for manufacturing the semiconductor device.

[0166] [A1] A semiconductor layer (101, 201) having a first main surface (101a, 201a) and a second main surface (101b, 201b) facing the first main surface (101a, 201a), a first electrode layer (102, 102g, 102s, 202) formed on the first main surface (101a, 201a), a second electrode layer (103, 203) formed on the second main surface (101b, 201b), an insulating film (104, 204) covering an end portion of the first electrode layer (102, 102g, 102s, 202), and a plating layer (105, 205) covering at least a portion of an insulating film (104, 204) other than the end portion of the semiconductor layer (101, 201), the semiconductor layer (101, 201) including a semiconductor substrate (101c, 201) constituting the second main surface (101b, 201b), and a thickness of the semiconductor substrate (101c, 201) being thinner than a thickness of the plating layer (105, 205).

[0167] [A2] The semiconductor device (100, 100a, 100b, 100c, 200) according to A1, wherein the semiconductor substrate (101c, 201) has a thickness of 5 μm or more and 40 μm or less.

[0168] [A3] The semiconductor device (100, 100a, 100b, 100c, 200) according to A1 or A2, wherein, in a plan view, the mold layer (106, 206) is annular along the outer periphery of the semiconductor layer (101, 201).

[0169] [A4] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A3, wherein a surface of the plating layer (105, 205) and a surface of the mold layer (106, 206) are flush with each other.

[0170] [A5] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A4, wherein the plating layer (105, 205) and the mold layer (106, 206) are in direct contact with each other.

[0171] [A6] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A5, wherein the semiconductor layer (101, 201) is made of SiC.

[0172] [A7] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A6, wherein the semiconductor device (100, 100a, 100b, 100c, 200) functions as a transistor, the semiconductor layer (101, 201) includes the semiconductor substrate (101c, 201) and an epitaxial layer (101d) on the semiconductor substrate (101c, 201), the second electrode layer (103, 203) is a drain electrode (40) of the transistor, and the first electrode layer (102, 102g, 102s, 202) includes a source electrode (102s) of the transistor and a gate electrode (102g) of the transistor insulated from the source electrode (102s).

[0173] [A8] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A7, wherein the semiconductor device (100, 100a, 100b, 100c, 200) functions as a Schottky barrier diode with the first electrode layer (102, 102g, 102s, 202) as an anode and the second electrode layer (103, 203) as a cathode.

[0174] [A9] A semiconductor layer (101, 201) having a first main surface (101a, 201a) and a second main surface (101b, 201b) facing away from the first main surface (101a, 201a), the semiconductor layer (101, 201) including a semiconductor substrate (101c, 201) constituting the second main surface (101b, 201b), a first electrode layer (102, 102g, 102s, 202) is formed on the first main surface (101a, 201a) of the semiconductor layer (101, 201), the first electrode layer (102, 102g, 102s, 202) is formed on an insulating film (104, 204) covering an end portion of the first electrode layer (102, 102g, 102s, 202), and a part of the first electrode layer (102, 102g, 102s, 202) other than the end portion is formed. a plating layer (105, 205) covering at least a portion of the insulating film (104, 204), forming a mold layer (106, 206) covering the insulating film (104, 204), grinding the semiconductor substrate (101c, 201) from the second main surface (101b, 201b) until the thickness of the semiconductor substrate (101c, 201) becomes thinner than the thickness of the plating layer (105, 205), and forming a second electrode layer (103, 203) on the second main surface (101b, 201b) of the semiconductor layer (101, 201) after the semiconductor substrate (101c, 201) has been ground.

[0175] The following [B1] to [B22] provide a semiconductor device capable of improving mechanical strength. The structures according to the following [B1] to [B22] are also effective in reducing the on-resistance.

[0176] [B1] A semiconductor device (100, 100a, 100b, 100c, 200) including a semiconductor substrate (101c, 201) having a first thickness, a semiconductor layer (101, 201) having a main surface (101a, 201a), a main surface electrode (102, 102g, 102s, 202) disposed on the main surface (101a, 201a) and having a second thickness less than the first thickness, and a pad electrode (105, 105c, 105g, 105s, 105t, 205) disposed on the main surface electrode (102, 102g, 102s, 202) and having a third thickness greater than the first thickness.

[0177] [B2] The semiconductor device (100, 100a, 100b, 100c, 200) according to B1, further comprising a resin (106, 206) covering a peripheral portion of the principal surface electrode (102, 102g, 102s, 202) so as to expose an inner portion of the principal surface electrode (102, 102g, 102s, 202), and the pad electrode (105, 105c, 105g, 105s, 105t, 205) is disposed on the inner portion of the principal surface electrode (102, 102g, 102s, 202).

[0178] [B3] The semiconductor device (100, 100a, 100b, 100c, 200) according to B2, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) is in contact with the resin (106, 206).

[0179] [B4] The semiconductor device (100, 100a, 100b, 100c, 200) according to B2 or B3, wherein the resin (106, 206) has a fourth thickness that exceeds the first thickness of the semiconductor substrate (101c, 201).

[0180] [B5] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B2 to B4, wherein the resin (106, 206) covers a peripheral portion of the main surface (101a, 201a).

[0181] [B6] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B2 to B5, wherein the resin (106, 206) is formed in a ring shape surrounding an inner portion of the main surface (101a, 201a) in a plan view.

[0182] [B7] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B2 to B6, wherein the resin (106, 206) includes a thermosetting resin.

[0183] [B8] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B2 to B7, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) has an electrode surface, and the resin (106, 206) has an outer surface continuous with the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205).

[0184] [B9] The semiconductor device (100, 100a, 100b, 100c, 200) according to B8, wherein the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205) is a ground surface, and the outer surface of the resin (106, 206) is a ground surface.

[0185] [B10] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B2 to B9, further comprising an insulating film (104, 204) covering a peripheral portion of the principal surface electrode (102, 102g, 102s, 202) so as to expose an inner portion of the principal surface electrode (102, 102g, 102s, 202), and the resin (106, 206) covers the insulating film (104, 204).

[0186] [B11] The semiconductor device (100, 100a, 100b, 100c, 200) according to B10, wherein the insulating film (104, 204) has a thickness that is greater than the second thickness and less than the first thickness.

[0187] [B12] The semiconductor device (100, 100a, 100b, 100c, 200) according to B10 or B11, wherein the insulating film (104, 204) contains a resin material different from the resin (106, 206).

[0188] [B13] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B10 to B12, wherein the insulating film (104, 204) contains a photosensitive resin.

[0189] [B14] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B10 to B13, wherein the resin (106, 206) partially exposes the insulating film (104, 204) on the inner side of the principal surface electrode (102, 102g, 102s, 202), and the pad electrode (105, 105c, 105g, 105s, 105t, 205) is in contact with the principal surface electrode (102, 102g, 102s, 202), the insulating film (104, 204) and the resin (106, 206) on the inner side of the principal surface electrode (102, 102g, 102s, 202).

[0190] [B15] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B14, wherein the semiconductor layer (101, 201) includes an epitaxial layer (101d) stacked on the semiconductor substrate (101c, 201), and the pad electrode (105, 105c, 105g, 105s, 105t, 205) has the third thickness that exceeds a total thickness of the semiconductor substrate (101c, 201) and the epitaxial layer (101d).

[0191] [B16] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B15, wherein the semiconductor layer (101, 201) includes a wide band gap semiconductor.

[0192] [B17] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B16, wherein the semiconductor layer (101, 201) contains SiC.

[0193] [B18] A semiconductor layer (101, 201) having a first thickness and including a principal surface (101a, 201a), a principal surface electrode (102, 102g, 102s, 202) disposed on the principal surface (101a, 201a) and having a second thickness less than the first thickness, a photosensitive resin layer (104, 204) covering a peripheral portion of the principal surface electrode (102, 102g, 102s, 202) so as to expose an inner portion of the principal surface electrode (102, 102g, 102s, 202) and having a third thickness greater than the second thickness, and a thermosetting resin layer (106, 206) covering a peripheral portion of the principal surface electrode (102, 102g, 102s, 202) with the photosensitive resin layer (104, 204) sandwiched therebetween so as to expose an inner portion of the principal surface electrode (102, 102g, 102s, 202) and having a fourth thickness that exceeds the third thickness, and a pad electrode (105, 105c, 105g, 105s, 105t, 205) disposed on the inner portion of the principal surface electrode (102, 102g, 102s, 202) and having a fifth thickness that exceeds the third thickness.

[0194] [B19] The semiconductor device (100, 100a, 100b, 100c, 200) according to B18, wherein the thermosetting resin layer (106, 206) partially exposes the photosensitive resin layer (104, 204) on the inner side of the principal surface electrode (102, 102g, 102s, 202), and the pad electrode (105, 105c, 105g, 105s, 105t, 205) is in contact with the principal surface electrode (102, 102g, 102s, 202), the photosensitive resin layer (104, 204) and the thermosetting resin layer (106, 206) on the inner side of the principal surface electrode (102, 102g, 102s, 202).

[0195] [B20] The semiconductor device (100, 100a, 100b, 100c, 200) according to B18 or B19, wherein the semiconductor layer (101, 201) contains SiC.

[0196] [B21] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B18 to B20, wherein the fourth thickness exceeds the first thickness, and the fifth thickness exceeds the first thickness.

[0197] [B22] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B17 to B20, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) is made of a plating film.

[0198] The following structures [C1] to [C18] provide semiconductor devices that can improve the mechanical strength. The structures according to the following structures [C1] to [C18] are also effective in reducing the on-resistance.

[0199] [C1] A semiconductor device (100, 100a, 100b, 100c, 200) including a semiconductor substrate (101c, 201) having a first thickness, a semiconductor layer (101, 201) having a main surface (101a, 201a), a main surface electrode (102, 102g, 102s, 202) disposed on the main surface (101a, 201a) and having a second thickness less than the first thickness, and a resin (106, 206) covering a peripheral portion of the main surface electrode (102, 102g, 102s, 202) so as to expose an inner portion of the main surface electrode (102, 102g, 102s, 202) and having a third thickness exceeding the first thickness.

[0200] [C2] The semiconductor device (100, 100a, 100b, 100c, 200) according to C1, wherein the resin (106, 206) covers a peripheral portion of the main surface (101a, 201a).

[0201] [C3] The semiconductor device (100, 100a, 100b, 100c, 200) according to C1 or C2, wherein the resin (106, 206) is formed in a ring shape surrounding an inner portion of the principal surface electrode (102, 102g, 102s, 202) in a plan view.

[0202] [C4] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C1 to C3, wherein the resin (106, 206) includes a thermosetting resin.

[0203] [C5] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C1 to C4, further including a pad electrode (105, 105c, 105g, 105s, 105t, 205) arranged on an inner portion of the main surface electrode (102, 102g, 102s, 202).

[0204] [C6] The semiconductor device (100, 100a, 100b, 100c, 200) according to C5, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) is in contact with the resin (106, 206).

[0205] [C7] The semiconductor device (100, 100a, 100b, 100c, 200) according to C5 or C6, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) has a fourth thickness that exceeds the first thickness of the semiconductor substrate (101c, 201).

[0206] [C8] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C5 to C7, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) has an electrode surface, and the resin (106, 206) has an outer surface continuous with the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205).

[0207] [C9] The semiconductor device (100, 100a, 100b, 100c, 200) according to C8, wherein the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205) is a ground surface, and the outer surface of the resin (106, 206) is a ground surface.

[0208] [C10] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C5 to C9, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) is made of a plating film.

[0209] [C11] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C1 to C10, further comprising an insulating film (104, 204) covering a peripheral portion of the principal surface electrode (102, 102g, 102s, 202) so as to expose an inner portion of the principal surface electrode (102, 102g, 102s, 202), and the resin (106, 206) covers the insulating film (104, 204).

[0210] [C12] The semiconductor device (100, 100a, 100b, 100c, 200) according to C11, wherein the insulating film (104, 204) has a thickness that is greater than the second thickness and less than the first thickness.

[0211] [C13] The semiconductor device (100, 100a, 100b, 100c, 200) according to C11 or C12, wherein the insulating film (104, 204) contains a resin material different from the resin (106, 206).

[0212] [C14] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C11 to C13, wherein the insulating film (104, 204) contains a photosensitive resin.

[0213] [C15] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C11 to C14, wherein the resin (106, 206) partially exposes the insulating film (104, 204) on the inner side of the main surface electrode (102, 102g, 102s, 202).

[0214] [C16] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C1 to C15, wherein the semiconductor layer (101, 201) includes an epitaxial layer (101d) stacked on the semiconductor substrate (101c, 201), and the resin (106, 206) has the third thickness that exceeds a total thickness of the semiconductor substrate (101c, 201) and the epitaxial layer (101d).

[0215] [C17] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C1 to C16, wherein the semiconductor layer (101, 201) includes a wide band gap semiconductor.

[0216] [C18] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C1 to C17, wherein the semiconductor layer (101, 201) contains SiC.

[0217] The following [D1] to [D6] provide a semiconductor device capable of improving mechanical strength. The structures according to the following [D1] to [D6] are also effective in reducing the on-resistance.

[0218] [D1] A semiconductor device (100, 100a, 100b, 100c, 200) including: a semiconductor layer (101, 201) having a first thickness and having a main surface (101a, 201a); a main surface electrode (102, 102g, 102s, 202) disposed on the main surface (101a, 201a) and having a second thickness less than the first thickness; and a resin (106, 206) partially covering the main surface electrode (102, 102g, 102s, 202) so as to expose a portion of the main surface electrode (102, 102g, 102s, 202) and having a third thickness greater than the first thickness.

[0219] [D2] A semiconductor device (100, 100a, 100b, 100c, 200) including: a semiconductor layer (101, 201) having a first thickness and having a main surface (101a, 201a); a main surface electrode (102, 102g, 102s, 202) disposed on the main surface (101a, 201a) and having a second thickness less than the first thickness; and a pad electrode (105, 105c, 105g, 105s, 105t, 205) disposed on the main surface electrode (102, 102g, 102s, 202) and having a third thickness greater than the first thickness.

[0220] [D3] A semiconductor layer (101, 201) having a first thickness and a principal surface (101a, 201a), a principal surface electrode (102, 102g, 102s, 202) disposed on the principal surface (101a, 201a) and having a second thickness less than the first thickness, and a semiconductor layer (101, 201) having a first thickness and a second ... a resin (106, 206) covering a peripheral portion of a main surface electrode (102, 102g, 102s, 202) and having a third thickness that exceeds the first thickness, and a pad electrode (105, 105c, 105g, 105s, 105t, 205) disposed on an inner portion of the main surface electrode (102, 102g, 102s, 202) and having a fourth thickness that exceeds the first thickness.

[0221] [D4] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of D1 to D3, wherein the semiconductor layer (101, 201) has a layered structure including a semiconductor substrate (101c, 201) and an epitaxial layer (101d).

[0222] [D5] The semiconductor device (100, 100a, 100b, 100c, 200) according to D4, wherein the semiconductor substrate (101c, 201) has a thickness less than a thickness of the epitaxial layer (101d).

[0223] [D6] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of D1 to D3, wherein the semiconductor layer (101, 201) has a single-layer structure made of an epitaxial layer (101d).

[0224] [E1] A semiconductor layer (101, 201) including a semiconductor substrate (101c, 201) having a first thickness and having a principal surface (101a, 201a), a principal surface electrode (102, 102g, 102s, 202) disposed on the principal surface (101a, 201a) and having a second thickness less than the first thickness, an insulating film (104, 204) covering a peripheral portion of the principal surface electrode (102, 102g, 102s, 202) so as to expose an inner portion of the principal surface electrode (102, 102g, 102s, 202), and a gate insulating film (104, 204) covering the peripheral portion of the principal surface electrode (102, 102g, 102s, 202) so as to expose an inner portion of the principal surface electrode (102, 102g, 102s, 202) and on the inner portion side of the principal surface electrode (102, 102g, 102s, 202), a resin (106, 206) covering the insulating film (104, 204) so ​​as to partially expose the insulating film; and a pad electrode (105, 105c, 105g, 105s, 105t, 205) arranged on an inner portion of the principal surface electrode (102, 102g, 102s, 202) and having a third thickness exceeding the first thickness, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) is in contact with the principal surface electrode (102, 102g, 102s, 202), the insulating film (104, 204), and the resin (106, 206) on the inner side of the principal surface electrode (102, 102g, 102s, 202).

[0225] [E2] The semiconductor device (100, 100a, 100b, 100c, 200) according to E1, wherein the resin (106, 206) has a fourth thickness that exceeds the first thickness of the semiconductor substrate (101c, 201).

[0226] [E3] The semiconductor device (100, 100a, 100b, 100c, 200) according to E1 or E2, wherein the resin (106, 206) covers a peripheral portion of the main surface (101a, 201a).

[0227] [E4] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of E1 to E3, wherein the resin (106, 206) is formed in a ring shape surrounding an inner portion of the main surface (101a, 201a) in a plan view.

[0228] [E5] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of E1 to E4, wherein the resin (106, 206) includes a thermosetting resin.

[0229] [E6] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of E1 to E5, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) has an electrode surface, and the resin (106, 206) has an outer surface continuous with the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205).

[0230] [E7] The semiconductor device (100, 100a, 100b, 100c, 200) according to E6, wherein the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205) is a ground surface, and the outer surface of the resin (106, 206) is a ground surface.

[0231] [E8] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of E1 to E7, wherein the insulating film (104, 204) has a thickness that is greater than the second thickness and less than the first thickness.

[0232] [E9] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of E1 to E8, wherein the insulating film (104, 204) contains a photosensitive resin.

[0233] [E10] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of E1 to E9, wherein the semiconductor layer (101, 201) includes an epitaxial layer (101d) stacked on the semiconductor substrate (101c, 201), and the pad electrode (105, 105c, 105g, 105s, 105t, 205) has the third thickness that exceeds a total thickness of the semiconductor substrate (101c, 201) and the epitaxial layer (101d).

[0234] [E11] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of E1 to E10, wherein the semiconductor layer (101, 201) includes a wide band gap semiconductor.

[0235] [E12] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of E1 to E11, wherein the semiconductor layer (101, 201) contains SiC. [Explanation of symbols]

[0236] 100 Semiconductor device 100a Semiconductor device 100b Semiconductor device 100c Semiconductor device 101 Semiconductor layer 101a First main surface (main surface) 101c Semiconductor substrate 101d epitaxial layer 102 1st electrode layer (main surface electrode) 102g 1st electrode layer (main surface electrode) 102s 1st electrode layer (main surface electrode) 104 Insulating film (photosensitive resin layer) 105 Plating layer (pad electrode) 105c Current sensing pad (pad electrode) 105g Gate pad (pad electrode) 105s Source pad (pad electrode) 105t Temperature sensing pad (pad electrode) 106 Mold layer (thermosetting resin layer) 200 Semiconductor device 201 Semiconductor layer (semiconductor substrate) 201a First main surface (main surface) 202 1st electrode layer (main surface electrode) 204 Insulating film (photosensitive resin layer) 205 Plating layer (pad electrode) 206 Mold layer (thermosetting resin layer)

Claims

1. a semiconductor layer having a first major surface and a second major surface facing away from the first major surface; A first electrode layer formed on the first major surface; A second electrode layer formed on the second major surface; an insulating film covering an end portion of the first electrode layer; a plating layer covering at least a portion of the first electrode layer other than the end portion; a mold layer covering the insulating film; the semiconductor layer includes a semiconductor substrate that constitutes the second main surface, The semiconductor device, wherein the thickness of the semiconductor substrate is thinner than the thickness of the plating layer.

2. 2. The semiconductor device according to claim 1, wherein the semiconductor substrate has a thickness of 5 [mu]m or more and 40 [mu]m or less.

3. The semiconductor device according to claim 1 , wherein the molding layer is annular in plan view and extends along an outer periphery of the semiconductor layer.

4. 4. The semiconductor device according to claim 1, wherein a surface of the plating layer and a surface of the mold layer are flush with each other.

5. 5. The semiconductor device according to claim 1, wherein the plating layer and the mold layer are in direct contact with each other.

6. 6. The semiconductor device according to claim 1, wherein the semiconductor layer is made of SiC.

7. The semiconductor device functions as a transistor, the semiconductor layer includes the semiconductor substrate and an epitaxial layer on the semiconductor substrate; the second electrode layer is a drain electrode of the transistor, 7. The semiconductor device according to claim 1, wherein the first electrode layer includes a source electrode of the transistor and a gate electrode of the transistor insulated from the source electrode.

8. 8. The semiconductor device according to claim 1, wherein the semiconductor device functions as a Schottky barrier diode with the first electrode layer as an anode and the second electrode layer as a cathode.

9. a semiconductor layer having a first main surface and a second main surface facing away from the first main surface, the first electrode layer being formed on the first main surface of the semiconductor layer including a semiconductor substrate constituting the second main surface; forming an insulating film covering an end portion of the first electrode layer; forming a plating layer covering at least a portion of the first electrode layer other than the end portion; forming a mold layer covering the insulating film; grinding the semiconductor substrate from the second main surface side until the thickness of the semiconductor substrate becomes thinner than the thickness of the plating layer; forming a second electrode layer on the second main surface of the semiconductor layer after the semiconductor substrate is ground; A method for manufacturing a semiconductor device.

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