Semiconductor light-emitting device

Abstract

To provide a semiconductor light-emitting device which can increase the output of short-wave infrared light.SOLUTION: A semiconductor light-emitting device 1 includes an InP substrate 10 and a semiconductor light-emitting laminate 20 supported by the InP substrate 10. The semiconductor light-emitting laminate 20 includes a semiconductor light-emitting layer 26 which can emit short-wave infrared light. A semiconductor light-emitting layer 26 has a multiquantum well structure including a well layer 28 and a barrier layer 27. The well layer 28 is formed of InGaAs or InGaAsP. The barrier layer 27 is formed of Iny(AlxGa1-x)1-y)As. x is greater than 0 and is 1 or smaller, and y is greater than 0 and is 1 or smaller.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to semiconductor light emitting devices. [Background technology]

[0002] Japanese Patent Application Laid-Open No. 2020-65041 (Patent Document 1) discloses a semiconductor light-emitting device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-65041 A [Summary]

[0004] An object of the present disclosure is to provide a semiconductor light emitting device capable of increasing the output of short wave infrared light.

[0005] The semiconductor light emitting device of the present disclosure includes an InP substrate and a semiconductor light emitting stack supported by the InP substrate. The semiconductor light emitting stack includes a semiconductor light emitting layer capable of emitting shortwave infrared light. The semiconductor light emitting layer has a multiple quantum well structure including a well layer and a barrier layer. The well layer is made of InGaAs or InGaAsP. The barrier layer is made of (In y (Al x Ga 1-x ) 1-y ) As, where x is greater than 0 and less than or equal to 1, and y is greater than 0 and less than or equal to 1. [Brief description of the drawings]

[0006]

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[0007] Details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be arbitrarily combined.

[0008] With reference to FIGS. 1 and 2, the semiconductor light-emitting device 1 according to the embodiment will be described. The semiconductor light-emitting device 1 is, for example, a light-emitting diode (LED). The semiconductor light-emitting device 1 includes an InP substrate 10, an anode electrode 13, a reflective layer 14, a current constriction layer 15, a semiconductor light-emitting laminate 20, and a cathode electrode 37.

[0009] The InP substrate 10 includes a main surface 11 and a main surface 12 opposite to the main surface 11. The main surfaces 11 and 12 each extend in the x direction and the y direction perpendicular to the x direction. The main surface 11 and the main surface 12 are spaced apart from each other in the z direction. The z direction is perpendicular to the x direction and the y direction and is the thickness direction of the InP substrate 10. The InP substrate 10 is, for example, a p-type InP substrate.

[0010] The reflective layer 14 is disposed on the main surface 11 of the InP substrate 10. The reflective layer 14 reflects the short-wave infrared light emitted from the semiconductor light-emitting laminate 20. The thickness of the reflective layer 14 is, for example, 0.1 μm or more and 3.0 μm or less. The reflective layer 14 is formed of, for example, Au or an alloy containing Au. The reflective layer 14 may be a single layer of an Au layer, a single layer of an Au alloy layer, a laminate of an Au layer and another metal layer, or a laminate of an Au alloy layer and another metal layer. When the reflective layer 14 is a laminate, the outermost surface of the reflective layer 14 proximal to the semiconductor light-emitting laminate 20 is preferably formed of an Au layer or an Au alloy layer (such as a gold-beryllium-nickel (AuBeNi) alloy, etc.). When the reflective layer 14 is a laminate, the reflective layer 14 is, for example, a laminate of Au / Ti (on the side of the current confinement layer 15) / Ti (on the side of the InP substrate 10).

[0011] The reflective layer 14 may be formed by bonding the growth substrate 40 (see FIG. 6) and the InP substrate 10 and joining the first metal layer 14a (see FIG. 6) and the second metal layer 14b (see FIG. 6). Therefore, a boundary (bonding surface) between the first metal layer 14a and the second metal layer 14b may exist in the reflective layer 14. Further, when the reflective layer 14 is formed of a plurality of metal materials, a clear boundary may not be formed between the plurality of metal materials, and the composition of the plurality of metal materials may gradually change in the thickness direction of the reflective layer 14.

[0012] The current confinement layer 15 is disposed between the InP substrate 10 and the semiconductor light-emitting laminate 20. Specifically, the current confinement layer 15 is disposed on the reflective layer 14. The current confinement layer 15 includes an insulating layer 16 and a plurality of conductive portions 17. The insulating layer 16 is formed of, for example, silicon dioxide (SiO 2 )).

[0013] The plurality of conductive portions 17 are disposed in the insulating layer 16. Specifically, the plurality of conductive portions 17 are formed in a plurality of through holes formed in the insulating layer 16. The plurality of conductive portions 17 are, for example, a plurality of conductive pillars. The plurality of conductive portions 17 are electrically connected to the semiconductor light-emitting laminate 20. Specifically, the plurality of conductive portions 17 are in contact with the reflective layer 14 and the p-type contact layer 22, and electrically connect the reflective layer 14 and the p-type contact layer 22. In a plan view (plan view of the main surface 11) from the stacking direction (z direction) of the semiconductor light-emitting laminate 20 and the InP substrate 10, each of the plurality of conductive portions 17 has a diameter of, for example, 5 μm or more and 15 μm or less. The plurality of conductive portions 17 are formed of, for example, a metal material such as Au or an alloy such as a gold-beryllium (AuBe) alloy.

[0014] The semiconductor light-emitting laminate 20 is supported by the InP substrate 10 via the reflective layer 14 and the current confinement layer 15. The semiconductor light-emitting laminate 20 is in contact with the current confinement layer 15. A mesa structure 2 may be formed in the semiconductor light-emitting laminate 20. The semiconductor light-emitting laminate 20 includes a p-type layer 21, a guide layer 25, a semiconductor light-emitting layer 26, a guide layer 29, and an n-type layer 31.

[0015] The p-type layer 21 is disposed on the current confinement layer 15. The p-type layer 21 includes a p-type contact layer 22, a p-type window layer 23, and a p-type cladding layer 24.

[0016] The p-type contact layer 22 is disposed closest to the InP substrate 10 in the semiconductor light-emitting laminate 20. The p-type contact layer 22 is disposed on the current confinement layer 15 and is in contact with the plurality of conductive portions 17. The p-type contact layer 22 is a low-resistance layer for making an ohmic contact with the plurality of conductive portions 17. The p-type contact layer 22 is, for example, the layer having the highest carrier concentration (hole concentration) in the p-type layer 21. The carrier concentration (hole concentration) of the p-type contact layer 22 is, for example, 1×10 19 cm -3The above is the case. The p-type contact layer 22 is a p-type AlGaAs layer or a p-type GaAs layer. The p-type contact layer 22 is, for example, an AlGaAs layer doped with zinc (Zn), or a GaAs layer doped with zinc (Zn).

[0017] The p-type window layer 23 is disposed on the p-type contact layer 22. The p-type window layer 23 is, for example, an InP layer doped with zinc (Zn). The carrier concentration (hole concentration) of the p-type window layer 23 is lower than the carrier concentration (hole concentration) of the p-type contact layer 22.

[0018] The p-type cladding layer 24 is disposed on the p-type window layer 23. The p-type cladding layer 24 is, for example, an InP layer doped with zinc (Zn). The carrier concentration (hole concentration) of the p-type cladding layer 24 is lower than the carrier concentration (hole concentration) of the p-type window layer 23.

[0019] The guide layer 25 is disposed on the p-type cladding layer 24. The guide layer 25 prevents the p-type dopant of the p-type layer 21 from diffusing into the semiconductor light-emitting layer 26. The guide layer 25 is, for example, an InAlGaAs layer. The guide layer 25 may be formed of the same material as the barrier layer 27.

[0020] The semiconductor light-emitting layer 26 is disposed on the guide layer 25. The semiconductor light-emitting layer 26 emits short-wavelength infrared light when current is injected into the semiconductor light-emitting device 1. The short-wavelength infrared light is light having a wavelength of 1000 nm or more and 2000 nm or less. The semiconductor light-emitting layer 26 is, for example, an undoped layer. The semiconductor light-emitting layer 26 has a multiple quantum well (MQW) structure in which the barrier layer 27 and the well layer 28 are alternately stacked. The barrier layer 27 is formed of (In y (Al x Ga 1-x ) 1-y )As, where x is greater than 0 and less than or equal to 1. x may be greater than or equal to 0.6 and less than or equal to 1. y is greater than 0 and less than or equal to 1. The well layer 28 is formed of InGaAs or InGaAsP.

[0021] The guide layer 29 is disposed on the semiconductor light-emitting layer 26. The guide layer 29 prevents the n-type dopant of the n-type layer 31 from diffusing into the semiconductor light-emitting layer 26. The guide layer 29 is, for example, an InAlGaAs layer. The guide layer 29 may be formed of the same material as the barrier layer 27.

[0022] The n-type layer 31 is disposed on the guide layer 29. The n-type layer 31 includes an n-type cladding layer 32, an n-type window layer 33, and an n-type contact layer 34.

[0023] The n-type cladding layer 32 is disposed on the guide layer 29. The n-type cladding layer 32 is, for example, an InP layer doped with silicon (Si).

[0024] The n-type window layer 33 is disposed on the n-type cladding layer 32. The n-type window layer 33 is, for example, an InP layer doped with silicon (Si). The carrier concentration (electron concentration) of the n-type window layer 33 is higher than that of the n-type cladding layer 32. An uneven structure 33a is formed on a portion of the surface of the n-type window layer 33 that is exposed from the n-type contact layer 34 and the cathode electrode 37. The uneven structure 33a improves the extraction efficiency of short-wave infrared light from the semiconductor light-emitting device 1.

[0025] The n-type contact layer 34 is disposed on the n-type window layer 33. The n-type contact layer 34 is a low-resistance layer for making an ohmic contact with the cathode electrode 37. The n-type contact layer 34 is, for example, the layer with the highest carrier concentration (electron concentration) among the n-type layers 31. The n-type contact layer 34 is, for example, an InP layer doped with selenium (Se).

[0026] The anode electrode 13 is disposed on the main surface 12 of the InP substrate 10. The anode electrode 13 is formed of, for example, a metal material such as Au or an alloy containing Au. In the present embodiment, the anode electrode 13 is, for example, a laminate of Ti / Au (on the side of the InP substrate 10).

[0027] The cathode electrode 37 is disposed on the semiconductor light-emitting laminate 20 (specifically, the n-type contact layer 34). The cathode electrode 37 is formed of, for example, a metal material such as Au or an alloy containing Au. In the present embodiment, the cathode electrode 37 is, for example, a laminate of AuGeNi / Au (on the n-type contact layer 34 side). The cathode electrode 37 includes a pad electrode 38 and a branched electrode 39.

[0028] To inject current into the semiconductor light-emitting device 1, a conductive wire (not shown) is bonded to the pad electrode 38. As shown in FIG. 1, in a plan view from the stacking direction (z direction) of the semiconductor light-emitting laminate 20 and the InP substrate 10, the pad electrode 38 is displaced in the first direction (+y direction) with respect to the center 20c of the semiconductor light-emitting laminate 20. In the above plan view, the pad electrode 38 does not overlap the center 20c of the semiconductor light-emitting laminate 20.

[0029] The branched electrode 39 is connected to the pad electrode 38. The branched electrode 39 extends from the pad electrode 38 so as to divide the semiconductor light-emitting laminate 20 into a plurality of regions in a plan view from the stacking direction (z direction) of the semiconductor light-emitting laminate 20 and the InP substrate 10 (plan view of the main surface 11). The branched electrode 39 includes an outer branched electrode 39a and an inner branched electrode 39b.

[0030] As shown in FIG. 1, the outer branched electrode 39a extends along the outer edge of the semiconductor light-emitting laminate 20 in a plan view from the stacking direction (z direction) of the semiconductor light-emitting laminate 20 and the InP substrate 10. The outer branched electrode 39a is connected to, for example, the central portion 38c of the pad electrode 38 in the first direction (+y direction).

[0031] As shown in FIG. 1, in a plan view from the stacking direction (z direction) of the semiconductor light-emitting laminate 20 and the InP substrate 10, the plurality of conductive portions 17 may be disposed only on the side in the second direction (-y direction) with respect to the outer branched electrode 39a.

[0032] In a plan view (plan view of the main surface 11) from the stacking direction (z direction) of the semiconductor light-emitting laminate 20 and the InP substrate 10, the inner branched electrode 39b is disposed on a region surrounded by the outer branched electrode 39a in the semiconductor light-emitting laminate 20. The inner branched electrode 39b is connected to, for example, an end portion 38a of the pad electrode 38. The end portion 38a of the pad electrode 38 is an end portion in the second direction (-y direction) opposite to the first direction (+y direction) of the pad electrode 38.

[0033] With reference to FIGS. 1 to 11, an example of a method for manufacturing the semiconductor light-emitting device 1 according to the present embodiment will be described.

[0034] With reference to FIG. 3, the semiconductor light-emitting laminate 20 is formed on the growth substrate 40. The growth substrate 40 includes a support substrate 41 and an etching stop layer 42. The support substrate 41 is, for example, an InP substrate. The etching stop layer 42 is disposed on the support substrate 41. The etching stop layer 42 is formed of, for example, InGaAs. The etching stop layer 42 is formed on the support substrate 41 by an epitaxial growth method such as, for example, a metalorganic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method.

[0035] The semiconductor light-emitting laminate 20 is formed on the growth substrate 40 (etching stop layer 42) by an epitaxial growth method such as, for example, a metalorganic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. The semiconductor light-emitting laminate 20 is formed by laminating, in order from the growth substrate 40 side, an n-type contact layer 34, an n-type window layer 33, an n-type clad layer 32, a guide layer 29, a semiconductor light-emitting layer 26, a guide layer 25, a p-type clad layer 24, a p-type window layer 23, and a p-type contact layer 22.

[0036] Referring to FIG. 4, a current constriction layer 15 is formed on the p-type contact layer 22. Specifically, an insulating layer 16 is formed on the p-type contact layer 22 by chemical vapor deposition (CVD). By etching a part of the insulating layer 16, a plurality of through holes are formed in the insulating layer 16. By vapor deposition, a plurality of conductive portions 17 are formed in the plurality of through holes. Thus, the current constriction layer 15 is formed.

[0037] Referring to FIG. 5, a first metal layer 14a is formed on the current constriction layer 15 by vapor deposition. The first metal layer 14a is formed of Au or an alloy containing Au. At least the outermost surface of the first metal layer 14a is formed of Au. Thus, a laminate including the semiconductor light-emitting laminate 20, the current constriction layer 15, and the first metal layer 14a is formed on the growth substrate 40.

[0038] Referring to FIG. 6, an InP substrate 10 is bonded to the laminate formed on the growth substrate 40. Specifically, a second metal layer 14b is formed on the main surface 11 of the InP substrate 10 by vapor deposition. The second metal layer 14b is formed of Au or an alloy containing Au. At least the outermost surface of the second metal layer 14b is formed of Au. Then, the first metal layer 14a and the second metal layer 14b are joined. The first metal layer 14a and the second metal layer 14b are joined, for example, by thermocompression bonding. The first metal layer 14a and the second metal layer 14b are joined to each other to form the reflective layer 14.

[0039] Referring to FIG. 7, the growth substrate 40 is removed. Specifically, the support substrate 41 is removed by wet etching. The etching stop layer 42 functions as an etching stop layer for this wet etching. Then, the etching stop layer 42 is removed by another etching. Thus, the growth substrate 40 is removed.

[0040] Referring to FIG. 8, the n-type contact layer 34 is patterned. Specifically, a resist 43 is formed on the n-type contact layer 34. The resist 43 has, for example, the same pattern as the cathode electrode 37. Then, using the resist 43 as a mask, the n-type contact layer 34 is etched. A part of the n-type contact layer 34 exposed from the resist 43 is removed, and an n-type contact layer 34 having the same pattern as the cathode electrode 37 is formed. The n-type window layer 33 is exposed from the resist 43 and the n-type contact layer 34 through the openings of the resist 43 and the n-type contact layer 34.

[0041] Referring to FIG. 9, for example, by a frosting process, an uneven structure 33a is formed on the surface of the n-type window layer 33 exposed from the resist 43. The frosting process may be performed by wet etching or by dry etching.

[0042] Referring to FIG. 10, the resist 43 is removed. A cathode electrode 37 is formed on the n-type contact layer 34. The cathode electrode 37 is formed, for example, by vapor deposition of a metal layer and removal of a part of the metal layer by a lift-off method.

[0043] Referring to FIG. 11, a mesa structure 2 is formed in the semiconductor light-emitting laminate 20. The mesa structure 2 is formed, for example, by wet etching the side surface of the semiconductor light-emitting laminate 20. Then, an anode electrode 13 is formed on the main surface 12 of the InP substrate 10, for example, by vapor deposition. Thus, the semiconductor light-emitting device 1 shown in FIGS. 1 and 2 is obtained.

[0044] The operation of the semiconductor light-emitting device 1 of the present embodiment will be described.

[0045] A voltage higher than that of the cathode electrode 37 is applied to the anode electrode 13 to apply a forward voltage V f to the semiconductor light-emitting device 1. A forward current I fA current flows. Holes are injected from the anode electrode 13 into the semiconductor light-emitting laminate 20 through the InP substrate 10, the reflective layer 14, and the plurality of conductive portions 17. Electrons are injected from the cathode electrode 37 into the semiconductor light-emitting laminate 20. Carriers (electrons and holes) are injected into the semiconductor light-emitting layer 26. In the semiconductor light-emitting layer 26, electrons and holes are combined, and the semiconductor light-emitting layer 26 emits short-wavelength infrared light. The short-wavelength infrared light is reflected by the reflective layer 14 and the plurality of conductive portions 17. The short-wavelength infrared light is taken out to the outside of the semiconductor light-emitting device 1 by the uneven structure 33a or the like. Thus, the semiconductor light-emitting device 1 emits short-wavelength infrared light.

[0046] While comparing the sample 1 of the semiconductor light-emitting device 1 of the present embodiment and the sample 2 of the semiconductor light-emitting device of the comparative example, the operation of the semiconductor light-emitting device 1 of the present embodiment will be described. The sample 2 has the same configuration as the sample 1, but is different from the sample 1 in the following points. In the sample 1, the barrier layer 27 and the guide layers 25 and 29 are lattice-matched to the InP substrate 10 (In y (Al x Ga 1-x ) 1-y )As (x = 0.8) P, and the p-type contact layer 22 is a zinc (Zn)-doped AlGaAs layer. On the other hand, in the sample 2, the barrier layer 27 and the guide layers 25 and 29 are formed of InP, and the p-type contact layer 22 is a zinc (Zn)-doped p-type InGaAsP layer.

[0047] Fig. 12 shows the output of the short-wavelength infrared light of the samples 1 and 2 when a forward current I f of 20 mA is passed through the samples 1 and 2. The wavelength of the short-wavelength infrared light emitted from the samples 1 and 2 is 1450 nm. As shown in Fig. 12, the output of the short-wavelength infrared light of the sample 1 is larger than the output of the short-wavelength infrared light of the sample 2. Thus, the reason why the output of the short-wavelength infrared light of the semiconductor light-emitting device 1 of the present embodiment is larger than the output of the short-wavelength infrared light of the semiconductor light-emitting device of the comparative example is considered as follows.

[0048] In the semiconductor light-emitting device 1 of the present embodiment, the boundary between the barrier layer 27 and the well layer 28 (see FIG. 13) is clearer and steeper than the boundary between the barrier layer 27 and the well layer 28 in the semiconductor light-emitting device of the comparative example (see FIG. 14). In addition, the barrier layer 27 of the present embodiment is formed of In y (Al x Ga 1-x ) 1-y )As, while the barrier layer 27 of the comparative example is formed of InP. Therefore, the bandgap energy of the barrier layer 27 of the present embodiment is larger than the bandgap energy of the barrier layer 27 of the comparative example. The difference in bandgap energy between the well layer 28 and the barrier layer 27 in the present embodiment is larger than the difference in bandgap energy between the well layer 28 and the barrier layer 27 in the comparative example. Therefore, in the present embodiment, the confinement of carriers (holes and electrons) in the well layer 28 is improved more than in the comparative example, and the light emission efficiency in the semiconductor light-emitting layer 26 is improved. As a result, the output of short-wavelength infrared light of the semiconductor light-emitting device 1 of the present embodiment becomes larger than the output of short-wavelength infrared light of the semiconductor light-emitting device of the comparative example.

[0049] FIG. 15 shows the forward voltage V f of samples 1 and 3 of the semiconductor light-emitting device 1 of the present embodiment when a forward current I f of 20 mA is passed through them. Sample 3 is configured in the same manner as sample 1, but sample 3 is different from sample 1 in that the p-type contact layer 22 is a p-type InGaAsP layer doped with zinc (Zn). The wavelength of the short-wavelength infrared light emitted from samples 1 and 3 is 1450 nm. As shown in FIG. 15, the forward voltage V f of sample 1 is smaller than the forward voltage V f of sample 3. Thus, the reason why the forward voltage V f of sample 1 is smaller than the forward voltage V f of sample 3 is considered as follows.

[0050] Since the p-type contact layer 22 of Sample 3 is a p-type InGaAsP layer doped with zinc (Zn), the carrier concentration of the p-type contact layer 22 of Sample 3 remains at 3.0×10 18 cm -3 . In contrast, since the p-type contact layer 22 of Sample 1 is a p-type AlGaAs layer doped with zinc (Zn), the carrier concentration of the p-type contact layer 22 of Sample 1 increases to 2.0×10 19 cm -3 .

[0051] Thus, by adopting a p-type AlGaAs layer or a p-type GaAs layer as the p-type contact layer 22, it becomes possible to dope more p-type dopants into the p-type contact layer 22. The carrier concentration of the p-type contact layer 22 can be increased to, for example, 1×10 19 cm -3 or more. Therefore, the ohmic contact between the plurality of conductive portions 17 and the p-type contact layer 22 is improved. The forward voltage V f of the semiconductor light-emitting device 1 decreases.

[0052] A modification of this embodiment will be described.

[0053] As in the semiconductor light-emitting device 1 of the first modification shown in FIG. 16, the outer branched electrode 39a may be connected to the end portion 38b of the pad electrode 38. The end portion 38b of the pad electrode 38 is the end portion of the pad electrode 38 in the first direction (+y direction). As in the semiconductor light-emitting device 1 of the second modification shown in FIG. 17, the cathode electrode 37 may include two inner branched electrodes 39b. As in the semiconductor light-emitting device 1 of the third modification shown in FIG. 18, in the semiconductor light-emitting device 1 of the first modification shown in FIG. 16, the cathode electrode 37 may include two inner branched electrodes 39b. In the second and third modifications, the inner branched electrode 39b may be connected to a portion between the end portion 38a and the central portion 38c of the pad electrode 38. As in the semiconductor light-emitting device 1 of the fourth modification shown in FIG. 19, the branched electrode 39 may extend radially from the pad electrode 38.

[0054] Figure 20 shows the output of short-wavelength infrared light of Sample 1 of the present embodiment, the output of short-wavelength infrared light of Sample 4 of the first modification of the present embodiment, the output of short-wavelength infrared light of Sample 5 of the second modification of the present embodiment, the output of short-wavelength infrared light of Sample 6 of the third modification of the present embodiment, and the output of short-wavelength infrared light of Sample 7 of the fourth modification of the present embodiment. Samples 1, 4 - 7 have the same configuration except for the cathode electrode 37. The output of short-wavelength infrared light of each of Samples 1, 4 - 7 is the output of short-wavelength infrared light when a current of 20 mA is passed through each of Samples 1, 4 - 7. The wavelength of the short-wavelength infrared light emitted from Samples 1, 4 - 7 is 1450 nm. Also, in Figure 20, each of these outputs is normalized by the output of short-wavelength infrared light of Sample 1.

[0055] As shown in Figure 20, the output of short-wavelength infrared light of each of Samples 1, 4 - 6 is larger than the output of short-wavelength infrared light of Sample 7. The reason is considered as follows.

[0056] First, in a plan view in the stacking direction (z direction) of the semiconductor light-emitting laminate 20 and the InP substrate 10, the intensity of the short-wavelength infrared light is the highest at the center 20c of the semiconductor light-emitting laminate 20 in the semiconductor light-emitting laminate 20. In Sample 7, in the above-mentioned plan view, since the pad electrode 38 overlaps the center 20c of the semiconductor light-emitting laminate 20, the absorption of the short-wavelength infrared light by the pad electrode 38 increases. On the other hand, in Samples 1, 4 - 6, in the above-mentioned plan view, since the pad electrode 38 does not overlap the center 20c of the semiconductor light-emitting laminate 20, the absorption of the short-wavelength infrared light by the pad electrode 38 decreases. Therefore, the output of short-wavelength infrared light of each of Samples 1, 4 - 6 becomes larger than the output of short-wavelength infrared light of Sample 7.

[0057] Second, in Samples 1, 4 - 6, in a plan view in the stacking direction (z - direction) of the semiconductor light - emitting laminate 20 and the InP substrate 10, the plurality of conductive portions 17 are arranged only on the side in the second direction (-y direction) with respect to the outer branched electrode 39a. The second direction is opposite to the first direction (+y direction) in which the pad electrode 38 is displaced with respect to the center 20c of the semiconductor light - emitting laminate 20. Therefore, in Samples 1, 4 - 6, compared with Sample 7, the forward current I f density passing through the plurality of conductive portions 17 increases. The output of the short - wavelength infrared light of each of Samples 1, 4 - 6 becomes larger than the output of the short - wavelength infrared light of Sample 7.

[0058] As shown in FIG. 20, from the comparison between Sample 1 and Sample 4, the output of the short - wavelength infrared light of the semiconductor light - emitting device 1 when the outer branched electrode 39a is connected to the central portion 38c of the pad electrode 38 as in Sample 1 is larger than the output of the short - wavelength infrared light of the semiconductor light - emitting device 1 when the outer branched electrode 39a is connected to the end portion 38a of the pad electrode 38 as in Sample 4. Similarly, from the comparison between Sample 5 and Sample 6, the output of the short - wavelength infrared light of the semiconductor light - emitting device 1 when the outer branched electrode 39a is connected to the central portion 38c of the pad electrode 38 as in Sample 5 is larger than the output of the short - wavelength infrared light of the semiconductor light - emitting device 1 when the outer branched electrode 39a is connected to the end portion 38a of the pad electrode 38 as in Sample 6. The reason for this is that in a plan view in the stacking direction (z - direction) of the semiconductor light - emitting laminate 20 and the InP substrate 10, the area of the outer branched electrode 39a decreases, and the absorption of the short - wavelength infrared light by the outer branched electrode 39a decreases.

[0059] In the semiconductor light - emitting device 1, the guide layers 25, 29 may be omitted. The number of semiconductor light - emitting layers 26 included in the semiconductor light - emitting device 1 may be two or more. The semiconductor light - emitting device 1 may be a laser diode (LD).

[0060] The effects of the semiconductor light - emitting device 1 of the present embodiment will be described.

[0061] The semiconductor light-emitting device 1 of this embodiment includes an InP substrate 10 and a semiconductor light-emitting laminate 20 supported by the InP substrate 10. The semiconductor light-emitting laminate 20 includes a semiconductor light-emitting layer 26 capable of emitting short-wavelength infrared light. The semiconductor light-emitting layer 26 has a multiple quantum well structure including a well layer 28 and a barrier layer 27. The well layer 28 is formed of InGaAs or InGaAsP. The barrier layer 27 is formed of (In y (Al x Ga 1-x ) 1-y )As. x is greater than 0 and less than or equal to 1, and y is greater than 0 and less than or equal to 1.

[0062] As the boundary between the barrier layer 27 and the well layer 28 becomes steeper, the difference in bandgap energy between the well layer 28 and the barrier layer 27 increases. Therefore, the confinement of carriers (holes and electrons) in the well layer 28 is improved, and the light emission efficiency in the semiconductor light-emitting layer 26 is improved. The output of the short-wavelength infrared light of the semiconductor light-emitting device 1 increases.

[0063] In the semiconductor light-emitting device 1 of this embodiment, x is 0.6 or more and 1 or less.

[0064] As the aluminum composition ratio of the barrier layer 27 increases and the band energy of the barrier layer 27 increases, the difference in bandgap energy between the well layer 28 and the barrier layer 27 increases. Therefore, the confinement of carriers (holes and electrons) in the well layer 28 is improved, and the light emission efficiency in the semiconductor light-emitting layer 26 is improved. The output of the short-wavelength infrared light of the semiconductor light-emitting device 1 increases.

[0065] In the semiconductor light-emitting device 1 of this embodiment, the semiconductor light-emitting laminate 20 further includes a p-type contact layer 22. The p-type contact layer 22 is disposed closest to the InP substrate 10 in the semiconductor light-emitting laminate 20 and is a p-type AlGaAs layer or a p-type GaAs layer.

[0066] Therefore, the carrier concentration of the p-type contact layer 22 can be increased. The forward voltage V f of the semiconductor light-emitting device 1 decreases.

[0067] The semiconductor light-emitting device 1 of the present embodiment further includes a cathode electrode 37 disposed on the semiconductor light-emitting laminate 20. The cathode electrode 37 includes a pad electrode 38. In a plan view from the stacking direction (z direction) of the semiconductor light-emitting laminate 20 and the InP substrate 10, the pad electrode 38 does not overlap with the center 20c of the semiconductor light-emitting laminate 20.

[0068] Since the absorption of short-wavelength infrared light by the pad electrode 38 is reduced, the output of short-wavelength infrared light of the semiconductor light-emitting device 1 increases.

[0069] The semiconductor light-emitting device 1 of the present embodiment further includes a current constriction layer 15 disposed between the InP substrate 10 and the semiconductor light-emitting laminate 20. The current constriction layer 15 includes an insulating layer 16 and a plurality of conductive portions 17. The plurality of conductive portions 17 are disposed in the insulating layer 16 and are electrically connected to the semiconductor light-emitting laminate 20. The cathode electrode 37 is connected to the pad electrode 38 and includes an outer branched electrode 39a extending along the outer edge of the semiconductor light-emitting laminate 20 in a plan view from the stacking direction (z direction) of the semiconductor light-emitting laminate 20 and the InP substrate 10. In the above plan view, the pad electrode 38 is displaced and disposed in a first direction (+y direction) with respect to the center 20c of the semiconductor light-emitting laminate 20. In the above plan view, the plurality of conductive portions 17 are disposed only on the side in a second direction (-y direction) opposite to the first direction with respect to the outer branched electrode 39a.

[0070] Therefore, the density of the forward current I passing through the plurality of conductive portions 17 f increases. The output of short-wavelength infrared light of the semiconductor light-emitting device 1 increases.

[0071] In the semiconductor light-emitting device of the present embodiment, the outer branched electrode 39a is connected to the central portion 38c of the pad electrode 38 in the first direction (+y direction).

[0072] Therefore, the output of short-wavelength infrared light of the semiconductor light-emitting device 1 increases.

[0073] Hereinafter, aspects of the present disclosure will be collectively described as appendices. (Appendix 1) An InP substrate, and a semiconductor light-emitting laminate supported by the InP substrate, wherein the semiconductor light-emitting laminate includes a semiconductor light-emitting layer capable of emitting short-wave infrared light, the semiconductor light-emitting layer has a multiple quantum well structure including a well layer and a barrier layer, the well layer is formed of InGaAs or InGaAsP, the barrier layer is (In y (Al x Ga 1-x ) 1-y )As, where x is greater than 0 and less than or equal to 1, and y is greater than 0 and less than or equal to 1, a semiconductor light-emitting device. (Appendix 2) The semiconductor light-emitting device according to Appendix 1, wherein x is greater than or equal to 0.6 and less than or equal to 1. (Appendix 3) The semiconductor light-emitting laminate further includes a p-type contact layer, the p-type contact layer is disposed closest to the InP substrate in the semiconductor light-emitting laminate, and is a p-type AlGaAs layer or a p-type GaAs layer, the semiconductor light-emitting device according to Appendix 1 or Appendix 2. (Appendix 4) The semiconductor light-emitting device further includes a cathode electrode disposed on the semiconductor light-emitting laminate, the cathode electrode includes a pad electrode, in a plan view from the stacking direction of the semiconductor light-emitting laminate and the InP substrate, the pad electrode does not overlap the center of the semiconductor light-emitting laminate, the semiconductor light-emitting device according to any one of Appendices 1 to 3. (Appendix 5) The semiconductor light-emitting device further includes a current constriction layer disposed between the InP substrate and the semiconductor light-emitting laminate, the current constriction layer includes an insulating layer and a plurality of conductive portions disposed in the insulating layer, the plurality of conductive portions are disposed in the insulating layer and are electrically connected to the semiconductor light-emitting laminate, The cathode electrode is connected to the pad electrode and includes an outer branched electrode extending along the outer edge of the semiconductor light-emitting laminate in the plan view. In the plan view, the pad electrode is arranged to be displaced in a first direction with respect to the center of the semiconductor light-emitting laminate. The semiconductor light-emitting device according to Supplementary Note 4, wherein, in the plan view, the plurality of conductive portions are arranged only on a side in a second direction opposite to the first direction with respect to the outer branched electrode. (Supplementary Note 6) The semiconductor light-emitting device according to Supplementary Note 5, wherein the outer branched electrode is connected to a central portion of the pad electrode in the first direction.

[0074] The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Explanation of Reference Numerals

[0075] 1 Semiconductor light-emitting device, 2 Mesa structure, 10 InP substrate, 11, 12 Main surfaces, 13 Anode electrode, 14 Reflective layer, 14a First metal layer, 14b Second metal layer, 15 Current constriction layer, 16 Insulating layer, 17 Conductive portion, 20 Semiconductor light-emitting laminate, 20c Center, 21 p-type layer, 22 p-type contact layer, 23 p-type window layer, 24 p-type clad layer, 25, 29 Guide layer, 26 Semiconductor light-emitting layer, 27 Barrier layer, 28 Well layer, 31 n-type layer, 32 n-type clad layer, 33 n-type window layer, 33a Concavo-convex structure, 34 n-type contact layer, 37 Cathode electrode, 38 Pad electrode, 38a, 38b End portions, 38c Central portion, 39 Branched electrode, 39a Outer branched electrode, 39b Inner branched electrode, 40 Growth substrate, 41 Support substrate, 42 Etching stop layer, 43 Resist.

Claims

1. An InP substrate, and a semiconductor light-emitting laminate supported by the InP substrate, wherein the semiconductor light-emitting laminate includes a semiconductor light-emitting layer capable of emitting short-wavelength infrared light, the semiconductor light-emitting layer has a multiple quantum well structure including a well layer and a barrier layer, and the well layer is formed of InGaAs or InGaAsP. The barrier layer is (In ｙ (Al ｘ Ga １－ｘ ) １－ｙ )As, where x is greater than 0 and less than or equal to 1, and y is greater than 0 and less than or equal to 1, a semiconductor light-emitting device.

2. The semiconductor light-emitting device according to claim 1, wherein x is 0.6 or more and 1 or less.

3. The semiconductor light-emitting laminate further includes a p-type contact layer, wherein the p-type contact layer is disposed closest to the InP substrate in the semiconductor light-emitting laminate and is a p-type AlGaAs layer or a p-type GaAs layer. The semiconductor light-emitting device according to claim 1 or claim 2.

4. The semiconductor light-emitting device further includes a cathode electrode disposed on the semiconductor light-emitting laminate, wherein the cathode electrode includes a pad electrode, and in a plan view from the stacking direction of the semiconductor light-emitting laminate and the InP substrate, the pad electrode does not overlap the center of the semiconductor light-emitting laminate. The semiconductor light-emitting device according to claim 1 or claim 2.

5. The semiconductor light-emitting device further includes a current constriction layer disposed between the InP substrate and the semiconductor light-emitting laminate, wherein the current constriction layer includes an insulating layer and a plurality of conductive portions, the plurality of conductive portions are disposed in the insulating layer and are electrically connected to the semiconductor light-emitting laminate, the cathode electrode is connected to the pad electrode and includes an outer branched electrode extending along the outer edge of the semiconductor light-emitting laminate in the plan view, in the plan view, the pad electrode is displaced in a first direction with respect to the center of the semiconductor light-emitting laminate, and in the plan view, the plurality of conductive portions are disposed only on a side in a second direction opposite to the first direction with respect to the outer branched electrode. The semiconductor light-emitting device according to claim 4.

6. The semiconductor light-emitting device according to claim 5, wherein the outer branched electrode is connected to a central portion of the pad electrode in the first direction.

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