Semiconductor device

Abstract

To provide a semiconductor device enabling a reduction in manufacturing costs.SOLUTION: A semiconductor device 10A comprises: a semiconductor element 30; a first organic substrate 40 that is provided to coat at least an outer peripheral edge of an upper surface of an electrode pad 32; a wiring layer 70 that is provided on an upper surface of the first organic substrate 40; and a conductive layer A1 that is formed on a lower surface of the semiconductor element 30. The semiconductor device 10A comprises: a second organic substrate 50 that is provided to coat at least an outer peripheral edge of a lower surface of the conductive layer A1; and an encapsulation 60 that encapsulates the semiconductor element 30 which is provided between the first organic substrate 40 and the second organic substrate 50. The conductive layer A1 comprises an electrode pad 31. The first organic substrate 40 comprises: a first substrate body 41; and a first adhesion layer 42 that is formed on a lower surface of the first substrate body 41 and is bonded to an upper surface of the semiconductor element 30. The second organic substrate 50 comprises: a second substrate body 51; and a second adhesion layer 52 that is formed on an upper surface of the second substrate body 51 and is bonded to a lower surface of the conductive layer A1.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Conventionally, as a semiconductor device, a power semiconductor device (power module) that controls power and supplies power is known (see, for example, Patent Document 1). As this type of semiconductor device, there is known one having a semiconductor element mounted between a lower substrate and an upper substrate, a sealing resin that seals the semiconductor element provided between the lower substrate and the upper substrate, and a wiring layer formed on the upper surface of the upper substrate. In this type of semiconductor device, a ceramic substrate is used as the lower substrate, and an organic substrate is used as the upper substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above semiconductor device, reduction of manufacturing cost is desired.

Means for Solving the Problems

[0005] According to one aspect of the present invention, there is provided one or more semiconductor elements having a first electrode pad formed on the lower surface and a second electrode pad formed on the upper surface, a first organic substrate provided on the upper surface of the semiconductor element so as to cover at least the outer peripheral edge of the upper surface of the second electrode pad, a first wiring layer provided on the upper surface of the first organic substrate and electrically connected to the second electrode pad, a conductive layer formed on the lower surface of the semiconductor element, a second organic substrate provided on the lower surface of the conductive layer so as to cover at least the outer peripheral edge of the lower surface of the conductive layer, and a sealing resin for sealing the semiconductor element provided between the first organic substrate and the second organic substrate. The conductive layer has the first electrode pad. The first organic substrate has a first substrate body and a first adhesive layer formed on the lower surface of the first substrate body and adhered to the upper surface of the semiconductor element. The second organic substrate has a second substrate body and a second adhesive layer formed on the upper surface of the second substrate body and adhered to the lower surface of the conductive layer.

Advantages of the Invention

[0006] According to one aspect of the present invention, there is an effect that the manufacturing cost can be reduced.

Brief Description of the Drawings

[0007]

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[0008] Hereinafter, each embodiment will be described with reference to the accompanying drawings. Note that, for convenience, the accompanying drawings may show an enlarged view of a characteristic part in order to make the characteristic easier to understand, and the dimensional ratios of the respective components may be different in each drawing. In the cross-sectional view, in order to make the cross-sectional structure of each member easier to understand, the hatching of some members is shown by a satin pattern instead, and the hatching of some members is omitted. In the plan view, hatching is applied to some members in order to make the planar shape of each member easier to understand. In this specification, "plan view" means viewing an object from the vertical direction (up and down direction) of FIG. 1, and "planar shape" means the shape of an object viewed from the vertical direction of FIG. 1. The "up and down direction" and "left and right direction" in this specification are the directions when the reference signs indicating each member in each drawing can be correctly read in the correct position.

[0009] (First Embodiment) Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 9. (Overall Configuration of Semiconductor Device 10A) First, with reference to FIG. 1, the overall configuration of the semiconductor device 10A will be described.

[0010] The semiconductor device 10A is, for example, a power system semiconductor device (power module) that controls and supplies power. For example, the semiconductor device 10A is a DC-DC converter. The semiconductor device 10A includes a metal plate 20, a joint portion 21, one or more (in this embodiment, four) semiconductor elements 30, and a first organic substrate 40 provided on the upper surface of the semiconductor element 30. The semiconductor device 10A includes a second organic substrate 50 provided on the lower surface of the metal plate 20, a sealing resin 60 that seals the semiconductor element 30, and a wiring layer 70 provided on the upper surface of the first organic substrate 40. In the semiconductor device 10A, the semiconductor element 30 is built in between the first organic substrate 40 and the second organic substrate 50.

[0011] (Configuration of Semiconductor Element 30) Each semiconductor element 30 is joined to the upper surface of the metal plate 20 via the joint portion 21. Each semiconductor element 30 is formed of, for example, silicon (Si) or silicon carbide (SiC). Each semiconductor element 30 is, for example, a power system semiconductor element. For example, as the semiconductor element 30, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a diode, or the like can be used. Each semiconductor element 30 of this embodiment is a MOSFET. The thickness of each semiconductor element 30 can be, for example, about 50 μm to 600 μm. The plurality of semiconductor elements 30 are, for example, formed to have the same thickness as each other. The thermal expansion coefficient of each semiconductor element 30 can be, for example, about 3 ppm / °C to 6 ppm / °C.

[0012] As shown in FIG. 2, the planar shape of each semiconductor element 30 is formed, for example, in a rectangular shape. Note that the planar shape of each semiconductor element 30 is not limited to a rectangular shape and can be any shape. The planar shapes of the four semiconductor elements 30 are formed, for example, in the same shape as each other. The four semiconductor elements 30 are provided, for example, apart from each other in a plane direction orthogonal to the stacking direction of the semiconductor device 10A. For example, the four semiconductor elements 30 are arranged side by side along the left - right direction in the figure and are also arranged side by side along the up - down direction in the figure.

[0013] As shown in FIG. 1, the semiconductor element 30 has, for example, an electrode pad 31, an electrode pad 32, and an electrode pad 33. The electrode pad 31 is formed, for example, on the lower surface of the semiconductor element 30. The electrode pad 31 is formed, for example, so as to cover the entire lower surface of the semiconductor element 30. The electrode pads 32 and 33 are formed, for example, on the upper surface of the semiconductor element 30. The electrode pads 32 and 33 are provided apart from each other on the upper surface of the semiconductor element 30. The electrode pad 31 is, for example, the drain electrode of the MOSFET. The electrode pad 32 is, for example, the source electrode of the MOSFET. The electrode pad 33 is, for example, the gate electrode of the MOSFET.

[0014] As the material of the electrode pads 31, 32, and 33, for example, metals such as aluminum (Al) and copper (Cu), or an alloy containing at least one metal selected from these metals can be used. Note that, if necessary, a surface treatment layer may be formed on the surfaces of the electrode pads 31, 32, and 33. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating the Ni layer and the Au layer in this order), a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating the Ni layer, the Pd layer, and the Au layer in this order), and the like. As these Au layer, Ni layer, and Pd layer, for example, a metal layer formed by electroless plating (electroless plating metal layer) can be used. Also, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

[0015] (Configuration of Metal Plate 20) The metal plate 20 is formed in a flat plate shape. As the material of the metal plate 20, for example, metals such as aluminum and copper, or alloys containing at least one metal selected from these metals can be used. The metal plate 20 of the present embodiment is a copper plate.

[0016] As shown in FIG. 2, the planar shape of the metal plate 20 is formed, for example, in a rectangular shape. Note that the planar shape of the metal plate 20 is not limited to a rectangular shape and can be any shape. The planar size of the metal plate 20 is formed, for example, larger than the planar size of each semiconductor element 30. The metal plate 20 is provided so as to overlap, in plan view, the entirety of, for example, four semiconductor elements 30. The thickness of the metal plate 20 can be, for example, about 200 μm to 400 μm. The coefficient of thermal expansion of the metal plate 20 can be, for example, about 15 ppm / °C to 18 ppm / °C.

[0017] (Configuration of Joint Portion 21) As shown in FIG. 1, semiconductor elements 30 are joined to the upper surface of the metal plate 20 via a conductive joint portion 21. The joint portion 21 electrically connects the metal plate 20 and the electrode pads 31 of the semiconductor elements 30.

[0018] The joint portion 21 is provided, for example, individually for a plurality of semiconductor elements 30. Each joint portion 21 of the present embodiment is joined to the electrode pad 31 of each semiconductor element 30 and is also joined to the metal plate 20. Thereby, each electrode pad 31 and the metal plate 20 are electrically connected to each other via each joint portion 21.

[0019] As the material of the joint portion 21, for example, a sintered metal material can be used. As the sintered material, for example, a sintered material mainly composed of silver (Ag) particles (silver sintering material) or a sintered material mainly composed of copper particles (copper sintering material) can be used. Further, as the material of the joint portion 21, for example, solder, a conductive paste such as silver paste, or a metal brazing material can also be used. The thickness of the joint portion 21 can be, for example, about 10 μm to 60 μm.

[0020] In the semiconductor device 10A, the conductive layer A1 is constituted by the electrode pad 31, the joint portion 21, and the metal plate 20. (Configuration of the first organic substrate 40) The first organic substrate 40 is provided on the upper surface of the semiconductor element 30. The first organic substrate 40 is formed in a flat plate shape. The first organic substrate 40 is formed so as to cover at least the outer peripheral edge of the upper surface of the electrode pad 32. The first organic substrate 40 is formed so as to cover, for example, the entire upper surface of the electrode pad 32. The first organic substrate 40 is formed so as to cover at least the outer peripheral edge of the upper surface of the electrode pad 33. The first organic substrate 40 is formed so as to cover the entire upper surface of the electrode pad 33.

[0021] As shown in FIG. 2, the planar shape of the first organic substrate 40 is formed, for example, in a rectangular shape. The planar shape of the first organic substrate 40 is not limited to a rectangular shape and can be any shape. The planar size of the first organic substrate 40 is formed, for example, larger than the planar size of each semiconductor element 30. The first organic substrate 40 is provided so as to overlap, for example, the entire four semiconductor elements 30 in plan view. The planar size of the first organic substrate 40 is formed, for example, larger than the planar size of the metal plate 20. The planar size of the first organic substrate 40 is formed, for example, slightly larger than the planar size of the metal plate 20. The first organic substrate 40 is provided so as to overlap, for example, the entire metal plate 20 in plan view.

[0022] As shown in FIG. 1, the first organic substrate 40 has, for example, a first substrate body 41 and a first adhesive layer 42 formed on the lower surface of the first substrate body 41. The first substrate body 41 is made of an organic material. The first substrate body 41 is made of a high breakdown voltage resin material. That is, as the material of the first substrate body 41, an insulating resin with a high breakdown voltage (dielectric breakdown voltage) can be used. As the material of the first substrate body 41, for example, an insulating resin such as polyimide resin or polyester resin can be used. The first substrate body 41 of the present embodiment is made of polyimide resin. The breakdown voltage of the first substrate body 41 is, for example, higher than the breakdown voltage of the encapsulating resin 60. The breakdown voltage of the first substrate body 41 is, for example, 200 kV / mm or more. The breakdown voltage of the first substrate body 41 is preferably 300 kV / mm or more, and more preferably 350 kV / mm or more. The breakdown voltage of the first substrate body 41 of the present embodiment is 380 kV / mm. Note that the thickness of the first substrate body 41 can be, for example, about 30 μm to 150 μm.

[0023] As the first adhesive layer 42, for example, an epoxy-based, polyimide-based, or silicone-based adhesive can be used. The thickness of the first adhesive layer 42 can be, for example, about 15 μm to 45 μm. The thermal expansion coefficient of the first organic substrate 40 can be, for example, about 20 ppm / °C to 27 ppm / °C.

[0024] The first substrate body 41 is adhered to the upper surface of the semiconductor element 30 by, for example, the first adhesive layer 42. The first adhesive layer 42 is adhered to the upper surface of the semiconductor element 30 and also adhered to the lower surface of the first substrate body 41. The first adhesive layer 42 is provided so as to incorporate, for example, a part of the semiconductor element 30. In other words, a part of the semiconductor element 30 is embedded in the first adhesive layer 42. For example, the electrode pads 32, 33 of the semiconductor element 30 are embedded in the first adhesive layer 42. The first adhesive layer 42 is formed so as to cover the side surfaces of the electrode pads 32, 33, for example.

[0025] The first organic substrate 40 is formed with a plurality of through-holes 43 that penetrate the first organic substrate 40 in the thickness direction. Each through-hole 43 is formed, for example, so as to penetrate the first substrate body 41 and the first adhesive layer 42 in the thickness direction. The through-hole 43 is formed, for example, so as to expose a part of the upper surfaces of the electrode pads 32 and 33.

[0026] (Configuration of the wiring layer 70) The wiring layer 70 is formed on the upper surface of the first organic substrate 40. The wiring layer 70 has one or more (here, one) wiring patterns 71 and one or more (here, one) wiring patterns 72.

[0027] As the material of the wiring patterns 71 and 72, for example, copper or a copper alloy can be used. Incidentally, if necessary, a surface treatment layer may be formed on the surfaces (upper surface and side surfaces, or only the upper surface) of the wiring patterns 71 and 72. Examples of the surface treatment layer include metal layers such as an Au layer, a Ni layer / Au layer, and a Ni layer / Pd layer / Au layer. Incidentally, the thickness of the wiring patterns 71 and 72 can be, for example, about 50 μm to 200 μm. The coefficient of thermal expansion of the wiring layer 70 can be, for example, about 15 ppm / °C to 18 ppm / °C.

[0028] As shown in FIG. 2, the wiring patterns 71 and 72 are provided apart from each other on the upper surface of the first organic substrate 40. The planar shapes of the wiring patterns 71 and 72 can be any shape.

[0029] (Configuration of the wiring pattern 71) As shown in FIG. 1, the wiring pattern 71 is electrically connected to the electrode pad 32 via, for example, a via wiring V1 formed in a through hole 43 that exposes a part of the upper surface of the electrode pad 32. The wiring pattern 71 is formed integrally with, for example, the via wiring V1. The wiring pattern 71 of the present embodiment is formed integrally with a plurality of via wirings V1. The plurality of via wirings V1 are provided, for example, apart from each other in the planar direction (left - right direction in the figure). Each via wiring V1 is formed, for example, so as to fill the through hole 43. Each via wiring V1 is formed so as to penetrate the first substrate body 41 and the first adhesive layer 42 in the thickness direction.

[0030] As shown in FIG. 2, the planar shape of the wiring pattern 71 is formed, for example, in a rectangular shape as a whole. The wiring pattern 71 is formed, for example, so as to spread over the entire upper surface of the first organic substrate 40. The wiring pattern 71 has, for example, an opening 71X provided at the planar center of the wiring pattern 71 and an opening 71Y extending from the opening 71X in the planar direction (here, the left - right direction in the figure). The openings 71X and 71Y are formed so as to penetrate the wiring pattern 71 in the thickness direction.

[0031] The opening 71X is provided so as to be able to accommodate the wiring pattern 72 therein. The planar shape of the opening 71X is formed in a shape along the outer edge of the wiring pattern 72. The planar shape of the opening 71X is formed, for example, in an H shape as a whole. The wiring pattern 71 is formed so as to surround the outer periphery of the wiring pattern 72 by having the opening 71X. The wiring pattern 71 is provided so as to overlap a part of the semiconductor element 30 in a plan view. The wiring pattern 71 is provided so as to overlap the electrode pad 32 of the semiconductor element 30 in a plan view. The wiring pattern 71 is provided so as to overlap, for example, all of the four electrode pads 32 in a plan view. The wiring pattern 71 is, for example, electrically connected to the four electrode pads 32. And the wiring pattern 71 is formed so as to connect the four electrode pads 32 to each other. In other words, the four electrode pads 32 are electrically connected to each other via the wiring pattern 71. The wiring pattern 71 is provided so as not to overlap the electrode pad 33 of the semiconductor element 30 in a plan view.

[0032] The opening 71Y is formed so as to communicate with the opening 71X. The opening 71Y extends from the opening 71X to the outer surface of the wiring pattern 71 along the planar direction (left - right direction in the figure). The opening 71Y has, for example, a predetermined width in the up - down direction in the figure and is formed in a strip shape extending in the left - right direction in the figure.

[0033] (Configuration of the wiring pattern 72) As shown in FIG. 1, the wiring pattern 72 is electrically connected to the electrode pad 33 via, for example, a via wiring V2 formed in a through - hole 43 that exposes a part of the upper surface of the electrode pad 33. The wiring pattern 72 is, for example, integrally formed with the via wiring V2. The wiring pattern 72 of the present embodiment is integrally formed with a plurality of via wirings V2. The plurality of via wirings V2 are, for example, provided apart from each other in the planar direction (left - right direction in the figure). Each via wiring V2 is formed, for example, so as to fill the through - hole 43. Each via wiring V2 is formed so as to penetrate the first substrate body 41 and the first adhesive layer 42 in the thickness direction.

[0034] As shown in FIG. 2, the planar shape of the wiring pattern 72 is formed in an H shape as a whole, for example. The wiring pattern 72 is provided so as to overlap with the electrode pads 33 of the semiconductor element 30 in a plan view. The wiring pattern 72 is provided so as to overlap with all of the four electrode pads 33 in a plan view, for example. The wiring pattern 72 is electrically connected to the four electrode pads 33, for example. And the wiring pattern 72 is formed so as to connect the four electrode pads 33 to each other. In other words, the four electrode pads 33 are electrically connected to each other via the wiring pattern 72.

[0035] (Configuration of the second organic substrate 50) As shown in FIG. 1, the second organic substrate 50 is provided on the lower surface of the metal plate 20. The second organic substrate 50 is formed in a flat plate shape. The second organic substrate 50 is formed so as to cover at least the outer peripheral edge of the lower surface of the conductive layer A1. The second organic substrate 50 of the present embodiment is formed so as to cover at least the outer peripheral edge of the lower surface of the metal plate 20 provided on the lowermost layer of the conductive layer A1. The second organic substrate 50 is formed so as to cover the outer peripheral edge of the lower surface of the metal plate 20 over the entire circumferential direction of the metal plate 20, for example.

[0036] The second organic substrate 50 is formed so as to protrude outward from the outer surface of the metal plate 20, for example. The second organic substrate 50 is formed so as to protrude outward from the outer surface of the first organic substrate 40, for example.

[0037] The second organic substrate 50 has, for example, a second substrate body 51 and a second adhesive layer 52 formed on the upper surface of the second substrate body 51. The second substrate body 51 is made of an organic material. The second substrate body 51 is made of a high-voltage-resistant resin material. That is, as the material of the second substrate body 51, an insulating resin with high voltage resistance can be used. As the material of the second substrate body 51, for example, insulating resins such as polyimide resin and polyester resin can be used. The material of the second substrate body 51 may be the same as or different from the material of the first substrate body 41. The second substrate body 51 of the present embodiment is made of the same type of polyimide resin as the first substrate body 41. The voltage resistance of the second substrate body 51 is, for example, higher than that of the encapsulating resin 60. The voltage resistance of the second substrate body 51 is, for example, 200 kV / mm or more. The voltage resistance of the second substrate body 51 is preferably 300 kV / mm or more, and more preferably 350 kV / mm or more. The voltage resistance of the second substrate body 51 of the present embodiment is 380 kV / mm. Incidentally, the thickness of the second substrate body 51 can be, for example, about 20 μm to 50 μm.

[0038] As the second adhesive layer 52, for example, epoxy-based, polyimide-based or silicone-based adhesives can be used. The thickness of the second adhesive layer 52 can be, for example, about 15 μm to 45 μm.

[0039] The second organic substrate 50 has, for example, a coefficient of thermal expansion similar to that of the first organic substrate 40. Here, in this specification, "similar" in "similar coefficient of thermal expansion" means that the difference between the coefficient of thermal expansion of the first organic substrate 40 and that of the second organic substrate 50 is in the range of 10 ppm / °C or less. The coefficient of thermal expansion of the second organic substrate 50 can be, for example, about 20 ppm / °C to 27 ppm / °C. Here, the difference between the coefficient of thermal expansion of the second organic substrate 50 and that of the first organic substrate 40 is, for example, smaller than the difference between the coefficient of thermal expansion of the second organic substrate 50 and that of the semiconductor element 30. The difference between the coefficient of thermal expansion of the second organic substrate 50 and that of the first organic substrate 40 is, for example, smaller than the difference between the coefficient of thermal expansion of the second organic substrate 50 and that of the encapsulation resin 60.

[0040] The second substrate body 51 is adhered to the lower surface of the metal plate 20 by, for example, the second adhesive layer 52. The second adhesive layer 52 is adhered to the lower surface of the metal plate 20 and also adhered to the upper surface of the second substrate body 51. The second adhesive layer 52 may be provided, for example, so as to incorporate a part of the metal plate 20. In other words, a part of the metal plate 20 may be embedded in the second adhesive layer 52. In this case, the second adhesive layer 52 is formed, for example, so as to cover the lower side surface of the metal plate 20.

[0041] An opening 53 that penetrates the second organic substrate 50 in the thickness direction is formed in the second organic substrate 50. The opening 53 is formed so as to penetrate the second substrate body 51 and the second adhesive layer 52 in the thickness direction. The opening 53 is formed so as to expose a part of the lower surface of the metal plate 20. The opening 53 is formed so as to expose, for example, the central portion of the lower surface of the metal plate 20. Note that the lower surface of the metal plate 20 exposed from the opening 53 functions as, for example, an external connection pad. External connection terminals used when mounting the semiconductor device 10A on a mounting substrate such as a mother board are connected to the lower surface of the metal plate 20 exposed from the opening 53.

[0042] (Configuration of the encapsulation resin 60) The encapsulation resin 60 is formed to encapsulate the semiconductor element 30 provided between the first organic substrate 40 and the second organic substrate 50. The encapsulation resin 60 is formed, for example, to encapsulate a plurality (here, four) of semiconductor elements 30 collectively. The encapsulation resin 60 covers, for example, the entire side surface of each semiconductor element 30, the entire upper surface of the joint portion 21 exposed from each semiconductor element 30, and the entire side surface of the joint portion 21. The encapsulation resin 60 covers, for example, the entire upper surface of the metal plate 20 exposed from the joint portion 21.

[0043] The encapsulation resin 60 is provided, for example, on the upper surface of the second organic substrate 50 exposed from the metal plate 20. The encapsulation resin 60 covers the entire upper surface of the second organic substrate 50 exposed from the metal plate 20. The encapsulation resin 60 is formed so as to expose the outer side surface of the second organic substrate 50. The outer side surface of the encapsulation resin 60 is formed flush with, for example, the outer side surface of the second organic substrate 50. The encapsulation resin 60 covers, for example, the outer side surface of the metal plate 20. The encapsulation resin 60 covers, for example, the entire outer side surface of the metal plate 20. The encapsulation resin 60 covers the outer side surface of the metal plate 20 over the entire circumferential direction. The encapsulation resin 60 is formed, for example, to surround the metal plate 20 from the outside. The encapsulation resin 60 is formed, for example, to expose the lower surface of the metal plate 20.

[0044] The encapsulation resin 60 covers, for example, the outer side surface of the first organic substrate 40. The encapsulation resin 60 covers, for example, the entire outer side surface of the first organic substrate 40. The encapsulation resin 60 covers the outer side surface of the first organic substrate 40 over the entire circumferential direction. The encapsulation resin 60 is formed, for example, to surround the first organic substrate 40 from the outside. The encapsulation resin 60 covers, for example, the entire lower surface of the first organic substrate 40 exposed from the semiconductor element 30.

[0045] The sealing resin 60 is formed, for example, so as to cover the upper surface of the first organic substrate 40. The sealing resin 60 covers, for example, the entire upper surface of the first organic substrate 40 exposed from the wiring layer 70. The sealing resin 60 covers, for example, the side surface of the wiring layer 70. The sealing resin 60 covers, for example, the entire side surface of the wiring layer 70. The sealing resin 60 is in contact with, for example, the side surface of the wiring layer 70. The sealing resin 60 is formed, for example, so as to surround the wiring patterns 71 and 72. As shown in FIG. 2, the sealing resin 60 is formed, for example, so as to fill the openings 71X and 71Y of the wiring pattern 71. As shown in FIG. 1, the sealing resin 60 is formed, for example, so as to expose the upper surface of the wiring layer 70. The upper surface of the sealing resin 60 is formed, for example, flush with the upper surface of the wiring layer 70.

[0046] As the material of the sealing resin 60, for example, a non-photosensitive insulating resin mainly composed of a thermosetting resin can be used. As the material of the sealing resin 60, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which fillers such as silica and alumina are mixed into these resins can be used. As the sealing resin 60, for example, a mold resin can be used. The coefficient of thermal expansion of the sealing resin 60 can be, for example, about 5 ppm / °C to 18 ppm / °C.

[0047] (Method for manufacturing the semiconductor device 10A) Next, a method for manufacturing the semiconductor device 10A will be described. For the sake of convenience of explanation, the parts that will finally become the components of the semiconductor device 10A will be described with the reference numerals of the final components.

[0048] First, in the process shown in FIG. 3, the first organic substrate 40 is prepared. At this time, the first organic substrate 40 has a structure in which a first adhesive layer 42 is laminated on the lower surface of the first substrate body 41. Next, in the process shown in FIG. 4, through holes 43 are formed at required positions of the first organic substrate 40. The through holes 43 are formed so as to penetrate the first substrate body 41 and the first adhesive layer 42 in the thickness direction. The through holes 43 are, for example, CO 2It can be formed by laser processing using a laser such as a UV-YAG laser or punching processing.

[0049] Subsequently, in the process shown in FIG. 5, a semiconductor element 30 having electrode pads 31, 32, 33 is prepared. Next, a first organic substrate 40 is mounted on the upper surface of the semiconductor element 30. For example, the first organic substrate 40 is adhered to the upper surface of the semiconductor element 30 by a first adhesive layer 42. For example, a sheet-like first organic substrate 40 is laminated on the upper surface of the semiconductor element 30 by thermocompression bonding. At this time, the semiconductor element 30 and the first organic substrate 40 are aligned so that the through holes 43 expose a part of the upper surfaces of the electrode pads 32, 33.

[0050] Next, in the process shown in FIG. 6, via wirings V1, V2 are formed in the through holes 43, and a wiring layer 70 electrically connected to the electrode pads 32, 33 through these via wirings V1, V2 is formed on the upper surface of the first organic substrate 40. At this time, the wiring layer 70 has a wiring pattern 71 and a wiring pattern 72. The via wirings V1, V2 and the wiring layer 70 can be formed using various wiring formation methods such as a semi-additive method.

[0051] Next, in the process shown in FIG. 7, a metal plate 20 is prepared. Subsequently, a joint portion 21 is formed on the upper surface of the metal plate 20. The joint portion 21 can be formed, for example, by applying a paste-like sintering material (sintering paste) by a printing method or a dispenser method. As the sintering paste, for example, a silver sintering paste in which silver particles are dispersed in an organic solvent can be used. As the printing method, for example, a screen printing method or a stencil printing method can be used.

[0052] Next, the semiconductor element 30 is placed on the upper surface of the joint portion 21. At this time, the semiconductor element 30 is placed on the upper surface of the joint portion 21 so that the electrode pad 31 formed on the lower surface of the semiconductor element 30 contacts the upper surface of the joint portion 21.

[0053] Subsequently, by heating the joint portion 21, the joint portion 21 is sintered. As a result, the metal plate 20 and the electrode pad 31 of the semiconductor element 30 are joined by the joint portion 21, and the semiconductor element 30 is joined onto the metal plate 20 via the joint portion 21.

[0054] Next, in the process shown in FIG. 8, a second organic substrate 50 having an opening 53 is prepared. At this time, the second organic substrate 50 has a structure in which a second adhesive layer 52 is laminated on the upper surface of the second substrate body 51. Subsequently, the second organic substrate 50 is mounted on the lower surface of the metal plate 20. For example, the second organic substrate 50 is adhered to the lower surface of the metal plate 20 by the second adhesive layer 52. For example, a sheet-like second organic substrate 50 is laminated on the lower surface of the metal plate 20 by thermocompression bonding. At this time, the metal plate 20 and the second organic substrate 50 are aligned so that the opening 53 exposes the central portion of the lower surface of the metal plate 20. Further, the metal plate 20 and the second organic substrate 50 are aligned so that the second organic substrate 50 protrudes outward from the outer surface of the metal plate 20.

[0055] Next, in the process shown in FIG. 9, a sealing resin 60 is formed to seal the semiconductor element 30 provided between the first organic substrate 40 and the second organic substrate 50. The sealing resin 60 is formed, for example, to cover the outer surface of the metal plate 20 and expose the lower surface of the metal plate 20. The sealing resin 60 is formed, for example, to entirely cover the first organic substrate 40. The sealing resin 60 is formed, for example, to cover the upper surface of the first organic substrate 40 and the side surface of the wiring layer 70. The sealing resin 60 can be formed, for example, by a resin molding method. For example, when using a mold resin having thermosetting properties as the material of the sealing resin 60, the structure shown in FIG. 8 is placed on the lower mold of a mold composed of a set of upper and lower molds, and the structure is accommodated in the mold by sandwiching it from above with the upper mold. Subsequently, a pressurized (for example, a pressure of about 3 MPa to 10 MPa) and fluidized mold resin is introduced into the mold from the gate portion (not shown) of the mold. Thereafter, the mold resin is heated and cured at a temperature of about 180° C. to form the sealing resin 60. At this time, an opening 71Y (see FIG. 2) is provided in the wiring pattern 71 as a passage connecting the region where the sealing resin 60 covering the outer surface of the wiring pattern 71 is formed and the region where the sealing resin 60 filling the opening 71X is formed. Through this opening 71Y, the mold resin can be suitably introduced into the opening 71X. Then, after the required sealing process is completed, the structure with the sealing resin 60 formed is taken out of the mold. Note that, as a method for filling the mold resin, for example, methods such as a transfer molding method, a compression molding method, or an injection molding method can be used.

[0056] Through the above manufacturing process, the semiconductor device 10A of the present embodiment can be manufactured. Note that the semiconductor device 10A can be used in an upside-down state or arranged at an arbitrary angle.

[0057] Next, the effects of the present embodiment will be described. (1-1) The semiconductor device 10A includes one or more semiconductor elements 30 having an electrode pad 31 formed on the lower surface and an electrode pad 32 formed on the upper surface, and a first organic substrate 40 provided on the upper surface of the semiconductor element 30. The semiconductor device 10A includes a wiring layer 70 provided on the upper surface of the first organic substrate 40 and electrically connected to the electrode pad 32, and a conductive layer A1 formed on the lower surface of the semiconductor element 30. The conductive layer A1 of the present embodiment is composed of an electrode pad 31, a joint portion 21, and a metal plate 20 formed on the lower surface of the semiconductor element 30. The semiconductor device 10A includes a second organic substrate 50 provided on the lower surface of the metal plate 20 of the conductive layer A1, and a sealing resin 60 that seals the semiconductor element 30 provided between the first organic substrate 40 and the second organic substrate 50.

[0058] According to this configuration, the first organic substrate 40 is provided on the upper surface of the semiconductor element 30, and the second organic substrate 50 is provided on the lower surface of the conductive layer A1 formed on the lower surface of the semiconductor element 30. Then, the semiconductor element 30 provided between the first organic substrate 40 and the second organic substrate 50 is sealed with the sealing resin 60. For this reason, the semiconductor element 30 is sealed with the sealing resin 60 in a state of being sandwiched between two organic substrates, that is, the first organic substrate 40 and the second organic substrate 50. Thereby, both of the two substrates sandwiching the semiconductor element 30 from above and below can be constituted by organic substrates. Therefore, the manufacturing cost of the semiconductor device 10A can be reduced as compared with the case where at least one of the two substrates sandwiching the semiconductor element 30 from above and below is a ceramic substrate.

[0059] (1-2) Further, the first organic substrate 40 and the second organic substrate 50 can be easily formed thinner than a ceramic substrate. Therefore, the semiconductor device 10A can be made thinner as compared with the case where at least one of the two substrates sandwiching the semiconductor element 30 from above and below is a ceramic substrate.

[0060] (1-3) The first organic substrate 40 has a first substrate body 41 and a first adhesive layer 42 formed on the lower surface of the first substrate body 41 and adhered to the upper surface of the semiconductor element 30. The second organic substrate 50 has a second substrate body 51 and a second adhesive layer 52 formed on the upper surface of the second substrate body 51 and adhered to the lower surface of the conductive layer A1. According to this configuration, the first organic substrate 40 can be easily mounted on the upper surface of the semiconductor element 30 by the first adhesive layer 42, and the second organic substrate 50 can be easily mounted on the lower surface of the conductive layer A1 by the second adhesive layer 52.

[0061] (1-4) The first organic substrate 40 is formed of a high-voltage-resistant resin material. The second organic substrate 50 is formed of a high-voltage-resistant resin material. According to this configuration, the semiconductor element 30 is sandwiched from above and below by two organic substrates with high breakdown voltage (insulation breakdown voltage), that is, the first organic substrate 40 and the second organic substrate 50. Thereby, while reducing the manufacturing cost of the semiconductor device 10A, the insulation voltage of the semiconductor device 10A can be improved.

[0062] (1-5) The first organic substrate 40 formed of a high-voltage-resistant resin material is formed so as to cover at least the outer peripheral edge of the upper surface of the electrode pad 32. According to this configuration, the outer peripheral edge of the upper surface of the electrode pad 32 can be covered by the first organic substrate 40 with high breakdown voltage. Thereby, the occurrence of possible leakage occurring outward from the outer peripheral edge of the electrode pad 32 can be preferably suppressed. Furthermore, since the occurrence of leakage can be suppressed, the insulation breakdown voltage of the semiconductor device 10A can be further improved.

[0063] (1-6) The second organic substrate 50 formed of a high-voltage-resistant resin material is formed so as to cover at least the outer peripheral edge of the lower surface of the metal plate 20 constituting the conductive layer A1. According to this configuration, the outer peripheral edge of the lower surface of the electrode pad 31 can be covered by the second organic substrate 50 with high breakdown voltage. Thereby, the occurrence of possible leakage occurring outward from the outer peripheral edge of the electrode pad 31 can be preferably suppressed. Furthermore, since the occurrence of leakage can be suppressed, the insulation breakdown voltage of the semiconductor device 10A can be further improved.

[0064] (1-7) The first organic substrate 40 and the second organic substrate 50 can maintain a high dielectric breakdown voltage of the semiconductor device 10A. Therefore, a material with a low dielectric breakdown voltage can be used as the material of the encapsulation resin 60. In other words, the degree of freedom in selecting the material of the encapsulation resin 60 can be improved. For example, as the material of the encapsulation resin 60, a material with high fluidity can be preferably selected.

[0065] (1-8) The difference between the coefficient of thermal expansion of the first organic substrate 40 and the coefficient of thermal expansion of the second organic substrate 50 is smaller than the difference between the coefficient of thermal expansion of the second organic substrate 50 and the coefficient of thermal expansion of the semiconductor element 30. Thereby, for example, compared with the difference in the coefficient of thermal expansion of the two substrates when one of the two substrates sandwiching the semiconductor element 30 from above and below is a ceramic substrate, the difference in the coefficient of thermal expansion between the first organic substrate 40 and the second organic substrate 50 can be reduced. Therefore, the balance of the physical property values above and below centered on the semiconductor element 30 becomes good, and it is possible to preferably suppress the occurrence of warping or the like in the semiconductor device 10A due to thermal shrinkage or the like.

[0066] (1-9) The second organic substrate 50 is formed so as to protrude outward from the outer surface of the conductive layer A1. The encapsulation resin 60 is provided on the upper surface of the second organic substrate 50 exposed from the conductive layer A1. The encapsulation resin 60 is formed so as to cover the outer surface of the conductive layer A1. According to this configuration, since the outer surface of the conductive layer A1 is covered by the encapsulation resin 60, it is possible to preferably suppress the occurrence of leakage that may occur outward from the outer surface of the conductive layer A1.

[0067] (1-10) Further, the outer periphery of the metal plate 20 can be surrounded by the encapsulation resin 60. Thereby, it is possible to preferably suppress the peeling of the metal plate 20 from the second organic substrate 50 or the like inside the encapsulation resin 60.

[0068] (1-11) The sealing resin 60 is formed so as to cover the outer surface of the first organic substrate 40. According to this configuration, the outer periphery of the first organic substrate 40 can be surrounded by the sealing resin 60. Thereby, inside the sealing resin 60, it is possible to suitably suppress the separation of the first organic substrate 40 from the semiconductor element 30 or the like.

[0069] (1-12) A metal plate 20 is provided which is joined to the electrode pad 31 of the semiconductor element 30 via the joint portion 21. By providing the metal plate 20, the heat capacity of the semiconductor device 10A can be increased. Therefore, it is possible to suitably suppress the temperature rise of the semiconductor device 10A during energization.

[0070] (1-13) Further, by providing the metal plate 20, the rigidity of the entire semiconductor device 10A can be increased. Thereby, it is possible to suitably suppress the occurrence of warping or the like in the semiconductor device 10A.

[0071] (1-14) The second organic substrate 50 has an opening 53 that penetrates the second organic substrate 50 in the thickness direction and exposes a part of the lower surface of the metal plate 20. According to this configuration, through the opening 53, the metal plate 20 can be easily electrically connected to a mounting substrate such as a mother board.

[0072] (Second Embodiment) Hereinafter, the second embodiment will be described with reference to FIGS. 10 to 18. Hereinafter, the description will focus on the differences from the first embodiment. The same members as those shown in the previous FIGS. 1 to 9 are denoted by the same reference numerals, and detailed descriptions of these elements are omitted.

[0073] (Overall Configuration of Semiconductor Device 10B) First, the overall configuration of the semiconductor device 10B will be described with reference to FIG. 10. The semiconductor device 10B includes a metal plate 20A, a joint portion 21, one or more (in this embodiment, four) semiconductor elements 30, a first organic substrate 40, and a second organic substrate 50. The semiconductor device 10B includes a sealing resin 60A that seals the semiconductor element 30, a wiring layer 70, and a through electrode 75 that penetrates the sealing resin 60A in the thickness direction. In the semiconductor device 10B, the semiconductor element 30 is built in between the first organic substrate 40 and the second organic substrate 50.

[0074] (Configuration of the metal plate 20A) The metal plate 20A is formed in a flat plate shape. As the material of the metal plate 20A, for example, a metal such as aluminum, copper, iron (Fe), molybdenum (Mo), or an alloy containing at least one metal selected from these metals can be used. The metal plate 20A of this embodiment is a copper plate.

[0075] As shown in FIG. 11, the planar shape of the metal plate 20A is formed in a rectangular shape, for example. Note that the planar shape of the metal plate 20A is not limited to a rectangular shape and can be any shape. The planar size of the metal plate 20A is formed larger than the planar size of the first organic substrate 40, for example. The planar size of the metal plate 20A is formed slightly larger than the planar size of the first organic substrate 40, for example. The metal plate 20A is provided so as to overlap with the entire first organic substrate 40 in a plan view, for example.

[0076] As shown in FIG. 10, in the semiconductor device 10B of this embodiment, a conductive layer A1 is formed by the metal plate 20A, the joint portion 21, and the electrode pad 31. (Configuration of the second organic substrate 50) The second organic substrate 50 is provided on the lower surface of the metal plate 20A. The second organic substrate 50 is formed so as to cover at least the outer peripheral edge of the lower surface of the metal plate 20A. The second organic substrate 50 is formed so as to cover the outer peripheral edge of the lower surface of the metal plate 20A over the entire circumferential direction of the metal plate 20A, for example. The second organic substrate 50 is formed so as to protrude outward from the outer surface of the metal plate 20A, for example.

[0077] (Configuration of Encapsulation Resin 60A) The encapsulation resin 60A is formed, for example, to encapsulate the semiconductor element 30 provided between the first organic substrate 40 and the second organic substrate 50. The encapsulation resin 60A is formed, for example, to encapsulate a plurality (here, 4) of semiconductor elements 30 collectively. The encapsulation resin 60A covers, for example, the side surfaces of each semiconductor element 30, the upper surface of the joint portion 21 exposed from each semiconductor element 30, and the side surface of the joint portion 21. The encapsulation resin 60A covers, for example, the entire upper surface of the metal plate 20A exposed from the joint portion 21.

[0078] The encapsulation resin 60A is provided, for example, on the upper surface of the second organic substrate 50 exposed from the metal plate 20A. The encapsulation resin 60A covers, for example, the entire upper surface of the second organic substrate 50 exposed from the metal plate 20A. The encapsulation resin 60A is formed so as to expose the outer side surface of the second organic substrate 50. The outer side surface of the encapsulation resin 60A is formed flush with, for example, the outer side surface of the second organic substrate 50. The encapsulation resin 60A covers, for example, the entire outer side surface of the metal plate 20A. The encapsulation resin 60A covers, for example, the outer side surface of the metal plate 20A over the entire circumferential direction. The encapsulation resin 60A is formed so as to expose the lower surface of the metal plate 20A.

[0079] The encapsulation resin 60A covers, for example, the entire outer side surface of the first organic substrate 40. The encapsulation resin 60A covers, for example, the outer side surface of the first organic substrate 40 over the entire circumferential direction. The encapsulation resin 60A covers, for example, the entire lower surface of the first organic substrate 40 exposed from the semiconductor element 30.

[0080] The encapsulation resin 60A covers, for example, the entire upper surface of the first organic substrate 40 exposed from the wiring layer 70. The encapsulation resin 60A covers, for example, the entire side surface of the wiring layer 70. The encapsulation resin 60A is formed so as to expose the upper surface of the wiring layer 70. The upper surface of the encapsulation resin 60A is formed flush with, for example, the upper surface of the wiring layer 70.

[0081] As the material of the sealing resin 60A, for example, a non-photosensitive insulating resin mainly composed of a thermosetting resin can be used. As the material of the sealing resin 60A, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which fillers such as silica or alumina are mixed into these resins can be used. As the sealing resin 60A, for example, a mold resin can be used. The coefficient of thermal expansion of the sealing resin 60A can be, for example, about 5 ppm / °C to 18 ppm / °C.

[0082] In the sealing resin 60A, one or more (eight in this embodiment) through holes 60X are provided that penetrate the sealing resin 60A in the thickness direction and expose a part of the upper surface of the metal plate 20A. Each through hole 60X is provided, for example, in an outer peripheral region outside the first organic substrate 40. Each through hole 60X is formed, for example, in a tapered shape in which the opening width (opening diameter) decreases as it goes from the upper side (the upper surface side of the sealing resin 60A) to the lower side (the metal plate 20A side) in FIG. 10. For example, each through hole 60X is formed in an inverted frustum shape in which the opening diameter of the lower opening end is smaller than the opening diameter of the upper opening end.

[0083] As shown in FIG. 11, the plurality of through holes 60X are provided, for example, arranged along the vertical direction in the figure. The plurality of through holes 60X are provided, for example, outside the first organic substrate 40 in the left-right direction in the figure. The plurality of through holes 60X are provided, for example, on both sides of the first organic substrate 40 in the left-right direction in the figure.

[0084] (Configuration of the through electrode 75) As shown in FIG. 10, the through electrode 75 is formed inside the through hole 60X. The through electrode 75 is formed, for example, so as to fill the through hole 60X. The through electrode 75 is formed so as to penetrate the sealing resin 60A in the thickness direction. The upper end surface of the through electrode 75 is exposed from the sealing resin 60A. The upper end surface of the through electrode 75 is formed flush with the upper surface of the sealing resin 60A, for example. The upper end surface of the through electrode 75 is provided on the same plane as the upper surface of the wiring layer 70, for example.

[0085] The through electrode 75 is electrically connected to the metal plate 20A. The through electrode 75 is electrically connected to the electrode pad 31 of the semiconductor element 30 via the metal plate 20A and the joint portion 21. In other words, the electrode pad 31 is led out to the upper surface of the sealing resin 60A through the joint portion 21, the metal plate 20A, and the through electrode 75. Thus, all of the electrode pad 31, the electrode pad 32, and the electrode pad 33 are led out to the upper surface of the sealing resin 60A.

[0086] (Manufacturing Method of Semiconductor Device 10B) Next, the manufacturing method of the semiconductor device 10B will be described. For convenience of explanation, the parts that will finally become the components of the semiconductor device 10B will be described with the reference numerals of the final components.

[0087] First, in the process shown in FIG. 12, similar to the processes shown in FIGS. 3 and 4, a first organic substrate 40 having a through hole 43 is formed. Subsequently, in the process shown in FIG. 13, a semiconductor element 30 having electrode pads 31, 32, 33 is prepared. Next, similar to the process shown in FIG. 5, the first organic substrate 40 is mounted on the upper surface of the semiconductor element 30.

[0088] Next, similar to the process shown in FIG. 6, via wirings V1, V2 are formed in the through hole 43, and a wiring layer 70 electrically connected to the electrode pads 32, 33 through the via wirings V1, V2 is formed on the upper surface of the first organic substrate 40.

[0089] Subsequently, in the process shown in FIG. 14, a metal plate 20A is prepared. Next, similar to the process shown in FIG. 7, after forming the joint portion 21 on the upper surface of the metal plate 20A, the semiconductor element 30 is joined to the upper surface of the joint portion 21.

[0090] Next, in the process shown in FIG. 15, a second organic substrate 50 having an opening 53 is prepared. Subsequently, similar to the process shown in FIG. 8, the second organic substrate 50 is mounted on the lower surface of the metal plate 20A. Next, in the process shown in FIG. 16, similarly to the process shown in FIG. 9, a sealing resin 60A for sealing the semiconductor element 30 provided between the first organic substrate 40 and the second organic substrate 50 is formed. The sealing resin 60A is formed, for example, so as to cover the outer surface of the metal plate 20A and expose the lower surface of the metal plate 20A. The sealing resin 60A is formed, for example, so as to entirely cover the first organic substrate 40. The sealing resin 60A is formed, for example, so as to cover the upper surface of the first organic substrate 40 and the side surface of the wiring layer 70.

[0091] Next, in the process shown in FIG. 17, a through hole 60X is formed that penetrates the sealing resin 60A in the thickness direction and exposes a part of the upper surface of the metal plate 20A. The through hole 60X can be formed, for example, by laser processing using a CO 2 laser, a UV-YAG laser, or the like. Subsequently, when the through hole 60X is formed by a laser processing method, a desmear treatment is performed to remove the resin smear adhering to the exposed surface of the metal plate 20A exposed at the bottom of the through hole 60X.

[0092] Next, in the process shown in FIG. 18, a through electrode 75 is formed inside the through hole 60X. The through electrode 75 is formed so as to fill the through hole 60X. The through electrode 75 can be formed, for example, by filling the through hole 60X with a conductive paste by a screen printing method. As the conductive paste, for example, a solder paste or a copper paste can be used.

[0093] Through the above manufacturing process, the semiconductor device 10B of the present embodiment can be manufactured. Note that the semiconductor device 10B can be used in an upside-down state or arranged at an arbitrary angle.

[0094] According to the present embodiment described above, in addition to the effects (1-1) to (1-14) of the first embodiment, the following effects can be achieved. (2-1) The metal plate 20A is formed so as to protrude outward from the outer surface of the first organic substrate 40. The semiconductor device 10B has a through-hole 60X that penetrates the encapsulation resin 60A in the thickness direction and exposes a part of the upper surface of the metal plate 20A, and a through electrode 75 that fills the through-hole 60X and is electrically connected to the metal plate 20A.

[0095] According to this configuration, the through electrode 75 is electrically connected to the electrode pad 31 formed on the lower surface of the semiconductor element 30 via the metal plate 20A and the joint portion 21. Thereby, the electrode pad 31 can be drawn out to the upper surface of the encapsulation resin 60A through the joint portion 21, the metal plate 20A, and the through electrode 75. Therefore, all of the electrode pad 31, the electrode pad 32, and the electrode pad 33 can be drawn out to the upper surface of the encapsulation resin 60A.

[0096] (Third Embodiment) Hereinafter, the third embodiment will be described with reference to FIGS. 19 to 27. Hereinafter, the description will focus on the differences from the second embodiment. The same members as those shown in the previous FIGS. 1 to 18 are denoted by the same reference numerals, and detailed descriptions of these elements are omitted.

[0097] (Overall Configuration of Semiconductor Device 10C) First, with reference to FIG. 19, the overall configuration of the semiconductor device 10C will be described. The semiconductor device 10C includes a substrate 80, a structure 11B, a resin layer 90, a wiring layer 100, and a wiring layer 110.

[0098] The substrate 80 is provided, for example, at the central portion in the thickness direction of the semiconductor device 10C. The substrate 80 is, for example, a core substrate. As the substrate 80, for example, a so-called glass epoxy substrate obtained by impregnating a glass cloth (glass woven fabric), which is a reinforcing material, with a thermosetting insulating resin mainly composed of an epoxy resin and curing it can be used. The reinforcing material is not limited to glass cloth, and for example, glass non-woven fabric, aramid woven fabric, aramid non-woven fabric, liquid crystal polymer (LCP) woven fabric, or LCP non-woven fabric can be used. Further, the thermosetting insulating resin is not limited to epoxy resin, and for example, resin materials such as polyimide resin and cyanate resin can be used. Also, as the material of the substrate 80, an insulating resin not containing a reinforcing material can be used.

[0099] In the substrate 80, a through hole 80X penetrating the substrate 80 in the thickness direction is formed. In the through hole 80X, a through electrode 82 penetrating the substrate 80 in the thickness direction is formed. The through electrode 82 is formed, for example, so as to fill the through hole 80X.

[0100] On the upper surface of the substrate 80, a wiring layer 83 is formed. The wiring layer 83 is electrically connected to the through electrode 82. The thickness of the wiring layer 83 can be, for example, about 35 μm to 50 μm.

[0101] On the lower surface of the substrate 80, a wiring layer 84 is formed. The wiring layer 84 is electrically connected to the wiring layer 83 via the through electrode 82. The thickness of the wiring layer 84 can be, for example, about 35 μm to 50 μm. As the material of the through electrode 82 and the wiring layers 83 and 84, for example, copper or a copper alloy can be used.

[0102] The substrate 80 is provided with one or more (one in this embodiment) accommodation holes 80Y for accommodating the structure 11B. The accommodation holes 80Y are formed so as to penetrate the substrate 80 in the thickness direction. The accommodation holes 80Y are provided, for example, at the central portion of the substrate 80. The accommodation holes 80Y are formed to have a size capable of accommodating the structure 11B therein.

[0103] The planar shape of the accommodation hole 80Y is, for example, the same shape as the planar shape of the structure 11B, and here it is formed in a rectangular shape. The planar size of the accommodation hole 80Y is formed larger than the planar size of the structure 11B. The planar size of the accommodation hole 80Y is formed, for example, slightly larger than the planar size of the structure 11B.

[0104] (Configuration of the structure 11B) The structure 11B has, for example, the same structure as the semiconductor device 10B shown in FIG. 10. The structure 11B includes a metal plate 20A, a joint portion 21, one or more semiconductor elements 30, a first organic substrate 40, a second organic substrate 50, a sealing resin 60A, a wiring layer 70, and a through electrode 75. In the structure 11B, the semiconductor element 30 is built in between the first organic substrate 40 and the second organic substrate 50.

[0105] (Configuration of the resin layer 90) The resin layer 90 is formed so as to fill the accommodation hole 80Y. The resin layer 90 is formed so as to cover the structure 11B entirely. The resin layer 90 is formed so as to cover the entire outer surface, the upper surface, and the lower surface of the structure 11B. The resin layer 90 is formed so as to cover, for example, the upper surface and the lower surface of the substrate 80.

[0106] The resin layer 90 has, for example, a resin layer 91 and a resin layer 92. As the material of the resin layers 91 and 92, for example, an insulating resin such as an epoxy resin or a polyimide resin can be used. The material of the resin layer 91 and the material of the resin layer 92 may be the same material as each other or different materials from each other.

[0107] The resin layer 91 is formed so as to cover a part of the outer surface of the structure 11B and the upper surface of the structure 11B. The resin layer 91 is formed so as to cover the upper surface of the substrate 80 and the upper surface and side surfaces of the wiring layer 83.

[0108] The resin layer 92 is formed so as to cover the outer surface of the structure 11B exposed from the resin layer 91 and to cover the lower surface of the structure 11B. For example, the resin layer 92 is formed so as to fill the opening 53 of the second organic substrate 50 of the structure 11B. The resin layer 92 is formed so as to cover the lower surface of the substrate 80 and to cover the lower surface and side surfaces of the wiring layer 84.

[0109] A plurality of through holes 93 and 94 penetrating the resin layer 91 in the thickness direction are formed in the resin layer 91. For example, the through hole 93 is formed so as to expose a part of the upper surface of the wiring layer 70 or a part of the upper surface of the through electrode 75. For example, the through hole 94 is formed so as to expose a part of the upper surface of the wiring layer 83. Each of the through holes 93 and 94 is formed in a tapered shape in which the opening width (opening diameter) becomes smaller as going from the upper side (the upper surface side of the resin layer 91) to the lower side in FIG. 19. For example, each of the through holes 93 and 94 is formed in an inverted frustum shape in which the opening diameter of the lower opening end is smaller than the opening diameter of the upper opening end.

[0110] A plurality of through holes 95 and 96 penetrating the resin layer 92 in the thickness direction are formed in the resin layer 92. For example, the through hole 95 is formed so as to expose a part of the lower surface of the metal plate 20A. For example, the through hole 96 is formed so as to expose a part of the lower surface of the wiring layer 84. Each of the through holes 95 and 96 is formed in a tapered shape in which the opening width (opening diameter) becomes smaller as going from the lower side (the lower surface side of the resin layer 92) to the upper side in FIG. 19. For example, each of the through holes 95 and 96 is formed in a frustum shape in which the opening diameter of the upper opening end is smaller than the opening diameter of the lower opening end.

[0111] (Configuration of the wiring layer 100) The wiring layer 100 is formed on the upper surface of the resin layer 91. The wiring layer 100 has one or more wiring patterns 101 and one or more wiring patterns 102.

[0112] As materials for the wiring patterns 101 and 102, for example, copper or a copper alloy can be used. Note that, if necessary, a surface treatment layer may be formed on the surface (upper surface and side surfaces, or only the upper surface) of the wiring patterns 101 and 102. Examples of the surface treatment layer include metal layers such as an Au layer, a Ni layer / Au layer, and a Ni layer / Pd layer / Au layer. Note that the thickness of the wiring patterns 101 and 102 can be, for example, about 50 μm to 200 μm.

[0113] Some of the wiring patterns 101 are electrically connected to the wiring pattern 71, for example, via via wiring filled in a through hole 93 that exposes a part of the upper surface of the wiring pattern 71. Some of the wiring patterns 101 are electrically connected to the wiring pattern 72, for example, via via wiring filled in a through hole 93 that exposes a part of the upper surface of the wiring pattern 72. Some of the wiring patterns 101 are electrically connected to the through electrode 75, for example, via via wiring filled in a through hole 93 that exposes a part of the upper surface of the through electrode 75. The wiring pattern 101 is formed integrally with, for example, the via wiring filled in the through hole 93. The wiring pattern 102 is electrically connected to the wiring layer 83 via via wiring filled in a through hole 94. The wiring pattern 102 is formed integrally with, for example, the via wiring filled in the through hole 94.

[0114] (Configuration of the wiring layer 110) The wiring layer 110 is formed on the lower surface of the resin layer 92. The wiring layer 110 has one or more wiring patterns 111 and one or more wiring patterns 112.

[0115] As materials for the wiring patterns 111 and 112, for example, copper or a copper alloy can be used. Note that, if necessary, a surface treatment layer may be formed on the surface (lower surface and side surfaces, or only the lower surface) of the wiring patterns 111 and 112. Examples of the surface treatment layer include metal layers such as an Au layer, a Ni layer / Au layer, and a Ni layer / Pd layer / Au layer. Note that the thickness of the wiring patterns 111 and 112 can be, for example, about 50 μm to 200 μm.

[0116] The wiring pattern 111 is electrically connected to the metal plate 20A, for example, via the via wiring filled in the through hole 95. The wiring pattern 111 is formed integrally with, for example, the via wiring filled in the through hole 95. The wiring pattern 111 is formed, for example, in a planar shape. The wiring pattern 112 is electrically connected to the wiring layer 84 via the via wiring filled in the through hole 96. The wiring pattern 112 is formed integrally with, for example, the via wiring filled in the through hole 96.

[0117] (Method for manufacturing the semiconductor device 10C) Next, a method for manufacturing the semiconductor device 10C will be described. For the sake of convenience of explanation, the parts that will finally become the respective components of the semiconductor device 10C will be described with the reference numerals of the final components.

[0118] First, in the process shown in FIG. 20, a structure having a substrate 80, a through electrode 82 that penetrates the substrate 80 in the thickness direction, a wiring layer 83 formed on the upper surface of the substrate 80, and a wiring layer 84 formed on the lower surface of the substrate 80 is prepared using a known technique. Subsequently, an accommodation hole 80Y that penetrates the substrate 80 in the thickness direction is formed in the substrate 80. The accommodation hole 80Y can be formed, for example, by laser processing, router processing, die processing using a die, mechanical drill processing, or the like.

[0119] Next, in the process shown in FIG. 21, an adhesive film 120 is attached to the lower surface of the substrate 80. The adhesive film 120 is provided, for example, so as to incorporate the wiring layer 84. The adhesive film 120 is provided, for example, so as to cover the lower surface and the side surfaces of the wiring layer 84. The adhesive film 120 is provided, for example, so as to incorporate a part of the substrate 80. The adhesive film 120 is provided, for example, so as to cover a part of the inner surface of the accommodation hole 80Y of the substrate 80. At this time, as shown in FIG. 21, a part of the upper surface of the adhesive film 120 is exposed from the accommodation hole 80Y. As the material of the adhesive film 120, for example, a material excellent in chemical resistance and heat resistance can be used. As the adhesive film 120, for example, a PET (polyethylene terephthalate) film provided with an adhesive layer can be used.

[0120] Next, in the process shown in FIG. 22, a structure 11B having a metal plate 20A, a semiconductor element 30, a first organic substrate 40, a second organic substrate 50, a sealing resin 60A, a wiring layer 70, and a through electrode 75 is prepared. The structure 11B can be manufactured, for example, by the processes shown in FIGS. 12 to 18. Subsequently, using a mounter, the structure 11B is mounted on the adhesive film 120 within the accommodation hole 80Y. At this time, the structure 11B is mounted on the adhesive film 120 such that the lower part of the structure 11B is embedded in the adhesive film 120. For example, the structure 11B is mounted on the adhesive film 120 such that the second organic substrate 50 of the structure 11B is embedded in the adhesive film 120.

[0121] Subsequently, in the process shown in FIG. 23, the accommodation hole 80Y exposed from the adhesive film 120 is filled, and a resin layer 91 is formed to cover the upper surface of the adhesive film 120, the upper surface of the substrate 80, and the upper and side surfaces of the wiring layer 83. As a result, the entire inner surface of the accommodation hole 80Y exposed from the adhesive film 120 and the entire surface of the structure 11B exposed from the adhesive film 120 are covered by the resin layer 91. Also, the entire upper surface of the substrate 80, the entire upper surface of the wiring layer 83, and the entire side surface of the wiring layer 83 are covered by the resin layer 91. That is, as shown in FIG. 23, the entire surface on the side opposite to the surface to which the adhesive film 120 is adhered is covered by the resin layer 91.

[0122] Here, the resin layer 91 can be formed, for example, by laminating a sheet-like insulating resin material in a semi-cured state (B-stage) on the upper surface of the wiring layer 83 so as to block the accommodation hole 80Y, and heating and pressing it in a reduced-pressure atmosphere (for example, in a vacuum) to fill and cure the accommodation hole 80Y. As the insulating resin material, for example, an epoxy-based resin or a polyimide-based resin can be used.

[0123] Next, in the process shown in FIG. 24, the adhesive film 120 shown in FIG. 23 is peeled off. As a result, the portions embedded in the adhesive film 120, that is, the lower surface of the substrate 80, the lower and side surfaces of the wiring layer 84, and the lower part of the structure 11B are exposed.

[0124] Next, in the process shown in FIG. 25, the accommodation hole 80Y exposed from the resin layer 91 is filled, and a resin layer 92 is formed to cover the lower surface of the substrate 80 and the lower and side surfaces of the wiring layer 84. As a result, the entire inner surface of the accommodation hole 80Y exposed from the resin layer 91 and the entire surface of the structure 11B exposed from the resin layer 91 are covered by the resin layer 92. Also, the entire lower surface of the substrate 80, the entire upper surface of the wiring layer 84, and the entire side surface of the wiring layer 84 are covered by the resin layer 92.

[0125] Here, the resin layer 92 can be formed by laminating, for example, a sheet-like insulating resin material in a semi-cured state (B-stage) on the lower surface of the wiring layer 84 so as to close the accommodation hole 80Y, and heating and pressurizing it in a reduced-pressure atmosphere (for example, in a vacuum) to fill and cure the accommodation hole 80Y. As the insulating resin material, for example, an epoxy-based resin or a polyimide-based resin can be used.

[0126] Through the above manufacturing process, the resin layer 90, which is composed of the resin layer 91 and the resin layer 92 and seals the structure 11B, is formed. Subsequently, in the process shown in FIG. 26, through holes 93 are formed in required portions of the resin layer 91 so that a part of the upper surface of the wiring layer 70 and the through electrodes 75 is exposed, and through holes 94 are formed in required portions of the resin layer 91 so that a part of the upper surface of the wiring layer 83 is exposed. Also, in this process, through holes 95 are formed in required portions of the resin layer 92 so that a part of the lower surface of the metal plate 20A is exposed, and through holes 96 are formed in required portions of the resin layer 92 so that a part of the lower surface of the wiring layer 84 is exposed. The through holes 93, 94, 95, and 96 can be formed, for example, by laser processing using a CO 2 laser or a UV-YAG laser. Subsequently, when the through holes 93 to 96 are formed by the laser processing method, a desmear treatment is performed to remove the resin smear adhering to the exposed surfaces of the wiring layers 70, 83, and 84, the through electrodes 75, and the metal plate 20A exposed at the bottoms of the through holes 93 to 96.

[0127] Next, in the process shown in FIG. 27, via wirings for filling the through holes 93 are formed, and wiring patterns 101 electrically connected to the wiring layer 70 or the through electrodes 75 through the via wirings are formed on the upper surface of the resin layer 91. Further, via wirings for filling the through holes 94 are formed, and wiring patterns 102 electrically connected to the wiring layer 83 through the via wirings are formed on the upper surface of the resin layer 91. Thereby, a wiring layer 100 having the wiring pattern 101 and the wiring pattern 102 is formed on the upper surface of the resin layer 91. In this process, via wirings for filling the through holes 95 are formed, and wiring patterns 111 electrically connected to the metal plate 20A through the via wirings are formed on the lower surface of the resin layer 92. Further, via wirings for filling the through holes 96 are formed, and wiring patterns 112 electrically connected to the wiring layer 84 through the via wirings are formed on the lower surface of the resin layer 92. Thereby, a wiring layer 110 having the wiring pattern 111 and the wiring pattern 112 is formed on the lower surface of the resin layer 92. The wiring layers 100 and 110 can be formed using various wiring formation methods such as the semi-additive method, for example.

[0128] Through the above manufacturing process, the semiconductor device 10C of the present embodiment can be manufactured. Note that the semiconductor device 10C can be used in an upside-down state or arranged at an arbitrary angle.

[0129] According to the present embodiment described above, the same effects as those of the first embodiment and the second embodiment can be obtained. (Modification example) Each of the above embodiments can be modified and implemented as follows. Each of the above embodiments and the following modification examples can be implemented in combination with each other within a technically non-conflicting range.

[0130] · As shown in FIG. 28, a metal layer 25 may be provided on the lower surface of the metal plate 20A. The metal layer 25 is formed, for example, in a paste shape. The metal layer 25 is formed so as to cover, for example, the entire lower surface of the metal plate 20A exposed from the opening 53 of the second organic substrate 50. The metal layer 25 is formed so as to protrude downward from the lower surface of the second organic substrate 50, for example. In this case, the through hole 95 penetrating the resin layer 92 in the thickness direction is formed so as to expose a part of the lower surface of the metal layer 25. Also, in this case, the wiring pattern 111 is electrically connected to the metal layer 25 via the via wiring filled in the through hole 95.

[0131] Note that the metal layer 25 can be formed, for example, by an electroless plating method, an electrolytic plating method, or a sputtering method. As the material of the metal layer 25, copper or a copper alloy can be used. According to this configuration, by providing the metal layer 25, the heat capacity of the semiconductor device 10C can be increased. Therefore, the temperature rise of the semiconductor device 10C during energization can be more suitably suppressed.

[0132] · In the modification shown in FIG. 28, the metal layer 25 may be formed so as to cover the lower surface of the second organic substrate 50. That is, the metal layer 25 may be formed so as to spread outward from the inner surface of the opening 53. The metal layer 25 may be formed so as to spread outward until it covers the lower surface of the substrate 80, for example. In this case, the metal layer 25 is formed so as to incorporate the second organic substrate 50.

[0133] · In the above-described third embodiment, the arrangement position of the structure 11B in the resin layer 90 is not particularly limited. For example, the structure 11B may be arranged in the resin layer 90 such that the lower surface of the second organic substrate 50 and the lower surface of the substrate 80 are arranged on the same plane.

[0134] · In each of the above embodiments, the opening 53 is formed so as to expose the central portion of the lower surface of the metal plates 20 and 20A, but the present invention is not limited to this. The opening 53 can be appropriately changed in other structures as long as, for example, a part of the lower surface of the metal plates 20 and 20A can be exposed.

[0135] · As shown in FIG. 29, the second organic substrate 50 may be formed to cover the entire lower surface of the metal plate 20A. That is, the formation of the opening 53 may be omitted. · In each of the above embodiments, the sealing resins 60 and 60A are formed to cover the outer surfaces of the metal plates 20 and 20A, but the present invention is not limited to this.

[0136] For example, as in the semiconductor device 10D shown in FIG. 29, the sealing resin 60A may be formed so as to expose the outer surface of the metal plate 20A. For example, the outer surface of the metal plate 20A may be flush with the outer surface of the sealing resin 60A. For example, the outer surface of the metal plate 20A may be flush with the outer surface of the second organic substrate 50.

[0137] · In each of the above embodiments, a plurality of semiconductor elements 30 are commonly joined on one metal plate 20 or 20A, but the present invention is not limited to this. In other words, the four electrode pads 31 of the four semiconductor elements 30 are commonly connected to the metal plates 20 and 20A, but the present invention is not limited to this.

[0138] For example, as in the semiconductor device 10E shown in FIG. 30, by forming through holes 20X in the metal plate 20A, the metal plate 20A may be divided into a plurality (for example, four) of pieces. Then, four semiconductor elements 30 may be joined to each of the four divided metal plates 20A. In this case, the sealing resin 60A is formed, for example, to fill the through holes 20X.

[0139] · In each of the above embodiments, the second organic substrate 50 is joined to the lower surfaces of the metal plates 20 and 20A by the second adhesive layer 52, but the present invention is not limited to this. For example, the metal plates 20 and 20A may be changed to metal layers formed on the upper surface of the second substrate body 51. In this case, the metal layer is formed, for example, in a paste-like manner on the upper surface of the second substrate body 51. In this case, a joint portion 21 is formed on the upper surface of the metal layer, and the semiconductor element 30 is joined to the upper surface of the metal layer via the joint portion 21. In this modified example, the second adhesive layer 52 of the second organic substrate 50 can be omitted.

[0140] · In each of the above embodiments, the metal plates 20 and 20A are joined to the lower surfaces of the electrode pads 31 of the semiconductor element 30 via the joint portion 21, but the present invention is not limited to this. For example, as in the semiconductor device 10F shown in FIG. 31, the metal plate 20 and the joint portion 21 may be omitted. In this case, the conductive layer A1 is composed only of the electrode pads 31. The second organic substrate 50 of this modified example is provided on the lower surface of the electrode pad 31 that constitutes the conductive layer A1. The second organic substrate 50 of this modified example is formed so as to cover at least the outer peripheral edge of the lower surface of the conductive layer A1. The second organic substrate 50 of this modified example is adhered to the lower surface of the electrode pad 31 by the second adhesive layer 52. The opening 53 of this modified example is formed so as to expose a part of the lower surface of the electrode pad 31 and a part of the lower surface of the sealing resin 60.

[0141] According to this configuration, the semiconductor device 10F can be thinned by the amount corresponding to the omission of the metal plate 20 and the joint portion 21. Note that the metal plate 20A and the joint portion 21 in the semiconductor device 10B in the second embodiment can also be omitted in the same manner.

[0142] · In the above third embodiment, the structure of the structure body 11B embedded in the resin layer 90 can be appropriately changed. For example, a structure body having the same structure as the semiconductor device 10A in the first embodiment may be embedded in the resin layer 90. For example, a structure body having the same structure as the semiconductor devices 10D, 10E, and 10F in the modified examples may be embedded in the resin layer 90.

[0143] ·The planar shape of the wiring layer 70 in each of the above embodiments can be appropriately changed. For example, as shown in FIG. 32, the planar shape of the wiring pattern 71 may be changed to a shape in which the opening 71Y is omitted. In this case, the wiring pattern 71 is formed so as to surround the outer periphery of the wiring pattern 72 over the entire circumference in the circumferential direction.

[0144] ·In the above-described third embodiment, the number of layers of the wiring layer and the insulating layer, the routing of the wiring, etc. in the wiring structure formed on the upper surface of the substrate 80 can be variously deformed and changed. ·In the above-described third embodiment, the number of layers of the wiring layer and the insulating layer, the routing of the wiring, etc. in the wiring structure formed on the lower surface of the substrate 80 can be variously deformed and changed.

[0145] ·In each of the above embodiments, the upper surfaces of the sealing resins 60 and 60A are formed flush with the upper surface of the wiring layer 70, but the sealing resins 60 and 60A may be formed so as to cover the upper surface of the wiring layer 70. Alternatively, a solder resist layer covering the upper surface of the wiring layer 70 may be formed. In this case, an opening for exposing a part of the upper surface of the wiring layer 70 as a connection pad may be provided in the sealing resins 60 and 60A or the solder resist layer.

[0146] ·In each of the above embodiments, the upper surfaces of the sealing resins 60 and 60A may be provided at a position lower than the upper surface of the wiring layer 70. In this case, the sealing resins 60 and 60A are formed so as to cover a part of the side surface of the wiring layer 70 in the stacking direction. That is, the sealing resins 60 and 60A are formed so as to expose the side surface at the upper part of the wiring layer 70 in the stacking direction.

[0147] ·In each of the above embodiments, the sealing resins 60 and 60A are formed so as to expose the outer side surface of the second organic substrate 50, but the present invention is not limited to this. For example, the sealing resins 60 and 60A may be formed so as to cover the outer side surface of the second organic substrate 50.

[0148] ·In each of the above embodiments, the sealing resins 60 and 60A are formed so as to cover the outer surface of the first organic substrate 40, but the present invention is not limited to this. For example, the sealing resins 60 and 60A may be formed so as to expose the outer surface of the first organic substrate 40. In this case, the outer surfaces of the sealing resins 60 and 60A may be formed flush with the outer surface of the first organic substrate 40, for example.

[0149] ·The structure of the through hole 43 in each of the above embodiments is not particularly limited. For example, the through hole 43 may be formed in a tapered shape in which the opening width (opening diameter) decreases as it extends from the wiring layer 70 side toward the electrode pads 32 and 33.

[0150] ·The structure of the through hole 60X in the second embodiment is not particularly limited. For example, the inner surface of the through hole 60X may be formed so as to extend perpendicular to the upper surface of the first organic substrate 40.

[0151] ·The structures of the through holes 93 and 94 in the third embodiment are not particularly limited. For example, the inner surfaces of the through holes 93 and 94 may be formed so as to extend perpendicular to the upper surface of the resin layer 91.

[0152] ·The structures of the through holes 95 and 96 in the third embodiment are not particularly limited. For example, the inner surfaces of the through holes 95 and 96 may be formed so as to extend perpendicular to the lower surface of the resin layer 92.

[0153] ·The number of semiconductor elements 30 in each of the above embodiments is not particularly limited. For example, the number of semiconductor elements 30 incorporated in the sealing resins 60 and 60A may be one, two, or three, or may be five or more.

[0154] ·In each of the above embodiments, the first substrate body 41 of the first organic substrate 40 is embodied as a single-layer structure, but the present invention is not limited to this. For example, the first substrate body 41 may be embodied as a laminated structure in which one or more wiring layers and a plurality of insulating layers are laminated.

[0155] ·In each of the above embodiments, the second substrate body 51 of the second organic substrate 50 is embodied as a single-layer structure, but it is not limited thereto. For example, the second substrate body 51 may be embodied as a laminated structure in which one or more wiring layers and a plurality of insulating layers are laminated.

[0156] ·In each of the above embodiments and each of the above modification examples, the semiconductor devices 10A, 10B, 10C, 10D, 10E, and 10F are embodied as power semiconductor devices, but it is not limited thereto. For example, the semiconductor devices 10A, 10B, 10C, 10D, 10E, and 10F may be embodied as various semiconductor devices other than power semiconductor devices. For example, as long as the semiconductor devices 10A, 10B, 10C, 10D, 10E, and 10F have a semiconductor element 30, a first organic substrate 40, a conductive layer A1, a second organic substrate 50, a sealing resin 60, and a wiring layer 70, other structures, functions, etc. are not particularly limited.

[0157] ·In each of the above embodiments, the semiconductor element 30 is embodied as a power semiconductor element, but it is not limited thereto. For example, the semiconductor element 30 may be embodied as various semiconductor elements other than power semiconductor elements.

[0158] ·In each of the above embodiments, the semiconductor element 30 is embodied as a semiconductor element having three electrode pads 31, 32, and 33, but the number of the electrode pads 31, 32, and 33 is not particularly limited. For example, the semiconductor element 30 may be embodied as a semiconductor element having two electrode pads.

Explanation of Reference Numerals

[0159] 10A~10F Semiconductor device 11B Structure 20, 20A Metal plate 21 Joint part 30 Semiconductor element 31 Electrode pad (first electrode pad) 32, 33 Electrode pad (second electrode pad) 40 First organic substrate 41 First substrate body 42 First adhesive layer 50 Second organic substrate 51 Second substrate body 52 Second adhesive layer 53 Opening 60, 60A Encapsulation resin 60X Through-hole 70 Wiring layer (first wiring layer) 75 Through electrode 80 Substrate 80Y Receiving hole 90, 91, 92 Resin layer 100 Wiring layer (second wiring layer) A1 Conductive layer

Claims

1. One or more semiconductor elements having a first electrode pad formed on the lower surface and a second electrode pad formed on the upper surface, A first organic substrate is provided on the upper surface of the semiconductor element so as to cover at least the outer peripheral edge of the upper surface of the second electrode pad, A first wiring layer provided on the upper surface of the first organic substrate and electrically connected to the second electrode pad, A conductive layer formed on the lower surface of the semiconductor element, A second organic substrate is provided on the lower surface of the conductive layer so as to cover at least the outer peripheral edge of the lower surface of the conductive layer, The device comprises a sealing resin that seals the semiconductor element, which is provided between the first organic substrate and the second organic substrate, The conductive layer has the first electrode pad, The first organic substrate comprises a first substrate body and a first adhesive layer formed on the lower surface of the first substrate body and bonded to the upper surface of the semiconductor element. The semiconductor device comprises a second organic substrate, a second substrate body, and a second adhesive layer formed on the upper surface of the second substrate body and bonded to the lower surface of the conductive layer.

2. The first organic substrate is formed from a high-voltage-resistant resin material. The semiconductor device according to claim 1, wherein the second organic substrate is formed of a high-voltage-resistant resin material.

3. The semiconductor device according to claim 1, wherein the difference between the thermal expansion coefficient of the first organic substrate and the thermal expansion coefficient of the second organic substrate is smaller than the difference between the thermal expansion coefficient of the second organic substrate and the thermal expansion coefficient of the semiconductor element.

4. The second organic substrate is formed to protrude outward from the outer surface of the conductive layer, The sealing resin is provided on the upper surface of the second organic substrate that is exposed from the conductive layer. The semiconductor device according to claim 1, wherein the sealing resin is formed to cover the outer surface of the conductive layer.

5. The second organic substrate is formed to protrude outward from the outer surface of the first organic substrate. The semiconductor device according to claim 4, wherein the sealing resin is formed to cover the outer surface of the first organic substrate.

6. The conductive layer is A metal plate provided below the semiconductor element, The present invention further includes a joint that electrically connects the metal plate and the first electrode pad, The semiconductor device according to claim 1, wherein the second organic substrate is provided on the lower surface of the metal plate.

7. The metal plate is formed to protrude outward from the outer surface of the first organic substrate. The aforementioned semiconductor device is A through hole that penetrates the sealing resin in the thickness direction and exposes a part of the upper surface of the metal plate, The semiconductor device according to claim 6, further comprising a through electrode that fills the through hole and is electrically connected to the metal plate.

8. The semiconductor device according to claim 6, wherein the second organic substrate has an opening that penetrates the second organic substrate in the thickness direction and exposes a part of the lower surface of the metal plate.

9. The semiconductor device according to claim 6, wherein the metal plate is thicker than the first organic substrate and thicker than the second organic substrate.

10. The sealing resin exposes the lower surface of the metal plate, The semiconductor device according to claim 6, wherein the second adhesive layer is bonded to the lower surface of the metal plate and the lower surface of the sealing resin.

11. A structure comprising the first organic substrate, the semiconductor element, the first wiring layer, the conductive layer, the second organic substrate, and the sealing resin, The aforementioned structure comprises a substrate having a housing hole in which the structure is arranged, A resin layer that covers the upper and lower surfaces of the substrate and incorporates the structure, The semiconductor device according to claim 1, further comprising a second wiring layer formed on the upper surface of the resin layer and electrically connected to the first wiring layer.

Images