Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device in which reliability can be improved.SOLUTION: In a silicon carbide semiconductor device 100, an active region IR comprises: a first super junction layer 10; and an element layer 40. The first super junction layer alternately has a first region 41 and a second region 42. A peripheral region OR comprises: a second super junction layer 20; a termination layer 50; and an insulation layer 7. The second super junction layer alternately has a third region 43 and a fourth region 44. The termination layer is provided above the second super junction layer by being contacted with the second super junction layer, and alternately has a fifth region 45 and a sixth region 46. The fifth region is provided corresponding to the third region, and the sixth region is provided corresponding to the fourth region. Impurity density of the sixth region is larger than impurity density of the fifth region, and is less than or equal to 68 times of the impurity density of the fifth region.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device. This application claims priority based on Japanese Patent Application No. 2020-118900, filed on July 10, 2020. All the descriptions described in the Japanese patent application are incorporated herein by reference.

Background Art

[0002] Japanese Unexamined Patent Application Publication No. 2006-73987 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2003-273355 (Patent Document 2) describe MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) having a super junction structure mainly targeting silicon semiconductors.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

[0004] The silicon carbide semiconductor device according to the present disclosure includes a substrate, an active region, a peripheral region, and a first electrode. The substrate is made of a silicon carbide semiconductor of a first conductivity type. The active region is provided on a part of the first main surface of the substrate. The peripheral region is provided on the substrate and surrounds the active region in a plan view. The first electrode is provided on a second main surface facing the first main surface of the substrate. The active region includes a first superjunction layer, an element layer, and a second electrode. The first superjunction layer is provided above the substrate and has a first region of a first conductivity type and a second region of a second conductivity type alternately. The element layer is provided above the first superjunction layer. The second electrode is provided on the element layer. The peripheral region includes a second superjunction layer, a termination layer, and an insulating layer. The second superjunction layer is provided above the substrate and has a third region of a first conductivity type and a fourth region of a second conductivity type alternately. The termination layer is provided in contact with the second superjunction layer and has a fifth region of a second conductivity type and a sixth region of a second conductivity type alternately. The insulating layer is in contact with each of the upper end surfaces of the fifth region and the sixth region. The fifth region is provided corresponding to the third region, and the sixth region is provided corresponding to the fourth region. The impurity concentration of the sixth region is greater than the impurity concentration of the fifth region and is 68 times or less the impurity concentration of the fifth region.

Brief Description of the Drawings

[0005]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0006] [Problems to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of improving reliability. [Effects of the Present Disclosure] According to the present disclosure, a silicon carbide semiconductor device capable of improving reliability can be provided. [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the crystallographic description of this specification, individual orientations are indicated by [], collective orientations are indicated by <>, individual planes are indicated by (), and collective planes are indicated by {}. The fact that a crystallographic index is negative is usually expressed by attaching "-" (bar) above the number, but in this specification, a negative crystallographic index is expressed by attaching a negative sign before the number.

[0007] (1) The silicon carbide semiconductor device 100 according to the present disclosure includes a substrate 90, an active region IR, a peripheral region OR, and a first electrode 61. The substrate 90 is made of a silicon carbide semiconductor of a first conductivity type. The active region IR is provided on a part of the first main surface 1 of the substrate 90. The peripheral region OR is provided on the substrate 90 and surrounds the active region IR in a plan view. The first electrode 61 is provided on the second main surface 2 facing the first main surface 1 of the substrate 90. The active region IR includes a first superjunction layer 10, an element layer 40, and a second electrode 62. The first superjunction layer 10 is provided above the substrate 90 and has first regions 41 of a first conductivity type and second regions 42 of a second conductivity type alternately. The element layer 40 is provided above the first superjunction layer 10. The second electrode 62 is provided on the element layer 40. The peripheral region OR includes a second superjunction layer 20, a termination layer 50, and an insulating layer 7. The second superjunction layer 20 is provided above the substrate 90 and has third regions 43 of a first conductivity type and fourth regions 44 of a second conductivity type alternately. The termination layer 50 is provided in contact with the second superjunction layer 20 and has fifth regions 45 of a second conductivity type and sixth regions 46 of a second conductivity type alternately. The insulating layer 7 is in contact with each of the upper end surfaces of the fifth region 45 and the sixth region 46. The fifth region 45 is provided corresponding to the third region 43, and the sixth region 46 is provided corresponding to the fourth region 44. The impurity concentration of the sixth region 46 is greater than the impurity concentration of the fifth region 45 and is 68 times or less the impurity concentration of the fifth region 45.

[0008] (2) In the silicon carbide semiconductor device 100 according to (1) above, the impurity concentration of the sixth region 46 may be greater than the impurity concentration of the fourth region 44.

[0009] (3) In the silicon carbide semiconductor device 100 according to (1) or (2) above, the absolute value of the difference between the impurity concentration of the fifth region 45 and the impurity concentration of the sixth region 46 may be substantially equal to the sum of the impurity concentration of the third region 43 and the impurity concentration of the fourth region 44.

[0010] (4) In the silicon carbide semiconductor device 100 according to any one of (1) to (3) above, the first distance D1 between the upper end surface of the element layer 40 and the interface between the element layer 40 and the first super junction layer 10 may be greater than the second distance D2 between the upper end surface of the termination layer 50 and the interface between the termination layer 50 and the second super junction layer 20.

[0011] (5) In the silicon carbide semiconductor device 100 according to any one of (1) to (4) above, each of the first region 41 and the third region 43 may have a first portion 71 and a second portion 72 located between the first portion 71 and the substrate 90. Each of the second region 42 and the fourth region 44 may have a third portion 73 in contact with the first portion 71 and a fourth portion 74 in contact with the second portion 72 and located between the third portion 73 and the substrate 90. In a cross-section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the second portion 72 may be greater than the width of the first portion 71, the width of the fourth portion 74 may be smaller than the width of the third portion 73, the width of the first portion 71 may be smaller than the height of the first portion 71, and the width of the third portion 73 may be smaller than the height of the third portion 73. The impurity concentration of each of the first portion 71 and the third portion 73 may be greater than the impurity concentration of each of the second portion 72 and the fourth portion 74.

[0012] (6) In the silicon carbide semiconductor device 100 according to any one of (1) to (5) above, the impurity concentration of each of the first region 41 and the third region 43 may be 3×10 16 cm -3 or more and 5×10 17 cm -3 or less. The impurity concentration of each of the second region 42 and the fourth region 44 may be 3×10 16 cm -3 or more and 5×10 17 cm -3 or less.

[0013] (7) In the silicon carbide semiconductor device 100 according to any one of (1) to (6) above, a first buffer layer 12 of a first conductivity type may be provided between the first superjunction layer 10 and the substrate 90. A second buffer layer 52 of a first conductivity type may be provided between the second superjunction layer 20 and the substrate 90.

[0014] (8) In the silicon carbide semiconductor device 100 according to any one of (1) to (7) above, the element layer 40 may include a first impurity region 14 of a first conductivity type, a second impurity region 23 that is in contact with the first impurity region 14 and has a second conductivity type, and a third impurity region 30 that is separated from the first impurity region 14 by the second impurity region 23 and has a first conductivity type. The element layer 40 may be provided with a trench 5 having a side surface 8 formed by each of the first impurity region 14, the second impurity region 23, and the third impurity region 30, and a bottom surface 9 that is continuous with the side surface 8 and is formed by the first impurity region 14. The first electrode 61 may be a source electrode. The second electrode 62 may be a drain electrode. A gate electrode 63 may be provided inside the trench 5.

[0015] (9) In the silicon carbide semiconductor device 100 according to any one of (1) to (8) above, the first main surface 1 may be a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane. [Details of Embodiments of the Present Disclosure] Hereinafter, details of embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0016] (First Embodiment) First, the configuration of the silicon carbide semiconductor device 100 according to the first embodiment will be described. FIG. 1 is a schematic longitudinal sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0017] As shown in FIG. 1, the silicon carbide semiconductor device 100 according to the first embodiment is a planar MOSFET. The silicon carbide semiconductor device 100 according to the first embodiment mainly includes, for example, a substrate 90, an active region IR, a peripheral region OR, and a first electrode 61. The substrate 90 is made of a silicon carbide semiconductor of the first conductivity type. The first conductivity type is, for example, n-type. The substrate 90 contains, for example, an n-type impurity capable of imparting an n-type such as N (nitrogen). The substrate 90 has a first main surface 1 and a second main surface 2. The second main surface 2 faces the first main surface 1. The second main surface 2 is the surface on the opposite side of the first main surface 1.

[0018] The substrate 90 is composed of, for example, polytype 4H hexagonal silicon carbide. The first main surface 1 may be, for example, a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane. Specifically, the first main surface 1 may be a (0001) plane or a plane inclined at an angle of 8° or less with respect to the (0001) plane. The first main surface 1 may be a (000-1) plane or a plane inclined at an angle of 8° or less with respect to the (000-1) plane. The substrate 90 has a first substrate portion 11 and a second substrate portion 51.

[0019] The active region IR is provided on a part of the first main surface 1 of the substrate 90. The first main surface 1 has a first region 91 and a second region 92. The active region IR is on the first region 91. The active region IR mainly includes a first buffer layer 12, a first superjunction layer 10, an element layer 40, a second electrode 62, a gate electrode 63, a gate insulating film 6, and a separation insulating film 64. The first buffer layer 12 is located between the first superjunction layer 10 and the substrate 90. The first buffer layer 12 has, for example, an n-type (first conductivity type). The first buffer layer 12 contains, for example, an n-type impurity capable of imparting an n-type such as N (nitrogen). The first buffer layer 12 is in contact with the first region 91.

[0020] The first super junction layer 10 is provided above the substrate 90. The first super junction layer 10 is in contact with, for example, the first buffer layer 12. The first super junction layer 10 has the first region 41 and the second region 42 alternately. The first region 41 and the second region 42 are alternately arranged, for example, along a direction parallel to the first main surface 1. From another perspective, the first region 41 and the second region 42 are alternately arranged, for example, along a direction intersecting the thickness direction of the substrate 90.

[0021] The first region 41 has an n-type (first conductivity type). The first region 41 contains an n-type impurity capable of imparting an n-type, such as N (nitrogen) for example. The second region 42 has a p-type (second conductivity type). The second region 42 contains a p-type impurity capable of imparting a p-type, such as Al (aluminum) for example.

[0022] The element layer 40 is provided above the first super junction layer 10. The element layer 40 is, for example, a switching element part. The element layer 40 has, for example, a first impurity region 14, a second impurity region 23, a third impurity region 30, and a fourth impurity region 24. The first impurity region 14 is, for example, a drift region. The first impurity region 14 has an n-type (first conductivity type). The first impurity region 14 contains an n-type impurity capable of imparting an n-type, such as N (nitrogen) for example. The first impurity region 14 is in contact with the first region 41.

[0023] The second impurity region 23 is, for example, a body region. The second impurity region 23 is in contact with the first impurity region 14. The second impurity region 23 has a p-type (second conductivity type). The second impurity region 23 contains a p-type impurity capable of imparting a p-type, such as Al (aluminum) for example. The second impurity region 23 is in contact with the first region 41 and the second region 42. The concentration of the p-type impurity contained in the second impurity region 23 may be higher than the concentration of the n-type impurity contained in the first impurity region 14.

[0024] The third impurity region 30 is, for example, a source region. The third impurity region 30 is separated from the first impurity region 14 by the second impurity region 23. The third impurity region 30 has an n-type (first conductivity type). The third impurity region 30 contains an n-type impurity capable of imparting an n-type, such as P (phosphorus). The concentration of the n-type impurity contained in the third impurity region 30 may be higher than the concentration of the p-type impurity contained in the second impurity region 23.

[0025] The fourth impurity region 24 is, for example, a contact region. The fourth impurity region 24 is in contact with the second impurity region 23 and the third impurity region 30. The fourth impurity region 24 has a p-type (second conductivity type). The fourth impurity region 24 contains a p-type impurity capable of imparting a p-type, such as Al (aluminum). The concentration of the p-type impurity contained in the fourth impurity region 24 may be higher than the concentration of the p-type impurity contained in the second impurity region 23.

[0026] The gate insulating film 6 is provided on the element layer 40. The gate insulating film 6 is composed of, for example, silicon dioxide. The gate insulating film 6 is in contact with, for example, each of the first impurity region 14, the second impurity region 23, and the third impurity region 30. In the second impurity region 23 in contact with the gate insulating film 6, a channel can be formed.

[0027] The gate electrode 63 is provided on the gate insulating film 6. The gate electrode 63 is in contact with the gate insulating film 6. The gate electrode 63 is composed of a conductor such as, for example, polysilicon doped with an impurity.

[0028] The second electrode 62 is, for example, a source electrode. The second electrode 62 is provided on the element layer 40. The second electrode 62 is in contact with the third impurity region 30 and the fourth impurity region 24. The second electrode 62 may cover the isolation insulating film 64.

[0029] The isolation insulating film 64 is provided so as to cover the gate electrode 63. The isolation insulating film 64 is in contact with each of the gate electrode 63 and the gate insulating film 6. The isolation insulating film 64 is composed of, for example, an NSG (None-doped Silicate Glass) film or a PSG (Phosphorus Silicate Glass) film. The isolation insulating film 64 electrically insulates the gate electrode 63 and the second electrode 62.

[0030] The first electrode 61 is, for example, a drain electrode. The first electrode 61 is provided on the second main surface 2 of the substrate 90. The second main surface 2 has a third region 93 and a fourth region 94. The third region 93 is on the opposite side of the first region 91. The fourth region 94 is on the opposite side of the second region 92. The first electrode 61 is in contact with each of the third region 93 and the fourth region 94.

[0031] The peripheral region OR is provided on the substrate 90. The peripheral region OR is on the second region 92 of the first main surface 1. The peripheral region OR surrounds the active region IR in plan view. Plan view is a view of the silicon carbide semiconductor device 100 in a direction perpendicular to the first main surface 1. The peripheral region OR mainly includes a second buffer layer 52, a second superjunction layer 20, a termination layer 50, and an insulating layer 7.

[0032] The second buffer layer 52 is located between the second superjunction layer 20 and the substrate 90. The second buffer layer 52 has, for example, an n-type (first conductivity type). The second buffer layer 52 contains an n-type impurity capable of imparting an n-type, such as N (nitrogen). The second buffer layer 52 is in contact with the second region 92 of the first main surface 1. The second buffer layer 52 is electrically connected to the first buffer layer 12.

[0033] The second superjunction layer 20 is provided above the substrate 90. The second superjunction layer 20 is in contact with, for example, the second buffer layer 52. The second superjunction layer 20 has the third region 43 and the fourth region 44 alternately. The third region 43 and the fourth region 44 are alternately arranged, for example, along a direction parallel to the first main surface 1. In other words, the third region 43 and the fourth region 44 are alternately arranged, for example, along a direction intersecting the thickness direction of the substrate 90. The arrangement direction of the third region 43 and the fourth region 44 is the same as the arrangement direction of the first region 41 and the second region 42.

[0034] The third region 43 has an n-type (first conductivity type). The third region 43 contains an n-type impurity capable of imparting an n-type, such as N (nitrogen), for example. The fourth region 44 has a p-type (second conductivity type). The fourth region 44 contains a p-type impurity capable of imparting a p-type, such as Al (aluminum), for example.

[0035] The termination layer 50 is provided in contact with the second superjunction layer 20. The termination layer 50 has the fifth region 45 and the sixth region 46 alternately. The fifth region 45 is provided corresponding to the third region 43, and the sixth region 46 is provided corresponding to the fourth region 44. The fifth region 45 is in contact with the third region 43. The sixth region 46 is in contact with the fourth region 44. The fifth region 45 and the sixth region 46 are alternately arranged, for example, along a direction parallel to the first main surface 1. In other words, the fifth region 45 and the sixth region 46 are alternately arranged, for example, along a direction intersecting the thickness direction of the substrate 90.

[0036] Each of the fifth region 45 and the sixth region 46 has a p-type (second conductivity type). Each of the fifth region 45 and the sixth region 46 contains a p-type impurity capable of imparting a p-type, such as Al (aluminum). The impurity concentration of the sixth region 46 is greater than the impurity concentration of the fifth region 45 and is 68 times or less the impurity concentration of the fifth region 45. The lower limit of the impurity concentration of the sixth region 46 is not particularly limited, but may be, for example, 1.09 times or more, or 1.58 times or more the impurity concentration of the fifth region 45. The upper limit of the impurity region of the sixth region 46 is not particularly limited, but may be, for example, 20 times or less, 33.3 times or less, or 55 times or less the impurity concentration of the fifth region 45.

[0037] The fifth region 45 is formed, for example, by implanting a p-type impurity into the third region 43. Similarly, the sixth region 46 is formed, for example, by implanting a p-type impurity into the fourth region 44. In this case, the impurity concentration of the sixth region 46 is greater than the impurity concentration of the fourth region 44. The absolute value of the difference between the impurity concentration of the fifth region 45 and the impurity concentration of the sixth region 46 may be substantially equal to the sum of the impurity concentration of the third region 43 and the impurity concentration of the fourth region 44. Specifically, the value obtained by dividing the absolute value of the difference between the impurity concentration of the fifth region 45 and the impurity concentration of the sixth region 46 by the sum of the impurity concentration of the third region 43 and the impurity concentration of the fourth region 44 is, for example, 0.8 or more and 1.2 or less.

[0038] The impurity concentration of the first region 41 is substantially the same as the impurity concentration of the third region 43. The impurity concentration of each of the first region 41 and the third region 43 is, for example, 3×10 16 cm -3 or more and 5×10 17 cm -3 or less. The lower limit of the impurity concentration of each of the first region 41 and the third region 43 is not particularly limited, but may be, for example, 4×10 16 cm -3 or more, or 5×10 16 cm -3The above may be the case. The upper limit of the impurity concentration in each of the first region 41 and the third region 43 is not particularly limited. For example, it may be 4×10 17 cm -3 or less, or it may be 3×10 17 cm -3 or less.

[0039] The impurity concentration in the second region 42 is substantially the same as the impurity concentration in the fourth region 44. The impurity concentration in each of the second region 42 and the fourth region 44 may be, for example, 3×10 16 cm -3 or more and 5×10 17 cm -3 or less. The lower limit of the impurity concentration in each of the second region 42 and the fourth region 44 is not particularly limited. For example, it may be 4×10 16 cm -3 or more, or it may be 5×10 16 cm -3 or more. The upper limit of the impurity concentration in each of the second region 42 and the fourth region 44 is not particularly limited. For example, it may be 4×10 17 cm -3 or less, or it may be 3×10 17 cm -3 or less.

[0040] The insulating layer 7 is provided on the terminal layer 50. The terminal layer 50 has a third main surface 3. The third main surface 3 is in contact with the insulating layer 7. The third main surface 3 has a first upper end surface 3a and a second upper end surface 3b. The insulating layer 7 is in contact with each of the upper end surface (the first upper end surface 3a) of the fifth region 45 and the upper end surface (the second upper end surface 3b) of the sixth region 46. The fifth region 45 is located between the third region 43 and the insulating layer 7. The sixth region 46 is located between the fourth region 44 and the insulating layer 7. The insulating layer 7 is formed of, for example, an oxide film such as an LTO (Low Temperature Oxide) film, an HTO (High Temperature Oxide) film, an NSG film, or a PSG film. A thermal oxide film may be formed under the insulating layer 7.

[0041] As shown in FIG. 1, a first distance D1 between the upper end surface (the fourth main surface 4) of the element layer 40 and the boundary surface (the first boundary surface 81) between the element layer 40 and the first super junction layer 10 is greater than a second distance D2 between the upper end surface (the third main surface 3) of the termination layer 50 and the boundary surface (the second boundary surface 82) between the termination layer 50 and the second super junction layer 20. The value obtained by subtracting the second distance D2 from the first distance D1 may be 0.5 μm or more, or may be 1 μm or more. The thickness (the fourth thickness T4) of the second super junction layer 20 is greater than the thickness (the third thickness T3) of the first super junction layer 10.

[0042] (Second Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the second embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the second embodiment is mainly different from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment in that the peripheral region OR has a plurality of peripheral region portions, and the other points are the same as the configuration of the silicon carbide semiconductor device 100 according to the first embodiment. Hereinafter, the description will focus on the configuration different from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0043] FIG. 2 is a partial cross-sectional schematic view showing the configuration of the silicon carbide semiconductor device 100 according to the second embodiment. As shown in FIG. 2, in a plan view, the peripheral region OR surrounds the active region IR. The peripheral region OR has a first peripheral region portion OR1, a second peripheral region portion OR2, and a third peripheral region portion OR3. In a plan view, the first peripheral region portion OR1 surrounds the active region IR. The first peripheral region portion OR1 is continuous with the active region IR. In a plan view, the second peripheral region portion OR2 surrounds the first peripheral region portion OR1. The second peripheral region portion OR2 is continuous with the first peripheral region portion OR1.

[0044] The silicon carbide semiconductor device 100 has a first superjunction layer 10 and a second superjunction layer 20. The first superjunction layer 10 has a first region 41 and a second region 42. The first region 41 and the second region 42 are alternately arranged along the first direction 101. In plan view, the longitudinal direction of each of the first region 41 and the second region 42 is the second direction 102. In plan view, the short transverse direction of each of the first region 41 and the second region 42 is the first direction 101.

[0045] Each of the first direction 101 and the second direction 102 is parallel to the first main surface 1. The first direction 101 is a direction perpendicular to the second direction 102. The first direction 101 is, for example, the <1-100> direction. The second direction 102 is, for example, the <11-20> direction. The first direction 101 may be, for example, the direction obtained by projecting the <1-100> direction onto the first main surface 1. The second direction 102 may be, for example, the direction obtained by projecting the <11-20> direction onto the first main surface 1.

[0046] The second superjunction layer 20 has a third region 43 and a fourth region 44. The third region 43 and the fourth region 44 are alternately arranged along the first direction 101. In plan view, the longitudinal direction of each of the third region 43 and the fourth region 44 is the second direction 102. In plan view, the short transverse direction of each of the third region 43 and the fourth region 44 is the first direction 101.

[0047] In plan view, the third peripheral region portion OR3 surrounds the second peripheral region portion OR2. The third peripheral region portion OR3 is continuous with the second peripheral region portion OR2. The third peripheral region portion OR3 has, for example, a channel stopper 66. In plan view, the channel stopper 66 surrounds the second peripheral region portion OR2. The channel stopper 66 has, for example, an n-type (first conductivity type). The impurity concentration of the channel stopper 66 is, for example, higher than the impurity concentration of each of the first region 41 and the third region 43.

[0048] As shown in FIG. 2, the channel stopper 66 has a first channel stopper region 66a extending along the first direction 101 and a second channel stopper region 66b extending along the second direction 102. The second channel stopper region 66b may be provided along the third region 43. The first channel stopper region 66a may cross the third region 43 and the fourth region 44. The first channel stopper region 66a may cross the first region 41 and the second region 42.

[0049] FIG. 3 is a schematic longitudinal sectional view taken along line III-III of FIG. 2. As shown in FIG. 3, the first peripheral region portion OR1 has a first terminal layer 56. The first terminal layer 56 has a fifth region 45 and a sixth region 46. The second peripheral region portion OR2 has a second terminal layer 55. The second terminal layer 55 has a seventh region 47 and an eighth region 48. The seventh region 47 corresponds to the third region 43, and the eighth region 48 corresponds to the fourth region 44. The seventh region 47 is in contact with the third region 43. The eighth region 48 is in contact with the fourth region 44. The insulating layer 7 is in contact with, for example, the first terminal layer 56, the second terminal layer 55, and the channel stopper 66.

[0050] The impurity concentration of the second terminal layer 55 may be smaller than the impurity concentration of the first terminal layer 56. Specifically, the impurity concentration of the seventh region 47 may be smaller than the impurity concentration of the fifth region 45. Similarly, the impurity concentration of the eighth region 48 may be smaller than the impurity concentration of the sixth region 46. In the above description, the two-stage JTE (Junction Termination Extension) having two terminal layers has been described, but a three-stage JTE having three terminal layers may be adopted.

[0051] As shown in FIG. 3, in a cross section that traverses the first region 41 and the second region 42, the height of the first region 41 in the third direction 103 may be greater than the width of the first region 41 in the first direction 101. Similarly, in a cross section that traverses the first region 41 and the second region 42, the height of the second region 42 in the third direction 103 may be greater than the width of the second region 42 in the first direction 101. The third direction 103 is a direction perpendicular to each of the first direction 101 and the second direction 102. The third direction 103 is, for example, the <0001> direction. The third direction 103 may be, for example, a direction inclined with respect to the <0001> direction.

[0052] As shown in FIG. 3, in a cross section that traverses the third region 43 and the fourth region 44, the height of the third region 43 in the third direction 103 may be greater than the width of the third region 43 in the first direction 101. Similarly, in a cross section that traverses the third region 43 and the fourth region 44, the height of the fourth region 44 in the third direction 103 may be greater than the width of the fourth region 44 in the first direction 101.

[0053] In a cross section that traverses the first region 41 and the third region 43, the height of the third region 43 in the third direction 103 may be greater than the height of the first region 41 in the third direction 103. Similarly, in a cross section that traverses the second region 42 and the fourth region 44, the height of the fourth region 44 in the third direction 103 may be greater than the height of the second region 42 in the third direction 103.

[0054] As shown in FIG. 3, in a cross-sectional view, a plurality of gate electrodes 63 may be arranged along the first direction 101. Similarly, each of the first impurity region 14, the second impurity region 23, the third impurity region 30, and the fourth impurity region 24 may be arranged in plurality along the first direction 101. The fourth impurity region 24 may penetrate the third impurity region 30 and be in contact with the first region 41.

[0055] Figure 4 is a schematic longitudinal sectional view taken along line IV-IV of Figure 2. As shown in Figure 4, the peripheral region OR has a plurality of JTE regions. The first peripheral region part OR1 has a first JTE region 53. The second peripheral region part OR2 has a second JTE region 54. The second JTE region 54 is continuous with the first JTE region 53. Each of the first JTE region 53 and the second JTE region 54 has, for example, a p-type. The impurity concentration of the second JTE region 54 is, for example, smaller than the impurity concentration of the first JTE region 53. The value obtained by dividing the impurity concentration of the second JTE region 54 by the impurity concentration of the first JTE region 53 is, for example, 0.5.

[0056] As shown in Figure 4, the first region 41 may extend along the second direction 102 to the peripheral region OR. In the peripheral region OR, the first region 41 may be in contact with the first JTE region 53, the second JTE region 54, and the channel stopper 66. In the present embodiment, the case where the peripheral region OR has two JTE regions has been described, but the number of JTE regions is not limited to two. The peripheral region OR may have, for example, three or more JTE regions. In this case, the impurity concentration of the JTE regions may decrease as going outward from the active region IR.

[0057] (Third Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the third embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the third embodiment is mainly different from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment in that the active region IR is a trench-type MOSFET, and the other points are the same as the configuration of the silicon carbide semiconductor device 100 according to the first embodiment. Hereinafter, the description will focus on the configuration different from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0058] FIG. 5 is a schematic longitudinal sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the third embodiment. As shown in FIG. 5, a trench 5 is provided in the element layer 40. The shape of the trench 5 is, for example, V-shaped. The trench 5 is defined by a side surface 8 and a bottom surface 9. The side surface 8 is composed of each of a first impurity region 14, a second impurity region 23, and a third impurity region 30. The bottom surface 9 is continuous with the side surface 8. The bottom surface 9 is composed of the first impurity region 14.

[0059] At least a part of the gate insulating film 6 is provided, for example, inside the trench 5. The gate insulating film 6 is in contact with each of the first impurity region 14, the second impurity region 23, and the third impurity region 30 on the side surface 8. The gate insulating film 6 is in contact with the first impurity region 14 on the bottom surface 9. At least a part of the gate electrode 63 is provided, for example, inside the trench 5.

[0060] (Fourth Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment is mainly different from the configuration of the silicon carbide semiconductor device 100 according to the second embodiment in that the active region IR is a trench-type MOSFET, and other points are the same as the configuration of the silicon carbide semiconductor device 100 according to the second embodiment. Hereinafter, the description will focus on the configuration different from the configuration of the silicon carbide semiconductor device 100 according to the second embodiment.

[0061] FIG. 6 is a partial cross-sectional schematic view showing the configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment. As shown in FIG. 6, in a plan view, the peripheral region OR surrounds the active region IR. The peripheral region OR has a first peripheral region portion OR1, a second peripheral region portion OR2, and a third peripheral region portion OR3. The channel stopper 66 has a first channel stopper region 66a extending along the first direction 101 and a second channel stopper region 66b extending along the second direction 102. The second channel stopper region 66b may be provided along the fourth region 44. The first channel stopper region 66a may cross the third region 43 and the fourth region 44. The first channel stopper region 66a may cross the first region 41 and the second region 42.

[0062] FIG. 7 is a longitudinal cross-sectional schematic view taken along line VII-VII of FIG. 6. As shown in FIG. 7, a trench 5 is provided in the element layer 40. The trench 5 is defined by a side surface 8 and a bottom 9. The side surface 8 is composed of each of a first impurity region 14, a second impurity region 23, and a third impurity region 30. The bottom 9 is continuous with the side surface 8. The bottom 9 is composed of the first impurity region 14.

[0063] At least a part of the gate insulating film 6 is provided, for example, inside the trench 5. The gate insulating film 6 is in contact with each of the first impurity region 14, the second impurity region 23, and the third impurity region 30 on the side surface 8. The gate insulating film 6 is in contact with the first impurity region on the bottom 9. At least a part of the gate electrode 63 is provided, for example, inside the trench 5. At least a part of the isolation insulating film 64 is provided, for example, inside the trench 5.

[0064] The active region IR may have, for example, a sixth impurity region 67. The sixth impurity region 67 has, for example, a p-type (second conductivity type). The sixth impurity region 67 faces the bottom 9 of the trench 5. The sixth impurity region 67 is in contact with, for example, the first region 41, the second region 42, and the first impurity region 14. The sixth impurity region 67 is located between the second region 42 and the first impurity region 14 in the third direction 103. In the first direction 101, the width of the sixth impurity region 67 may be larger than the width of the second region 42. In the first direction 101, the width of the sixth impurity region 67 may be larger than the width of the bottom 9 of the trench 5.

[0065] FIG. 8 is a schematic longitudinal sectional view taken along line VIII-VIII of FIG. 6. As shown in FIG. 8, the sixth impurity region 67 may extend along the second direction 102. The width of the sixth impurity region 67 in the second direction 102 may be larger than the width of the sixth impurity region 67 in the first direction 101. Similarly, the first impurity region 14 may extend along the second direction 102. The width of the first impurity region 14 in the second direction 102 may be larger than the width of the first impurity region 14 in the first direction 101.

[0066] As shown in FIG. 8, the second region 42 may extend into the peripheral region OR along the second direction 102. In the peripheral region OR, the second region 42 may be in contact with the first JTE region 53, the second JTE region 54, and the channel stopper 66.

[0067] (Fifth Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the fifth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the fifth embodiment is mainly different from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment in that the active region IR is a PN diode, and in other respects, it is the same as the configuration of the silicon carbide semiconductor device 100 according to the first embodiment. Hereinafter, the description will focus on the configuration different from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0068] FIG. 9 is a schematic longitudinal sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the fifth embodiment. As shown in FIG. 9, the element layer 40 may be, for example, a rectifying element portion. The element layer 40 has, for example, a p-type (second conductivity type). The second electrode 62 is in contact with the element layer 40. The second electrode 62 is provided on the element layer 40. The element layer 40 is provided on the first superjunction layer 10. The element layer 40 is in contact with, for example, each of the first region 41 and the second region 42. The first electrode 61 is, for example, a cathode electrode. The second electrode 62 is, for example, an anode electrode.

[0069] (Sixth Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the sixth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the sixth embodiment is mainly different from the configuration of the silicon carbide semiconductor device 100 according to the third embodiment in that each of the first region 41 and the third region 43 has a first portion 71 and a second portion 72, and each of the second region 42 and the fourth region 44 has a third portion 73 and a fourth portion 74, and the other points are the same as the configuration of the silicon carbide semiconductor device 100 according to the third embodiment. Hereinafter, the description will focus on the configuration different from the configuration of the silicon carbide semiconductor device 100 according to the third embodiment.

[0070] FIG. 10 is a schematic longitudinal sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the sixth embodiment. As shown in FIG. 10, each of the first region 41 and the third region 43 has a first portion 71 and a second portion 72. The second portion 72 is continuous with the first portion 71. The second portion 72 is located between the first portion 71 and the substrate 90. The first portion 71 may be in contact with the first impurity region 14. The first portion 71 may be in contact with the fifth region 45. The second portion 72 may be in contact with the first buffer layer 12. The second portion 72 may be in contact with the second buffer layer 52.

[0071] As shown in FIG. 10, each of the second region 42 and the fourth region 44 has a third portion 73 and a fourth portion 74. The third portion 73 is in contact with the first portion 71. The fourth portion 74 is in contact with the second portion 72. The fourth portion 74 is continuous with the third portion 73. The fourth portion 74 is located between the third portion 73 and the substrate 90. The third portion 73 may be in contact with the first impurity region 14. The third portion 73 may be in contact with the sixth region 46. The fourth portion 74 may be in contact with the first buffer layer 12. The fourth portion 74 may be in contact with the second buffer layer 52.

[0072] The third portion 73 and the first portion 71 are adjacent to each other in the first direction 101. The third portion 73 and the first portion 71 are alternately arranged in the first direction 101. The fourth portion 74 and the second portion 72 are adjacent to each other in the first direction 101. The fourth portion 74 and the second portion 72 are alternately arranged in the first direction 101.

[0073] The impurity concentration in the third portion 73 may be higher than the impurity concentration in the fourth portion 74. The impurity concentration in the first portion 71 is substantially the same as the impurity concentration in the second portion 72. The impurity concentration in the first portion 71 is substantially the same as the impurity concentration in the third portion 73. The impurity concentration in the fourth portion 74 may be lower than the impurity concentration in the second portion 72.

[0074] The impurity concentration of each of the first portion 71 and the third portion 73 is, for example, 3×10 16 cm -3 or more and 5×10 17 cm -3 or less. The lower limit of the impurity concentration of each of the first portion 71 and the third portion 73 is not particularly limited, but may be, for example, 4×10 16 cm -3 or more, or 5×10 16 cm -3 or more. The upper limit of the impurity concentration of each of the first portion 71 and the third portion 73 is not particularly limited, but may be, for example, 4×10 17 cm -3It may also be as follows, or 3×10 17 cm -3 or less may also be acceptable.

[0075] As shown in FIG. 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the second portion 72 is larger than the width of the first portion 71 (the first width W1). As going from the first portion 71 toward the first main surface 1, the width of the second portion 72 may monotonically increase. The width of the second portion 72 (the second width W2) in contact with the buffer layer 49 is larger than the first width W1.

[0076] As shown in FIG. 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the fourth portion 74 is smaller than the width of the third portion 73 (the third width W3). As going from the third portion 73 toward the first main surface 1, the width of the fourth portion 74 may monotonically decrease. The width of the fourth portion 74 (the fourth width W4) in contact with the buffer layer 49 is smaller than the third width W3.

[0077] As shown in FIG. 10, the total value of the width of the first portion 71 (the first width W1) and the width of the third portion 73 (the third width W3) is, for example, 0.5 μm or more and 4 μm or less. The total value of the width of the first portion 71 (the first width W1) and the width of the third portion 73 (the third width W3) is the pitch P of each of the first superjunction layer 10 and the second superjunction layer 20. The height (the third height) of each of the first region 41 and the second region 42 is, for example, 2 μm or more.

[0078] As shown in FIG. 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the first portion 71 (the first width W1) may be smaller than the height of the first portion 71 (the first height T1). The height of the first portion 71 (the first height T1) may be larger than the height of the second portion 72 (the second height T2).

[0079] As shown in FIG. 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width (third width W3) of the third portion 73 may be smaller than the height (first height T1) of the third portion 73. The height (first height T1) of the third portion 73 may be larger than the height (second height T2) of the fourth portion 74.

[0080] Next, a method for forming the superjunction layer will be described. First, a buffer layer 49 is formed on a substrate 90. The buffer layer 49 is formed, for example, by epitaxial growth. Next, a first region 41 and a third region 43 are formed on the buffer layer 49. The first region 41 and the third region 43 are formed, for example, by epitaxial growth. Each of the buffer layer 49, the first region 41, and the third region 43 has an n-type (first conductivity type). The impurity concentration of the buffer layer 49 may be the same as the impurity concentration of each of the first region 41 and the third region 43, or may be lower than the impurity concentration of each of the first region 41 and the third region 43. Next, a mask layer (not shown) is formed on the first region 41 and the third region 43.

[0081] Next, a channeling ion implantation process is performed. Specifically, with the mask layer disposed on the first region 41 and the third region 43, impurity ions capable of imparting a p-type (second conductivity type), such as aluminum, are implanted into the first region 41 and the third region 43. The implantation energy is, for example, 960 keV. The implantation temperature is, for example, room temperature. As a result, a second region 42 is formed in a part of the first region 41. The second regions 42 are provided spaced apart in the first direction 101. Similarly, a fourth region 44 is formed in a part of the third region 43. The fourth regions 44 are provided spaced apart in the first direction 101. As described above, a first superjunction layer 10 in which the first region 41 and the second region 42 are alternately arranged, and a second superjunction layer 20 in which the third region 43 and the fourth region 44 are alternately arranged are formed (see FIG. 10).

[0082] In the channeling ion implantation process, impurity ions are implanted in a direction substantially parallel to the <0001> direction, which is the crystal axis of silicon carbide. The implantation direction of the impurity ions may be inclined by an angle of, for example, 0.5° or less with respect to the <0001> direction. Specifically, the implantation direction of the impurity ions may be a direction in which the third direction 103 is inclined in the off direction. The off direction may be, for example, the first direction 101 or the second direction 102. Thereby, by reducing the scattering between the impurity ions and silicon carbide, the impurity ions can be implanted deeply. As a result, the second region 42 and the fourth region 44 are formed (see FIG. 10). Each of the second region 42 and the fourth region 44 has a third portion 73 and a fourth portion 74. The width of the fourth portion 74 is formed smaller than the width of the third portion 73.

[0083] Next, a method for measuring the concentration of p-type impurities and the concentration of n-type impurities in each impurity region will be described.

[0084] The concentration of p-type impurities and the concentration of n-type impurities in each impurity region can be measured using SIMS (Secondary Ion Mass Spectrometry). The measuring device is, for example, a secondary ion mass spectrometer manufactured by Cameca. The measurement pitch is, for example, 0.01 μm. When the n-type impurity to be detected is nitrogen, the primary ion beam is cesium (Cs). The primary ion energy is 14.5 keV. The secondary ion polarity is negative. When the p-type impurity to be detected is aluminum or boron, the primary ion beam is oxygen ( 2 )). The primary ion energy is 8 keV. The secondary ion polarity is positive.

[0085] Next, a method for discriminating between the p-type region and the n-type region will be described. For the method of discriminating between the p-type region and the n-type region, SCM (Scanning Capacitance Microscope) is used. The measuring device is, for example, NanoScope IV manufactured by Bruker AXS. SCM is a method for visualizing the carrier concentration distribution in a semiconductor. Specifically, a silicon probe coated with metal is used to scan the surface of the sample. At this time, a high-frequency voltage is applied to the sample. The majority carriers are excited and the capacitance of the system is modulated. The frequency of the high-frequency voltage applied to the sample is 100 kHz, and the voltage is 4.0 V. For the method of discriminating between the p-type region and the n-type region, SNDM (Scanning Nonlinear Dielectric Microscopy) or SMM (Scanning Microwave Microscopy) may be used.

[0086] In the above description, it has been described that the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. The impurity concentration of the impurity region having n-type is the concentration of n-type impurities. The impurity concentration of the impurity region having p-type is the concentration of p-type impurities.

[0087] Next, the operation and effect of the silicon carbide semiconductor device 100 according to the above embodiment will be described. Silicon has a lower dielectric breakdown strength than silicon dioxide. Therefore, in the case of a Si-MOSFET, the reliability can be improved by designing the MOSFET so that the electric field strength in the peripheral region OR is higher than the electric field strength in the active region IR. On the other hand, silicon carbide has a higher dielectric breakdown strength than silicon dioxide. Therefore, in the case of a SiC-MOSFET, if the MOSFET is designed so that the electric field strength in the peripheral region OR is higher than the electric field strength in the active region IR, the insulating layer 7 is broken first rather than the semiconductor layer, so it has been difficult to sufficiently improve the reliability.

[0088] Therefore, the inventors conceived the design concept of suppressing the concentration of the electric field at the interface between the semiconductor layer and the insulating layer 7 by reducing the electric field strength in the peripheral region OR, and actively generating avalanche in the active region IR by increasing the electric field strength in the active region IR.

[0089] The inventors intensively studied a specific structure for realizing the above design concept. As a result, it was found that by adopting the following structure for the silicon carbide semiconductor device 100, the reliability of the silicon carbide semiconductor device 100 can be improved as compared with a structure that concentrates the electric field in the peripheral region OR.

[0090] Specifically, the silicon carbide semiconductor device 100 according to the present disclosure includes a substrate 90, an active region IR, a peripheral region OR, and a first electrode 61. The substrate 90 is made of a silicon carbide semiconductor of a first conductivity type. The active region IR is provided on a part of the first main surface 1 of the substrate 90. The peripheral region OR is provided on the substrate 90 and surrounds the active region IR in a plan view. The first electrode 61 is provided on the second main surface 2 facing the first main surface 1 of the substrate 90. The active region IR includes a first superjunction layer 10, an element layer 40, and a second electrode 62. The first superjunction layer 10 is provided above the substrate 90 and has alternately a first region 41 of a first conductivity type and a second region 42 of a second conductivity type. The element layer 40 is provided above the first superjunction layer 10. The second electrode 62 is provided on the element layer 40. The peripheral region OR includes a second superjunction layer 20, a termination layer 50, and an insulating layer 7. The second superjunction layer 20 is provided above the substrate 90 and has alternately a third region 43 of a first conductivity type and a fourth region 44 of a second conductivity type. The termination layer 50 is provided in contact with the second superjunction layer 20 and has alternately a fifth region 45 of a second conductivity type and a sixth region 46 of a second conductivity type. The insulating layer 7 is in contact with each of the upper end surfaces of the fifth region 45 and the sixth region 46. The fifth region 45 is provided corresponding to the third region 43, and the sixth region 46 is provided corresponding to the fourth region 44. The impurity concentration of the sixth region 46 is greater than the impurity concentration of the fifth region 45 and is 68 times or less the impurity concentration of the fifth region 45. Thereby, the reliability of the silicon carbide semiconductor device 100 can be improved.

Example

[0091] In order to investigate the relationship between the impurity concentration in the sixth region 46 and the impurity concentration in the fifth region 45, and the reliability of the silicon carbide semiconductor device 100, a breakdown voltage simulation was carried out. First, simulation models (1200V designed elements) with different impurity concentrations in the super junction layer were created. As shown in Table 1, in the first simulation model (conditions 2 to 8), the impurity concentration in the super junction layer (in other words, the impurity concentration in each of the third region 43 and the fourth region 44: see Figure 1) was 1×10 17 cm -3 . In the second simulation model (condition 1), the impurity concentration in the super junction layer was 3×10 16 cm -3 . The thickness of the super junction layer was 7.5 μm. For each of the third region 43 and the fourth region 44, p-type impurities with the same impurity concentration were added to form each of the fifth region 45 and the sixth region 46.

[0092]

Table 1

[0093] As shown in Table 1, in the first simulation model, the value obtained by dividing the impurity concentration in the sixth region 46 by the impurity concentration in the fifth region 45 was in the range of 1.48 or more and 67.7 or less. In the second simulation model, the value obtained by dividing the impurity concentration in the sixth region 46 by the impurity concentration in the fifth region 45 was 1.11.

[0094] Figure 11 is a diagram showing the breakdown voltage simulation results. As shown in Figure 11 and Table 1, it was shown that a high breakdown voltage of about 1.2 kV or more can be realized when the impurity concentration in the sixth region 46 is in the range of 1.11 times or more and 67.7 times or less the impurity concentration in the fifth region 45. In particular, it was shown that a higher breakdown voltage can be realized when the impurity concentration in the sixth region 46 is greater than 1.48 times and less than 33.3 times the impurity concentration in the fifth region 45.

[0095] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims rather than the above description, and it is intended that all modifications within the meaning and scope equivalent to the claims be included.

Description of Reference Numerals

[0096] 1 First main surface, 2 Second main surface, 3 Third main surface, 3a First upper end surface, 3b Second upper end surface, 4 Fourth main surface, 5 Trench, 6 Gate insulating film, 7 Insulating layer, 8 Side surface, 9 Bottom, 10 First superjunction layer, 11 First substrate portion, 12 First buffer layer, 14 First impurity region, 20 Second superjunction layer, 23 Second impurity region, 24 Fourth impurity region, 30 Third impurity region, 40 Element layer, 41 First region, 42 Second region, 43 Third region, 44 Fourth region, 45 Fifth region, 46 Sixth region, 47 Seventh region, 48 Eighth region, 49 Buffer layer, 50 Terminal layer, 51 Second substrate portion, 52 Second buffer layer, 53 First JTE region, 54 Second JTE region, 55 Second terminal layer, 56 First terminal layer, 61 First electrode, 62 Second electrode, 63 Gate electrode, 64 Separation insulating film, 66 Channel stopper, 66a First channel stopper region, 66b Second channel stopper region, 67 Sixth impurity region, 71 First portion, 72 Second portion, 73 Third portion, 74 Fourth portion, 81 First interface, 82 Second interface, 90 Substrate, 91 First region, 92 Second region, 93 Third region, 94 Fourth region, 100 Silicon carbide semiconductor device, 101 First direction, 102 Second direction, 103 Third direction, D1 First distance, D2 Second distance, IR Active region, OR Peripheral region, OR1 First peripheral region portion, OR2 Second peripheral region portion, OR3 Third peripheral region portion, P Pitch, T1 First height, T2 Second height, T3 Third thickness, T4 Fourth thickness, W1 First width, W2 Second width, W3 Third width, W4 Fourth width.

Claims

1. a substrate made of a first conductivity type silicon carbide semiconductor; an active region provided on a portion of a first main surface of the substrate; a peripheral region provided on the substrate and surrounding the active region in a plan view; a first electrode provided on a second main surface of the substrate opposite to the first main surface, The active region comprises: a first superjunction layer provided above the substrate and having alternating first regions of the first conductivity type and second regions of the second conductivity type; an element layer provided above the first superjunction layer; a second electrode provided on the element layer; The peripheral region is a second superjunction layer provided above the substrate and having alternating third regions of the first conductivity type and fourth regions of the second conductivity type; a termination layer provided on and in contact with the second superjunction layer and having alternating fifth regions of the second conductivity type and sixth regions of the second conductivity type; an insulating layer in contact with each of an upper end surface of the fifth region and an upper end surface of the sixth region; the fifth region is provided corresponding to the third region, and the sixth region is provided corresponding to the fourth region; an impurity concentration of the sixth region is greater than an impurity concentration of the fifth region and is not more than 68 times the impurity concentration of the fifth region.

2. The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of said sixth region is higher than an impurity concentration of said fourth region.

3. 3 . The silicon carbide semiconductor device according to claim 1 , wherein an absolute value of a difference between an impurity concentration of said fifth region and an impurity concentration of said sixth region is substantially equal to a sum of an impurity concentration of said third region and an impurity concentration of said fourth region.

4. 4. The silicon carbide semiconductor device according to claim 1, wherein a first distance between an upper end surface of the element layer and an interface between the element layer and the first superjunction layer is greater than a second distance between an upper end surface of the termination layer and an interface between the termination layer and the second superjunction layer.

5. each of the first region and the third region has a first portion and a second portion located between the first portion and the substrate; each of the second region and the fourth region has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the substrate; In a cross section perpendicular to the second main surface and parallel to a direction from the first region to the second region, The width of the second portion is greater than the width of the first portion, The width of the fourth portion is smaller than the width of the third portion, The width of the first portion is less than the height of the first portion; The width of the third portion is less than the height of the third portion; 5 . The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of each of the first portion and the third portion is higher than an impurity concentration of each of the second portion and the fourth portion.

6. The impurity concentration of each of the first region and the third region is 3×10 16 cm -3 Above 5 x 10 17 cm -3 is as follows: The impurity concentration of each of the second region and the fourth region is 3×10 16 cm -3 Above 5 x 10 17 cm -3 The silicon carbide semiconductor device according to claim 1 , wherein:

7. a first buffer layer of the first conductivity type is provided between the first superjunction layer and the substrate; The silicon carbide semiconductor device according to claim 1 , further comprising a second buffer layer of the first conductivity type provided between the second superjunction layer and the substrate.

8. the element layer includes a first impurity region of the first conductivity type, a second impurity region in contact with the first impurity region and having the second conductivity type, and a third impurity region separated from the first impurity region by the second impurity region and having the first conductivity type; the element layer is provided with a trench having a side surface formed by each of the first impurity region, the second impurity region, and the third impurity region, and a bottom portion continuing to the side surface and formed by the first impurity region; the first electrode is a source electrode and the second electrode is a drain electrode; The silicon carbide semiconductor device according to claim 1 , wherein a gate electrode is provided inside said trench.

9. 9 . The silicon carbide semiconductor device according to claim 1 , wherein the first main surface is a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane.

Images