Semiconductor element and imaging device

Abstract

To output a signal of visible light and a signal of infrared light.SOLUTION: A semiconductor element 10 includes: a first substrate 100; a second substrate 200 on the first substrate 100, the second substrate being smaller than the first substrate 100; a third substrate 300 on the second substrate 200, the third substrate being larger than the second substrate 200; and a connection unit 500 provided outside the second substrate 200, the connection unit connecting the first substrate 100 and the third substrate 300 to each other.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an imaging device.

Background Art

[0002] Infrared sensors are known (see Patent Document 1). There is a demand for outputting a visible light signal together with an infrared signal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] A semiconductor device according to an aspect of the present invention includes a first substrate, a second substrate laminated on the first substrate and having an area smaller than that of the first substrate, a third substrate laminated on the second substrate and having an area larger than that of the second substrate, and a connection portion provided outside the second substrate and connecting the first substrate and the third substrate.

Brief Description of the Drawings

[0005]

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Figure 10A

Figure 10B

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Embodiments for Carrying Out the Invention

[0006] (First Embodiment) Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a schematic exploded perspective view of a semiconductor device 10. FIG. 1 shows the first substrate 100, the second substrate 200, and the third substrate 300 separated from each other. The semiconductor device 10 includes a first substrate 100, a second substrate 200 laminated on the first substrate 100 and having a smaller area than the first substrate 100, and a third substrate 300 laminated on the second substrate 200 and having a larger area than the second substrate 200.

[0007] The first substrate 100 includes a first pixel portion 110, a first control portion 120, and a first output portion 130. The first pixel portion 110, the first control portion 120, and the first output portion 130 are formed on the first substrate 100 by photolithography technology.

[0008] FIG. 2 is a plan view showing an example of the electrical structure of the first pixel portion 110 and the first control portion 120 in the first substrate of the semiconductor device in FIG. 1. The first pixel portion 110 has a plurality of first pixel blocks 111 in the row direction and the column direction. The first pixel block 111 is a block that divides the in-plane of the first pixel portion 110 into a predetermined region. The first pixel block 111 includes a plurality of first pixels 112. The first pixel 112 includes a photoelectric conversion element that photoelectrically converts light such as a photodiode. The photoelectric conversion element of the first pixel 112 is an example of a first photoelectric conversion portion that photoelectrically converts light.

[0009] The first pixel portion 110 is composed of a plurality of first pixels 112 arranged in a matrix. The first pixel 112 has a first photoelectric conversion portion and a first readout portion described later. Under the control of the first control portion 120, the first pixel portion 110 outputs an electrical signal corresponding to the received incident light.

[0010] The first control unit 120 includes a first control circuit 121, a first vertical scanning circuit 122, a first column signal processing circuit 123, a first horizontal scanning circuit 124, and a first output circuit 125.

[0011] In the semiconductor element 10, the first vertical scanning circuit 122 is arranged along one side of the first pixel portion 110. Also, the horizontal scanning circuit 124 and the first column signal processing circuit 123 are arranged along a side orthogonal to the side arranged in parallel with the first vertical scanning circuit 122.

[0012] The first control circuit 121 generates a clock signal and a control signal that serve as the basis for the operations of the first vertical scanning circuit 122, the first column signal processing circuit 123, and the first horizontal scanning circuit 124 based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. Also, the generated clock signal and control signal are sent to the first vertical scanning circuit 122, the first column signal processing circuit 123, and the first horizontal scanning circuit 124.

[0013] The first vertical scanning circuit 122 is connected to each row of the first pixels 112 through a plurality of signal lines arranged horizontally in FIG. 2. Also, the first vertical scanning circuit 122 has a shift register and sequentially supplies a control signal and the like to each row of the first pixels 112 through the connected plurality of signal lines. As a result, the first pixels 112 are sequentially and vertically selected and scanned row by row.

[0014] The first column signal processing circuit 123 is arranged, for example, for each column of the first pixels 112 and performs signal processing such as noise removal for each pixel column on the signals output from the first pixels 112 for one row. The first column signal processing circuit 123 performs signal processing such as Correlated Double Sampling for removing fixed pattern noise of the first pixels 112, signal amplification, and analog-to-digital conversion (hereinafter sometimes referred to as AD conversion).

[0015] The first horizontal scanning circuit 124 has a shift register, sequentially outputs horizontal scanning pulses, and sequentially selects each of the first column signal processing circuits 123. The first horizontal scanning circuit 124 causes the pixel signals from the selected first column signal processing circuits 123 to be sent to the first output circuit 125 through signal lines.

[0016] The first output circuit 125 performs signal processing on the signals sequentially sent through the signal lines from each of the column signal processing circuits 123 and outputs them.

[0017] FIG. 3 is an example of a circuit diagram of the first pixel 112 in FIG. 2. The first pixel 112 has a first photodiode 105 and a first readout unit 115. The first readout unit 115 has a first transfer unit, a first storage unit, a first discharge unit, and a first output unit. The first transfer unit is, for example, the first transfer transistor TX1. The first storage unit is, for example, the floating diffusion FD. The first discharge unit is, for example, the first reset transistor RST1. The first output unit is the first amplification transistor AMP1 and the first selection transistor SEL1. In FIG. 3, the potential VSS is supplied as the ground potential. The first readout unit 115 is an example of a first readout circuit that reads out a signal based on the charge photoelectrically converted by the first photoelectric conversion unit.

[0018] The cathode of the first photodiode 105 is connected to the source of the first transfer transistor TX1. The anode of the first photodiode 105 is electrically connected to, for example, ground. The drain of the first transfer transistor TX1 is connected to the floating diffusion FD. The source of the first reset transistor RST1 is connected to the gate of the first amplification transistor AMP1. The drain of the first reset transistor RST1 is connected to the voltage source VRST1. The drain of the first amplification transistor AMP1 is connected to the voltage source VPIX1. The source of the first amplification transistor AMP1 is connected to the drain of the first selection transistor SEL1. The source of the first selection transistor SEL1 is connected to the first signal line Column.

[0019] The first transfer transistor TX1 is, for example, an N-type MOS transistor. The source of the first transfer transistor TX1 is connected to the output terminal of the first photodiode 105, and the drain is connected to the floating diffusion FD. The gate of the first transfer transistor TX1 is connected to the transfer signal line. The first transfer transistor TX1 turns on when a voltage equal to or higher than the threshold value is applied to the gate by a signal sent from the transfer signal line. When it turns on, it sends the charge generated by the first photodiode 105 to the floating diffusion FD. The first transfer transistor is an example of a first transfer unit that transfers charge.

[0020] The floating diffusion FD is connected to the drain of the first transfer transistor TX1, the source of the first reset transistor RST1, and the gate of the first amplification transistor AMP1. The floating diffusion FD is an example of a first accumulation unit that accumulates charge.

[0021] The floating diffusion FD accumulates and holds the transferred charge when the first transfer transistor TX1 turns on. The floating diffusion FD applies the voltage generated by the held charge to the gate of the first amplification transistor AMP1. The floating diffusion FD turns on the first amplification transistor AMP1 by applying a voltage equal to or higher than the threshold value to the gate of the first amplification transistor AMP1. Also, when the first reset transistor RST1 turns on, the charge held by the floating diffusion FD is discharged and reset.

[0022] The first reset transistor RST1 is, for example, an N-type MOS transistor. The drain of the first reset transistor RST1 is connected to the voltage source VRST1. The gate of the first reset transistor RST1 is connected to the reset signal line. The first reset transistor RST1 turns on when a voltage equal to or higher than the threshold voltage is applied to the gate through the reset signal line. Also, the first reset transistor RST1 is turned off by applying a voltage lower than the threshold voltage to the gate. When the first reset transistor RST1 turns on, the charge held by the floating diffusion FD is discharged to the voltage source VRST1 and reset.

[0023] The first amplification transistor AMP1 is, for example, an N-type MOS transistor. The first amplification transistor AMP1 turns on when a voltage equal to or higher than the threshold voltage is applied to the gate by the charge output from the floating diffusion FD. Also, the first amplification transistor AMP1 turns off when a voltage lower than the threshold voltage is applied to the gate. When the first amplification transistor AMP1 turns on, it outputs the current input from the voltage source VPIX1 to the first selection transistor SEL1.

[0024] The first selection transistor SEL1 is, for example, an N-type MOS transistor. The gate of the first selection transistor SEL1 is connected to the selection signal line. The first selection transistor SEL1 turns on when a voltage equal to or higher than the gate threshold voltage is applied. The first selection transistor SEL1 turns off when a voltage lower than the gate threshold voltage is applied. When the first selection transistor SEL1 turns on, it outputs the signal output by the first amplification transistor AMP1 to the first signal line Column1.

[0025] As shown in FIG. 1, the second substrate 200 includes a photodiode array 210 in which photoelectric conversion elements such as photodiodes are arranged. The photoelectric conversion elements constituting the photodiode array 210 are an example of a second photoelectric conversion unit that photoelectrically converts light.

[0026] The third substrate 300 includes a second control unit 320 and a second output unit 330. The second control unit 320 and the second output unit 330 are formed on the third substrate 300 by photolithography technology.

[0027] The second substrate 200 and the third substrate 300 are joined so that the photodiode array 210 of the second substrate 200 and a second readout unit (described later) of the third substrate 300 are electrically connected. FIG. 4 is a diagram showing an example of the electrical structure of the photodiode array 210 in the second substrate 200 and the second control unit of the third substrate 300. The second pixel unit 220 is composed of the photodiode array 210 of the second substrate 200 and a plurality of second readout units in the second control unit 320 (described later). The second pixel unit 220 has a plurality of second pixel blocks 221 in the row direction and the column direction. The second pixel block 221 is a block that divides a predetermined area in the plane of the second pixel unit 220. The second pixel block 221 includes a plurality of second pixels 222. The second pixel 212 has a second photoelectric conversion unit. The second pixel unit 220 outputs an electrical signal corresponding to the received incident light under the control of the second control unit 320.

[0028] The second control unit 320 includes a second control circuit 321, a second vertical scanning circuit 322, a second column signal processing circuit 323, a second horizontal scanning circuit 324, a second output circuit 325, and a second readout unit. The second readout unit will be described later.

[0029] Based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, the second control circuit 321 generates a clock signal and a control signal that serve as the basis for the operations of the second vertical scanning circuit 322, the second column signal processing circuit 323, and the second horizontal scanning circuit 324. Further, the generated clock signal and control signal are sent to the second vertical scanning circuit 322, the second column signal processing circuit 323, and the second horizontal scanning circuit 324.

[0030] The second vertical scanning circuit 322 is connected to each row of the second pixels 222 through a plurality of signal lines arranged horizontally in FIG. 4. The second vertical scanning circuit 322 has a shift register and sequentially supplies control signals and the like to each row of the second pixels 222 through the connected plurality of signal lines. Thereby, the second pixels 222 are sequentially selected and scanned in the vertical direction in row units.

[0031] The second column signal processing circuit 323 is arranged, for example, for each column of the second pixels 222, and performs signal processing such as noise removal for each pixel column on the signals output from the second pixels 222 for one row. The second column signal processing circuit 323 performs signal processing such as Correlated Double Sampling for removing fixed pattern noise of the second pixels 222, signal amplification, and AD conversion.

[0032] The second horizontal scanning circuit 324 has a shift register, sequentially outputs horizontal scanning pulses, and sequentially selects each of the second column signal processing circuits 323. The pixel signals are sent from the selected second column signal processing circuit 323 to the second output circuit 325 through signal lines.

[0033] The second output circuit 325 performs signal processing on the signals sequentially sent from each of the second column signal processing circuits 323 through signal lines and outputs them.

[0034] FIG. 5 is an example of a circuit diagram of the second pixel 222 of the semiconductor element 10 in FIG. 4. FIG. 6 is a planar layout of the second pixel 222 of the semiconductor element 10 in FIG. 5. The second photodiode 205A is disposed on the second substrate 200, and the other parts are disposed on the third substrate 300. The second pixel 222 has a photodiode 205A and a second readout unit 215. The second readout unit 215 has a second transfer unit, a second storage unit, a second discharge unit, and a second output unit. The second transfer unit is, for example, the second transfer transistor TX2. The second storage unit is, for example, the capacitors C1 and C2. The second discharge unit is, for example, the second reset transistor RST2. The second output unit is the second amplification transistor AMP2 and the first selection transistor SEL1. In FIG. 5, the potential VSS is supplied as a ground potential. The second readout unit 215 is an example of a second readout circuit that reads out a signal based on the charge photoelectrically converted by the second photoelectric conversion unit.

[0035] The output terminal of the second photodiode 205A is connected to the source (diffusion layer) SN2 of the second transfer transistor TX2 and the capacitor C1. The drain of the second transfer transistor TX2 is connected to the source of the second reset transistor RST2, the gate of the second amplification transistor AMP2, and the capacitor C2. The drain of the second reset transistor RST2 is connected to the voltage source VRST2. The drain of the second amplification transistor AMP2 is connected to the voltage source VPIX2. The source of the second amplification transistor AMP2 is connected to the drain of the selection transistor SEL2. The source of the second selection transistor SEL2 is connected to the signal line Column2.

[0036] The charge held by the capacitor C1 is transferred to the diffusion layer FD2 when the second transfer transistor TX2 is turned on.

[0037] The second transfer transistor TX2 is, for example, a P-type MOS transistor. The source of the second transfer transistor TX2 is connected to the output terminal of the second photodiode 205A, and the drain is connected to the diffusion layer FD2. The gate of the second transfer transistor TX2 is connected to the transfer signal line. When a voltage equal to or lower than the threshold value is applied to the gate of the second transfer transistor TX2 by a signal sent from the transfer signal line, the second transfer transistor TX2 turns on. When it turns on, the charge generated by the second photodiode 205A and stored in the capacitor C1 is sent to the diffusion layer FD2.

[0038] The diffusion layer FD2 is connected to the drain of the second transfer transistor TX2, the source of the second reset transistor RST2, and the gate of the amplification transistor AMP.

[0039] When the second transfer transistor TX2 turns on, the charge held in the capacitor C1 is transferred, and the capacitor C2 accumulates and holds the transferred charge. The capacitor C2 applies the voltage generated by the held charge to the gate of the second amplification transistor AMP2. When the capacitor C2 applies a voltage equal to or higher than the threshold value to the gate of the second amplification transistor AMP2, the second amplification transistor AMP2 is turned on. Also, when the second reset transistor RST2 turns on, the charge held by the capacitor C2 is discharged and reset.

[0040] The second reset transistor RST2 is, for example, a P-type MOS transistor. The drain of the second reset transistor RST2 is connected to the voltage source VRST2. The gate of the second reset transistor RST2 is connected to the reset signal line. When a voltage equal to or lower than the threshold value is applied to the gate of the second reset transistor RST2 by the reset signal line, the second reset transistor RST2 turns on. Also, when a voltage greater than the threshold value is applied to the gate of the second reset transistor RST2, the second reset transistor RST2 is turned off. When the second reset transistor RST2 turns on, the charge held by the capacitor C2 is discharged to the voltage source VRST2 and reset.

[0041] The second amplification transistor AMP2 is, for example, an N-type MOS transistor. When a voltage equal to or higher than the threshold voltage is applied to the gate of the second amplification transistor AMP2 by the charge output from the capacitor C2, the transistor turns on. Also, when a voltage lower than the threshold voltage is applied to the gate of the second amplification transistor AMP2, the transistor turns off. When the second amplification transistor AMP2 turns on, it outputs the current input from the voltage source VPIX2 to the second selection transistor SEL2.

[0042] The second selection transistor SEL2 is, for example, an N-type MOS transistor. The gate of the second selection transistor SEL2 is connected to the selection signal line. When a voltage equal to or higher than the gate threshold voltage is applied to the second selection transistor SEL2, the transistor turns on. When a voltage lower than the gate threshold voltage is applied to the second selection transistor SEL2, the transistor turns off. When the second selection transistor SEL2 turns on, it outputs the signal output by the second amplification transistor AMP2 to the second signal line Column2.

[0043] FIG. 7 is a plan view of the semiconductor element 10, FIG. 8 is a cross-sectional view taken along the line A-A' of the semiconductor element 10 in FIG. 7, and is a cross-sectional view of the region where the first pixel 112 is located. FIG. 9 is a cross-sectional view taken along the line B-B' of the semiconductor element 10 in FIG. 7, and is a cross-sectional view of the region where the first output portion 130 is provided.

[0044] The region where the first pixel portion 110 is located is the first pixel region. The region outside the first pixel region is defined as the first peripheral region.

[0045] With reference to FIG. 8, the cross-sectional structure of the semiconductor element 10 in the first pixel region will be described. The first substrate 100 has a first semiconductor layer 160 and a first wiring layer 161. The first semiconductor layer 160 includes a first photodiode 105 and an element 151. In the semiconductor element 10, the first photodiode 105 converts visible light into electric charges. The element 151 is, for example, a transistor, a capacitor, or the like. In the first pixel region, the first pixel 112 is formed from the first photodiode 105 and the element 151. The first wiring layer 161 includes a plurality of conductor layers 106 and an insulating layer 107. The plurality of conductor layers 106 form control lines such as signal lines and transfer control lines. In the semiconductor element 10, the first wiring layer 161 is between the first semiconductor layer 160 and the second substrate 200. The first substrate 100 and the second substrate 200 are laminated. The insulating layer 107 transmits light having a wavelength converted by the photoelectric conversion layer 205 of the second substrate 200.

[0046] In the optical axis direction of the microlens 101, the second substrate 200 is between the first substrate 100 and the third substrate 300. The second substrate 200 is disposed only in the first pixel region and is not disposed in the first peripheral region, and is inside a connection portion 500 (described later) that connects the first substrate 100 and the third substrate 300. The second substrate 200 includes a second semiconductor layer 203 and a second wiring layer 208. The first contact layer 201, the second contact layer 202, and the second photoelectric conversion layer 205 are an example of the configuration of the semiconductor layer. That is, the second semiconductor layer 203 has the first contact layer 201, the second contact layer 202, and the second photoelectric conversion layer 205. The second semiconductor layer 203 and the first substrate 100 are laminated. In the semiconductor element 10, the first contact layer 201 is in contact with the first substrate 100. The second wiring layer 208 is interposed between the second semiconductor layer 203 and the third substrate 300. The second wiring layer 208 includes a plurality of conductor layers 206, an insulating layer 207, and a pad 209.

[0047] The first contact layer 201 faces the second contact layer 202 with the second photoelectric conversion layer 205 therebetween. Among the charges generated in the second photoelectric conversion layer 205, the charges not used as signal charges move in the first contact layer 201. When holes are extracted as signal charges, electrons move. The first contact layer 201 may be connected to an electrode for discharging electrons. The first contact layer 201 is, for example, n-type InP.

[0048] The photoelectric conversion layer 205 converts infrared light, particularly short-wavelength infrared (hereinafter sometimes referred to as SWIR) light, into charges. The photoelectric conversion layer 205 is made of a compound semiconductor such as an i-type III-V semiconductor. Examples of the i-type III-V semiconductor include InGaAs and the like.

[0049] The second contact layer 202 electrically separates adjacent pixels. The second contact layer 202 has a plurality of diffusion regions 202A. The second contact layer 202 is, for example, n-type InP. The diffusion region 202A contains, for example, p-type impurities. A pn junction is formed between the diffusion region 202A and the second contact layer 202 other than the diffusion region 202A. Thereby, adjacent pixels are separated. Also, the diffusion region 202A and the conductor layer 206 are electrically connected. The photodiode 205A is composed of the first contact layer 201, the photoelectric conversion layer 205, and the diffusion region 202A.

[0050] The third substrate 300 has a substrate layer 360 and a third wiring layer 308. The substrate layer 360 includes a substrate 301 and an element 351. The element 351 is a transistor, a capacitor, or the like. The element 351 constitutes a second readout unit, a scanning circuit, and the like. The third wiring layer 308 is disposed between the substrate layer 360 and the second substrate 200. The third wiring layer 308 includes a plurality of conductor layers 306 and an insulating layer 307. The plurality of conductor layers constitute signal lines and control lines. The second substrate 200 and the third substrate 300 are electrically connected. Specifically, the pad 209 of the second substrate 200 and the pad 309 of the third substrate 300 are electrically connected. The pad 209 and the pad 309 are, for example, a Cu-Cu junction.

[0051] The first pixel 112 and the second pixel 222 are located at overlapping positions in a plan view. In the semiconductor element 10, the visible light component of the incident light is detected by the first pixel 112, and the SWIR component is detected by the second pixel 222.

[0052] Next, the cross-sectional structure of the semiconductor element 10 in the first peripheral region will be described with reference to FIG. 9. As shown in FIG. 9, in the first peripheral region, the first substrate 100 includes a first output portion 130. The first output portion 130 includes a mounting pad 133A and a mounting pad 133B. Through the mounting pad 133A, the electrical signal output from the first pixel portion 110 is sent to an external device. The mounting pad 133B is electrically connected to the third substrate 300 via a through electrode 132 that penetrates the first semiconductor layer 160. Through the mounting pad 133B, the electrical signal output from the second pixel portion 220 is sent to an external device. The through electrode 132 of the first substrate 100 is electrically connected to the conductive portion 502 of the connection portion 500.

[0053] The semiconductor element 10 is provided outside the second substrate 200 and includes a connection portion 500 that connects the first substrate 100 and the third substrate 300. The connection portion 500 that connects the first substrate 100 and the third substrate 300 is provided in the first peripheral region. The connection portion 500 is provided between the peripheral portion of the first substrate 100 and the peripheral portion of the third substrate 300. The connection portion 500 includes an insulating film 501 and a conductive portion 502 that penetrates the insulating film 501. The conductive portion 502 electrically connects the first substrate 100 and the third substrate 300. The conductive portion 502 has a pad 503 for electrically connecting to the third substrate 300.

[0054] The third substrate 300 includes a second output portion 330. The second output portion 330 includes a mounting pad 333. The mounting pad 333 is electrically connected to the conductive portion 502 of the connection portion 500. The third substrate 300 is connected to the first substrate 100 via the mounting pad 333.

[0055] The semiconductor device 10 may have a microlens 101, a first planarization film 102, a color filter layer 103, and a second planarization film 104 on the first substrate 100. The second planarization film 104, the color filter layer 103, and the first planarization film 102 are sequentially stacked on the first photodiode 105. The color filter layer 103 is flattened and stacked by the first planarization film 102 and the second planarization film 104. Also, the surfaces between the first photodiodes 105 and the surface of the first photodiode 105 may be flattened by the second planarization film 104. The microlens 101 is stacked on the outermost surface of the first substrate 100. The first photoelectric conversion unit photoelectrically converts the light transmitted through the microlens 101.

[0056] Next, an example of the manufacturing method of the semiconductor device 10 will be described, but the manufacturing method of the semiconductor device 10 of the present disclosure is not limited to the following manufacturing method. In the following description, the description of processes such as the mask shape and resist coating used in each process will be omitted.

[0057] FIG. 10A is a diagram for explaining one step of the first embodiment, and is a cross-sectional view of a region (first photoelectric conversion region) where the first pixel 112 is to be formed. FIG. 10B is a diagram for explaining one step of the first embodiment, and is a cross-sectional view of a region (peripheral region) where the first output unit 130 is provided.

[0058] In the steps of FIGS. 10A and 10B, the compound semiconductor substrate 270 and the photodiode substrate 170 that becomes the first substrate 100 are stacked. The bonding is, for example, plasma-activated bonding. The compound semiconductor substrate 270 has, for example, a first contact layer 201 (for example, an n-type InP layer), a second photoelectric conversion layer 205 (for example, an i-type InGaAs layer), a second contact layer 202 (for example, an n-type InP layer), and a substrate 280 (for example, an InP substrate that is a growth substrate). The diode substrate 170 has a second planarization film 104, a first photodiode 105, a first wiring layer 161, an element 151, and a support substrate 180.

[0059] FIG. 11 is a diagram for explaining one step of the first embodiment, and is a cross-sectional view of a region where the first pixel 112 is to be formed. In the step of FIG. 11, after laminating the compound semiconductor substrate 270 and the photodiode substrate 170 that will be the first substrate 100, the substrate 280 is removed, and a diffusion region 202A is formed for each second pixel 222. The removal of the substrate 280 can be performed by CMP (Chemical Mechanical Polishing), wet etching, or the like.

[0060] FIG. 12A is a diagram for explaining one step of the first embodiment, and is a cross-sectional view of a region where the first pixel 112 is to be formed. FIG. 12B is a diagram for explaining one step of the first embodiment, and is a cross-sectional view of a region where the first output portion 130 is to be provided. In the steps of FIGS. 12A and 12B, after forming the diffusion region 202A, the second wiring layer 208 is formed to create the second substrate 200. Also, in the steps of FIGS. 12A and 12B, an insulating film 501 made of an insulator is formed in a gap outside the second substrate 200. Thereafter, a conductive portion 502 made of a conductor that penetrates the insulating film 501 and electrically connects the first substrate 100 and the third substrate 300 is formed. The conductive portion 502 is, for example, Cu. The insulating film 501 is, for example, SiO2. The conductive portion 502 transmits the signal read by the second readout circuit to the first substrate 100.

[0061] FIG. 13A is a diagram for explaining one step of the first embodiment, and is a cross-sectional view of a region where the first pixel 112 is to be formed. FIG. 13B is a diagram for explaining one step of the first embodiment, and is a cross-sectional view of a region where the first output portion 130 is to be provided. In the steps of FIGS. 13A and 13B, after forming the connection portion 500, the third substrate 300 is laminated on the second substrate 200. The pad 209 and the pad 309 are, for example, Cu-Cu junctions.

[0062] After laminating the third substrate 300 on the second substrate 200, a microlens 101, a first planarization film 102, mounting pads 333A, mounting pads 333B, a through electrode 132, etc. are formed by a known method to obtain the semiconductor element 10.

[0063] The semiconductor element 10 has been described in detail above. Since the first pixel 112 of the first substrate 100 and the second pixel 222 of the second substrate 200 overlap in plan view, signals in the SWIR range as well as visible light signals can be output simultaneously. In the semiconductor element 10, an electrical signal of the first substrate 100 can be obtained from the pad 133A of the first substrate 100. And an electrical signal of the second substrate 200 can be obtained from the pad 133B of the first substrate 100. Since the pads of the first substrate 100 can be placed on the upper surface, it can be implemented by a general method. And since the space that is outside the second substrate 200 and between the first substrate 100B and the third substrate 300 is filled with the insulating film 501, the strength of the semiconductor element 10B can be increased, and breakage of the substrate due to dicing can be prevented.

[0064] The first embodiment has been described in detail above. Since the first pixel 112 and the second pixel 222 overlap in plan view, signals in the SWIR range as well as visible light signals can be output simultaneously.

[0065] In the semiconductor element 10 of the first embodiment, the second substrate 200 is a compound semiconductor such as an expensive III-V semiconductor. Therefore, in the semiconductor element 10 of the first embodiment, only the photodiode portion is formed of a III-V semiconductor, and the control circuit is formed of a semiconductor such as inexpensive Si. Since a scanning circuit or the like is provided, the first substrate 100 and the third substrate 300 are larger than the second substrate 200. In the semiconductor element 10 of the first embodiment, since the second substrate 200 is smaller than the first substrate 100 and the third substrate 300, a space is formed outside the second substrate and between the first substrate 100 and the third substrate 300. That is, the connection portion 500 is provided in the space that can be formed between the first substrate 100 and the third substrate 300 outside the second substrate 200. In the semiconductor element 10, this gap is filled by the connection portion 500 which is an insulating film. That is, the connection portion 500 fills the aforementioned space. Therefore, the strength of the semiconductor element 10 can be increased, and breakage due to dicing can be prevented.

[0066] In the semiconductor element 10, in the optical axis direction of the microlens 101, a first photoelectric conversion unit, a first readout circuit that reads a signal based on the charges photoelectrically converted by the first photoelectric conversion unit, a second photoelectric conversion unit, and a second readout circuit that reads a signal based on the charges photoelectrically converted by the second photoelectric conversion unit may be provided in this order.

[0067] Since the pads 209 and 309 of the semiconductor element 10 are directly joined, the cell size can be reduced.

[0068] In the semiconductor element 10, an AD conversion circuit for AD - converting the signal output from the second substrate 200 may be provided around the first substrate or the third substrate.

[0069] In the semiconductor element 10, the signal output from the second substrate 200 may be output outside the semiconductor element 10 as an analog signal and be AD - converted by an AD conversion circuit outside the semiconductor element 10.

[0070] The second substrate 200 may include only the second semiconductor layer 203, or may include the second semiconductor layer 203 and the second wiring layer 208.

[0071] The first substrate 100 and the third substrate 300 may include an image processing circuit that generates an image file.

[0072] The first substrate 100 and the second substrate 200 may be laminated via an adhesive layer.

[0073] The following embodiments are also within the scope of the present invention, and it is also possible to combine one or more of the embodiments with the above - described embodiments.

[0074] (Second Embodiment) Next, the semiconductor element 10A of the second embodiment will be described. FIG. 14 is a plan view of the semiconductor element 10A. FIG. 15 is a cross-sectional view taken along the line C-C' of the semiconductor element in FIG. 14. For elements common to the semiconductor element 10, the same reference numerals are assigned and redundant descriptions are omitted.

[0075] Unlike the semiconductor element 10, the semiconductor element 10A has a gap between the outside of the second substrate 200 and between the first substrate 100A and the third substrate 300A. The semiconductor element 10A has a connection portion 500A made of a conductor that electrically connects the first substrate 100A and the third substrate 300A. The first substrate 100A has a pad 134 that is electrically connected to the connection portion 500A and electrically connected to the first wiring layer 161. Further, the third substrate 300A has a mounting pad 333A that is electrically connected to the connection portion 500A and electrically connected to the third wiring layer 308.

[0076] The connection portion 500A is not particularly limited as long as it can electrically connect the first substrate 100A and the third substrate 300A. The connection portion 500A is, for example, a bump. That is, the connection portion 500A is made of a conductor. The material of the connection portion 500A is not particularly limited and may be the same material as the pad or a different material. For the lamination of the connection portion 500A, Cu bump lamination by solid-phase diffusion, micro bump lamination by solder melting, etc. can be used.

[0077] Next, an example of the manufacturing method of the semiconductor element 10A will be described. For the same processes, the description will be omitted. In the process of FIG. 12B of the semiconductor element 10, the connection portion 500 composed of an insulating film and a conductive portion was formed, but in the semiconductor element 10A, instead of the insulating film and the conductive portion, only the connection portion 500A of the conductor that electrically connects the first substrate 100 and the third substrate 300A is formed, which is different.

[0078] FIG. 16 is a diagram for explaining one step of the second embodiment, and is a cross-sectional view of a region where the first output unit 130A is to be provided. In the step of FIG. 16, instead of forming the connection part 500 which is an insulating film, the connection part 500A which is a bump is formed on the pad 134 of the photodiode substrate 170A. The photodiode substrate 170A is different from the photodiode substrate 170 in that it includes a pad 134 for connecting to the connection part 500.

[0079] FIG. 17 is a diagram for explaining one step of the second embodiment, and is a cross-sectional view of a region where the first output unit 130A is to be provided. In the step of FIG. 16, the third substrate 300A is laminated on the second substrate 200 and heated or the like to join the connection part 500A to the pad 333A.

[0080] As described above in detail for the semiconductor element 10A. Since the first pixel 112 and the second pixel 222 of the semiconductor element 10A overlap in plan view, the SWIR signal can be output simultaneously with the visible light signal. In the semiconductor element 10A, since the mounting pads 133A and 133B of the first substrate 100A can be placed on the upper surface, it can be mounted by a general method.

[0081] (Third Embodiment) Next, the semiconductor element 10B of the third embodiment will be described. FIG. 18 is a plan view of the semiconductor element 10B. FIG. 19 is a cross-sectional view taken along the line D-D' of the semiconductor element of FIG. 18. For elements common to the semiconductor element 10 and the semiconductor element 10A, the same reference numerals are given and redundant descriptions are omitted.

[0082] The first substrate 100B of the semiconductor element 10B has a mounting pad 133C for transmitting the electrical signal of the first pixel portion 110 to the outside.

[0083] The semiconductor element 10B is provided outside the second substrate 200 and includes a connection portion 500B that connects the first substrate 100B and the third substrate 300. In the semiconductor element 10, the connection portion 500B is an insulating film. That is, the connection portion 500B is made of an insulator. The insulating film is, for example, SiO2, an organic resin, or the like. The connection portion 500B is provided between the peripheral portion of the first substrate 100 and the peripheral portion of the third substrate 300.

[0084] The third substrate 300B of the semiconductor element 10B has a mounting pad 333B that sends out the electrical signal of the second pixel portion 220 to the outside.

[0085] Next, an example of a method for manufacturing the semiconductor element 10B will be described. The description of the same steps will be omitted. In the step of FIG. 11B of the semiconductor element 10, the connection portion 500 including the insulating film and the conductive portion was formed, but the semiconductor element 10B is different in that only the insulating film is formed. Also, in FIG. 12B, the third substrate was laminated on the second substrate 200, but the semiconductor element 10A is different in that the third substrate 300B including the pad 333B is laminated.

[0086] FIG. 19 is a diagram for explaining one step of the third embodiment and is a cross-sectional view of a region where the first output portion 130B is to be provided. In the step of FIG. 19, a connection portion 500, which is an insulating film (for example, SiO2), is formed in a gap outside the second substrate 200.

[0087] FIG. 20 is a diagram for explaining one step of the third embodiment and is a cross-sectional view of a region where the first output portion 130B is to be provided. In the step of FIG. 20, after forming the connection portion 500B, the third substrate 300B is laminated on the second substrate 200.

[0088] After laminating the third substrate 300B on the second substrate 200, a microlens 101, a first planarization film 102, a mounting pad 133C, a mounting pad 333B, etc. are formed by a known method, and the semiconductor element 10B is obtained. The above has described the third embodiment in detail. Since the first pixel 112 and the second pixel 222 of the semiconductor element 10 overlap in plan view, signals in the SWIR as well as signals in visible light can be output simultaneously.

[0089] In the semiconductor element 10B of the third embodiment, the second substrate 200 is a compound semiconductor such as an expensive III-V semiconductor. Therefore, in the semiconductor element 10B of the third embodiment, only the photodiode portion is formed of a III-V semiconductor, and the control circuit is formed of a semiconductor such as inexpensive Si. Since a scanning circuit or the like is provided, the first substrate 100B and the third substrate 300B are larger than the second substrate 200. In the semiconductor element 10B of the third embodiment, since the second substrate 200 is smaller than the first substrate 100B and the third substrate 300B, a space is formed outside the second substrate and between the first substrate 100 and the third substrate 300. That is, the connection portion 500B is provided in the space formed between the first substrate 100B and the third substrate 300B outside the second substrate 200. In the semiconductor element 10, this gap is filled by the connection portion 500B which is an insulating film. That is, the connection portion 500B fills the aforementioned space. Therefore, the strength of the semiconductor element 10 can be increased, and breakage due to dicing can be prevented.

[0090] (Fourth Embodiment) Next, the semiconductor element 10C of the fourth embodiment will be described. FIG. 22 is a plan view of the semiconductor element 10C. FIG. 23 is a cross-sectional view taken along line E-E' of the semiconductor element of FIG. 22. For elements common to the semiconductor element 10, the semiconductor element 10A, and the semiconductor element 10B, the same reference numerals are given and redundant descriptions are omitted.

[0091] Unlike the semiconductor element 10, the semiconductor element 10C includes a light condensing portion 185 that condenses light on the photoelectric conversion layer 205 of the second substrate 200 on the first substrate 100C. The light condensing portion 185 condenses light having a wavelength that is converted by the semiconductor layer 203. The light condensing portion 185 is disposed on the surface of the first substrate 100C on the side where the first substrate 100C is laminated with the second substrate 200.

[0092] The light condensing portion 185 of the semiconductor element 10C condenses the light that has passed through the first photodiode 105. As a result, it is possible to suppress the detection of light across the second pixels 222. Crosstalk of the semiconductor element 10C can be reduced.

[0093] (Fifth Embodiment) Next, the semiconductor element 10D of the fifth embodiment will be described. FIG. 24 is a plan view of the semiconductor element 10D. FIG. 25 is a cross-sectional view of the semiconductor element 10D taken along the line F-F' of FIG. 24. For elements common to the semiconductor element 10, the semiconductor element 10A, the semiconductor element 10B, and the semiconductor element 10C, the same reference numerals are given and redundant descriptions are omitted. In the semiconductor element 10D, the first substrate 100D includes an optical filter 195 that attenuates the intensity of light in a specific wavelength band.

[0094] The semiconductor element 10D includes an optical filter 195 that attenuates or absorbs the intensity of light in a specific wavelength band on the second planarization film 104. The optical filter 195 attenuates or absorbs, for example, the intensity of light in a wavelength band where the visible light and SWIR wavelength ranges overlap. The wavelength band to be attenuated or absorbed is, for example, 650 nm to 1100 nm. The optical filter 195 is planarized by the third planarization film 196.

[0095] The optical filter 195 of the semiconductor element 10D attenuates the intensity of light in a wavelength band where the visible light and SWIR wavelength ranges overlap. As a result, the separation performance between the visible light signal and the SWIR signal can be improved.

[0096] In the above, various embodiments and modifications have been described, but the present invention is not limited to these contents. Other aspects conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention. Further, the semiconductor element of the present disclosure may be incorporated into an imaging device. The imaging device of the present disclosure includes the semiconductor element of the present disclosure, and may further include a generation unit that generates image data based on a signal output from the semiconductor element of the present disclosure.

Description of Reference Numerals

[0097] 10 semiconductor element, 100 first substrate, 101 microlens, 102 first planarization film, 103 color filter, 104 second planarization film, 105 photodiode, 106 conductor layer, 107 insulating layer, 110 first pixel portion, 112 first pixel, 161 first wiring layer, 200 second substrate, 201 first contact layer, 202 second contact layer, 203 second semiconductor layer, 205 second photoelectric conversion layer, 206 conductor layer, 207 insulating layer, 208 second wiring layer, 300 third substrate, 306 conductor layer, 307 insulating layer, 308 third wiring layer

Claims

1. A first substrate, A second substrate laminated on the first substrate and having an area smaller than that of the first substrate, A third substrate laminated on the second substrate and having an area larger than that of the second substrate, A connection portion provided outside the second substrate and connecting the first substrate and the third substrate, A semiconductor device comprising the same.

2. In the semiconductor device according to Claim 1, The first substrate has a first photoelectric conversion portion that photoelectrically converts light, The second substrate has a second photoelectric conversion portion that photoelectrically converts light, The third substrate has a readout circuit that reads out a signal based on charges photoelectrically converted by the second photoelectric conversion portion.

3. In the semiconductor device according to Claim 1 or 2, The connection portion is provided in a space formed between the first substrate and the third substrate outside the second substrate.

4. In the semiconductor device according to Claim 3, The connection portion is a semiconductor device that fills the space.

5. In the semiconductor device according to Claim 1 or 2, The connection portion is a semiconductor device made of an insulator.

6. In the semiconductor device according to Claim 1 or 2, The connection portion is a semiconductor device made of a conductor.

7. In the semiconductor device according to Claim 6, The connection portion is a semiconductor device made of a conductor that electrically connects the first substrate and the third substrate.

8. In the semiconductor device according to Claim 2, The connection part is a semiconductor element having an insulator and a conductor that penetrates the insulator and electrically connects the first substrate and the third substrate.

9. In the semiconductor element according to claim 8, The conductor is a semiconductor element that transmits a signal read by the readout circuit to the first substrate.

10. In the semiconductor element according to claim 2, The first substrate is a semiconductor element having a first readout circuit that reads a signal based on charges photoelectrically converted by the first photoelectric conversion unit.

11. In the semiconductor element according to claim 10, In the optical axis direction of the microlens, a semiconductor element provided in the order of the first photoelectric conversion unit, a first readout circuit that reads a signal based on charges photoelectrically converted by the first photoelectric conversion unit, the second photoelectric conversion unit, and a second readout circuit that reads a signal based on charges photoelectrically converted by the second photoelectric conversion unit.

12. A first substrate having a first photoelectric conversion unit that photoelectrically converts light transmitted through a microlens and a first readout circuit that reads a signal based on charges photoelectrically converted by the first photoelectric conversion unit, A second substrate having a second photoelectric conversion unit that photoelectrically converts light and laminated on the first substrate, A third substrate having a second readout circuit that reads a signal based on charges photoelectrically converted by the second photoelectric conversion unit and laminated on the second substrate, and a semiconductor element including the third substrate.

13. In the semiconductor element according to claim 12, In the optical axis direction of the microlens, a semiconductor element provided in the order of the first photoelectric conversion unit, the first readout circuit, the second photoelectric conversion unit, and the second readout circuit.

14. In the semiconductor element according to claim 2, The first substrate is a semiconductor element including a condensing unit that condenses light on the second photoelectric conversion unit.

15. In the semiconductor device according to claim 1 or 2, The first substrate is a semiconductor device including an optical filter that absorbs light in a specific wavelength band.

16. A semiconductor device according to claim 1 or 2, and An imaging device including a generation unit that generates image data based on a signal output from the semiconductor device.

Images