Semiconductor device

Abstract

To provide a transistor structure and a manufacturing method of the same which achieve a normally-off switching element; and provide a constitution and a manufacturing method of the same which achieve high-speed response and high-speed drive of a semiconductor device; and provide a semiconductor device having high reliability while improving ON characteristics of a transistor.SOLUTION: In a transistor where a semiconductor layer, a source electrode layer or a drain electrode layer, a gate insulation film and a gate electrode layer are sequentially laminated, an oxide semiconductor layer which contains at least four elements such as indium, gallium, zinc and oxygen and when composition ratios of the four elements are represented by atomic percentages, a ratio of indium is equal to or larger than twice the ratio of each of gallium and zinc is used as the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called TFTs) is attracting attention. It is widely used in electronic devices such as ICs and image display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors are attracting attention.

[0004] For example, indium (In), gallium (Ga), and nickel are used as active layers of transistors. A transistor using an amorphous oxide containing lead (Zn) has been disclosed (see Patent Document 1). ). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] The threshold voltage of a transistor that uses an oxide semiconductor in the channel formation region is plotted. This transistor structure realizes a so-called normally-off switching element. One of the objectives of the present invention is to provide a structure and a method for manufacturing the same.

[0007] In order to realize a semiconductor device with higher performance, the on-characteristics of a transistor (e.g., A configuration that improves the current and field effect mobility to realize high-speed response and high-speed operation of semiconductor devices. It is another object of the present invention to provide a method for manufacturing the same.

[0008] Furthermore, the threshold voltage is unlikely to fluctuate even when used for a long period of time, making the semiconductor device highly reliable. One of our goals is to provide the following:

[0009] The object of the present invention is to solve at least one of the above problems. [Means for solving the problem]

[0010] A semiconductor layer, a source electrode layer or a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order. In the layered transistor, the semiconductor layer is made of indium, gallium, zinc, and oxide. When the composition ratio of the four elements is expressed in atomic percentage, The oxide semiconductor layer has a ratio of gallium or more that is twice as large as the ratio of gallium and the ratio of zinc.

[0011] One embodiment of the configuration of the present invention disclosed in this specification is a channel formation region provided on an oxide insulating layer. a gate insulating film on the oxide semiconductor layer; and an oxide semiconductor layer on the gate insulating film. a gate electrode layer overlapping the oxide semiconductor layer, When the composition ratio of the four elements is expressed in atomic percentage, The semiconductor device has an indium content of at least twice the gallium content and the zinc content. .

[0012] One form of the configuration of the invention disclosed in this specification is an oxide semiconductor layer including a channel formation region provided on an oxide insulating layer, a source electrode layer and a drain electrode layer on the oxide semiconductor layer, a gate insulating film on the source electrode layer and the drain electrode layer, and a gate electrode layer overlapping the oxide semiconductor layer on the gate insulating film. The oxide semiconductor layer contains at least four elements of indium, gallium, zinc, and oxygen. When the composition ratios of the four elements are expressed in atomic percentages, the ratio of indium is two times or more the sum of the ratios of gallium and zinc. This is a semiconductor device. One form of the configuration of the invention disclosed in this specification is a pair of first oxide semiconductor layers provided with a gap on an oxide insulating layer, a second oxide semiconductor layer including a channel formation region in contact with the oxide insulating layer and the pair of first oxide semiconductor layers, a gate insulating film on the oxide insulating layer and the second oxide semiconductor layer, and a gate electrode layer overlapping the second oxide semiconductor layer on the gate insulating film. The second oxide semiconductor layer contains at least four elements of indium, gallium, zinc, and oxygen. When the composition ratios of the four elements are expressed in atomic percentages, the ratio of indium is two times or more the sum of the ratios of gallium and zinc. This is a semiconductor device. The oxide semiconductor layer or the second oxide semiconductor layer is a non-single crystal semiconductor and may include a c-axis oriented crystal region. The oxide semiconductor layer or the second oxide semiconductor layer is a non-single crystal semiconductor and can be formed using an oxide target having a composition ratio of indium:gallium:zinc of 3:1:2. When the composition ratios of the four elements are expressed in atomic percentages, the ratio of indium is two times or more the sum of the ratios of gallium and zinc. This is a semiconductor device.

[0013] One form of the configuration of the invention disclosed in this specification is a pair of first oxide semiconductor layers provided with a gap on an oxide insulating layer. A second oxide semiconductor layer including a channel formation region in contact with the oxide insulating layer and the pair of first oxide semiconductor layers, a gate insulating film on the oxide insulating layer and the second oxide semiconductor layer, and a gate electrode layer overlapping the second oxide semiconductor layer on the gate insulating film. The second oxide semiconductor layer contains at least four elements of indium, gallium, zinc, and oxygen. When the composition ratios of the four elements are expressed in atomic percentages, the ratio of indium is two times or more the sum of the ratios of gallium and zinc. This is a semiconductor device. The ratio of indium. Is two times or more the sum of the ratios of gallium and zinc.

[0014] The oxide semiconductor layer or the second oxide semiconductor layer is a non-single crystal semiconductor and may include a c-axis oriented crystal region. This is a semiconductor device.

[0015] The oxide semiconductor layer or the second oxide semiconductor layer is a non-single crystal semiconductor and can be formed using an oxide target having a composition ratio of indium:gallium:zinc of 3:1:2. This is a semiconductor device.

[0016] In the oxide semiconductor layer or the second oxide semiconductor layer, a region that does not overlap with the gate electrode layer may be configured to contain a dopant.

[0017] Further, in the oxide semiconductor layer or the second oxide semiconductor layer, a region that does not overlap with the source electrode layer or the drain electrode layer may be configured to have an oxygen concentration higher than that of a region that overlaps with the source electrode layer or the drain electrode layer.

[0018] Also, a dopant may be self-alignedly introduced into the oxide semiconductor layer using the gate electrode layer as a mask, and a low-resistance region containing a dopant and having a lower resistance than the channel formation region may be formed in the oxide semiconductor layer, sandwiching the channel formation region. The dopant is an impurity that changes the conductivity of the oxide semiconductor layer. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

[0019] By having an oxide semiconductor layer including a low-resistance region sandwiching the channel formation region in the channel length direction, the transistor can have high on characteristics (e.g., on-current and field-effect mobility), enabling high-speed operation and high-speed response.

[0020] Also, a heat treatment (dehydration or dehydrogenation treatment) for releasing hydrogen or moisture into the oxide semiconductor layer may be performed. Further, when a crystalline oxide semiconductor layer is used as the oxide semiconductor layer, a heat treatment for crystallization may be performed.

[0021] Also, by the dehydration or dehydrogenation treatment, oxygen, which is the main component material constituting the oxide semiconductor, There is a risk that they will simultaneously desorb and decrease. In the oxide semiconductor film, oxygen desorbs and oxygen vacancies exist at the desorbed locations, which causes donor levels that lead to fluctuations in the electrical characteristics of the transistor to occur.

[0022] Therefore, it is preferable to supply oxygen to the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment. By supplying oxygen to the oxide semiconductor layer, oxygen vacancies in the film can be filled.

[0023] For example, by providing an oxide insulating film containing a large amount (excess) of oxygen that serves as an oxygen supply source in contact with the oxide semiconductor layer, oxygen can be supplied from the oxide insulating film to the oxide semiconductor layer. In the above configuration, heat treatment may be performed in a state where at least a part of the oxide semiconductor layer and the oxide insulating film that have been heat-treated as dehydration or dehydrogenation treatment are in contact with each other to supply oxygen to the oxide semiconductor layer.

[0024] Also, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment to supply oxygen into the film. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, etc. can be used.

[0025] Furthermore, preferably, the oxide semiconductor layer provided in the transistor is a film containing a region where the oxygen content is excessive with respect to the stoichiometric composition ratio in the crystalline state of the oxide semiconductor. In this case, the oxygen content is set to exceed the stoichiometric composition ratio of the oxide semiconductor. ​​​​​​​Alternatively, the oxygen content is set to exceed the amount of oxygen in the case of a single crystal. Oxygen may be present in the interstices of the lattice of the oxide semiconductor.

[0026] Hydrogen or moisture is removed from the oxide semiconductor, and it is purified to contain as few impurities as possible. By supplying oxygen to compensate for the oxygen deficiency, a type-I (intrinsic) oxide semiconductor or an oxide semiconductor that is extremely close to type-I (intrinsic) can be obtained. By doing so, the Fermi level (Ef) of the oxide semiconductor can be made the same level as the intrinsic Fermi level (Ei). Therefore, by using the oxide semiconductor layer in a transistor, variations in the threshold voltage Vth of the transistor due to oxygen deficiency and the shift ΔVth of the threshold voltage can be reduced.

[0027] One embodiment of the present invention relates to a semiconductor device having a transistor or a circuit including a transistor. For example, it relates to a semiconductor device having a transistor or a circuit including a transistor in which a channel formation region is formed of an oxide semiconductor. For example, it relates to a semiconductor integrated circuit including an LSI, a CPU, a power device mounted on a power supply circuit, a memory, a thyristor, a converter, an image sensor, etc., and an electronic device mounted with a component such as an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having a light-emitting element.

Advantages of the Invention

[0028] The threshold voltage of the electrical characteristics of a transistor using an oxide semiconductor in the channel formation region can be made flat, and a transistor structure and a manufacturing method thereof that realize a so-called normally-off switching element can be provided.

[0029] Also, in order to realize a higher-performance semiconductor device, the on characteristics of the transistor (e.g., on current and field-effect mobility) are improved to realize high-speed response and high-speed driving of the semiconductor device and a manufacturing method thereof can be provided.

[0030] Also, even during long-term use, a semiconductor device with a threshold voltage that is less likely to shift and high reliability can be provided.

Brief Description of the Drawings

[0031]

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Figure 17

Mode for Carrying Out the Invention

[0032] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and it will be easily understood by those skilled in the art that its form and details can be changed in various ways. Also, the invention disclosed in this specification is not to be construed as being limited to the description of the embodiments shown below. Note that the ordinal numbers attached as the first, second, etc. are for convenience and do not indicate the process order or the stacking order. Also, it does not indicate a unique name as a matter for specifying the invention in this specification.

[0033] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method of manufacturing the semiconductor device will be described with reference to FIGS. 1 and 3. In this embodiment, a transistor having an oxide semiconductor film is shown as an example of the semiconductor device.

[0034] The transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two are formed, or a triple gate structure in which three are formed. Also, it may be a dual gate type having two gate electrode layers disposed via a gate insulating film above and below the channel region.

[0035] The transistor 440a shown in FIGS. 1(A) to (E) has a top gate structure play This is an example of an n-type transistor.

[0036] Transistor 440a has a substrate 400 with an insulating surface provided with an oxide insulating layer 436 On it, there is an oxide semiconductor layer 403 including a channel formation region 409, low-resistance regions 404a and 404b 03, a source electrode layer 405a, a drain electrode layer 405b, a gate insulating film 402, and a gate elec trode layer 401. An insulating film 407 is formed on transistor 440a.

[0037] FIG. 1 shows a structure in which on the oxide semiconductor layer 403, the source electrode layer 405a and the drain electrode layer 405b do not overlap with the gate electrode layer 401. However, a structure in which the source electrode layer 405a and the drain electrode layer 405b partially overlap with the gate electrode layer 401, like the transistor 440b shown in FIG. 2(A), may be used.

[0038] The oxide semiconductor layer 403 contains at least four elements of indium, gallium, zinc, and oxygen

[0039]

[0040]

[0041] The oxide semiconductor is non-single crystal and may be amorphous or polycrystalline. Also, a structure including a crystalline portion in the amorphous state or non-amorphous may be used.

[0041] Since the amorphous oxide semiconductor can relatively easily obtain a flat surface, When a transistor is fabricated using this, interface scattering can be reduced, and relatively high mobility can be obtained relatively easily.

[0042] In addition, in an oxide semiconductor having crystallinity, more bulk defects can be reduced, and if the flatness of the surface is improved, mobility higher than that of an amorphous oxide semiconductor can be obtained. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, it may be formed on a surface having an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less.

[0043] Note that Ra is an arithmetic mean roughness defined by JIS B0601 extended three-dimensionally so that it can be applied to a surface, and can be expressed as "the average value of the absolute values of the deviations from the reference surface to the specified surface", and is defined by the following formula.

[0044]

Equation

[0045] Note that in the above, S0 refers to the area of the measurement surface (a rectangular region surrounded by four points represented by coordinates (x1, y1), (x1, y2), (x2, y1), and (x2, y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope).

[0046] As the oxide semiconductor layer 403, an oxide semiconductor layer containing crystals and having crystallinity (crystalline oxide semiconductor layer) can be used. The crystal state in the crystalline oxide semiconductor layer may be a state where the directions of the crystal axes are disordered or a state having a certain orientation. ​

[0047] For example, as the crystalline oxide semiconductor layer, an oxide semiconductor layer including a crystal having a c-axis substantially perpendicular to the surface can be used.

[0048] The oxide semiconductor layer including a crystal having a c-axis substantially perpendicular to the surface is not a single crystal structure, nor an amorphous structure, but an oxide semiconductor (CAAC - OS) layer including a crystal having a c-axis orientation (also referred to as C Axis Aligned Crystal; CAAC).

[0049] CAAC - OS refers to a crystal having a c-axis orientation and having a trigonal or hexagonal atomic arrangement when viewed from a direction perpendicular to the ab-plane, surface, or interface. In the direction perpendicular to the c-axis, metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. In the ab-plane (or surface or interface), it is a crystal in which the directions of the a-axis or b-axis are different (rotated around the c-axis). A thin film including CAAC is a thin film crystallized with respect to the c-axis and not necessarily arranged with respect to the ab-plane.

[0050] In a broad sense, CAAC refers to a non-single crystal that has a trigonal or hexagonal, or equilateral triangle or regular hexagon atomic arrangement when viewed from a direction perpendicular to its ab-plane, and includes a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers when viewed from a direction perpendicular to the c-axis direction.

[0051] A thin film including CAAC is not a single crystal, nor is it formed only from amorphous materials. Also, a thin film including CAAC includes a crystallized portion (crystal portion), but in some cases, the boundary between one crystal portion and another crystal portion cannot be clearly distinguished.

[0052] ​​​​​​​​​​​​ A part of the oxygen constituting the CAAC may be substituted with nitrogen. Further, a thin film containing CAAC is The c-axes of the individual crystal parts constituting it may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface on which the CAAC is formed, the surface of the CAAC, the film surface, the interface, etc.). Alternatively, the normal vectors of the ab-planes of the individual crystal parts constituting the thin film containing CAAC may be oriented in a certain direction (for example, a direction perpendicular to the substrate surface, the surface, the film surface, the interface, etc.). By using such a crystalline oxide semiconductor layer, changes in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be further suppressed, and a highly reliable semiconductor device can be obtained. the film surface, the interface, etc.).

[0053] By using such a crystalline oxide semiconductor layer, changes in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be further suppressed, and a highly reliable semiconductor device can be obtained. By using such a crystalline oxide semiconductor layer, changes in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be further suppressed, and a highly reliable semiconductor device can be obtained.

[0054] As methods for obtaining a crystalline oxide semiconductor layer having a c-axis orientation, three methods can be mentioned. The first is to form an oxide semiconductor layer by setting the film formation temperature to 200°C or higher and 500°C or lower, and c-axis-orienting it substantially perpendicular to the surface. The second is to perform a heat treatment at 200°C or higher and 70 0°C or lower after forming a thin film, and c-axis-orienting it substantially perpendicular to the surface. The third is to perform a heat treatment at 200°C or higher and 700°C or lower after forming the first layer with a thin film thickness, and then form the second layer and c-axis-orient it substantially perpendicular to the surface. After forming the first layer with a thin film thickness, perform a heat treatment at 200°C or higher and 700°C or lower, then form the second layer and c-axis-orient it substantially perpendicular to the surface.

[0055] The film thickness of the oxide semiconductor layer 403 is 1 nm or more and 30 nm or less (preferably 5 nm or more and 10 n m or less), and a sputtering method, MBE (Molecular Beam Epita xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Dep osition) method, etc. can be appropriately used. Further, for the oxide semiconductor layer 403, film formation is performed in a state where a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target surface. Film formation may be performed using a sputtering apparatus that performs

[0056] The CAAC-OS film is formed, for example, using a target for oxide semiconductor sputtering that is polycrystalline and by a sputtering method. When ions collide with the sputtering target, the crystal regions contained in the sputtering target are cleaved from the a-b plane and peeled off as flat plate-shaped or pellet-shaped sputtering particles having a plane parallel to the a -b plane. In this case, the flat plate-shaped sputtering particles reach the substrate while maintaining their crystal state, whereby the CAAC-OS film can be formed. substrate, and the CAAC-OS film can be formed.

[0057] In addition, in order to form the CAAC-OS film, it is preferable to apply the following conditions.

[0058] By reducing the incorporation of impurities during film formation, it is possible to suppress the crystal state from being disrupted by impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber may be reduced. Further, the impurity concentration in the film formation gas may be reduced. Specifically, a film formation gas having a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0059] In addition, by increasing the substrate heating temperature during film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower for film formation. By increasing the substrate heating temperature during film formation, when flat plate-shaped sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate.

[0060] ​​​​​​In addition, by increasing the oxygen ratio in the film-forming gas and optimizing the power, plasma damage during film formation is preferably reduced. The oxygen ratio in the film-forming gas is 30% by volume or more, preferably 100% by volume.

[0061] As an example of the sputtering target, the In-Ga-Zn-O compound target is shown below.

[0062] InO X powder, GaO Y powder, and ZnO Z powder are mixed at a predetermined molar ratio, and after pressure treatment heat treatment is performed at a temperature of 1000°C or higher and 1500°C or lower to obtain a polycrystalline In-Ga-Zn-O compound target. Here, X, Y, and Z are arbitrary positive numbers. Here, the predetermined molar ratio is, for example, InO powder, GaO powder, and ZnO X powder are Y in a molar ratio of 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. Note that the type of powder and the mixing ratio can be appropriately changed depending on the sputtering target to be produced. Z

[0063] An example of the manufacturing method is shown using the transistor 440a in FIGS. 1(A) to (E).

[0064] First, an oxide insulating layer 436 is formed on a substrate 400 having an insulating surface.

[0065] There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, ​​​​​​​​ Quartz substrates, sapphire substrates, etc. can be used. Also, single-crystalline semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can also be applied, and those with semiconductor elements provided on these substrates can be used as the substrate 400.

[0066] Also, as the substrate 400, a semiconductor device may be manufactured using a flexible substrate. To manufacture a semiconductor device having flexibility, a transistor 440a including an oxide semiconductor layer 403 may be directly manufactured on the flexible substrate, or a transistor 440a including an oxide semiconductor layer 403 may be manufactured on another manufacturing substrate and then peeled off and transferred onto the flexible substrate. In addition, in order to peel off and transfer from the manufacturing substrate to the flexible substrate, a peeling layer may be provided between the manufacturing substrate and the transistor 440a including an oxide semiconductor film.

[0067] As the oxide insulating layer 436, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, or a mixed material thereof can be formed by a plasma CVD method, a sputtering method, or the like.

[0068] The oxide insulating layer 436 may be a single layer or a laminate. For example, a silicon oxide film, an In-Hf-Zn-based oxide film, and an oxide semiconductor layer 403 may be laminated in this order on the substrate 400, or a silicon oxide film, an In-Zr-Zn-based oxide film having an atomic ratio of In:Zr:Zn = 1:1:1, and an oxide semiconductor layer 403 may be laminated in this order on the substrate 400, or a silicon oxide film, an In-Gd-Zn-based oxide film having an atomic ratio of In:Gd:Zn = 1:1:1, and an oxide The semiconductor layers 403 may be stacked in order.

[0069] In this embodiment, a silicon oxide film formed by a sputtering method is used as the oxide insulating layer 436. is used.

[0070] Also, a nitride insulating film may be provided between the oxide insulating layer 436 and the substrate 400. The nitride insulating film is formed by a plasma CVD method, a sputtering method, or the like using silicon nitride, silicon oxide nitride, aluminum nitride, aluminum oxynitride, or a mixed material thereof. can be formed.

[0071] Next, an oxide semiconductor layer 403 is formed on the oxide insulating layer 436.

[0072] Since the oxide insulating layer 436 is in contact with the oxide semiconductor layer 403, it is preferable that at least an amount of oxygen exceeding the stoichiometric composition ratio is present in the film (in the bulk). For example, when using a silicon oxide film as the oxide insulating layer 436, SiO 2+α (where α > 0) and do. By using such an oxide insulating layer 436, oxygen can be supplied to the oxide semiconductor layer 403, and the characteristics can be improved. By supplying oxygen to the oxide semiconductor layer 403, oxygen vacancies in the film can be filled.

[0073] For example, by providing an oxide insulating layer 436 containing a large amount (excessively) of oxygen serving as an oxygen supply source in contact with the oxide semiconductor layer 403, oxygen can be supplied from the oxide insulating layer 436 to the oxide semiconductor layer 40 3. By performing a heat treatment in a state where at least a part of the oxide semiconductor layer 403 and the oxide insulating layer 436 are in contact, oxygen can be supplied to the oxide semiconductor layer 40 3. supply may be performed. supply may be performed.

[0074] In the step of forming the oxide semiconductor layer 403, hydrogen or water is added to the oxide semiconductor layer 403. In order to prevent the inclusion of the oxide semiconductor layer 403, a sputtering process was performed as a pretreatment for the formation of the oxide semiconductor layer 403. The substrate on which the oxide insulating layer 436 is formed is preheated in a preheating chamber of the deposition apparatus, and the substrate and It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed in the oxide insulating layer 436. The exhaust means provided in the preheating chamber is preferably a cryopump.

[0075] A planarization treatment is performed on a region of the oxide insulating layer 436 that is to be in contact with the oxide semiconductor layer 403. The planarization process may be, but is not limited to, a polishing process (e.g., chemical polishing). Chemical Mechanical Polishing (CMP) A method for removing the impurities, a dry etching process, or a plasma process can be used.

[0076] The plasma treatment may be, for example, a reverse sputtering treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma in the vicinity of the substrate to modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the cleaning is performed, powdery substances (particles, dust, etc.) attached to the surface of the oxide insulating layer 436 are removed. (also called) can be removed.

[0077] As the planarization process, the polishing process, the dry etching process, and the plasma process may be performed multiple times. In addition, when performing the steps in combination, the order of the steps is not particularly limited. It is not fixed and may be appropriately set according to the uneven state of the surface of the oxide insulating layer 436.

[0078] Note that the oxide semiconductor layer 403 is formed under conditions where a large amount of oxygen is contained during film formation (for example, film formation is performed by sputtering in an atmosphere of 100% oxygen, etc.), so that a large amount of oxygen is contained. It is preferably a film containing (preferably containing a region where the oxygen content is excessive with respect to the stoichiometric composition ratio in the crystalline state of the oxide semiconductor).

[0079] In this embodiment, as a target for producing the oxide semiconductor layer 403 by sputtering, an oxide target having a composition ratio of In:Ga:Zn = 3:1:2 [atomic percentage] is used to form an In-Ga-Zn-based oxide film (IGZO film).

[0080] Also, the relative density (filling rate) of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the formed oxide semiconductor film can be a dense film.

[0081] As the sputtering gas used when forming the oxide semiconductor layer 403, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed.

[0082] The substrate is held in a film formation chamber maintained in a reduced pressure state. Then, while removing the residual moisture in the film formation chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the oxide semiconductor layer 403 is formed on the substrate 400 using the above target. In order to remove the residual moisture in the film formation chamber, an adsorption type vacuum pump, for example, a cryopump, an ion pump, a titanium sublimation pump ​​​​​​​​​​It is preferable to use P. Further, as the exhaust means, a turbo molecular pump with a cold trap added thereto may be used. The film forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms too) etc. are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer 403 formed in the film forming chamber can be reduced. It is also preferable to continuously form the oxide insulating layer 436 and the oxide semiconductor layer 403 without exposing them to the atmosphere. When the oxide insulating layer 436 and the oxide semiconductor layer 403 are continuously formed without being exposed to the atmosphere, it is possible to prevent impurities such as hydrogen and moisture from adsorbing on the surface of the oxide insulating layer 436. The oxide semiconductor layer 403 can be formed by processing a film-like oxide semiconductor film into an island-like oxide semiconductor layer by a photolithography process. Further, a resist mask for forming the island-like oxide semiconductor layer 403 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0083] Note that the etching of the oxide semiconductor film may be dry etching, wet etching, or both may be used. For example, as the etching solution used for wet etching of the oxide semiconductor film, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. Further, IT O07N (manufactured by Kanto Chemical Co., Inc.) may be used. It is preferable to use P. Further, as the exhaust means, a turbo molecular pump with a cold trap added thereto may be used. The film forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms too) etc. are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer 403 formed in the film forming chamber can be reduced.

[0084] It is also preferable to continuously form the oxide insulating layer 436 and the oxide semiconductor layer 403 without exposing them to the atmosphere. When the oxide insulating layer 436 and the oxide semiconductor layer 403 are continuously formed without being exposed to the atmosphere, it is possible to prevent impurities such as hydrogen and moisture from adsorbing on the surface of the oxide insulating layer 436. The oxide semiconductor layer 403 can be formed by processing a film-like oxide semiconductor film into an island-like oxide semiconductor layer by a photolithography process.

[0085] Further, a resist mask for forming the island-like oxide semiconductor layer 403 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Note that the etching of the oxide semiconductor film may be dry etching, wet etching, or both may be used. For example, as the etching solution used for wet etching of the oxide semiconductor film, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. Further, IT O07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0086] Note that the etching of the oxide semiconductor film may be dry etching, wet etching, or both may be used. For example, as the etching solution used for wet etching of the oxide semiconductor film, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. Further, IT O07N (manufactured by Kanto Chemical Co., Inc.) may be used. It is also preferable to continuously form the oxide insulating layer 436 and the oxide semiconductor layer 403 without exposing them to the atmosphere. When the oxide insulating layer 436 and the oxide semiconductor layer 403 are continuously formed without being exposed to the atmosphere, it is possible to prevent impurities such as hydrogen and moisture from adsorbing on the surface of the oxide insulating layer 436. The oxide semiconductor layer 403 can be formed by processing a film-like oxide semiconductor film into an island-like oxide semiconductor layer by a photolithography process.

[0087] In addition, excess hydrogen (including water and a hydroxyl group) is removed (dehydrated or The temperature for the heat treatment is 300° C. or higher and 700° C. or lower. The temperature should be below ℃ or below the distortion point of the substrate. Heat treatment should be performed under reduced pressure or in a nitrogen atmosphere. For example, the substrate can be introduced into an electric furnace, which is one type of heat treatment device, and an oxide semiconductor The layer 403 is subjected to a heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0088] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Transformer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0089] For example, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0090] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. , it is preferably free of hydrogen and the like. Alternatively, the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is preferably 6N (99.9999%) or higher, and more preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0091] After heating the oxide semiconductor layer 403 by heat treatment, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (the moisture content when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method is 20 ppm (dew point conversion of -55 °C) or lower, preferably 1 ppm or lower, more preferably 10 ppb or lower of air) may be introduced into the same furnace. It is preferable that water, hydrogen, etc. are not contained in the oxygen gas or dinitrogen monoxide gas. Also, the purity of the oxygen gas or dinitrogen monoxide gas introduced into the heat treatment apparatus is preferably 6N or higher, and more preferably 7N or higher (that is, the impurity concentration in the oxygen gas or dinitrogen monoxide gas is 1 ppm or lower, preferably 0.1 ppm or lower). By supplying oxygen, which is the main component material constituting the oxide semiconductor that has simultaneously decreased through the impurity elimination process by dehydration or dehydrogenation treatment due to the action of the oxygen gas or dinitrogen monoxide gas, the oxide semiconductor layer 403 can be purified to high purity and electrically made into the I-type (intrinsic) type.

[0092] Note that the heat treatment for dehydration or dehydrogenation can be performed at any timing in the manufacturing process of the transistor 440a as long as it is after the formation of the film-like oxide semiconductor film before the processing of the oxide semiconductor layer 403 and before the formation of the insulating film 407. For example, after the formation of the film-like oxide semiconductor film, or ​​​​​​​It can be performed after the formation of the island-shaped oxide semiconductor layer 403.

[0093] Also, the heat treatment for dehydration or dehydrogenation may be performed multiple times and may be combined with other heat treatments. It may be combined.

[0094] When the heat treatment for dehydration or dehydrogenation is performed in a state where the film-shaped oxide semiconductor film covers the oxide insulating layer 436 before being processed into an island shape as the oxide semiconductor layer 403, it is preferable because it is possible to prevent oxygen contained in the oxide insulating layer 436 from being released by the heat treatment. Before being processed into an island shape as the oxide semiconductor layer 403, it is preferable because it is possible to prevent oxygen contained in the oxide insulating layer 436 from being released by the heat treatment. It is preferable because it is possible to prevent oxygen contained in the oxide insulating layer 436 from being released by the heat treatment. It is preferable.

[0095] Also, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor layer that has undergone the dehydration or dehydrogenation treatment to supply oxygen into the film. It may be introduced into the oxide semiconductor layer that has undergone the dehydration or dehydrogenation treatment to supply oxygen into the film. It may be introduced into the oxide semiconductor layer that has undergone the dehydration or dehydrogenation treatment to supply oxygen into the film.

[0096] By introducing oxygen into the oxide semiconductor layer 403 that has undergone the dehydration or dehydrogenation treatment to supply oxygen into the film, the oxide semiconductor layer 403 can be purified to a high purity and electrically made into a type-I (intrinsic) state. By introducing oxygen into the oxide semiconductor layer 403 that has undergone the dehydration or dehydrogenation treatment to supply oxygen into the film, the oxide semiconductor layer 403 can be purified to a high purity and electrically made into a type-I (intrinsic) state. A transistor having the oxide semiconductor layer 403 that has been purified to a high purity and electrically made into a type-I (intrinsic) state has suppressed electrical characteristic variations and is electrically stable. A transistor having the oxide semiconductor layer 403 that has been purified to a high purity and electrically made into a type-I (intrinsic) state has suppressed electrical characteristic variations and is electrically stable.

[0097] As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, etc. can be used. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, etc. can be used.

[0098] In the step of introducing oxygen, when introducing oxygen into the oxide semiconductor layer 403, it may be directly introduced into the oxide semiconductor layer 403, or may pass through other films such as the gate insulating film 402 and the insulating film 407 and then be oxidized. In the step of introducing oxygen, when introducing oxygen into the oxide semiconductor layer 403, it may be directly introduced into the oxide semiconductor layer 403, or may pass through other films such as the gate insulating film 402 and the insulating film 407 and then be oxidized. It may be introduced into the oxide semiconductor layer 403. When introducing oxygen through other films, ion implantation method, ion doping method, plasma immersion ion implantation method, etc. may be used. When directly introducing oxygen into the exposed oxide semiconductor layer 403, plasma treatment or the like can also be used.

[0099] The introduction of oxygen into the oxide semiconductor layer 403 may be performed after dehydration or dehydrogenation treatment, and is not particularly limited. Further, the introduction of oxygen into the oxide semiconductor layer 40 3 that has undergone the above dehydration or dehydrogenation treatment may be performed multiple times.

[0100] Next, a conductive film that will become a source electrode layer and a drain electrode layer (including wirings formed of the same layer) is formed on the oxide semiconductor layer 403. A material that can withstand subsequent heat treatment is used for the conductive film. As the conductive film used for the source electrode layer and the drain electrode layer, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film ) etc. can be used. Also, a high melting point metal film such as Ti, Mo, W or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) may be laminated on one or both of the lower side and the upper side of a metal film such as Al or Cu. Further, the conductive film used for the source electrode layer and the drain electrode layer may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2 ), zinc oxide (ZnO), indium tin oxide (In2O3―SnO2), indium zinc oxide (In2O3―ZnO) or silicon oxide added to these metal oxide materials may be used. ​ Those included can be used.

[0101] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b, and then the resist mask is removed.

[0102] Next, a gate insulating film 402 that covers the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b is formed (see FIG. 1(C)). Note that in order to improve the coverage of the gate insulating film 402, the above planarization process may also be performed on the surfaces of the oxide semiconductor layer 403, the source

[0103] electrode layer 405a, and the drain electrode layer 405b. Particularly, when an insulating film with a thin film thickness is used as the gate insulating film 402, it is preferable that the flatness of the surfaces of the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b is good. is preferable.

[0104] The film thickness of the gate insulating film 402 is set to 1 nm or more and 20 nm or less, and a sputtering method, MBE method, CVD method, pulsed laser deposition method, ALD method, etc. can be appropriately used. Also, the gate insulating film 402 may be formed using a sputtering apparatus in which a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target and film formation is performed.

[0105] As the material of the gate insulating film 402, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used to form it. The gate insulating film 402 is formed on the oxide semiconductor layer 40 ​It is preferable that the portion in contact with 3 contains oxygen. In particular, for the gate insulating film 402, it is preferable that there is oxygen in the film (in the bulk) in an amount exceeding at least the stoichiometric composition ratio. , for example, when a silicon oxide film is used as the gate insulating film 402, it is set as SiO 2+α (where α > 0). In this embodiment, a silicon oxide film of SiO 2+ α (where α > 0) is used as the gate insulating film 402. By using this silicon oxide film as the gate insulating film 402, oxygen can be supplied to the oxide semiconductor layer 403, and the characteristics can be improved. Further, the gate insulating film 402 is preferably formed in consideration of the size of the transistors to be fabricated and the step coverage of the gate insulating film 402.

[0106] Also, as the material of the gate insulating film 402, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x > 0, y > 0)), hafnium silicate with nitrogen added (HfSiO N x N y (x > 0, y > 0)), hafnium aluminate (HfAl x O y (x > 0, y > 0)), high-k materials such as lanthanum oxide, etc. can be used to reduce the gate leakage current. Further, the gate insulating film 402 may have a single-layer structure or a laminated structure.

[0107] Then, the gate electrode layer 401 is formed on the gate insulating film 402 by plasma CVD method, sputtering method, etc. (see Fig. 1(B)). The material of the gate electrode layer 401 is molybdenum N, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium It can be formed using a metal material such as these or an alloy material having these as a main component. Further, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used as the gate electrode layer 401. A silicide film such as nickel silicide may also be used. The gate electrode layer 401 may have a single-layer structure or a stacked structure.

[0108] Further, as the material of the gate electrode layer 401, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide doped indium tin oxide, etc. can also be applied. Further, a stacked structure of the above conductive material and the above metal material can also be formed. material and the above metal material can also be formed. Further, a stacked structure of the above conductive material and the above metal material can also be formed.

[0109] Further, as a layer of the gate electrode layer 401 in contact with the gate insulating film 402, a metal oxide containing nitrogen, specifically, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen or an In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen, an Sn-O film containing nitrogen or an In-O film containing nitrogen, a metal nitride film (InN, SnN, etc.) can be used. These films have a work function of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive, and a so-called normally-off switching element can be realized. When used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive, and a so-called normally-off switching element can be realized. When used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive, and a so-called normally-off switching element can be realized. When used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive, and a so-called normally-off switching element can be realized.

[0110] Next, the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b are masked As a dopant 421 is introduced into the oxide semiconductor layer 403 as K, low resistance regions 404a and 40 4b are formed.

[0111] Depending on the film thicknesses of the source electrode layer 405a and the drain electrode layer 405b and the introduction conditions of the dopant 421, there are cases where the dopant 421 is introduced into the oxide semiconductor layer 403 under the source electrode layer 405a and the drain electrode layer 405b and cases where it is not introduced. Also, even when it is introduced, the concentration may be low and the region may have a higher resistance than the low resistance regions other than under the source electrode layer 405a or the drain electrode layer 405b.

[0112] For the transistor 440c shown in Fig. 2(B), a tungsten film with a thin film thickness, for example, 10 nm, is formed as the source electrode layer 405a and the drain electrode layer 40 5b. When the film thicknesses of the source electrode layer 405a and the drain electrode layer 405b are thus thin, when introducing a dopant into the oxide semiconductor layer 403 to form a low resistance region, the dopant can also be introduced into the oxide semiconductor layer 403 under the source electrode layer 405a and the drain electrode layer 405b through the source electrode layer 405a and the drain electrode layer 405b. Therefore, in the transistor 440c, low resistance regions 404a and 404b are also formed in the region of the oxide semiconductor layer 403 under the source electrode layer 405a and the drain electrode layer 405b. The dopant 421 is an impurity that changes the conductivity of the oxide semiconductor layer 403. As the dopant 421, group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), argon (Ar)

[0113] , one or more selected from helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl ), titanium (Ti), and zinc (Zn) can be used. It is possible.

[0114] The dopant 421 can also be introduced into the oxide semiconductor layer 403 through other films (for example, the insulating film 407, the source electrode layer 405 a, and the drain electrode layer 405b) by an implantation method. As a method for introducing the dopant 421, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. At that time , it is preferable to use ions of the dopant 421 alone or ions of fluoride or chloride. It is preferable.

[0115] The introduction process of the dopant 421 may be appropriately set and controlled by implantation conditions such as acceleration voltage and dose amount, and the film thickness of the film to be passed through. In this embodiment, boron is used as the dopant 421 and boron ions are implanted by an ion implantation method. Note that the dose amount of the dopant 421 is 1×10 ions / cm or more and 5×10 13 ions / cm 2 or less. 16 ions / cm 2 That's all right.

[0116] The concentration of the dopant 421 in the low resistance region is preferably 5×10 18 / cm 3 or more and 1×10 22 / cm 3 or less.

[0117] When introducing the dopant 421, it may be performed while heating the substrate 400.

[0118] Note that the process of introducing the dopant 421 into the oxide semiconductor layer 403 may be performed multiple times. Also, multiple types of dopants may be used.

[0119] Further, heat treatment may be performed after the introduction process of the dopant 421. As the heat treatment conditions, the temperature is 300°C or higher and 700°C or lower, preferably 300°C or higher and 450°C or lower for 1 hour, and it is preferably performed in an oxygen atmosphere. Also, heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in the atmosphere (ultra-dry air).

[0120] When the oxide semiconductor layer 403 is a crystalline oxide semiconductor film, it may partially become amorphous due to the introduction of the dopant 421. In this case, by performing heat treatment after the introduction of the dopant 421, the crystallinity of the oxide semiconductor layer 403 can be restored.

[0121] Thus, in the oxide semiconductor layer 403, an oxide semiconductor layer 403 is formed in which low-resistance regions 40 4a and 404b are provided with the channel formation region 409 interposed therebetween.

[0122] The transistor 440a of the present embodiment is fabricated through the above steps (see Fig. 1(C)). By using an oxide semiconductor layer 403 using an IGZO film containing at least indium, gallium, zinc, and oxygen, and when the composition ratio of these four elements is represented by atomic percentage, the ratio of indium is more than twice the ratio of gallium and the ratio of zinc, it is possible to impart high on characteristics (field-effect mobility), low off-current, and high reliability to the transistor 440a.

[0123] Next, the oxide semiconductor layer 403, the source electrode layer 405a, the drain electrode layer 405b, the gate An insulating film 407 is formed over the gate insulating film 402 and the gate electrode layer 401 (see FIG. 1(D)).

[0124] The insulating film 407 is formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like. The insulating film 407 is typically a silicon oxide film, a silicon oxynitride film, or a silicon oxide nitride film. For example, an inorganic insulating film such as an aluminum oxide film or a gallium oxide film can be used.

[0125] The insulating film 407 may be an aluminum oxide film, a hafnium oxide film, or a magnesium oxide film. film, zirconium oxide film, lanthanum oxide film, barium oxide film), or metal nitride film (e.g. For example, an aluminum nitride film can also be used.

[0126] The insulating film 407 may be a single layer or a multilayer, for example, a silicon oxide film and an aluminum oxide film. A stack of the above can be used.

[0127] The insulating film 407 is formed by mixing impurities such as water and hydrogen into the insulating film 407 by a method such as sputtering. In addition, the insulating film 407 is preferably formed by using an appropriate method. When the insulating film in contact with the conductor layer 403 contains excess oxygen, the oxide semiconductor layer 403 This is preferable because it serves as a source of oxygen.

[0128] In this embodiment, a silicon oxide film having a thickness of 100 nm is formed as the insulating film 407 by sputtering. The silicon oxide film is formed by sputtering. Typically, under an argon atmosphere, oxygen atmosphere, or a mixture of rare gas and oxygen atmosphere. This can be done.

[0129] In order to remove residual moisture in the deposition chamber of the insulating film 407, similarly to the deposition of the oxide semiconductor film, It is preferable to use an adsorption-type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating film 407 formed in the film-forming chamber evacuated using the cryopump can be reduced. In addition, as an exhaust means for removing residual moisture in the film-forming chamber of the insulating film 407, a turbo molecular pump with a cold trap added thereto may be used.

[0130] As the sputtering gas used when forming the insulating film 407, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrogen compounds have been removed.

[0131] The aluminum oxide film that can be used as the insulating film 407 provided on the oxide semiconductor layer 403 has a high blocking effect (blocking effect) that does not allow the film to pass through impurities such as hydrogen and moisture, and oxygen.

[0132] Therefore, the aluminum oxide film functions as a protective film that prevents the incorporation of impurities such as hydrogen and moisture, which are factors of variation, into the oxide semiconductor layer 403 during and after the manufacturing process, and the release of oxygen, which is the main component of the oxide semiconductor, from the oxide semiconductor layer 403.

[0133] In addition, a planarization insulating film may be formed to reduce surface irregularities caused by transistors. As the planarization insulating film, organic materials such as polyimide, acrylic, and benzocyclobutene-based resins can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) and the like can be used. Note that a planarization insulating film may be formed by laminating a plurality of insulating films formed of these materials.

[0134] Further, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the gate insulating film 402 and the insulating film 407, and wiring layers 465a and 465b that are electrically connected to the source electrode layer 405a and the drain electrode layer 405b are formed in the openings (see FIG. 1(E)). Using the wiring layers 465a and 465b, connection with other transistors can be made to configure various circuits. Also, as in the transistor 440d shown in FIG. 2(C), the wiring layers 465a and 465b may be provided in contact directly with the oxide semiconductor layer 403 without providing the source electrode layer 405a and the drain electrode layer 405b. The wiring layers 465a and 465b can be formed using the same materials and methods as the gate electrode layer 401, the source electrode layers 405a and 405b. For example, a laminate of a tantalum nitride film and a copper film, or a laminate of a tantalum nitride film and a tungsten film can be used as the wiring layers 465a and 465b. The oxide semiconductor layer 403 that is highly purified and has oxygen vacancies filled is sufficiently free of impurities such as hydrogen and water, and the hydrogen concentration in the oxide semiconductor layer 403 is 5×10 / cm

[0135] or less, preferably 5×10 / cm or less. Note that the hydrogen concentration in the oxide semiconductor layer 403 is measured by secondary ion mass spectrometry (SIMS).

[0136] The oxide semiconductor layer 403 that is highly purified and has oxygen vacancies filled and contains excess oxygen and is fabricated using this embodiment Also, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the gate insulating film 402 and the insulating film 407, and wiring layers 465a and 465b that are electrically connected to the source electrode layer 405a and the drain electrode layer 405b are formed in the openings (see FIG. 1(E)). Using the wiring layers 465a and 465b, connection with other transistors can be made to configure various circuits. The wiring layers 465a and 465b can be formed using the same materials and methods as the gate electrode layer 401, the source electrode layers 405a and 405b. For example, a laminate of a tantalum nitride film and a copper film, or a laminate of a tantalum nitride film and a tungsten film can be used as the wiring layers 465a and 465b. The oxide semiconductor layer 403 that is highly purified and has oxygen vacancies filled is sufficiently free of impurities such as hydrogen and water, and the hydrogen concentration in the oxide semiconductor layer 403 is 5×10

[0137] / cm or less, preferably 5×10 19 / cm 3 or less. Note that the hydrogen concentration in the oxide semiconductor layer 403 is measured by secondary ion mass spectrometry (SIMS). The oxide semiconductor layer 403 that is highly purified and has oxygen vacancies filled and contains excess oxygen and is fabricated using this embodiment 18 / cm 3 or less. Note that the hydrogen concentration in the oxide semiconductor layer 403 is measured by secondary ion mass spectrometry (SIMS). The hydrogen concentration in the oxide semiconductor layer 403 is measured by secondary ion mass spectrometry (SIMS:Secondary Ion Mass Sp ectrometry).

[0138] The oxide semiconductor layer 403 that is highly purified and has oxygen vacancies filled and contains excess oxygen and is fabricated using this embodiment The transistor 440a using the oxide semiconductor layer 403 has a current value in the off state (off current value) of 100 zA / μm or less, preferably 50 zA / μm or less per 1-μm channel width at room temperature (1 zA (zeptoampere) is 1×10 -21 A). It can be made low.

[0139] As described above, the threshold voltage of the transistor using the oxide semiconductor in the channel formation region can be made positive, and a transistor structure and a method for manufacturing the same, which realize a so-called normally-off switching element, can be provided.

[0140] In addition, in order to realize a higher-performance semiconductor device, the on characteristics of the transistor (for example, on current and field-effect mobility) are improved to realize a configuration for high-speed response and high-speed driving of the semiconductor device and a method for manufacturing the same can be provided.

[0141] In addition, even when used for a long period of time, a semiconductor device with a threshold voltage that hardly fluctuates and high reliability can be provided.

[0142] (Embodiment 2) In this embodiment, another form of the semiconductor device and the method for manufacturing the semiconductor device will be described with reference to FIGS. 3 and 4. Parts and processes that are the same as or have the same functions as those in the above embodiment can be performed in the same manner as in the above embodiment, and repeated descriptions will be omitted. Also, detailed descriptions of the same locations will be omitted.

[0143] The transistor 450 shown in FIGS. 3(A) to (C) is an example of a transistor having a top gate structure. FIG. 3(A) is a plan view, and a cross-section cut along the dashed-dotted line X-Y in FIG. 3(A) ​​​​​corresponds to FIG. 3(B), and the cross-section cut along the one-dot chain line V-W in FIG. 3(A) corresponds to FIG. 3(C). corresponds to

[0144] As shown in FIG. 3(B) which is a cross-sectional view in the channel length direction, the transistor 450 includes an oxide semiconductor layer 408a, 408b which is a first oxide semiconductor layer, a channel formation region 409, a low resistance region 414a, 414b on a substrate 400 having an insulating surface provided with an oxide insulating layer 436, an oxide semiconductor layer 403 which is a second oxide semiconductor layer, a source electrode layer 405 a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. The oxide semiconductor layers 408a, 408b are formed in contact with and spaced apart from each other on the oxide insulating layer 436, and the oxide semiconductor layer 403 is formed in contact with the oxide semiconductor layers 408a, 408b and the oxide insulating layer 436. a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. The oxide semiconductor layers 408a, 408b are formed in contact with and spaced apart from each other on the oxide insulating layer 436, and the oxide semiconductor layer 403 is formed in contact with the oxide semiconductor layers 408a, 408b and the oxide insulating layer 436. a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. The oxide semiconductor layers 408a, 408b are formed in contact with and spaced apart from each other on the oxide insulating layer 436, and the oxide semiconductor layer 403 is formed in contact with the oxide semiconductor layers 408a, 408b and the oxide insulating layer 436. a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. The oxide semiconductor layers 408a, 408b are formed in contact with and spaced apart from each other on the oxide insulating layer 436, and the oxide semiconductor layer 403 is formed in contact with the oxide semiconductor layers 408a, 408b and the oxide insulating layer 436. a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. The oxide semiconductor layers 408a, 408b are formed in contact with and spaced apart from each other on the oxide insulating layer 436, and the oxide semiconductor layer 403 is formed in contact with the oxide semiconductor layers 408a, 408b and the oxide insulating layer 436. a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401. The oxide semiconductor layers 408a, 408b are formed in contact with and spaced apart from each other on the oxide insulating layer 436, and the oxide semiconductor layer 403 is formed in contact with the oxide semiconductor layers 408a, 408b and the oxide insulating layer 436.

[0145] FIG. 3(C) is a cross-sectional view in the channel width direction, and the oxide semiconductor layer 403 has a taper of 20 degrees to 50 degrees at the ends. If the ends are perpendicular, oxygen is likely to escape and oxygen defects are likely to occur, but by having a taper at the ends, oxygen defects are suppressed, and the generation of leakage current (parasitic channel) in the transistor 450 is reduced. 50 degrees at the ends. If the ends are perpendicular, oxygen is likely to escape and oxygen defects are likely to occur, but by having a taper at the ends, oxygen defects are suppressed, and the generation of leakage current (parasitic channel) in the transistor 450 is reduced. 50 degrees at the ends. If the ends are perpendicular, oxygen is likely to escape and oxygen defects are likely to occur, but by having a taper at the ends, oxygen defects are suppressed, and the generation of leakage current (parasitic channel) in the transistor 450 is reduced.

[0146] By providing the oxide semiconductor layers 408a, 408b under the oxide semiconductor layer 403 having a film thickness of 3 to 5 nm, the contact resistance with the source electrode layers 405a, 405b can be reduced. By providing the oxide semiconductor layers 408a, 408b under the oxide semiconductor layer 403 having a film thickness of 3 to 5 nm, the contact resistance with the source electrode layers 405a, 405b can be reduced. By providing the oxide semiconductor layers 408a, 408b under the oxide semiconductor layer 403 having a film thickness of 3 to 5 nm, the contact resistance with the source electrode layers 405a, 405b can be reduced.

[0147] The low resistance regions 414a, 414b can be formed by introducing a dopant into the oxide semiconductor layer 40 3 using the gate electrode layer 401 as a mask. Also, the low resistance region contains a metal element. It can also be formed by diffusion. By using the diffusion of dopants and metal elements to form a low-resistance region, the contact resistance with the wiring layer can be further reduced.

[0148] Also, a sidewall insulating layer with a sidewall structure may be provided on the side surface of the gate electrode layer 401. The transistor 450 has thin sidewall insulating layers 412a and 412b provided on the side surface of the gate electrode layer 401. The sidewall insulating layers 412a and 412b are formed by forming an insulating film covering the gate electrode layer 401 and then processing the insulating film by anisotropic etching using the RIE (Reactive Ion Etching) method, and the sidewall insulating layers 412a and 412b of the sidewall structure can be self-alignedly formed on the sidewalls of the gate electrode layer 401. Here, the insulating film is not particularly limited. For example, silicon oxide with good step coverage formed by reacting TEOS (Tetraethyl-Ortho-Silicate) or silane, etc., with oxygen or nitrous oxide, etc., can be used. The insulating film can be formed by methods such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECR CVD, sputtering. Also, silicon oxide formed by the low-temperature oxidation (LTO: Low Temperature Oxidation) method may be used. By providing the sidewall insulating layers 412a and 412b, a short circuit between the gate electrode layer 401 and the low-resistance regions 404a and 404b can be prevented. If dopants are introduced into the entire oxide semiconductor layers 408a and 408b to form low-resistance regions, the acid

[0149]

[0150] ​​​​​​​Under the oxide semiconductor layers 408a and 408b, electrical connection with other conductive layers can also be made from the side of the oxide insulating layer 436. Continuation can be carried out.

[0151] The oxide semiconductor layer 403 contains at least four elements of indium, gallium, zinc, and oxygen. When the composition ratios of the four elements are expressed in atomic percentages, the ratio of indium is more than twice the ratios of gallium and zinc. Using an IGZO film with a high field-effect mobility, the film thickness is reduced to 3 - 5 nm, thereby preventing the transistor's normal-on due to the short-channel effect. It is possible to prevent.

[0152] As the oxide semiconductor layers 408a and 408b, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn oxide, Sn-Zn oxide, Al-Zn oxide , Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide , ternary metal oxides such as In-Ga-Zn oxide (also denoted as IGZO), In -Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al- Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-L a-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd -Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd- Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Z n oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, quaternary metal oxides such as In-Sn-Ga-Z n oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In -Oxides of the Sn-Al-Zn system, oxides of the In-Sn-Hf-Zn system, and In-Hf-Al-Z n oxides can be used.

[0153] As the oxide semiconductor layers 408a and 408b, highly conductive oxide semiconductor layers such as indium oxide, tin oxide, and zinc oxide may be used.

[0154] In this embodiment, as the oxide semiconductor layers 408a and 408b, an oxide semiconductor layer formed from an oxide target having a composition ratio of indium:gallium: zinc of 1:1:1 is used.

[0155] The film thickness of the oxide semiconductor layers 408a and 408b may be 20 to 50 nm.

[0156] An example of a method for manufacturing the transistor 450 is shown in FIGS. 4(A) to (E).

[0157] First, an oxide insulating layer 436 is formed on a substrate 400 having an insulating surface, and an oxide semiconductor film 444 is formed on the oxide insulating layer 43 6 (see FIG. 4(A)). In this embodiment, the oxide semi conductor film 444 is formed by sputtering using an oxide target having a composition ratio of indium:gallium:zinc of 1:1:1.

[0158] Next, the oxide semiconductor film 444 is processed into an island shape by a photolithography process to form oxide semiconductor layers 408a and 408b provided with a pair of intervals. An oxide semiconductor layer 403 is formed in contact with the oxide semiconductor layers 40 8a, 408b, and the oxide insulating layer 436 (see FIG. 4 (B)). The oxide semiconductor layer 403 is formed by sputtering using an oxide target having a composition ratio of indium:gallium:zinc of 3:1 :2. The end portion of 3 preferably has a tapered shape, and in this embodiment, it has a shape with a 30-degree taper. It is set to such a shape.

[0159] Next, a gate insulating film 402, a gate electrode layer 401, and sidewall insulating layers 412a and 412b that cover the side surfaces of the gate electrode layer 401 are formed on the oxide semiconductor layer 403 (see FIG. 4(C)). The gate insulating film 402 can be formed by forming an insulating film on the oxide semiconductor layer 403 and etching the insulating film using the gate electrode layer 401 and the sidewall insulating layers 412a and 412b as masks. Note that a part of the oxide semiconductor layer 403 is exposed. Next, a film 417 containing a metal element is formed in contact with a part of the oxide semiconductor layer 403 on the oxide semiconductor layer 403, the source electrode layer 405a, the drain electrode layer 405b, the gate insulating film 402, and the gate electrode layer 401 (see FIG. 1(C)). Examples of the film 417 containing a metal element include a metal film, a metal oxide film, and a metal nitride film. Examples of the metal element in the film containing a metal element include one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni). As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing one or more selected from the above metal elements can be used. Further, dopants such as phosphorus (P) and boron (B) can be added to the film containing a metal element.

[0160] Next, on the oxide semiconductor layer 403, the source electrode layer 405a, the drain electrode layer 405b, the gate insulating film 402, and the gate electrode layer 401, a film 417 containing a metal element is formed in contact with a part of the oxide semiconductor layer 403 (see FIG. 1(C)). Examples of the film 417 containing a metal element include a metal film, a metal oxide film, and a metal nitride film. Examples of the metal element in the film containing a metal element include one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni). As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing one or more selected from the above metal elements can be used. Further, dopants such as phosphorus (P) and boron (B) can be added to the film containing a metal element.

[0161] Examples of the film 417 containing a metal element include a metal film, a metal oxide film, and a metal nitride film. .

[0162] Examples of the metal element in the film containing a metal element include one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni). As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing one or more selected from the above metal elements can be used. Further, dopants such as phosphorus (P) and boron (B) can be added to the film containing a metal element. Examples of the metal element in the film containing a metal element include one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni). As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing one or more selected from the above metal elements can be used. Further, dopants such as phosphorus (P) and boron (B) can be added to the film containing a metal element. Examples of the metal element in the film containing a metal element include one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni). As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing one or more selected from the above metal elements can be used. Further, dopants such as phosphorus (P) and boron (B) can be added to the film containing a metal element. Examples of the metal element in the film containing a metal element include one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni). As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing one or more selected from the above metal elements can be used. Further, dopants such as phosphorus (P) and boron (B) can be added to the film containing a metal element. Examples of the metal element in the film containing a metal element include one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni). As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing one or more selected from the above metal elements can be used. Further, dopants such as phosphorus (P) and boron (B) can be added to the film containing a metal element. Examples of the metal element in the film containing a metal element include one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni). As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing one or more selected from the above metal elements can be used. Further, dopants such as phosphorus (P) and boron (B) can be added to the film containing a metal element. Examples of the metal element in the film containing a metal element include one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni). As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing one or more selected from the above metal elements can be used. Further, dopants such as phosphorus (P) and boron (B) can be added to the film containing a metal element. It may also include a metal element. In this embodiment, the film 417 containing a metal element has conductivity. .

[0163] The film 417 containing a metal element can be formed by a plasma CVD method, a sputtering method, an evaporation method, or the like. The film thickness of the film 417 containing a metal element may be 5 nm or more and 30 nm or less. .

[0164] In this embodiment, an aluminum film with a film thickness of 10 nm is formed as the film 417 containing a metal element by the sputtering method. .

[0165] Next, using the gate insulating film 402, the gate electrode layer 401, and the sidewall insulating layers 412a and 412b as masks, the dopant 421 is selectively introduced through the film 417 containing a metal element into the oxide semiconductor layer 403 to form a low-resistance region (see FIG. 4(D)).

[0166] The dopant 421 is an impurity that changes the conductivity of the oxide semiconductor layer 403. As the dopant 421, one or more selected from group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn) can be used. .

[0167] The above dopant may be included in the film 417 containing a metal element.

[0168] The dopant 421 is introduced into the oxide semiconductor through the film 417 containing a metal element by an implantation method. It is introduced into layer 403. As a method for introducing dopant 421, an ion implantation method, an ion doping ping method, a plasma immersion ion implantation method, etc. can be used. At that time, it is preferable to use ions of a single dopant 421 or ions of a hydride, fluoride, or chloride.

[0169] The introduction process of dopant 421 may be appropriately set and controlled by implantation conditions such as acceleration voltage and dose amount, and the film thickness of film 417 containing a metal element to be passed through. For example, when boron is used and boron ions are implanted by the ion implantation method, the acceleration voltage may be 15 kV and the dose amount may be 1×10 ions / cm 15 ions / cm 2 It is sufficient to set the dose amount to 1×10 13 ions / cm 2 or more and 5× 10 16 ions / cm 2 or less.

[0170] The concentration of dopant 421 in the low-resistance region is preferably 5×10 18 / cm 3 or more and 1×10 22 / cm 3 or less.

[0171] When introducing the dopant, it may be performed while heating the substrate 400.

[0172] Note that the process of introducing dopant 421 into the oxide semiconductor layer 403 may be performed multiple times, and a plurality of types of dopants may also be used.

[0173] Further, a heat treatment may be performed after the introduction process of dopant 421. As the heating conditions, the temperature is 300°C or higher and 700°C or lower, preferably 300°C or higher and 450°C or lower for 1 hour in an oxygen atmosphere. It is preferably carried out under reduced pressure. Further, heating may be performed under a nitrogen atmosphere, under reduced pressure, or under air (ultra-dry air). The treatment may be carried out.

[0174] Next, heat treatment is carried out in a state where a film 417 containing a metal element and a part of the oxide semiconductor layer 403 are in contact with each other. The heat treatment is preferably carried out in an oxygen atmosphere. The heat treatment can also be carried out under reduced pressure or under a nitrogen atmosphere. Also, the heating temperature may be 100°C or higher and 700°C or lower, preferably 200 °C or higher and 400°C or lower.

[0175] For example, a substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and a heat treatment is carried out on the film 417 containing a metal element and the oxide semiconductor layer 403 at 200°C for 1 hour in an oxygen atmosphere. Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats an object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats an object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas such as argon or an inert gas such as nitrogen that does not react with the object to be treated by heat treatment is used.

[0176]

[0177] ​​​​​​​​​​For example, as a heat treatment, the substrate may be placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then GRTA may be performed to take the substrate out of the inert gas. After that, the substrate may be taken out of the inert gas and GRTA may be performed after heating for several minutes.

[0178] The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (argon, helium, etc.). However, it is preferable that the atmosphere such as the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Further, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (argon, helium, etc.). However, it is preferable that the atmosphere such as the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Further, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (argon, helium, etc.). However, it is preferable that the atmosphere such as the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Further, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (argon, helium, etc.). However, it is preferable that the atmosphere such as the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Further, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (argon, helium, etc.). However, it is preferable that the atmosphere such as the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Further, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (argon, helium, etc.). However, it is preferable that the atmosphere such as the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Further, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (argon, helium, etc.). However, it is preferable that the atmosphere such as the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Further, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0179] By the heat treatment, metal elements are introduced from the film 417 containing metal elements into the oxide semiconductor layer 403, and low-resistance regions 414a and 414b are formed. Therefore, in the oxide semiconductor layer 403, low-resistance regions 414a and 414b containing dopants and metal elements are formed with the channel formation region 409 interposed therebetween. By the heat treatment, metal elements are introduced from the film 417 containing metal elements into the oxide semiconductor layer 403, and low-resistance regions 414a and 414b are formed. Therefore, in the oxide semiconductor layer 403, low-resistance regions 414a and 414b containing dopants and metal elements are formed with the channel formation region 409 interposed therebetween. By the heat treatment, metal elements are introduced from the film 417 containing metal elements into the oxide semiconductor layer 403, and low-resistance regions 414a and 414b are formed. Therefore, in the oxide semiconductor layer 403, low-resistance regions 414a and 414b containing dopants and metal elements are formed with the channel formation region 409 interposed therebetween. By the heat treatment, metal elements are introduced from the film 417 containing metal elements into the oxide semiconductor layer 403, and low-resistance regions 414a and 414b are formed. Therefore, in the oxide semiconductor layer 403, low-resistance regions 414a and 414b containing dopants and metal elements are formed with the channel formation region 409 interposed therebetween.

[0180] In this embodiment, since boron is used as the dopant and aluminum is used as the metal element, the low-resistance regions 414a and 414b contain boron and aluminum. In this embodiment, since boron is used as the dopant and aluminum is used as the metal element, the low-resistance regions 414a and 414b contain boron and aluminum.

[0181] Next, the film 417 containing metal elements is removed by etching. In this embodiment, the film 417 containing metal elements is removed by a wet etching method. Next, the film 417 containing metal elements is removed by etching. In this embodiment, the film 417 containing metal elements is removed by a wet etching method.

[0182] Through the above steps, the transistor 450 of this embodiment is manufactured. In the channel length direction, the cha The oxide semiconductor layer 403 includes low-resistance regions 414a and 414b sandwiching the panel formation region 409. By having such a configuration, the transistor 450 has on-characteristics (e.g., on-current and field effect The high mobility enables high-speed operation and high-speed response.

[0183] The low resistance regions 414a and 414b can function as a source region or a drain region. By providing the low resistance regions 414a and 414b, The electric field applied to the channel forming region 409 formed between the first and second electrodes 14b can be reduced. In addition, the oxide semiconductor layer 403 and the source electrode layer 4 The drain electrode layer 405a and the drain electrode layer 405b are electrically connected to each other. The contact resistance between the layer 403 and the source electrode layer 405a and the drain electrode layer 405b is reduced. This can be done.

[0184] In addition, a planarizing insulating film may be formed to reduce surface irregularities caused by the transistors. The smoothing insulating film is made of organic materials such as polyimide, acrylic, and benzocyclobutene resins. In addition to the above organic materials, low-dielectric constant materials (low-k materials) can be used. In addition, by stacking a plurality of insulating films made of these materials, A planarizing insulating film may be formed.

[0185] In this embodiment, a planarization insulating film 415 is formed over the transistor 450. An opening is formed in the oxide insulating film 415 so as to reach the oxide semiconductor layer 403, and the oxide semiconductor layer 403 is 3, a source electrode layer 405a and a drain electrode layer 405b are formed (FIG. 4 (See (E)).

[0186] As described above, the threshold of the electrical characteristics of a transistor in which an oxide semiconductor is used for a channel formation region can be obtained. This allows a low voltage to be made positive, realizing what is called a normally-off switching element. A transistor structure and a method for fabricating the same may be provided.

[0187] In order to realize a semiconductor device with higher performance, the on-characteristics of a transistor (e.g., A configuration that improves the current and field effect mobility to realize high-speed response and high-speed operation of semiconductor devices. A method for producing the same can also be provided.

[0188] In addition, the threshold voltage is unlikely to shift even after long-term use, resulting in highly reliable semiconductor devices. Locations can be provided.

[0189] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0190] (Embodiment 3) In this embodiment, the transistor described in Embodiment 1 or 2 is used, and A semiconductor that can retain memory contents even when power is not supplied and has no limit on the number of times it can be written to. An example of a semiconductor device according to the present embodiment will be described with reference to the drawings. The transistor described in the first or second embodiment is used as the transistor 162. The transistor 162 can be any of the transistors described in Embodiment 1 and 2. The structure of the above can also be applied.

[0191] Since the off-state current of the transistor 162 is small, the use of the transistor 162 enables long-term recording. The contents of the memory can be retained, i.e., no refresh operation is required, or , it becomes possible to make a semiconductor memory device with an extremely low refresh operation frequency, and the power consumption can be sufficiently reduced.

[0192] FIG. 5 is an example of the configuration of a semiconductor device. In FIG. 5(A), a cross-sectional view of the semiconductor device is shown, in FIG. 5( B), a plan view of the semiconductor device is shown, and in FIG. 5(C), a circuit diagram of the semiconductor device is shown. Here , FIG. 5(A) corresponds to the cross-section at C1-C2 and D1-D2 in FIG. 5(B).

[0193] The semiconductor device shown in FIGS. 5(A) and 5(B) has a transistor 160 using a first semiconductor material at the lower part and a transistor 162 using a second semiconductor material at the upper part. The transistor 162 can have the same configuration as that shown in Embodiment 1 or Embodiment 2.

[0194] Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon) , and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can hold charges for a long time due to its characteristics.

[0195] Note that although the above transistors are all described as n-channel type transistors, it goes without saying that p-channel type transistors can also be used. Also, since the technical essence of the disclosed invention lies in using an oxide semiconductor for the transistor 162 to hold information, materials used in the semiconductor device, the structure of the semiconductor device, etc., the semiconductor device There is no need to limit the specific configuration shown here.

[0196] The transistor 160 in FIG. 5(A) includes a semiconductor material (e.g., silicon, etc.). A channel formation region 116 provided on a substrate 185, and impurity regions 120 provided so as to sandwich the channel formation region 116. A metal compound region 124 in contact with the impurity regions 120, a gate insulating layer 108 provided on the channel formation region 116, and a gate electrode 110 provided on the gate insulating layer 108. Note that in the figure, there may be cases where a source electrode and a drain electrode are not explicitly shown. For convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, it may be expressed as a source electrode and a drain electrode including a source region and a drain region. That is, in this specification, the description of the source electrode may include the source region. On the substrate 185, an element isolation insulating layer 106 is provided so as to surround the transistor 160, and an insulating layer 130 is provided so as to cover the transistor 160. In order to achieve high integration, it is desirable to adopt a configuration in which the transistor 160 does not have a sidewall insulating layer as shown in FIG. 5(A). On the other hand, when emphasizing the characteristics of the transistor 160, a sidewall insulating layer may be provided on the side surface of the gate electrode 110, and the impurity region 120 may include regions with different impurity concentrations. And a gate electrode 110 provided on the gate insulating layer 108. In the figure, there may be cases where a source electrode and a drain electrode are not explicitly shown. For convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, it may be expressed as a source electrode and a drain electrode including a source region and a drain region. That is, in this specification, the description of the source electrode may include the source region. Although there may be cases where it does not have a source electrode or a drain electrode, for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, it may be expressed as a source electrode and a drain electrode including a source region and a drain region. That is, in this specification, the description of the source electrode may include the source region. In addition, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. In other words, in this specification, the description of the source electrode may include the source region. In the specification, the description of the source electrode may include the source region.

[0197] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 160, and an insulating layer 130 is provided so as to cover the transistor 160. In order to achieve high integration, it is desirable that the transistor 160 does not have a sidewall insulating layer as shown in FIG. 5(A). On the other hand, when emphasizing the characteristics of the transistor 160, a sidewall insulating layer may be provided on the side surface of the gate electrode 110, and the impurity region 120 may include regions with different impurity concentrations. In order to achieve high integration, it is desirable that the transistor 160 does not have a sidewall insulating layer as shown in FIG. 5(A). On the other hand, when emphasizing the characteristics of the transistor 160, a sidewall insulating layer may be provided on the side surface of the gate electrode 110, and the impurity region 120 may include regions with different impurity concentrations. On the other hand, when emphasizing the characteristics of the transistor 160, a sidewall insulating layer may be provided on the side surface of the gate electrode 110, and the impurity region 120 may include regions with different impurity concentrations. When emphasizing the characteristics of the transistor 160, a sidewall insulating layer may be provided on the side surface of the gate electrode 110, and the impurity region 120 may include regions with different impurity concentrations. When emphasizing the characteristics of the transistor 160, a sidewall insulating layer may be provided on the side surface of the gate electrode 110, and the impurity region 120 may include regions with different impurity concentrations.

[0198] The transistor 162 shown in FIG. 5(A) is a transistor that uses an oxide semiconductor for the channel formation region. Here, the oxide semiconductor layer 144 included in the transistor 162 has high purity. It is desirable that it be degree - converted. By using a highly purified oxide semiconductor, a transistor 162 with extremely excellent off - characteristics can be obtained. A transistor 162 with extremely excellent off - characteristics can be obtained.

[0199] On the transistor 162, an insulating layer 150 is provided either as a single layer or in a stacked manner. Also, in a region overlapping with the electrode layer 142a of the transistor 162 via the insulating layer 150, a conductive layer 148b is provided, and a capacitor element 164 is formed by the electrode layer 142a, the insulating layer 150, and the conductive layer 148b. That is, the electrode layer 142a of the transistor 162 functions as one electrode of the capacitor element 164, and the conductive layer 148b functions as the other electrode of the capacitor element 164. Note that when capacitance is not required, a configuration without providing the capacitor element 164 can also be adopted. Also, the capacitor element 164 may be provided separately above the transistor 162 . On the transistor 162 and the capacitor element 164, an insulating layer 152 is provided. And on the insulating layer 152, a wiring 156 for connecting the transistor 162 and other transistors is provided. Although not shown in FIG. 5(A), the wiring 156 is electrically connected to the electrode layer 142b via an electrode formed in an opening formed in the insulating layer 150,

[0200] the insulating layer 152, the gate insulating film 146, etc. Here, it is preferable that the electrode be provided so as to overlap at least a part of the oxide semiconductor layer 144 of the transistor 162 . In FIGS. 5(A) and 5(B), the transistor 160 and the transistor 162 are provided so that at least a part thereof overlaps, and the source region of the transistor 160 or the drain region is electrically connected to the wiring 156. Here, it is preferable that the electrode overlap at least a part of the oxide semiconductor layer 144 of the transistor 162.

[0201] In FIGS. 5(A) and 5(B), the transistor 160 and the transistor 162 are provided so that at least a part thereof overlaps, and the source region or the drain region of the transistor 160 is electrically connected to the wiring 156. It is preferable that the drain region and a part of the oxide semiconductor layer 144 overlap each other. Further, the transistor 162 and the capacitor element 164 are provided so as to overlap at least a part of the transistor 160. For example, the conductive layer 143b of the capacitor element 164 is provided so as to overlap at least a part of the gate electrode 128 of the transistor 160. By adopting such a planar layout, the occupied area of the semiconductor device can be reduced, so that high integration can be achieved.

[0202] Note that the electrical connection between the electrode layer 142b and the wiring 156 may be made by directly contacting the electrode layer 142b and the wiring 156, or an electrode may be provided on the intervening insulating layer and the connection may be made through the electrode. Also, a plurality of intervening electrodes may be provided.

[0203] Next, an example of the circuit configuration corresponding to FIGS. 5(A) and 5(B) is shown in FIG. 5(C).

[0204] In FIG. 5(C), the first wiring (1st Line) is electrically connected to the source electrode of the transistor 160, and the second wiring (2nd Line) is electrically connected to the drain electrode of the transistor 160. Also, the third wiring (3rd Line) is electrically connected to one of the source electrode or the drain electrode of the transistor 162, and the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 162. Then, the gate electrode of the transistor 160 and one of the source electrode or the drain electrode of the transistor 162 are electrically connected to the other electrode of the capacitor element 164, and the fifth wiring (5th Line) is electrically connected to the other electrode of the capacitor element 164. ​

[0205] In the semiconductor device shown in FIG. 5(C), by taking advantage of the feature that the potential of the gate electrode of the transistor 160 can be held, writing, holding, and reading of information are possible as follows. Writing and holding of information will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result,

[0206] the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor element 164. That is, a predetermined charge is applied to the gate electrode of the transistor 160 (writing). Here, it is assumed that either of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. Then, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off. By doing so, the charge applied to the gate electrode of the transistor 160 is held (holding). Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time. Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time. Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time. Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time. Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time. Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time. Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time.

[0207] Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time. Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time.

[0208] Next, reading of information will be described. When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (reading potential) is applied to the fifth wiring, the second wiring takes a different potential according to the amount of charge held in the gate electrode of the transistor 160. Generally, when the transistor 160 is an n-channel type, when a High level charge is applied to the gate electrode of the transistor 160, the apparent threshold value V When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (reading potential) is applied to the fifth wiring, the second wiring takes a different potential according to the amount of charge held in the gate electrode of the transistor 160. Generally, when the transistor 160 is an n-channel type, when a High level charge is applied to the gate electrode of the transistor 160, the apparent threshold value V When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (reading potential) is applied to the fifth wiring, the second wiring takes a different potential according to the amount of charge held in the gate electrode of the transistor 160. Generally, when the transistor 160 is an n-channel type, when a High level charge is applied to the gate electrode of the transistor 160, the apparent threshold value V When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (reading potential) is applied to the fifth wiring, the second wiring takes a different potential according to the amount of charge held in the gate electrode of the transistor 160. Generally, when the transistor 160 is an n-channel type, when a High level charge is applied to the gate electrode of the transistor 160, the apparent threshold value V When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (reading potential) is applied to the fifth wiring, the second wiring takes a different potential according to the amount of charge held in the gate electrode of the transistor 160. Generally, when the transistor 160 is an n-channel type, when a High level charge is applied to the gate electrode of the transistor 160, the apparent threshold value V th_His the gate of transistor 160 When a low-level charge is applied to the electrode, the apparent threshold value V th_L becomes lower This is because. Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary to turn the transistor 160 "on state" Therefore, by setting the potential of the fifth wiring to the intermediate potential V0 between V and V th_H and V th_L the charge applied to the gate electrode of the transistor 160 can be discriminated. For example, in writing, when a high-level charge is applied, if the potential of the fifth wiring becomes V0 (> V th_H ), the transistor 160 will enter the "on state". When a low-level charge is applied, even if the potential of the fifth wiring becomes V0 (< V th_H ), the transistor 160 remains in the "off state". Therefore, by observing the potential of the second wiring, the stored information can be read out th_L th_H

[0209] .

[0209] When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. When the information is not read in this way, a potential such that the transistor 160 is in the "off state" regardless of the state of the gate electrode, that is, a potential lower than V th_H th_L

[0210] can be applied to the fifth wiring. Or, a potential such that the transistor 160 is in the "on state" regardless of the state of the gate electrode, that is, a potential higher than V can be applied to the fifth wiring

[0210] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region, and the off-current By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0211] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0212] The transistor 162 contains at least four elements: indium, gallium, zinc, and oxygen. When the composition ratio of the four elements is expressed in atomic percentage, the ratio of indium is 1:1, and the ratio of gallium is 1:1. The oxide semiconductor layer has a ratio of Zn and a ratio of Zn that are more than twice as high as those of the oxide semiconductor layer. By adopting such a transistor, Furthermore, the semiconductor device of the present embodiment can be used for a long period of time. In addition, since the transistors used are less susceptible to threshold voltage shift, This can improve the reliability of the device.

[0213] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0214] (Embodiment 4) In this embodiment, the transistor shown in Embodiment 1 or Embodiment 2 is used, and a semiconductor device that can retain stored content even in a situation where no power is supplied and has no limitation on the number of write operations will be described with reference to FIGS. 6 and 7 for a configuration different from the configuration shown in Embodiment 3. Note that the semiconductor device of this embodiment is configured by applying the transistor described in Embodiment 1 or Embodiment 2 as transistor 162. As transistor 162, any structure of the transistors shown in Embodiment 1 or 2 can be applied. FIG. 6(A) shows an example of the circuit configuration of a semiconductor device, and FIG. 6(B) is a conceptual diagram showing an example of the semiconductor device. First, the semiconductor device shown in FIG. 6(A) will be described, and then the semiconductor device shown in FIG. 6(B) will be described below.

[0215]

[0216] In the semiconductor device shown in FIG. 6(A), the bit line BL is electrically connected to the source electrode or drain electrode of transistor 162, the word line WL is electrically connected to the gate electrode of transistor 162, and the source electrode or drain electrode of transistor 162 is electrically connected to the first terminal of capacitor element 254.

[0217] The transistor 162 using an oxide semiconductor has the characteristic that the off-current is extremely small. ​​​​​​​​​​​​is in this state. Therefore, by turning off the transistor 162, the potential of the first terminal of the capacitive element 254 (or the charge stored in the capacitive element 254) can be maintained for an extremely long time.

[0218] Next, a case of writing and holding information in the semiconductor device (memory cell 250) shown in FIG. 6(A) will be described.

[0219] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the bit line BL is applied to the first terminal of the capacitive element 254 (writing). Then, the potential of the word line WL is set to a potential at which the transistor 1 62 is turned off, and the transistor 162 is turned off. Thereby, the potential of the first terminal of the capacitive element 254 is held (holding).

[0220] Since the off-current of the transistor 162 is extremely small, the potential of the first terminal of the capacitive element 254 (or the charge stored in the capacitive element) can be held for a long time.

[0221] Next, information reading will be described. When the transistor 162 is turned on, the floating bit line BL in the floating state is connected to the capacitive element 254, and charge is redistributed between the bit line BL and the capacitive element 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL takes different values depending on the potential of the first terminal of the capacitive element 254 (or the charge stored in the capacitive element 254).

[0222] For example, let the potential of the first terminal of the capacitive element 254 be V, the capacitance of the capacitive element 254 be C, and the bit line ​​​​​​The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, and before the charge is redistributed assuming that the potential of the bit line BL before the charge redistribution is VB0, the potential of the bit line BL after the charge redistribution is (CB * VB0 + C * V) / (CB + C). Therefore, as the state of the memory cell 250 assuming that the potential of the first terminal of the capacitive element 254 takes two states of V1 and V0 (V1 > V0), when holding the potential V1, the potential of the bit line BL (=(CB * VB0 + C * V1 ) / (CB + C)) can be seen to be higher than the potential of the bit line BL when holding the potential V0 (=(CB * VB0 + C * V0) / (CB + C)).

[0223] And by comparing the potential of the bit line BL with a predetermined potential, information can be read .

[0224] As described above, due to the extremely small off - current of the transistor 162 in the semiconductor device shown in FIG. 6(A), the charge stored in the capacitive element 254 can be held for a long time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also even when there is no power supply, the stored content can be held for a long time. .

[0225] Next, the semiconductor device shown in FIG. 6(B) will be described.

[0226] The semiconductor device shown in FIG. 6(B) has memory cell arrays 251a and 251b having a plurality of the memory cells 2 50 shown in FIG. 6(A) as memory circuits in the upper part, and in the lower part, the peripheral circuits necessary to operate the memory array 251 (memory cell arrays 251a and 251b) It has a path 253. Note that the peripheral circuit 253 is electrically connected to the memory cell array 251. to be.

[0227] By adopting the configuration shown in FIG. 6(B), the peripheral circuit 253 can be provided directly below the memory cell array 251 ( memory cell arrays 251a and 251b), so that the semiconductor device can be miniaturized. to be.

[0228] The transistor provided in the peripheral circuit 253 preferably uses a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide can be used, and it is preferable to use a single-crystal semiconductor. In addition, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various circuits (logic circuits, drive circuits, etc.) that require high-speed operation can be preferably realized by the transistor. to be. operation can be preferably realized. to be.

[0229] Note that in the semiconductor device shown in FIG. 6(B), a configuration in which two memory cell arrays 251 (memory cell array 251a and memory cell array 251b) are stacked is illustrated, but the number of memory cells to be stacked is not limited to this. A configuration in which three or more memory cells are stacked may also be good.

[0230] Next, the specific configuration of the memory cell 250 shown in FIG. 6(A) will be described with reference to FIG. 7. to be.

[0231] FIG. 7 is an example of the configuration of the memory cell 250. In FIG. 7(A), the plan view of the memory cell 250 The figures are respectively cross-sectional views of the line segment A-B in FIG. 7(A) shown in FIG. 7(B).

[0232] The transistors 162 shown in FIGS. 7(A) and 7(B) may have the same configuration as that shown in Embodiment 1 or Embodiment 2 described above.

[0233] As shown in FIG. 7(B), the transistor 162 is provided on the electrodes 502 and 504 The electrode 502 is a wiring that functions as the bit line BL in FIG. 6(A), and is provided in contact with the low-resistance region of the transistor 162. The electrode 504 functions as one electrode of the capacitor element 254 in FIG. 6(A) and is provided in contact with the low-resistance region of the transistor 162. An electrode 506 provided in a region overlapping with the electrode 504 on the transistor 162 functions as the other electrode of the capacitor element 254 .

[0234] Also, as shown in FIG. 7(A), the other electrode 506 of the capacitor element 254 is electrically connected to the capacitor line 508 . The gate electrode 148a provided on the oxide semiconductor layer 144 via the gate insulating film 146 is electrically connected to the word line 509 .

[0235] FIG. 7(C) shows a cross-sectional view of a connection portion between the memory cell array 251 and the peripheral circuit . The peripheral circuit may be configured to include, for example, an n-channel transistor 510 and a p-channel transistor 512. As the semiconductor material used for the n-channel transistor 510 and the p-channel transistor 512, a semiconductor material other than the oxide semiconductor (such as silicon) is preferably used. By using such a material, the high-speed operation of the transistors included in the peripheral circuit can be achieved . ​​

[0236] By adopting the planar layout shown in Fig. 7(A), the occupied area of the semiconductor device can be reduced, so that high integration can be achieved.

[0237] As described above, the plurality of memory cells formed in multiple layers on the upper part are formed by transistors using an oxide semiconductor. The transistor using an oxide semiconductor contains at least four elements of indium, gallium, zinc, and oxygen. When the composition ratio of the four elements is expressed in atomic percentage, the ratio of indium is more than twice the ratio of gallium and the ratio of zinc. Since the off-current is small, it is possible to retain the stored content for a long time by using this transistor. That is, the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Further, as shown in Fig. 7(B), the capacitor element 254 is formed by laminating the electrode 504, the oxide semiconductor layer 144, the gate insulating film 146, and the electrode 506. Since the relative permittivity of the oxide semiconductor layer having the above composition is very high (66 in terms of relative permittivity), the area required for the capacitor element 254 can be reduced by using this as a dielectric film.

[0238] In this way, by integrating a peripheral circuit using a transistor made of a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a memory circuit using a transistor made of an oxide semiconductor (more broadly, a transistor with a sufficiently small off-current), a semiconductor device having unprecedented characteristics can be realized. Further, by forming the peripheral circuit and the memory circuit in a stacked structure, the integration of the semiconductor device can be

[0239] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is.

[0240] (Embodiment 5) In this embodiment, an example of applying the semiconductor device shown in the previous embodiment to portable devices such as mobile phones, smartphones, and e-books will be described with reference to FIGS. 8 to 11. In portable devices such as mobile phones, smartphones, and e-books, SRAM or DRAM is used for temporary storage of image data. The reason for using SRAM or DRAM is that flash memory has a slow response and is not suitable for image processing.

[0241] On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics. That is. That is. When SRAM or DRAM is used for temporary storage of image data, it has the following characteristics. That is.

[0242] A normal SRAM is composed of six transistors, transistors 801 to 806, as shown in FIG. 8(A), and is driven by an X decoder 807 and a Y decoder 808. Transistors 803 and 805, and transistors 804 and 806 form inverters, enabling high-speed driving. However, since one memory cell is composed of six transistors, it has the drawback of a large cell area. When the minimum dimension of the design rule is F, the memory cell area of SRAM is usually 100 to 150F. That is. That is. That is. That is. That is. That is. 2 Therefore, the unit price per bit of SRAM is the highest among various memories. That is.

[0243] On the other hand, in a DRAM, the memory cell is composed of a transistor 811, as shown in FIG. 8(B), and a capacitor It is composed of a holding capacity 812, which is driven by an X decoder 813 and a Y decoder 814. One cell has a configuration of one transistor and one capacitor, and the area is small. D The memory cell area of the RAM is usually 10F 2 or less. However, DRAM always requires refreshing and consumes power even when no rewriting is performed.

[0244] However, the memory cell area of the semiconductor device described in the previous embodiment is around 10F 2 and frequent refreshing is not required. Therefore, the memory cell area can be reduced and the power consumption can be reduced.

[0245] Fig. 9 shows a block diagram of a portable device. The portable device shown in Fig. 9 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, a touch sensor 919, an audio circuit 917, a keyboard 918, etc. The display 913 is composed of a display unit 9 14, a source driver 915, and a gate driver 916. The application processor 906 has a CPU 907, a DSP 908, and an interface 909 (I F909). Generally, the memory circuit 912 is composed of SRAM or DRAM and by adopting the semiconductor device described in the previous embodiment in this part, the writing and reading of information can be fast, long-term memory retention is possible, and the power consumption can be sufficiently reduced.

[0246] Fig. 10 shows an example in which the semiconductor device described in the previous embodiment is used in the memory circuit 950 of the display. The memory circuit 950 shown in Fig. 10 is composed of a memory 952, a memory 953, switches 954 and 955, and a memory controller 951. In addition, the memory circuit 950 reads and controls the signal line of the image data (input image data), the data stored in the memory 952 and the memory 953 (stored image data), and is connected to a display controller 956. And a display 957 that is displayed by a signal from the display controller 956 is connected. First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. Then, the image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and is displayed. If there is no change in the input image data A, the stored image data A is normally read out from the memory 952 via the switch 955 to the display controller 956 at a period of about 30 to 60 Hz.

[0247] Next, for example, when the user performs an operation to rewrite the screen (that is, when there is a change in the input image data A), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this period, the stored image data A is also periodically read out from the memory 952 via the switch 955. And the image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and is displayed. During this period, the stored image data A is also periodically read out from the memory 952 via the switch 955. And is displayed.

[0248] If there is no change in the input image data A, the stored image data A is normally read out from the memory 952 via the switch 955 to the display controller 956 at a period of about 30 to 60 Hz. And is read out from the memory 952 via the switch 955 to the display controller 956. And is read out.

[0249] Next, for example, when the user performs an operation to rewrite the screen (that is, when there is a change in the input image data A), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this period, the stored image data A is also periodically read out from the memory 952 via the switch 955. During this period, the stored image data A is also periodically read out from the memory 952 via the switch 955. It has been done. When the new image data (stored image data B) finishes being stored in the memory 953, From the next frame of the display 957, the stored image data B is read out, and via the switch 95 5 and the display controller 956, the stored image data B is sent to the display 957 and the display is performed. This reading continues until new image data is stored in the memory 952 next.

[0250] In this way, the memories 952 and 953 alternately perform writing and reading of image data to perform the display on the display 957. Note that the memories 952 and 953 are not limited to separate memories, and one memory may be divided and used. By adopting the semiconductor device described in the previous embodiment for the memories 952 and 953, writing and reading of information can be performed at high speed, long-term memory retention is possible, and power consumption can be sufficiently reduced.

[0251] FIG. 11 shows a block diagram of an e-book. FIG. 11 is composed of a battery 1001, a power supply circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

[0252] Here, the semiconductor device described in the previous embodiment can be used for the memory circuit 1007 in FIG. 11. The role of the memory circuit 1007 has a function of temporarily holding the content of the book. Examples of functions include when the user uses the highlight function. When the user ​​​​​​​​​​​​When reading an e - book, there may be a case where you want to mark a specific location. This marking function is called a highlighting function, and it shows the difference from the surroundings by changing the display color, underlining, making the characters bold, changing the font of the characters, etc. It is a function to memorize and retain the information of the location specified by the user. When storing this information for a long time, it may be copied to the flash memory 1004. Even in such a case, by adopting the semiconductor device described in the previous embodiment, the writing and reading of information can be performed at high speed, long - term memory retention is possible, and the power consumption can be sufficiently reduced.

[0253] As described above, the portable device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. Therefore, a portable device with high - speed reading, long - term memory retention, and reduced power consumption is realized.

[0254] The configuration, method, etc. shown in this embodiment can be appropriately combined with the configuration, method, etc. shown in other embodiments and used.

Example

[0255] In this example, an oxide semiconductor film (IGZO film) containing indium, gallium, and zinc was fabricated, the ionization potential of the oxide semiconductor film was measured, and an energy band diagram was calculated based on the result. In this specification, the value of the ionization potential is the value obtained by adding the bandgap (energy gap) and the electron affinity, and the value of the bandgap is the value obtained by measuring by spectroscopic ellipsometry of a single film of the material. Also, the composition analysis of the oxide semiconductor film was performed.

[0256] First, the results of the band gap obtained by spectroscopic ellipsometry are shown.

[0257] As the oxide semiconductor film used as the sample, an IGZO film with a thickness of 100 nm was formed on a quartz substrate by sputtering. The film formation conditions were a substrate temperature of 300 °C, and an oxide target with In:Ga:Zn = 3:1:2 [atomic ratio] was used.

[0258] The band gap was measured for samples formed in an atmosphere of argon and oxygen (argon:oxygen = 30 sccm:15 sccm). For the sample without heat treatment after film formation, it was 2.83 eV. For the sample heat-treated at 450 °C after film formation (1 hour in a nitrogen atmosphere followed by 1 hour in an oxygen atmosphere), it was 2.90 eV. For the sample heat-treated at 650 °C after film formation (1 hour in a nitrogen atmosphere followed by 1 hour in an oxygen atmosphere), it was 2.94 eV. Also, for the sample formed in an oxygen atmosphere (100% oxygen) without heat treatment after film formation, it was 2.82 eV. For the sample heat-treated at 450 °C after film formation (1 hour in a nitrogen atmosphere followed by 1 hour in an oxygen atmosphere), it was 2.89 eV. For the sample heat-treated at 650 °C after film formation (1 hour in a nitrogen atmosphere followed by 1 hour in an oxygen atmosphere), it was 2.94 eV, and it was approximately 2.8 eV to 2.9 eV.

[0259] Also, on a single-crystalline silicon substrate, an IGZO film with a thickness of 15 nm formed by sputtering using an oxide target with In:Ga:Zn = 3:1:2 [atomic ratio] under an oxygen atmosphere (100% oxygen) at a substrate temperature of 300 °C was measured for the ionization potential by ultraviolet photoelectron spectroscopy (UPS:Ultraviolet Photoelectron Spectroscopy) while sputtering from the surface side of the film. tron Spctroscopy). The ionization potential represents the energy difference from the vacuum level to the valence band.

[0260] Subtract the band gap measured by spectroscopic ellipsometry from the value of the ionization potential to calculate the energy of the conduction band, and create the band structure of the IGZO film formed using an oxide target with In:Ga:Zn = 3:1:2 [atomic ratio]. However, the band gap of the IGZO film was set to 2.8 eV. The result is shown in Fig. 12.

[0261] Next, on a single-crystalline silicon substrate, under an oxygen atmosphere (100% oxygen), a substrate temperature of 300 °C, and using a sputtering method with an oxide target of In:Ga:Zn = 3:1:2 [atomic ratio] at a film thickness of 15 nm, the composition of the IGZO film obtained was determined and evaluated by X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) analysis.

[0262] In the IGZO film, indium (In) was 23.7 atomic%, gallium (Ga) was 7.5 atomic%, zinc (Zn) was 9 atomic%, and oxygen (O) was 59.7 at omic%.

[0263] Also, X-ray diffraction (XRD: X-Ray Diffraction) measurement of the IGZO film formed using an oxide target with In:Ga:Zn = 3:1:2 [atomic ratio] was performed.

[0264] As a sample, an IGZO film with a thickness of 100 nm was formed on a quartz substrate using the sputtering method. The film formation conditions were a substrate temperature of room temperature, 200 °C, 300 °C, or 400 °C, and the film formation atmosphere was argon and oxygen (argon:oxygen = 30 sccm:15 sccm), and the target​​​​ As a target, an oxide target with an atomic ratio of In:Ga:Zn = 3:1:2 was used.

[0265] For each IGZO film, XRD spectra were measured using the out-of-plane method. The measurement results are shown in Fig. 13. In Fig. 13, the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the rotation angle 2θ (deg.). The XRD spectra were measured using an X-ray diffractometer D8 ADVANCE manufactured by Bruker r AXS.

[0266] As shown in Fig. 13, the IGZO film formed at room temperature showed no peaks indicating crystals in the XRD spectrum, confirming that it was an amorphous oxide semiconductor film. Also, the IGZO films formed at 200 °C, 300 °C, or 400 °C showed peaks due to crystals near 2θ = 31° in the XRD spectrum, as shown in Fig. 13, confirming that they were crystalline oxide semiconductor films.

[0267] Next, the end face of the IGZO film was cut out, and cross-sectional observation of the IGZO film was performed using a high-resolution transmission electron microscope (Hitachi High-Technologies Corporation's " H9000-NAR": TEM) with an acceleration voltage of 300 kV.

[0268] As a sample, an IGZO film with a thickness of 100 nm was formed on a quartz substrate using the sputtering method. The film formation conditions were a substrate temperature of 300 °C, a film formation atmosphere of argon and oxygen (argon: oxygen = 30 sccm: 15 sccm), and as a target, an oxide target with an atomic ratio of In:Ga:Zn = 3:1 :2.

[0269] Fig. 16(A) shows without heat treatment after film formation, and Fig. 16(B) shows heat treatment at 450 °C after film formation (nitrogen atmosphere). ​​​​​After 1 hour and then heat treatment at 650 °C for 1 hour in an oxygen atmosphere (after 1 hour in a nitrogen atmosphere and then 1 hour in an oxygen atmosphere), a TEM image of the cross-section of the IGZO film is shown in Fig. 16(C). The TEM image of the cross-section of the IGZO film is shown, which is after heat treatment at 650 °C for 1 hour in an oxygen atmosphere (after 1 hour in a nitrogen atmosphere and then 1 hour in an oxygen atmosphere).

[0270] As shown in Figs. 16(A) to (C), an IGZO film containing crystals (CAA C) having a c-axis approximately perpendicular to the surface was confirmed.

[0271] As described above, it was confirmed that a polycrystalline IGZO film can be obtained using an oxide target with In:Ga:Zn = 3:1:2 [atomic ratio]. It was confirmed that a polycrystalline IGZO film can be obtained using an oxide target with In:Ga:Zn = 3:1:2 [atomic ratio].

Example

[0272] In this example, a transistor having an IGZO film formed using an oxide target with In:Ga:Zn = 3:1:2 [atomic ratio] was fabricated, and its electrical characteristics and reliability were evaluated. A transistor having an IGZO film formed using an oxide target with In:Ga:Zn = 3:1:2 [atomic ratio] was fabricated, and its electrical characteristics and reliability were evaluated. done.

[0273] As transistors, a transistor 1 having the structure of the transistor 440a shown in Fig. 1 and a transistor 2 having the structure of the transistor 440b shown in Fig. 2(A) were fabricated. The fabrication methods of the transistor 1 and the transistor 2 are shown below. The fabrication methods of the transistor 1 and the transistor 2 are shown below.

[0274] Using the sputtering method as an insulating layer on a glass substrate, a silicon oxide film with a thickness of 300 nm was formed (film formation conditions: in an oxygen atmosphere, pressure 0.4 Pa, power supply 1.5 kW, distance between the glass substrate and the target 60 mm, substrate temperature 100 °C). Using the sputtering method as an insulating layer on a glass substrate, a silicon oxide film with a thickness of 300 nm was formed (film formation conditions: in an oxygen atmosphere, pressure 0.4 Pa, power supply 1.5 kW, distance between the glass substrate and the target 60 mm, substrate temperature 100 °C). and the distance between the glass substrate and the target is 60 mm, substrate temperature 100 °C).

[0275] After polishing the surface of the silicon oxide film, using the sputtering method with an oxide target of In:Ga:Zn = 3:1:2 [atomic ratio], an IG film with a thickness of 20 nm was formed A ZO film was formed. The film formation conditions were as follows: in an atmosphere of argon and oxygen (argon: oxygen = 30 sccm: 1 5 sccm), at a pressure of 0.4 Pa, a power supply of 1.5 kW, a distance between the glass substrate and the target of 60 mm, and a substrate temperature of 200 °C.

[0276] Next, after heat treatment at 450 °C for 1 hour in a nitrogen atmosphere, heat treatment was performed for 1 hour in an oxygen atmosphere. The IGZO film was etched into an island shape by the ICP (Inductively Coupled Plasma: Inductively coupled plasma) etching method (etching conditions: etching gas (BCl3:Cl2 = 60 sccm:20 sccm), power supply power of 450 W, bias power of 100 W, pressure of 1.9 Pa).

[0277] A tungsten film with a thickness of 50 nm was formed by sputtering (film formation conditions: in an argon atmosphere, at a pressure of 0.8 Pa, power supply power of 1 kW), and etched by the ICP etching method (etching conditions: etching gas (CF4:Cl2:O2 = 25 sccm:25 sccm :10 sccm), power supply power of 500 W, bias power of 150 W, pressure of 1.0 Pa) to form a source electrode layer and a drain electrode layer.

[0278] Next, a 30-nm silicon oxynitride film was formed by CVD to form a gate insulating film.

[0279] A 15-nm tantalum nitride film (film formation conditions: in an atmosphere of argon and nitrogen (Ar:N2 = 50 sccm:10 sccm), at a pressure of 0.6 Pa, power supply power of 1 kW ) and a 135-nm tungsten film (film formation conditions: in an argon atmosphere, at a pressure of 2.0 Pa , power supply power of 4 kW) were laminated, and etched by an etching method (first etching Condition: Etching gas (Cl2:SF6:O2 = 33 sccm:33 sccm:10 sccm), power supply power 2000 W, bias power 50 W, pressure 0.67 Pa) (Second etching condition: Etching gas (Cl2 = 100 sccm, power supply power 2000 W, bias power 5 0 W, pressure 0.67 Pa) to form the gate electrode layer.

[0280] Only for transistor 1, phosphorus (P) ions were implanted into the IGZO film by ion implantation method using the gate electrode layer, source electrode layer, and drain electrode layer as masks. Note that the implantation conditions for phosphorus (P) ions were an acceleration voltage of 40 kV and a dose of 1.0×10 ions / cm 15 2

[0281] An aluminum oxide film was formed on the gate electrode layer as an insulating film by sputtering method (film formation conditions : Argon and oxygen (argon:oxygen = 25 sccm:25 sccm) atmosphere, pressure 0 .4 Pa, power supply power 2.5 kW, distance between the glass substrate and the target 60 mm, substrate temperature 250 °C), and a 300 - nm silicon oxynitride film was laminated by CVD method.

[0282] Next, an opening reaching the IGZO film was formed in the gate insulating film and the insulating film, and a titanium film with a thickness of 50 nm was formed in the opening by sputtering method (film formation conditions: argon (Ar = 20 sccm) atmosphere, pressure 0.1 Pa, power supply power 12 kW), an aluminum film with a thickness of 100 nm (film formation conditions : Argon (Ar = 50 sccm) atmosphere, pressure 0.4 Pa, power supply power 1 kW), and a titanium film with a thickness of 50 nm (film formation conditions: argon (Ar = 20 sccm) atmosphere, pressure 0. 1 Pa, power supply power 12 kW) were laminated, and etching was performed (etching conditions: etching conditions: Etching ​​​​​​Gas (BCl3:Cl2=60sccm:20sccm), power supply power 450W, bias A wiring layer was formed at a power of 100 W and a pressure of 1.9 Pa.

[0283] Through the above steps, transistors 1 and 2 were manufactured. The channel length (L) is 3.2 μm and the channel width (W) is 10.1 μm. The conductive film is provided with a layer that does not overlap any of the source electrode layer, the drain electrode layer, and the gate electrode layer. The width of the thin region in the channel length direction (also called Loff) was set to 0.15 μm. In transistor 2, the channel length (L) is 2.9 μm and the channel width (W) is 10 0.1 μm, and the source electrode layer or the drain electrode layer is connected to the gate electrode layer on the oxide semiconductor film. The width of the overlapping region in the channel length direction (also called Lov) was set to 1.15 μm.

[0284] The electrical characteristics of the obtained transistors 1 and 2 and the Reliability evaluation was also performed. Gate voltage (Vg) - drain current (Id) characteristics and drain voltage (Vd) of 0.1V The field-effect mobility at the drain voltage (Vd) of transistor 1 is shown in Fig. 14. Gate voltage (Vg)-drain current (Id) characteristics at .1V and drain voltage (V d) The field-effect mobility at 0.1 V is shown in Figures 15(A) and (B).

[0285] As shown in FIGS. 14 and 15, the transistors 1 and 2 exhibit high on-state characteristics. The field effect mobility is 20 cm 2 / Vs, and 20 cm for transistor 2. 2 The field-effect mobility exceeded 1000 V / Vs.

[0286] One of the methods for examining the reliability of a transistor is the bias - thermal stress test (hereinafter referred to as the GBT (Gate Bias Temperature) test). The GBT test is a type of accelerated test, and it can evaluate the characteristic changes of a transistor that occur due to long - term use in a short time. In particular, the amount of change in the threshold voltage of the transistor before and after the GBT test is an important indicator for examining reliability. Before and after the GBT test, the smaller the amount of change in the threshold voltage, the higher the reliability.

[0287] The substrate on which the transistor is formed is maintained at a constant temperature, the source and drain of the transistor are set to the same potential, and a potential different from that of the source and drain is applied to the gate for a certain period of time. The temperature of the substrate can be set appropriately according to the test purpose. In the case of the "+GBT test", the potential applied to the gate is higher than the potential of the source and drain (the source and drain have the same potential), and in the case of the "-GBT test", the potential applied to the gate is lower than the potential of the source and drain (the source and drain have the same potential). The temperature of the substrate can be set appropriately according to the test purpose. In the case of the "+GBT test", the potential applied to the gate is higher than the potential of the source and drain (the source and drain have the same potential), and in the case of the "-GBT test", the potential applied to the gate is lower than the potential of the source and drain (the source and drain have the same potential). The potential applied to the gate is higher than the potential of the source and drain (the source and drain are at the same potential). In the "-GBT test", the potential applied to the gate is lower than the potential of the source and drain (the source and drain are at the same potential).

[0288] The test intensity of the GBT test can be determined by the substrate temperature, the electric field strength applied to the gate insulating layer, and the time of electric field application. The electric field strength in the gate insulating layer is determined by dividing the potential difference between the gate and the source and drain by the thickness of the gate insulating layer. The electric field strength in the gate insulating layer is determined by dividing the potential difference between the gate and the source and drain by the thickness of the gate insulating layer. by the thickness of the gate insulating layer.

[0289] In this embodiment, the GBT test was performed on transistor 1. First, as the +GBT test, the substrate temperature was set to 40 °C, Vd was set to 3 V, and the Vg - Id characteristics of transistor 1 were measured. Next , the substrate temperature was set to 150 °C and Vd was set to 0.1 V. Next, 6 V was applied to Vg so that the electric field strength applied to the gate insulating film became 2 MV / cm, and it was held in the air atmosphere for 1 hour as it was. Next, Vg was set to 0 V. Next, the substrate temperature was set to 40 °C, Vd was set to 10 V, and the Vg-Id measurement of transistor 1 was performed. The +GBT test results are shown in Fig. 15(A). The electric field strength applied to the gate insulating film became 2 MV / cm, and it was held in the air atmosphere for 1 hour as it was. Next, Vg was set to 0 V. Next, the substrate temperature was set to 40 °C, Vd was set to 10 V, and the Vg-Id measurement of transistor 1 was performed. The +GBT test results are shown in Fig. 15(A).

[0290] Similarly, for the -GBT test, first the substrate temperature was set to 40 °C, V(ds) was set to 10 V, and the Vg-Id characteristics of transistor 1 were measured. Next, the substrate temperature was set to 150 °C and Vd was set to 0.1 V. Next, the substrate temperature was set to 150 °C and Vd was set to 0.1 V. Next, -6 V was applied to Vg so that the electric field strength applied to the gate insulating film became -2 MV / cm, and it was held in the air atmosphere for 1 hour as it was. Next, Vg was set to 0 V. Next, Next, -6 V was applied to Vg so that the electric field strength applied to the gate insulating film became -2 MV / cm, and it was held in the air atmosphere for 1 hour as it was. Next, Vg was set to 0 V. Next, the substrate temperature was set to 40 °C, Vd was set to 10 V, and the Vg-Id measurement of transistor 1 was performed. The -GBT test results are shown in Fig. 15(B).

[0291] In Figs. 15(A) and (B), before the GBT test is shown by a thick line and after the test is shown by a thin line.

[0292] As shown in Figs. 15(A) and (B), almost no variation in the threshold voltage was observed due to the +GBT test and -GBT test of transistor 1. Therefore, it was confirmed that the transistor of this embodiment has little variation in the threshold voltage before and after the GBT test and has high reliability. As shown in Figs. 15(A) and (B), almost no variation in the threshold voltage was observed due to the +GBT test and -GBT test of transistor 1. Therefore, it was confirmed that the transistor of this embodiment has little variation in the threshold voltage before and after the GBT test and has high reliability. As shown in Figs. 15(A) and (B), almost no variation in the threshold voltage was observed due to the +GBT test and -GBT test of transistor 1. Therefore, it was confirmed that the transistor of this embodiment has little variation in the threshold voltage before and after the GBT test and has high reliability. was confirmed.

[0293] Also, by the same manufacturing process as transistor 1, a transistor with a channel length (L) of 0.8 μm, a channel width (W) of 1000 μm, and Loff of 0.3 μm was manufactured, and the off-leakage current (off-current) of the transistor was measured. The measurement was performed at 125 °C or 85 °C. Also, by the same manufacturing process as transistor 1, a transistor with a channel length (L) of 0.8 μm, a channel width (W) of 1000 μm, and Loff of 0.3 μm was manufactured, and the off-leakage current (off-current) of the transistor was measured. The off-leakage current (off-current) of the transistor was measured. The measurement was performed at 125 °C or 85 °C. It was carried out under the conditions. The measurement results are shown in Fig. 17.

[0294] From Fig. 17, when the transistor according to this embodiment was operated at 85 °C for 41.5 hours the off-leakage current was 0.5 zA / μm, which was an extremely low value.

[0295] From the above, the transistor of this embodiment has an extremely low off-current value and is a highly reliable transistor It was shown that it is a transistor.

Claims

1. A semiconductor device having a plurality of circuits arranged in a matrix, wherein the circuits include a first transistor having a first channel formation region containing silicon, and a second transistor having a second channel formation region containing an oxide semiconductor, wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, a first conductive layer provided above the first channel formation region and having a function as a gate electrode of the first transistor, a first insulating layer having a region in contact with a side surface of the first conductive layer, a second insulating layer above the first insulating layer, an oxide semiconductor layer having a region in contact with an upper surface of the second insulating layer and having the second channel formation region, a second conductive layer provided above the oxide semiconductor layer and having a function as a gate electrode of the second transistor, a third conductive layer electrically connected to the oxide semiconductor layer and having a function as one of a source electrode and a drain electrode of the second transistor, a third insulating layer having a region above the second conductive layer and a region above the third conductive layer, a fourth conductive layer above the third insulating layer, and a fourth insulating layer having a region above the fourth conductive layer, wherein the oxide semiconductor layer contains In, Ga, and Zn, the second insulating layer contains silicon oxide, in a plan view, the second conductive layer has a first region having a first length above the oxide semiconductor layer, in a plan view, the fourth conductive layer has a second region having a second length greater than the first length, wherein the first length and the second length are lengths in a channel length direction of the second transistor, the second region of the fourth conductive layer overlaps with the third conductive layer via the third insulating layer, and in a plan view, the second channel formation region does not overlap with the first channel formation region.

2. A semiconductor device having a plurality of circuits arranged in a matrix, wherein the circuits include a first transistor having a first channel formation region containing silicon, and a second transistor having a second channel formation region containing an oxide semiconductor, A semiconductor device in which a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, a first conductive layer provided above the first channel formation region and having a function as a gate electrode of the first transistor, a first insulating layer having a region in contact with a side surface of the first conductive layer, a second insulating layer above the first insulating layer, an oxide semiconductor layer having a region in contact with an upper surface of the second insulating layer and having the second channel formation region, a second conductive layer provided above the oxide semiconductor layer and having a function as a gate electrode of the second transistor, a third conductive layer electrically connected to the oxide semiconductor layer and having a function as one of a source electrode and a drain electrode of the second transistor, a third insulating layer having a region located above the second conductive layer and a region located above the third conductive layer, a fourth conductive layer above the third insulating layer, a fourth insulating layer having a region located above the fourth conductive layer, a fifth conductive layer above the fourth insulating layer, and having the oxide semiconductor layer contains In, Ga, and Zn, the second insulating layer contains silicon oxide, in plan view, the second conductive layer has a first region having a first length above the oxide semiconductor layer, in plan view, the fourth conductive layer has a second region having a second length greater than the first length, the first length and the second length are lengths in a channel length direction of the second transistor, the second region of the fourth conductive layer overlaps with the third conductive layer via the third insulating layer, the fifth conductive layer has a region overlapping with the first conductive layer, in plan view, the second channel formation region does not overlap with the first channel formation region, a semiconductor device.

3. A semiconductor device having a plurality of circuits arranged in a matrix, wherein the circuits include a first transistor having a first channel formation region containing silicon, and a second transistor having a second channel formation region containing an oxide semiconductor, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, A first conductive layer provided above the first channel formation region and having a function as a gate electrode of the first transistor; A first insulating layer having a region in contact with a side surface of the first conductive layer; A second insulating layer above the first insulating layer; An oxide semiconductor layer having a region in contact with an upper surface of the second insulating layer and having the second channel formation region; A second conductive layer provided above the oxide semiconductor layer and having a function as a gate electrode of the second transistor; A third conductive layer electrically connected to the oxide semiconductor layer and having a function as one of a source electrode and a drain electrode of the second transistor; A third insulating layer having a region located above the second conductive layer and a region located above the third conductive layer; A fourth conductive layer above the third insulating layer; A fourth insulating layer having a region located above the fourth conductive layer; and having, The oxide semiconductor layer contains In, Ga, and Zn; The second insulating layer contains silicon oxide; In plan view, the second conductive layer has a first region having a first length above the oxide semiconductor layer; In plan view, the fourth conductive layer has a second region having a second length greater than the first length; The first length and the second length are lengths in the channel length direction of the second transistor; The second region of the fourth conductive layer has an overlap with the third conductive layer via the third insulating layer; In plan view, the oxide semiconductor layer does not overlap with the first conductive layer, a semiconductor device.

4. A semiconductor device having a plurality of circuits arranged in a matrix, The circuit is, A first transistor having a first channel formation region containing silicon; A second transistor having a second channel formation region containing an oxide semiconductor; and having, A gate electrode of the first transistor is a semiconductor device electrically connected to one of a source electrode and a drain electrode of the second transistor, A first conductive layer provided above the first channel formation region and having a function as a gate electrode of the first transistor; A first insulating layer having a region in contact with a side surface of the first conductive layer; A second insulating layer above the first insulating layer; An oxide semiconductor layer having a region in contact with an upper surface of the second insulating layer and having the second channel formation region; A second conductive layer provided above the oxide semiconductor layer and having a function as a gate electrode of the second transistor; A third conductive layer electrically connected to the oxide semiconductor layer and having a function as one of a source electrode and a drain electrode of the second transistor; A third insulating layer having a region located above the second conductive layer and a region located above the third conductive layer; A fourth conductive layer above the third insulating layer; A fourth insulating layer having a region located above the fourth conductive layer; A fifth conductive layer above the fourth insulating layer, and The oxide semiconductor layer contains In, Ga, and Zn. The second insulating layer contains silicon oxide. In plan view, the second conductive layer has a first region having a first length above the oxide semiconductor layer. In plan view, the fourth conductive layer has a second region having a second length greater than the first length. The first length and the second length are lengths in the channel length direction of the second transistor. The fourth conductive layer overlaps with the third conductive layer via the third insulating layer. The fifth conductive layer has a region overlapping with the first conductive layer. In plan view, the oxide semiconductor layer does not overlap with the first conductive layer, a semiconductor device.

5. In any one of Claims 1 to 4, The semiconductor device, wherein the fourth conductive layer has a region overlapping with the first conductive layer via the third insulating layer and the third conductive layer.

6. In any one of Claims 1 to 5, The semiconductor device, wherein the oxide semiconductor layer has crystallinity.

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